1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021, Linaro Limited 5 * 6 */ 7 8 #include <linux/interconnect-provider.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 #include <dt-bindings/interconnect/qcom,sm8350.h> 12 13 #include "bcm-voter.h" 14 #include "icc-rpmh.h" 15 16 static struct qcom_icc_node qhm_qspi; 17 static struct qcom_icc_node qhm_qup0; 18 static struct qcom_icc_node qhm_qup1; 19 static struct qcom_icc_node qhm_qup2; 20 static struct qcom_icc_node qnm_a1noc_cfg; 21 static struct qcom_icc_node xm_sdc4; 22 static struct qcom_icc_node xm_ufs_mem; 23 static struct qcom_icc_node xm_usb3_0; 24 static struct qcom_icc_node xm_usb3_1; 25 static struct qcom_icc_node qhm_qdss_bam; 26 static struct qcom_icc_node qnm_a2noc_cfg; 27 static struct qcom_icc_node qxm_crypto; 28 static struct qcom_icc_node qxm_ipa; 29 static struct qcom_icc_node xm_pcie3_0; 30 static struct qcom_icc_node xm_pcie3_1; 31 static struct qcom_icc_node xm_qdss_etr; 32 static struct qcom_icc_node xm_sdc2; 33 static struct qcom_icc_node xm_ufs_card; 34 static struct qcom_icc_node qnm_gemnoc_cnoc; 35 static struct qcom_icc_node qnm_gemnoc_pcie; 36 static struct qcom_icc_node xm_qdss_dap; 37 static struct qcom_icc_node qnm_cnoc_dc_noc; 38 static struct qcom_icc_node alm_gpu_tcu; 39 static struct qcom_icc_node alm_sys_tcu; 40 static struct qcom_icc_node chm_apps; 41 static struct qcom_icc_node qnm_cmpnoc; 42 static struct qcom_icc_node qnm_gemnoc_cfg; 43 static struct qcom_icc_node qnm_gpu; 44 static struct qcom_icc_node qnm_mnoc_hf; 45 static struct qcom_icc_node qnm_mnoc_sf; 46 static struct qcom_icc_node qnm_pcie; 47 static struct qcom_icc_node qnm_snoc_gc; 48 static struct qcom_icc_node qnm_snoc_sf; 49 static struct qcom_icc_node qhm_config_noc; 50 static struct qcom_icc_node llcc_mc; 51 static struct qcom_icc_node qnm_camnoc_hf; 52 static struct qcom_icc_node qnm_camnoc_icp; 53 static struct qcom_icc_node qnm_camnoc_sf; 54 static struct qcom_icc_node qnm_mnoc_cfg; 55 static struct qcom_icc_node qnm_video0; 56 static struct qcom_icc_node qnm_video1; 57 static struct qcom_icc_node qnm_video_cvp; 58 static struct qcom_icc_node qxm_mdp0; 59 static struct qcom_icc_node qxm_mdp1; 60 static struct qcom_icc_node qxm_rot; 61 static struct qcom_icc_node qhm_nsp_noc_config; 62 static struct qcom_icc_node qxm_nsp; 63 static struct qcom_icc_node qnm_aggre1_noc; 64 static struct qcom_icc_node qnm_aggre2_noc; 65 static struct qcom_icc_node qnm_snoc_cfg; 66 static struct qcom_icc_node qxm_pimem; 67 static struct qcom_icc_node xm_gic; 68 static struct qcom_icc_node qns_a1noc_snoc; 69 static struct qcom_icc_node srvc_aggre1_noc; 70 static struct qcom_icc_node qns_a2noc_snoc; 71 static struct qcom_icc_node qns_pcie_mem_noc; 72 static struct qcom_icc_node srvc_aggre2_noc; 73 static struct qcom_icc_node qhs_ahb2phy0; 74 static struct qcom_icc_node qhs_ahb2phy1; 75 static struct qcom_icc_node qhs_aoss; 76 static struct qcom_icc_node qhs_apss; 77 static struct qcom_icc_node qhs_camera_cfg; 78 static struct qcom_icc_node qhs_clk_ctl; 79 static struct qcom_icc_node qhs_compute_cfg; 80 static struct qcom_icc_node qhs_cpr_cx; 81 static struct qcom_icc_node qhs_cpr_mmcx; 82 static struct qcom_icc_node qhs_cpr_mx; 83 static struct qcom_icc_node qhs_crypto0_cfg; 84 static struct qcom_icc_node qhs_cx_rdpm; 85 static struct qcom_icc_node qhs_dcc_cfg; 86 static struct qcom_icc_node qhs_display_cfg; 87 static struct qcom_icc_node qhs_gpuss_cfg; 88 static struct qcom_icc_node qhs_hwkm; 89 static struct qcom_icc_node qhs_imem_cfg; 90 static struct qcom_icc_node qhs_ipa; 91 static struct qcom_icc_node qhs_ipc_router; 92 static struct qcom_icc_node qhs_lpass_cfg; 93 static struct qcom_icc_node qhs_mss_cfg; 94 static struct qcom_icc_node qhs_mx_rdpm; 95 static struct qcom_icc_node qhs_pcie0_cfg; 96 static struct qcom_icc_node qhs_pcie1_cfg; 97 static struct qcom_icc_node qhs_pdm; 98 static struct qcom_icc_node qhs_pimem_cfg; 99 static struct qcom_icc_node qhs_pka_wrapper_cfg; 100 static struct qcom_icc_node qhs_pmu_wrapper_cfg; 101 static struct qcom_icc_node qhs_qdss_cfg; 102 static struct qcom_icc_node qhs_qspi; 103 static struct qcom_icc_node qhs_qup0; 104 static struct qcom_icc_node qhs_qup1; 105 static struct qcom_icc_node qhs_qup2; 106 static struct qcom_icc_node qhs_sdc2; 107 static struct qcom_icc_node qhs_sdc4; 108 static struct qcom_icc_node qhs_security; 109 static struct qcom_icc_node qhs_spss_cfg; 110 static struct qcom_icc_node qhs_tcsr; 111 static struct qcom_icc_node qhs_tlmm; 112 static struct qcom_icc_node qhs_ufs_card_cfg; 113 static struct qcom_icc_node qhs_ufs_mem_cfg; 114 static struct qcom_icc_node qhs_usb3_0; 115 static struct qcom_icc_node qhs_usb3_1; 116 static struct qcom_icc_node qhs_venus_cfg; 117 static struct qcom_icc_node qhs_vsense_ctrl_cfg; 118 static struct qcom_icc_node qns_a1_noc_cfg; 119 static struct qcom_icc_node qns_a2_noc_cfg; 120 static struct qcom_icc_node qns_ddrss_cfg; 121 static struct qcom_icc_node qns_mnoc_cfg; 122 static struct qcom_icc_node qns_snoc_cfg; 123 static struct qcom_icc_node qxs_boot_imem; 124 static struct qcom_icc_node qxs_imem; 125 static struct qcom_icc_node qxs_pimem; 126 static struct qcom_icc_node srvc_cnoc; 127 static struct qcom_icc_node xs_pcie_0; 128 static struct qcom_icc_node xs_pcie_1; 129 static struct qcom_icc_node xs_qdss_stm; 130 static struct qcom_icc_node xs_sys_tcu_cfg; 131 static struct qcom_icc_node qhs_llcc; 132 static struct qcom_icc_node qns_gemnoc; 133 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; 134 static struct qcom_icc_node qhs_modem_ms_mpu_cfg; 135 static struct qcom_icc_node qns_gem_noc_cnoc; 136 static struct qcom_icc_node qns_llcc; 137 static struct qcom_icc_node qns_pcie; 138 static struct qcom_icc_node srvc_even_gemnoc; 139 static struct qcom_icc_node srvc_odd_gemnoc; 140 static struct qcom_icc_node srvc_sys_gemnoc; 141 static struct qcom_icc_node qhs_lpass_core; 142 static struct qcom_icc_node qhs_lpass_lpi; 143 static struct qcom_icc_node qhs_lpass_mpu; 144 static struct qcom_icc_node qhs_lpass_top; 145 static struct qcom_icc_node srvc_niu_aml_noc; 146 static struct qcom_icc_node srvc_niu_lpass_agnoc; 147 static struct qcom_icc_node ebi; 148 static struct qcom_icc_node qns_mem_noc_hf; 149 static struct qcom_icc_node qns_mem_noc_sf; 150 static struct qcom_icc_node srvc_mnoc; 151 static struct qcom_icc_node qns_nsp_gemnoc; 152 static struct qcom_icc_node service_nsp_noc; 153 static struct qcom_icc_node qns_gemnoc_gc; 154 static struct qcom_icc_node qns_gemnoc_sf; 155 static struct qcom_icc_node srvc_snoc; 156 157 static struct qcom_icc_node qhm_qspi = { 158 .name = "qhm_qspi", 159 .channels = 1, 160 .buswidth = 4, 161 .num_links = 1, 162 .link_nodes = { &qns_a1noc_snoc }, 163 }; 164 165 static struct qcom_icc_node qhm_qup0 = { 166 .name = "qhm_qup0", 167 .channels = 1, 168 .buswidth = 4, 169 .num_links = 1, 170 .link_nodes = { &qns_a2noc_snoc }, 171 }; 172 173 static struct qcom_icc_node qhm_qup1 = { 174 .name = "qhm_qup1", 175 .channels = 1, 176 .buswidth = 4, 177 .num_links = 1, 178 .link_nodes = { &qns_a1noc_snoc }, 179 }; 180 181 static struct qcom_icc_node qhm_qup2 = { 182 .name = "qhm_qup2", 183 .channels = 1, 184 .buswidth = 4, 185 .num_links = 1, 186 .link_nodes = { &qns_a2noc_snoc }, 187 }; 188 189 static struct qcom_icc_node qnm_a1noc_cfg = { 190 .name = "qnm_a1noc_cfg", 191 .channels = 1, 192 .buswidth = 4, 193 .num_links = 1, 194 .link_nodes = { &srvc_aggre1_noc }, 195 }; 196 197 static struct qcom_icc_node xm_sdc4 = { 198 .name = "xm_sdc4", 199 .channels = 1, 200 .buswidth = 8, 201 .num_links = 1, 202 .link_nodes = { &qns_a1noc_snoc }, 203 }; 204 205 static struct qcom_icc_node xm_ufs_mem = { 206 .name = "xm_ufs_mem", 207 .channels = 1, 208 .buswidth = 8, 209 .num_links = 1, 210 .link_nodes = { &qns_a1noc_snoc }, 211 }; 212 213 static struct qcom_icc_node xm_usb3_0 = { 214 .name = "xm_usb3_0", 215 .channels = 1, 216 .buswidth = 8, 217 .num_links = 1, 218 .link_nodes = { &qns_a1noc_snoc }, 219 }; 220 221 static struct qcom_icc_node xm_usb3_1 = { 222 .name = "xm_usb3_1", 223 .channels = 1, 224 .buswidth = 8, 225 .num_links = 1, 226 .link_nodes = { &qns_a1noc_snoc }, 227 }; 228 229 static struct qcom_icc_node qhm_qdss_bam = { 230 .name = "qhm_qdss_bam", 231 .channels = 1, 232 .buswidth = 4, 233 .num_links = 1, 234 .link_nodes = { &qns_a2noc_snoc }, 235 }; 236 237 static struct qcom_icc_node qnm_a2noc_cfg = { 238 .name = "qnm_a2noc_cfg", 239 .channels = 1, 240 .buswidth = 4, 241 .num_links = 1, 242 .link_nodes = { &srvc_aggre2_noc }, 243 }; 244 245 static struct qcom_icc_node qxm_crypto = { 246 .name = "qxm_crypto", 247 .channels = 1, 248 .buswidth = 8, 249 .num_links = 1, 250 .link_nodes = { &qns_a2noc_snoc }, 251 }; 252 253 static struct qcom_icc_node qxm_ipa = { 254 .name = "qxm_ipa", 255 .channels = 1, 256 .buswidth = 8, 257 .num_links = 1, 258 .link_nodes = { &qns_a2noc_snoc }, 259 }; 260 261 static struct qcom_icc_node xm_pcie3_0 = { 262 .name = "xm_pcie3_0", 263 .channels = 1, 264 .buswidth = 8, 265 .num_links = 1, 266 .link_nodes = { &qns_pcie_mem_noc }, 267 }; 268 269 static struct qcom_icc_node xm_pcie3_1 = { 270 .name = "xm_pcie3_1", 271 .channels = 1, 272 .buswidth = 8, 273 .num_links = 1, 274 .link_nodes = { &qns_pcie_mem_noc }, 275 }; 276 277 static struct qcom_icc_node xm_qdss_etr = { 278 .name = "xm_qdss_etr", 279 .channels = 1, 280 .buswidth = 8, 281 .num_links = 1, 282 .link_nodes = { &qns_a2noc_snoc }, 283 }; 284 285 static struct qcom_icc_node xm_sdc2 = { 286 .name = "xm_sdc2", 287 .channels = 1, 288 .buswidth = 8, 289 .num_links = 1, 290 .link_nodes = { &qns_a2noc_snoc }, 291 }; 292 293 static struct qcom_icc_node xm_ufs_card = { 294 .name = "xm_ufs_card", 295 .channels = 1, 296 .buswidth = 8, 297 .num_links = 1, 298 .link_nodes = { &qns_a2noc_snoc }, 299 }; 300 301 static struct qcom_icc_node qnm_gemnoc_cnoc = { 302 .name = "qnm_gemnoc_cnoc", 303 .channels = 1, 304 .buswidth = 16, 305 .num_links = 56, 306 .link_nodes = { &qhs_ahb2phy0, 307 &qhs_ahb2phy1, 308 &qhs_aoss, 309 &qhs_apss, 310 &qhs_camera_cfg, 311 &qhs_clk_ctl, 312 &qhs_compute_cfg, 313 &qhs_cpr_cx, 314 &qhs_cpr_mmcx, 315 &qhs_cpr_mx, 316 &qhs_crypto0_cfg, 317 &qhs_cx_rdpm, 318 &qhs_dcc_cfg, 319 &qhs_display_cfg, 320 &qhs_gpuss_cfg, 321 &qhs_hwkm, 322 &qhs_imem_cfg, 323 &qhs_ipa, 324 &qhs_ipc_router, 325 &qhs_lpass_cfg, 326 &qhs_mss_cfg, 327 &qhs_mx_rdpm, 328 &qhs_pcie0_cfg, 329 &qhs_pcie1_cfg, 330 &qhs_pdm, 331 &qhs_pimem_cfg, 332 &qhs_pka_wrapper_cfg, 333 &qhs_pmu_wrapper_cfg, 334 &qhs_qdss_cfg, 335 &qhs_qspi, 336 &qhs_qup0, 337 &qhs_qup1, 338 &qhs_qup2, 339 &qhs_sdc2, 340 &qhs_sdc4, 341 &qhs_security, 342 &qhs_spss_cfg, 343 &qhs_tcsr, 344 &qhs_tlmm, 345 &qhs_ufs_card_cfg, 346 &qhs_ufs_mem_cfg, 347 &qhs_usb3_0, 348 &qhs_usb3_1, 349 &qhs_venus_cfg, 350 &qhs_vsense_ctrl_cfg, 351 &qns_a1_noc_cfg, 352 &qns_a2_noc_cfg, 353 &qns_ddrss_cfg, 354 &qns_mnoc_cfg, 355 &qns_snoc_cfg, 356 &qxs_boot_imem, 357 &qxs_imem, 358 &qxs_pimem, 359 &srvc_cnoc, 360 &xs_qdss_stm, 361 &xs_sys_tcu_cfg }, 362 }; 363 364 static struct qcom_icc_node qnm_gemnoc_pcie = { 365 .name = "qnm_gemnoc_pcie", 366 .channels = 1, 367 .buswidth = 8, 368 .num_links = 2, 369 .link_nodes = { &xs_pcie_0, 370 &xs_pcie_1 }, 371 }; 372 373 static struct qcom_icc_node xm_qdss_dap = { 374 .name = "xm_qdss_dap", 375 .channels = 1, 376 .buswidth = 8, 377 .num_links = 56, 378 .link_nodes = { &qhs_ahb2phy0, 379 &qhs_ahb2phy1, 380 &qhs_aoss, 381 &qhs_apss, 382 &qhs_camera_cfg, 383 &qhs_clk_ctl, 384 &qhs_compute_cfg, 385 &qhs_cpr_cx, 386 &qhs_cpr_mmcx, 387 &qhs_cpr_mx, 388 &qhs_crypto0_cfg, 389 &qhs_cx_rdpm, 390 &qhs_dcc_cfg, 391 &qhs_display_cfg, 392 &qhs_gpuss_cfg, 393 &qhs_hwkm, 394 &qhs_imem_cfg, 395 &qhs_ipa, 396 &qhs_ipc_router, 397 &qhs_lpass_cfg, 398 &qhs_mss_cfg, 399 &qhs_mx_rdpm, 400 &qhs_pcie0_cfg, 401 &qhs_pcie1_cfg, 402 &qhs_pdm, 403 &qhs_pimem_cfg, 404 &qhs_pka_wrapper_cfg, 405 &qhs_pmu_wrapper_cfg, 406 &qhs_qdss_cfg, 407 &qhs_qspi, 408 &qhs_qup0, 409 &qhs_qup1, 410 &qhs_qup2, 411 &qhs_sdc2, 412 &qhs_sdc4, 413 &qhs_security, 414 &qhs_spss_cfg, 415 &qhs_tcsr, 416 &qhs_tlmm, 417 &qhs_ufs_card_cfg, 418 &qhs_ufs_mem_cfg, 419 &qhs_usb3_0, 420 &qhs_usb3_1, 421 &qhs_venus_cfg, 422 &qhs_vsense_ctrl_cfg, 423 &qns_a1_noc_cfg, 424 &qns_a2_noc_cfg, 425 &qns_ddrss_cfg, 426 &qns_mnoc_cfg, 427 &qns_snoc_cfg, 428 &qxs_boot_imem, 429 &qxs_imem, 430 &qxs_pimem, 431 &srvc_cnoc, 432 &xs_qdss_stm, 433 &xs_sys_tcu_cfg }, 434 }; 435 436 static struct qcom_icc_node qnm_cnoc_dc_noc = { 437 .name = "qnm_cnoc_dc_noc", 438 .channels = 1, 439 .buswidth = 4, 440 .num_links = 2, 441 .link_nodes = { &qhs_llcc, 442 &qns_gemnoc }, 443 }; 444 445 static struct qcom_icc_node alm_gpu_tcu = { 446 .name = "alm_gpu_tcu", 447 .channels = 1, 448 .buswidth = 8, 449 .num_links = 2, 450 .link_nodes = { &qns_gem_noc_cnoc, 451 &qns_llcc }, 452 }; 453 454 static struct qcom_icc_node alm_sys_tcu = { 455 .name = "alm_sys_tcu", 456 .channels = 1, 457 .buswidth = 8, 458 .num_links = 2, 459 .link_nodes = { &qns_gem_noc_cnoc, 460 &qns_llcc }, 461 }; 462 463 static struct qcom_icc_node chm_apps = { 464 .name = "chm_apps", 465 .channels = 2, 466 .buswidth = 32, 467 .num_links = 3, 468 .link_nodes = { &qns_gem_noc_cnoc, 469 &qns_llcc, 470 &qns_pcie }, 471 }; 472 473 static struct qcom_icc_node qnm_cmpnoc = { 474 .name = "qnm_cmpnoc", 475 .channels = 2, 476 .buswidth = 32, 477 .num_links = 2, 478 .link_nodes = { &qns_gem_noc_cnoc, 479 &qns_llcc }, 480 }; 481 482 static struct qcom_icc_node qnm_gemnoc_cfg = { 483 .name = "qnm_gemnoc_cfg", 484 .channels = 1, 485 .buswidth = 4, 486 .num_links = 5, 487 .link_nodes = { &qhs_mdsp_ms_mpu_cfg, 488 &qhs_modem_ms_mpu_cfg, 489 &srvc_even_gemnoc, 490 &srvc_odd_gemnoc, 491 &srvc_sys_gemnoc }, 492 }; 493 494 static struct qcom_icc_node qnm_gpu = { 495 .name = "qnm_gpu", 496 .channels = 2, 497 .buswidth = 32, 498 .num_links = 2, 499 .link_nodes = { &qns_gem_noc_cnoc, 500 &qns_llcc }, 501 }; 502 503 static struct qcom_icc_node qnm_mnoc_hf = { 504 .name = "qnm_mnoc_hf", 505 .channels = 2, 506 .buswidth = 32, 507 .num_links = 1, 508 .link_nodes = { &qns_llcc }, 509 }; 510 511 static struct qcom_icc_node qnm_mnoc_sf = { 512 .name = "qnm_mnoc_sf", 513 .channels = 2, 514 .buswidth = 32, 515 .num_links = 2, 516 .link_nodes = { &qns_gem_noc_cnoc, 517 &qns_llcc }, 518 }; 519 520 static struct qcom_icc_node qnm_pcie = { 521 .name = "qnm_pcie", 522 .channels = 1, 523 .buswidth = 16, 524 .num_links = 2, 525 .link_nodes = { &qns_gem_noc_cnoc, 526 &qns_llcc }, 527 }; 528 529 static struct qcom_icc_node qnm_snoc_gc = { 530 .name = "qnm_snoc_gc", 531 .channels = 1, 532 .buswidth = 8, 533 .num_links = 1, 534 .link_nodes = { &qns_llcc }, 535 }; 536 537 static struct qcom_icc_node qnm_snoc_sf = { 538 .name = "qnm_snoc_sf", 539 .channels = 1, 540 .buswidth = 16, 541 .num_links = 3, 542 .link_nodes = { &qns_gem_noc_cnoc, 543 &qns_llcc, 544 &qns_pcie }, 545 }; 546 547 static struct qcom_icc_node qhm_config_noc = { 548 .name = "qhm_config_noc", 549 .channels = 1, 550 .buswidth = 4, 551 .num_links = 6, 552 .link_nodes = { &qhs_lpass_core, 553 &qhs_lpass_lpi, 554 &qhs_lpass_mpu, 555 &qhs_lpass_top, 556 &srvc_niu_aml_noc, 557 &srvc_niu_lpass_agnoc }, 558 }; 559 560 static struct qcom_icc_node llcc_mc = { 561 .name = "llcc_mc", 562 .channels = 4, 563 .buswidth = 4, 564 .num_links = 1, 565 .link_nodes = { &ebi }, 566 }; 567 568 static struct qcom_icc_node qnm_camnoc_hf = { 569 .name = "qnm_camnoc_hf", 570 .channels = 2, 571 .buswidth = 32, 572 .num_links = 1, 573 .link_nodes = { &qns_mem_noc_hf }, 574 }; 575 576 static struct qcom_icc_node qnm_camnoc_icp = { 577 .name = "qnm_camnoc_icp", 578 .channels = 1, 579 .buswidth = 8, 580 .num_links = 1, 581 .link_nodes = { &qns_mem_noc_sf }, 582 }; 583 584 static struct qcom_icc_node qnm_camnoc_sf = { 585 .name = "qnm_camnoc_sf", 586 .channels = 2, 587 .buswidth = 32, 588 .num_links = 1, 589 .link_nodes = { &qns_mem_noc_sf }, 590 }; 591 592 static struct qcom_icc_node qnm_mnoc_cfg = { 593 .name = "qnm_mnoc_cfg", 594 .channels = 1, 595 .buswidth = 4, 596 .num_links = 1, 597 .link_nodes = { &srvc_mnoc }, 598 }; 599 600 static struct qcom_icc_node qnm_video0 = { 601 .name = "qnm_video0", 602 .channels = 1, 603 .buswidth = 32, 604 .num_links = 1, 605 .link_nodes = { &qns_mem_noc_sf }, 606 }; 607 608 static struct qcom_icc_node qnm_video1 = { 609 .name = "qnm_video1", 610 .channels = 1, 611 .buswidth = 32, 612 .num_links = 1, 613 .link_nodes = { &qns_mem_noc_sf }, 614 }; 615 616 static struct qcom_icc_node qnm_video_cvp = { 617 .name = "qnm_video_cvp", 618 .channels = 1, 619 .buswidth = 32, 620 .num_links = 1, 621 .link_nodes = { &qns_mem_noc_sf }, 622 }; 623 624 static struct qcom_icc_node qxm_mdp0 = { 625 .name = "qxm_mdp0", 626 .channels = 1, 627 .buswidth = 32, 628 .num_links = 1, 629 .link_nodes = { &qns_mem_noc_hf }, 630 }; 631 632 static struct qcom_icc_node qxm_mdp1 = { 633 .name = "qxm_mdp1", 634 .channels = 1, 635 .buswidth = 32, 636 .num_links = 1, 637 .link_nodes = { &qns_mem_noc_hf }, 638 }; 639 640 static struct qcom_icc_node qxm_rot = { 641 .name = "qxm_rot", 642 .channels = 1, 643 .buswidth = 32, 644 .num_links = 1, 645 .link_nodes = { &qns_mem_noc_sf }, 646 }; 647 648 static struct qcom_icc_node qhm_nsp_noc_config = { 649 .name = "qhm_nsp_noc_config", 650 .channels = 1, 651 .buswidth = 4, 652 .num_links = 1, 653 .link_nodes = { &service_nsp_noc }, 654 }; 655 656 static struct qcom_icc_node qxm_nsp = { 657 .name = "qxm_nsp", 658 .channels = 2, 659 .buswidth = 32, 660 .num_links = 1, 661 .link_nodes = { &qns_nsp_gemnoc }, 662 }; 663 664 static struct qcom_icc_node qnm_aggre1_noc = { 665 .name = "qnm_aggre1_noc", 666 .channels = 1, 667 .buswidth = 16, 668 .num_links = 1, 669 .link_nodes = { &qns_gemnoc_sf }, 670 }; 671 672 static struct qcom_icc_node qnm_aggre2_noc = { 673 .name = "qnm_aggre2_noc", 674 .channels = 1, 675 .buswidth = 16, 676 .num_links = 1, 677 .link_nodes = { &qns_gemnoc_sf }, 678 }; 679 680 static struct qcom_icc_node qnm_snoc_cfg = { 681 .name = "qnm_snoc_cfg", 682 .channels = 1, 683 .buswidth = 4, 684 .num_links = 1, 685 .link_nodes = { &srvc_snoc }, 686 }; 687 688 static struct qcom_icc_node qxm_pimem = { 689 .name = "qxm_pimem", 690 .channels = 1, 691 .buswidth = 8, 692 .num_links = 1, 693 .link_nodes = { &qns_gemnoc_gc }, 694 }; 695 696 static struct qcom_icc_node xm_gic = { 697 .name = "xm_gic", 698 .channels = 1, 699 .buswidth = 8, 700 .num_links = 1, 701 .link_nodes = { &qns_gemnoc_gc }, 702 }; 703 704 static struct qcom_icc_node qns_a1noc_snoc = { 705 .name = "qns_a1noc_snoc", 706 .channels = 1, 707 .buswidth = 16, 708 .num_links = 1, 709 .link_nodes = { &qnm_aggre1_noc }, 710 }; 711 712 static struct qcom_icc_node srvc_aggre1_noc = { 713 .name = "srvc_aggre1_noc", 714 .channels = 1, 715 .buswidth = 4, 716 }; 717 718 static struct qcom_icc_node qns_a2noc_snoc = { 719 .name = "qns_a2noc_snoc", 720 .channels = 1, 721 .buswidth = 16, 722 .num_links = 1, 723 .link_nodes = { &qnm_aggre2_noc }, 724 }; 725 726 static struct qcom_icc_node qns_pcie_mem_noc = { 727 .name = "qns_pcie_mem_noc", 728 .channels = 1, 729 .buswidth = 16, 730 .num_links = 1, 731 .link_nodes = { &qnm_pcie }, 732 }; 733 734 static struct qcom_icc_node srvc_aggre2_noc = { 735 .name = "srvc_aggre2_noc", 736 .channels = 1, 737 .buswidth = 4, 738 }; 739 740 static struct qcom_icc_node qhs_ahb2phy0 = { 741 .name = "qhs_ahb2phy0", 742 .channels = 1, 743 .buswidth = 4, 744 }; 745 746 static struct qcom_icc_node qhs_ahb2phy1 = { 747 .name = "qhs_ahb2phy1", 748 .channels = 1, 749 .buswidth = 4, 750 }; 751 752 static struct qcom_icc_node qhs_aoss = { 753 .name = "qhs_aoss", 754 .channels = 1, 755 .buswidth = 4, 756 }; 757 758 static struct qcom_icc_node qhs_apss = { 759 .name = "qhs_apss", 760 .channels = 1, 761 .buswidth = 8, 762 }; 763 764 static struct qcom_icc_node qhs_camera_cfg = { 765 .name = "qhs_camera_cfg", 766 .channels = 1, 767 .buswidth = 4, 768 }; 769 770 static struct qcom_icc_node qhs_clk_ctl = { 771 .name = "qhs_clk_ctl", 772 .channels = 1, 773 .buswidth = 4, 774 }; 775 776 static struct qcom_icc_node qhs_compute_cfg = { 777 .name = "qhs_compute_cfg", 778 .channels = 1, 779 .buswidth = 4, 780 }; 781 782 static struct qcom_icc_node qhs_cpr_cx = { 783 .name = "qhs_cpr_cx", 784 .channels = 1, 785 .buswidth = 4, 786 }; 787 788 static struct qcom_icc_node qhs_cpr_mmcx = { 789 .name = "qhs_cpr_mmcx", 790 .channels = 1, 791 .buswidth = 4, 792 }; 793 794 static struct qcom_icc_node qhs_cpr_mx = { 795 .name = "qhs_cpr_mx", 796 .channels = 1, 797 .buswidth = 4, 798 }; 799 800 static struct qcom_icc_node qhs_crypto0_cfg = { 801 .name = "qhs_crypto0_cfg", 802 .channels = 1, 803 .buswidth = 4, 804 }; 805 806 static struct qcom_icc_node qhs_cx_rdpm = { 807 .name = "qhs_cx_rdpm", 808 .channels = 1, 809 .buswidth = 4, 810 }; 811 812 static struct qcom_icc_node qhs_dcc_cfg = { 813 .name = "qhs_dcc_cfg", 814 .channels = 1, 815 .buswidth = 4, 816 }; 817 818 static struct qcom_icc_node qhs_display_cfg = { 819 .name = "qhs_display_cfg", 820 .channels = 1, 821 .buswidth = 4, 822 }; 823 824 static struct qcom_icc_node qhs_gpuss_cfg = { 825 .name = "qhs_gpuss_cfg", 826 .channels = 1, 827 .buswidth = 8, 828 }; 829 830 static struct qcom_icc_node qhs_hwkm = { 831 .name = "qhs_hwkm", 832 .channels = 1, 833 .buswidth = 4, 834 }; 835 836 static struct qcom_icc_node qhs_imem_cfg = { 837 .name = "qhs_imem_cfg", 838 .channels = 1, 839 .buswidth = 4, 840 }; 841 842 static struct qcom_icc_node qhs_ipa = { 843 .name = "qhs_ipa", 844 .channels = 1, 845 .buswidth = 4, 846 }; 847 848 static struct qcom_icc_node qhs_ipc_router = { 849 .name = "qhs_ipc_router", 850 .channels = 1, 851 .buswidth = 4, 852 }; 853 854 static struct qcom_icc_node qhs_lpass_cfg = { 855 .name = "qhs_lpass_cfg", 856 .channels = 1, 857 .buswidth = 4, 858 .num_links = 1, 859 .link_nodes = { &qhm_config_noc }, 860 }; 861 862 static struct qcom_icc_node qhs_mss_cfg = { 863 .name = "qhs_mss_cfg", 864 .channels = 1, 865 .buswidth = 4, 866 }; 867 868 static struct qcom_icc_node qhs_mx_rdpm = { 869 .name = "qhs_mx_rdpm", 870 .channels = 1, 871 .buswidth = 4, 872 }; 873 874 static struct qcom_icc_node qhs_pcie0_cfg = { 875 .name = "qhs_pcie0_cfg", 876 .channels = 1, 877 .buswidth = 4, 878 }; 879 880 static struct qcom_icc_node qhs_pcie1_cfg = { 881 .name = "qhs_pcie1_cfg", 882 .channels = 1, 883 .buswidth = 4, 884 }; 885 886 static struct qcom_icc_node qhs_pdm = { 887 .name = "qhs_pdm", 888 .channels = 1, 889 .buswidth = 4, 890 }; 891 892 static struct qcom_icc_node qhs_pimem_cfg = { 893 .name = "qhs_pimem_cfg", 894 .channels = 1, 895 .buswidth = 4, 896 }; 897 898 static struct qcom_icc_node qhs_pka_wrapper_cfg = { 899 .name = "qhs_pka_wrapper_cfg", 900 .channels = 1, 901 .buswidth = 4, 902 }; 903 904 static struct qcom_icc_node qhs_pmu_wrapper_cfg = { 905 .name = "qhs_pmu_wrapper_cfg", 906 .channels = 1, 907 .buswidth = 4, 908 }; 909 910 static struct qcom_icc_node qhs_qdss_cfg = { 911 .name = "qhs_qdss_cfg", 912 .channels = 1, 913 .buswidth = 4, 914 }; 915 916 static struct qcom_icc_node qhs_qspi = { 917 .name = "qhs_qspi", 918 .channels = 1, 919 .buswidth = 4, 920 }; 921 922 static struct qcom_icc_node qhs_qup0 = { 923 .name = "qhs_qup0", 924 .channels = 1, 925 .buswidth = 4, 926 }; 927 928 static struct qcom_icc_node qhs_qup1 = { 929 .name = "qhs_qup1", 930 .channels = 1, 931 .buswidth = 4, 932 }; 933 934 static struct qcom_icc_node qhs_qup2 = { 935 .name = "qhs_qup2", 936 .channels = 1, 937 .buswidth = 4, 938 }; 939 940 static struct qcom_icc_node qhs_sdc2 = { 941 .name = "qhs_sdc2", 942 .channels = 1, 943 .buswidth = 4, 944 }; 945 946 static struct qcom_icc_node qhs_sdc4 = { 947 .name = "qhs_sdc4", 948 .channels = 1, 949 .buswidth = 4, 950 }; 951 952 static struct qcom_icc_node qhs_security = { 953 .name = "qhs_security", 954 .channels = 1, 955 .buswidth = 4, 956 }; 957 958 static struct qcom_icc_node qhs_spss_cfg = { 959 .name = "qhs_spss_cfg", 960 .channels = 1, 961 .buswidth = 4, 962 }; 963 964 static struct qcom_icc_node qhs_tcsr = { 965 .name = "qhs_tcsr", 966 .channels = 1, 967 .buswidth = 4, 968 }; 969 970 static struct qcom_icc_node qhs_tlmm = { 971 .name = "qhs_tlmm", 972 .channels = 1, 973 .buswidth = 4, 974 }; 975 976 static struct qcom_icc_node qhs_ufs_card_cfg = { 977 .name = "qhs_ufs_card_cfg", 978 .channels = 1, 979 .buswidth = 4, 980 }; 981 982 static struct qcom_icc_node qhs_ufs_mem_cfg = { 983 .name = "qhs_ufs_mem_cfg", 984 .channels = 1, 985 .buswidth = 4, 986 }; 987 988 static struct qcom_icc_node qhs_usb3_0 = { 989 .name = "qhs_usb3_0", 990 .channels = 1, 991 .buswidth = 4, 992 }; 993 994 static struct qcom_icc_node qhs_usb3_1 = { 995 .name = "qhs_usb3_1", 996 .channels = 1, 997 .buswidth = 4, 998 }; 999 1000 static struct qcom_icc_node qhs_venus_cfg = { 1001 .name = "qhs_venus_cfg", 1002 .channels = 1, 1003 .buswidth = 4, 1004 }; 1005 1006 static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 1007 .name = "qhs_vsense_ctrl_cfg", 1008 .channels = 1, 1009 .buswidth = 4, 1010 }; 1011 1012 static struct qcom_icc_node qns_a1_noc_cfg = { 1013 .name = "qns_a1_noc_cfg", 1014 .channels = 1, 1015 .buswidth = 4, 1016 }; 1017 1018 static struct qcom_icc_node qns_a2_noc_cfg = { 1019 .name = "qns_a2_noc_cfg", 1020 .channels = 1, 1021 .buswidth = 4, 1022 }; 1023 1024 static struct qcom_icc_node qns_ddrss_cfg = { 1025 .name = "qns_ddrss_cfg", 1026 .channels = 1, 1027 .buswidth = 4, 1028 }; 1029 1030 static struct qcom_icc_node qns_mnoc_cfg = { 1031 .name = "qns_mnoc_cfg", 1032 .channels = 1, 1033 .buswidth = 4, 1034 }; 1035 1036 static struct qcom_icc_node qns_snoc_cfg = { 1037 .name = "qns_snoc_cfg", 1038 .channels = 1, 1039 .buswidth = 4, 1040 }; 1041 1042 static struct qcom_icc_node qxs_boot_imem = { 1043 .name = "qxs_boot_imem", 1044 .channels = 1, 1045 .buswidth = 8, 1046 }; 1047 1048 static struct qcom_icc_node qxs_imem = { 1049 .name = "qxs_imem", 1050 .channels = 1, 1051 .buswidth = 8, 1052 }; 1053 1054 static struct qcom_icc_node qxs_pimem = { 1055 .name = "qxs_pimem", 1056 .channels = 1, 1057 .buswidth = 8, 1058 }; 1059 1060 static struct qcom_icc_node srvc_cnoc = { 1061 .name = "srvc_cnoc", 1062 .channels = 1, 1063 .buswidth = 4, 1064 }; 1065 1066 static struct qcom_icc_node xs_pcie_0 = { 1067 .name = "xs_pcie_0", 1068 .channels = 1, 1069 .buswidth = 8, 1070 }; 1071 1072 static struct qcom_icc_node xs_pcie_1 = { 1073 .name = "xs_pcie_1", 1074 .channels = 1, 1075 .buswidth = 8, 1076 }; 1077 1078 static struct qcom_icc_node xs_qdss_stm = { 1079 .name = "xs_qdss_stm", 1080 .channels = 1, 1081 .buswidth = 4, 1082 }; 1083 1084 static struct qcom_icc_node xs_sys_tcu_cfg = { 1085 .name = "xs_sys_tcu_cfg", 1086 .channels = 1, 1087 .buswidth = 8, 1088 }; 1089 1090 static struct qcom_icc_node qhs_llcc = { 1091 .name = "qhs_llcc", 1092 .channels = 1, 1093 .buswidth = 4, 1094 }; 1095 1096 static struct qcom_icc_node qns_gemnoc = { 1097 .name = "qns_gemnoc", 1098 .channels = 1, 1099 .buswidth = 4, 1100 }; 1101 1102 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { 1103 .name = "qhs_mdsp_ms_mpu_cfg", 1104 .channels = 1, 1105 .buswidth = 4, 1106 }; 1107 1108 static struct qcom_icc_node qhs_modem_ms_mpu_cfg = { 1109 .name = "qhs_modem_ms_mpu_cfg", 1110 .channels = 1, 1111 .buswidth = 4, 1112 }; 1113 1114 static struct qcom_icc_node qns_gem_noc_cnoc = { 1115 .name = "qns_gem_noc_cnoc", 1116 .channels = 1, 1117 .buswidth = 16, 1118 .num_links = 1, 1119 .link_nodes = { &qnm_gemnoc_cnoc }, 1120 }; 1121 1122 static struct qcom_icc_node qns_llcc = { 1123 .name = "qns_llcc", 1124 .channels = 4, 1125 .buswidth = 16, 1126 .num_links = 1, 1127 .link_nodes = { &llcc_mc }, 1128 }; 1129 1130 static struct qcom_icc_node qns_pcie = { 1131 .name = "qns_pcie", 1132 .channels = 1, 1133 .buswidth = 8, 1134 }; 1135 1136 static struct qcom_icc_node srvc_even_gemnoc = { 1137 .name = "srvc_even_gemnoc", 1138 .channels = 1, 1139 .buswidth = 4, 1140 }; 1141 1142 static struct qcom_icc_node srvc_odd_gemnoc = { 1143 .name = "srvc_odd_gemnoc", 1144 .channels = 1, 1145 .buswidth = 4, 1146 }; 1147 1148 static struct qcom_icc_node srvc_sys_gemnoc = { 1149 .name = "srvc_sys_gemnoc", 1150 .channels = 1, 1151 .buswidth = 4, 1152 }; 1153 1154 static struct qcom_icc_node qhs_lpass_core = { 1155 .name = "qhs_lpass_core", 1156 .channels = 1, 1157 .buswidth = 4, 1158 }; 1159 1160 static struct qcom_icc_node qhs_lpass_lpi = { 1161 .name = "qhs_lpass_lpi", 1162 .channels = 1, 1163 .buswidth = 4, 1164 }; 1165 1166 static struct qcom_icc_node qhs_lpass_mpu = { 1167 .name = "qhs_lpass_mpu", 1168 .channels = 1, 1169 .buswidth = 4, 1170 }; 1171 1172 static struct qcom_icc_node qhs_lpass_top = { 1173 .name = "qhs_lpass_top", 1174 .channels = 1, 1175 .buswidth = 4, 1176 }; 1177 1178 static struct qcom_icc_node srvc_niu_aml_noc = { 1179 .name = "srvc_niu_aml_noc", 1180 .channels = 1, 1181 .buswidth = 4, 1182 }; 1183 1184 static struct qcom_icc_node srvc_niu_lpass_agnoc = { 1185 .name = "srvc_niu_lpass_agnoc", 1186 .channels = 1, 1187 .buswidth = 4, 1188 }; 1189 1190 static struct qcom_icc_node ebi = { 1191 .name = "ebi", 1192 .channels = 4, 1193 .buswidth = 4, 1194 }; 1195 1196 static struct qcom_icc_node qns_mem_noc_hf = { 1197 .name = "qns_mem_noc_hf", 1198 .channels = 2, 1199 .buswidth = 32, 1200 .num_links = 1, 1201 .link_nodes = { &qnm_mnoc_hf }, 1202 }; 1203 1204 static struct qcom_icc_node qns_mem_noc_sf = { 1205 .name = "qns_mem_noc_sf", 1206 .channels = 2, 1207 .buswidth = 32, 1208 .num_links = 1, 1209 .link_nodes = { &qnm_mnoc_sf }, 1210 }; 1211 1212 static struct qcom_icc_node srvc_mnoc = { 1213 .name = "srvc_mnoc", 1214 .channels = 1, 1215 .buswidth = 4, 1216 }; 1217 1218 static struct qcom_icc_node qns_nsp_gemnoc = { 1219 .name = "qns_nsp_gemnoc", 1220 .channels = 2, 1221 .buswidth = 32, 1222 .num_links = 1, 1223 .link_nodes = { &qnm_cmpnoc }, 1224 }; 1225 1226 static struct qcom_icc_node service_nsp_noc = { 1227 .name = "service_nsp_noc", 1228 .channels = 1, 1229 .buswidth = 4, 1230 }; 1231 1232 static struct qcom_icc_node qns_gemnoc_gc = { 1233 .name = "qns_gemnoc_gc", 1234 .channels = 1, 1235 .buswidth = 8, 1236 .num_links = 1, 1237 .link_nodes = { &qnm_snoc_gc }, 1238 }; 1239 1240 static struct qcom_icc_node qns_gemnoc_sf = { 1241 .name = "qns_gemnoc_sf", 1242 .channels = 1, 1243 .buswidth = 16, 1244 .num_links = 1, 1245 .link_nodes = { &qnm_snoc_sf }, 1246 }; 1247 1248 static struct qcom_icc_node srvc_snoc = { 1249 .name = "srvc_snoc", 1250 .channels = 1, 1251 .buswidth = 4, 1252 }; 1253 1254 static struct qcom_icc_bcm bcm_acv = { 1255 .name = "ACV", 1256 .enable_mask = BIT(3), 1257 .keepalive = false, 1258 .num_nodes = 1, 1259 .nodes = { &ebi }, 1260 }; 1261 1262 static struct qcom_icc_bcm bcm_ce0 = { 1263 .name = "CE0", 1264 .keepalive = false, 1265 .num_nodes = 1, 1266 .nodes = { &qxm_crypto }, 1267 }; 1268 1269 static struct qcom_icc_bcm bcm_cn0 = { 1270 .name = "CN0", 1271 .keepalive = true, 1272 .num_nodes = 2, 1273 .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie }, 1274 }; 1275 1276 static struct qcom_icc_bcm bcm_cn1 = { 1277 .name = "CN1", 1278 .keepalive = false, 1279 .num_nodes = 47, 1280 .nodes = { &xm_qdss_dap, 1281 &qhs_ahb2phy0, 1282 &qhs_ahb2phy1, 1283 &qhs_aoss, 1284 &qhs_apss, 1285 &qhs_camera_cfg, 1286 &qhs_clk_ctl, 1287 &qhs_compute_cfg, 1288 &qhs_cpr_cx, 1289 &qhs_cpr_mmcx, 1290 &qhs_cpr_mx, 1291 &qhs_crypto0_cfg, 1292 &qhs_cx_rdpm, 1293 &qhs_dcc_cfg, 1294 &qhs_display_cfg, 1295 &qhs_gpuss_cfg, 1296 &qhs_hwkm, 1297 &qhs_imem_cfg, 1298 &qhs_ipa, 1299 &qhs_ipc_router, 1300 &qhs_mss_cfg, 1301 &qhs_mx_rdpm, 1302 &qhs_pcie0_cfg, 1303 &qhs_pcie1_cfg, 1304 &qhs_pimem_cfg, 1305 &qhs_pka_wrapper_cfg, 1306 &qhs_pmu_wrapper_cfg, 1307 &qhs_qdss_cfg, 1308 &qhs_qup0, 1309 &qhs_qup1, 1310 &qhs_qup2, 1311 &qhs_security, 1312 &qhs_spss_cfg, 1313 &qhs_tcsr, 1314 &qhs_tlmm, 1315 &qhs_ufs_card_cfg, 1316 &qhs_ufs_mem_cfg, 1317 &qhs_usb3_0, 1318 &qhs_usb3_1, 1319 &qhs_venus_cfg, 1320 &qhs_vsense_ctrl_cfg, 1321 &qns_a1_noc_cfg, 1322 &qns_a2_noc_cfg, 1323 &qns_ddrss_cfg, 1324 &qns_mnoc_cfg, 1325 &qns_snoc_cfg, 1326 &srvc_cnoc 1327 }, 1328 }; 1329 1330 static struct qcom_icc_bcm bcm_cn2 = { 1331 .name = "CN2", 1332 .keepalive = false, 1333 .num_nodes = 5, 1334 .nodes = { &qhs_lpass_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc2, &qhs_sdc4 }, 1335 }; 1336 1337 static struct qcom_icc_bcm bcm_co0 = { 1338 .name = "CO0", 1339 .keepalive = false, 1340 .num_nodes = 1, 1341 .nodes = { &qns_nsp_gemnoc }, 1342 }; 1343 1344 static struct qcom_icc_bcm bcm_co3 = { 1345 .name = "CO3", 1346 .keepalive = false, 1347 .num_nodes = 1, 1348 .nodes = { &qxm_nsp }, 1349 }; 1350 1351 static struct qcom_icc_bcm bcm_mc0 = { 1352 .name = "MC0", 1353 .keepalive = true, 1354 .num_nodes = 1, 1355 .nodes = { &ebi }, 1356 }; 1357 1358 static struct qcom_icc_bcm bcm_mm0 = { 1359 .name = "MM0", 1360 .keepalive = true, 1361 .num_nodes = 1, 1362 .nodes = { &qns_mem_noc_hf }, 1363 }; 1364 1365 static struct qcom_icc_bcm bcm_mm1 = { 1366 .name = "MM1", 1367 .keepalive = false, 1368 .num_nodes = 3, 1369 .nodes = { &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1 }, 1370 }; 1371 1372 static struct qcom_icc_bcm bcm_mm4 = { 1373 .name = "MM4", 1374 .keepalive = false, 1375 .num_nodes = 1, 1376 .nodes = { &qns_mem_noc_sf }, 1377 }; 1378 1379 static struct qcom_icc_bcm bcm_mm5 = { 1380 .name = "MM5", 1381 .keepalive = false, 1382 .num_nodes = 6, 1383 .nodes = { &qnm_camnoc_icp, 1384 &qnm_camnoc_sf, 1385 &qnm_video0, 1386 &qnm_video1, 1387 &qnm_video_cvp, 1388 &qxm_rot 1389 }, 1390 }; 1391 1392 static struct qcom_icc_bcm bcm_sh0 = { 1393 .name = "SH0", 1394 .keepalive = true, 1395 .num_nodes = 1, 1396 .nodes = { &qns_llcc }, 1397 }; 1398 1399 static struct qcom_icc_bcm bcm_sh2 = { 1400 .name = "SH2", 1401 .keepalive = false, 1402 .num_nodes = 2, 1403 .nodes = { &alm_gpu_tcu, &alm_sys_tcu }, 1404 }; 1405 1406 static struct qcom_icc_bcm bcm_sh3 = { 1407 .name = "SH3", 1408 .keepalive = false, 1409 .num_nodes = 1, 1410 .nodes = { &qnm_cmpnoc }, 1411 }; 1412 1413 static struct qcom_icc_bcm bcm_sh4 = { 1414 .name = "SH4", 1415 .keepalive = false, 1416 .num_nodes = 1, 1417 .nodes = { &chm_apps }, 1418 }; 1419 1420 static struct qcom_icc_bcm bcm_sn0 = { 1421 .name = "SN0", 1422 .keepalive = true, 1423 .num_nodes = 1, 1424 .nodes = { &qns_gemnoc_sf }, 1425 }; 1426 1427 static struct qcom_icc_bcm bcm_sn2 = { 1428 .name = "SN2", 1429 .keepalive = false, 1430 .num_nodes = 1, 1431 .nodes = { &qns_gemnoc_gc }, 1432 }; 1433 1434 static struct qcom_icc_bcm bcm_sn3 = { 1435 .name = "SN3", 1436 .keepalive = false, 1437 .num_nodes = 1, 1438 .nodes = { &qxs_pimem }, 1439 }; 1440 1441 static struct qcom_icc_bcm bcm_sn4 = { 1442 .name = "SN4", 1443 .keepalive = false, 1444 .num_nodes = 1, 1445 .nodes = { &xs_qdss_stm }, 1446 }; 1447 1448 static struct qcom_icc_bcm bcm_sn5 = { 1449 .name = "SN5", 1450 .keepalive = false, 1451 .num_nodes = 1, 1452 .nodes = { &xm_pcie3_0 }, 1453 }; 1454 1455 static struct qcom_icc_bcm bcm_sn6 = { 1456 .name = "SN6", 1457 .keepalive = false, 1458 .num_nodes = 1, 1459 .nodes = { &xm_pcie3_1 }, 1460 }; 1461 1462 static struct qcom_icc_bcm bcm_sn7 = { 1463 .name = "SN7", 1464 .keepalive = false, 1465 .num_nodes = 1, 1466 .nodes = { &qnm_aggre1_noc }, 1467 }; 1468 1469 static struct qcom_icc_bcm bcm_sn8 = { 1470 .name = "SN8", 1471 .keepalive = false, 1472 .num_nodes = 1, 1473 .nodes = { &qnm_aggre2_noc }, 1474 }; 1475 1476 static struct qcom_icc_bcm bcm_sn14 = { 1477 .name = "SN14", 1478 .keepalive = false, 1479 .num_nodes = 1, 1480 .nodes = { &qns_pcie_mem_noc }, 1481 }; 1482 1483 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 1484 }; 1485 1486 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1487 [MASTER_QSPI_0] = &qhm_qspi, 1488 [MASTER_QUP_1] = &qhm_qup1, 1489 [MASTER_A1NOC_CFG] = &qnm_a1noc_cfg, 1490 [MASTER_SDCC_4] = &xm_sdc4, 1491 [MASTER_UFS_MEM] = &xm_ufs_mem, 1492 [MASTER_USB3_0] = &xm_usb3_0, 1493 [MASTER_USB3_1] = &xm_usb3_1, 1494 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, 1495 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, 1496 }; 1497 1498 static const struct qcom_icc_desc sm8350_aggre1_noc = { 1499 .nodes = aggre1_noc_nodes, 1500 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 1501 .bcms = aggre1_noc_bcms, 1502 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 1503 }; 1504 1505 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 1506 &bcm_ce0, 1507 &bcm_sn5, 1508 &bcm_sn6, 1509 &bcm_sn14, 1510 }; 1511 1512 static struct qcom_icc_node * const aggre2_noc_nodes[] = { 1513 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 1514 [MASTER_QUP_0] = &qhm_qup0, 1515 [MASTER_QUP_2] = &qhm_qup2, 1516 [MASTER_A2NOC_CFG] = &qnm_a2noc_cfg, 1517 [MASTER_CRYPTO] = &qxm_crypto, 1518 [MASTER_IPA] = &qxm_ipa, 1519 [MASTER_PCIE_0] = &xm_pcie3_0, 1520 [MASTER_PCIE_1] = &xm_pcie3_1, 1521 [MASTER_QDSS_ETR] = &xm_qdss_etr, 1522 [MASTER_SDCC_2] = &xm_sdc2, 1523 [MASTER_UFS_CARD] = &xm_ufs_card, 1524 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, 1525 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, 1526 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, 1527 }; 1528 1529 static const struct qcom_icc_desc sm8350_aggre2_noc = { 1530 .nodes = aggre2_noc_nodes, 1531 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 1532 .bcms = aggre2_noc_bcms, 1533 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 1534 }; 1535 1536 static struct qcom_icc_bcm * const config_noc_bcms[] = { 1537 &bcm_cn0, 1538 &bcm_cn1, 1539 &bcm_cn2, 1540 &bcm_sn3, 1541 &bcm_sn4, 1542 }; 1543 1544 static struct qcom_icc_node * const config_noc_nodes[] = { 1545 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, 1546 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, 1547 [MASTER_QDSS_DAP] = &xm_qdss_dap, 1548 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, 1549 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1, 1550 [SLAVE_AOSS] = &qhs_aoss, 1551 [SLAVE_APPSS] = &qhs_apss, 1552 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 1553 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1554 [SLAVE_CDSP_CFG] = &qhs_compute_cfg, 1555 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 1556 [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx, 1557 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, 1558 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1559 [SLAVE_CX_RDPM] = &qhs_cx_rdpm, 1560 [SLAVE_DCC_CFG] = &qhs_dcc_cfg, 1561 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 1562 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, 1563 [SLAVE_HWKM] = &qhs_hwkm, 1564 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1565 [SLAVE_IPA_CFG] = &qhs_ipa, 1566 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, 1567 [SLAVE_LPASS] = &qhs_lpass_cfg, 1568 [SLAVE_CNOC_MSS] = &qhs_mss_cfg, 1569 [SLAVE_MX_RDPM] = &qhs_mx_rdpm, 1570 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, 1571 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, 1572 [SLAVE_PDM] = &qhs_pdm, 1573 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 1574 [SLAVE_PKA_WRAPPER_CFG] = &qhs_pka_wrapper_cfg, 1575 [SLAVE_PMU_WRAPPER_CFG] = &qhs_pmu_wrapper_cfg, 1576 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1577 [SLAVE_QSPI_0] = &qhs_qspi, 1578 [SLAVE_QUP_0] = &qhs_qup0, 1579 [SLAVE_QUP_1] = &qhs_qup1, 1580 [SLAVE_QUP_2] = &qhs_qup2, 1581 [SLAVE_SDCC_2] = &qhs_sdc2, 1582 [SLAVE_SDCC_4] = &qhs_sdc4, 1583 [SLAVE_SECURITY] = &qhs_security, 1584 [SLAVE_SPSS_CFG] = &qhs_spss_cfg, 1585 [SLAVE_TCSR] = &qhs_tcsr, 1586 [SLAVE_TLMM] = &qhs_tlmm, 1587 [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg, 1588 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 1589 [SLAVE_USB3_0] = &qhs_usb3_0, 1590 [SLAVE_USB3_1] = &qhs_usb3_1, 1591 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1592 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 1593 [SLAVE_A1NOC_CFG] = &qns_a1_noc_cfg, 1594 [SLAVE_A2NOC_CFG] = &qns_a2_noc_cfg, 1595 [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg, 1596 [SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg, 1597 [SLAVE_SNOC_CFG] = &qns_snoc_cfg, 1598 [SLAVE_BOOT_IMEM] = &qxs_boot_imem, 1599 [SLAVE_IMEM] = &qxs_imem, 1600 [SLAVE_PIMEM] = &qxs_pimem, 1601 [SLAVE_SERVICE_CNOC] = &srvc_cnoc, 1602 [SLAVE_PCIE_0] = &xs_pcie_0, 1603 [SLAVE_PCIE_1] = &xs_pcie_1, 1604 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1605 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1606 }; 1607 1608 static const struct qcom_icc_desc sm8350_config_noc = { 1609 .nodes = config_noc_nodes, 1610 .num_nodes = ARRAY_SIZE(config_noc_nodes), 1611 .bcms = config_noc_bcms, 1612 .num_bcms = ARRAY_SIZE(config_noc_bcms), 1613 }; 1614 1615 static struct qcom_icc_bcm * const dc_noc_bcms[] = { 1616 }; 1617 1618 static struct qcom_icc_node * const dc_noc_nodes[] = { 1619 [MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc, 1620 [SLAVE_LLCC_CFG] = &qhs_llcc, 1621 [SLAVE_GEM_NOC_CFG] = &qns_gemnoc, 1622 }; 1623 1624 static const struct qcom_icc_desc sm8350_dc_noc = { 1625 .nodes = dc_noc_nodes, 1626 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 1627 .bcms = dc_noc_bcms, 1628 .num_bcms = ARRAY_SIZE(dc_noc_bcms), 1629 }; 1630 1631 static struct qcom_icc_bcm * const gem_noc_bcms[] = { 1632 &bcm_sh0, 1633 &bcm_sh2, 1634 &bcm_sh3, 1635 &bcm_sh4, 1636 }; 1637 1638 static struct qcom_icc_node * const gem_noc_nodes[] = { 1639 [MASTER_GPU_TCU] = &alm_gpu_tcu, 1640 [MASTER_SYS_TCU] = &alm_sys_tcu, 1641 [MASTER_APPSS_PROC] = &chm_apps, 1642 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc, 1643 [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg, 1644 [MASTER_GFX3D] = &qnm_gpu, 1645 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 1646 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 1647 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, 1648 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 1649 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 1650 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg, 1651 [SLAVE_MCDMA_MS_MPU_CFG] = &qhs_modem_ms_mpu_cfg, 1652 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, 1653 [SLAVE_LLCC] = &qns_llcc, 1654 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, 1655 [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc, 1656 [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc, 1657 [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc, 1658 }; 1659 1660 static const struct qcom_icc_desc sm8350_gem_noc = { 1661 .nodes = gem_noc_nodes, 1662 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 1663 .bcms = gem_noc_bcms, 1664 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 1665 }; 1666 1667 static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = { 1668 }; 1669 1670 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { 1671 [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc, 1672 [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core, 1673 [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi, 1674 [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu, 1675 [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top, 1676 [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc, 1677 [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, 1678 }; 1679 1680 static const struct qcom_icc_desc sm8350_lpass_ag_noc = { 1681 .nodes = lpass_ag_noc_nodes, 1682 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), 1683 .bcms = lpass_ag_noc_bcms, 1684 .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms), 1685 }; 1686 1687 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 1688 &bcm_acv, 1689 &bcm_mc0, 1690 }; 1691 1692 static struct qcom_icc_node * const mc_virt_nodes[] = { 1693 [MASTER_LLCC] = &llcc_mc, 1694 [SLAVE_EBI1] = &ebi, 1695 }; 1696 1697 static const struct qcom_icc_desc sm8350_mc_virt = { 1698 .nodes = mc_virt_nodes, 1699 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 1700 .bcms = mc_virt_bcms, 1701 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 1702 }; 1703 1704 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 1705 &bcm_mm0, 1706 &bcm_mm1, 1707 &bcm_mm4, 1708 &bcm_mm5, 1709 }; 1710 1711 static struct qcom_icc_node * const mmss_noc_nodes[] = { 1712 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, 1713 [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp, 1714 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, 1715 [MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg, 1716 [MASTER_VIDEO_P0] = &qnm_video0, 1717 [MASTER_VIDEO_P1] = &qnm_video1, 1718 [MASTER_VIDEO_PROC] = &qnm_video_cvp, 1719 [MASTER_MDP0] = &qxm_mdp0, 1720 [MASTER_MDP1] = &qxm_mdp1, 1721 [MASTER_ROTATOR] = &qxm_rot, 1722 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 1723 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, 1724 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 1725 }; 1726 1727 static const struct qcom_icc_desc sm8350_mmss_noc = { 1728 .nodes = mmss_noc_nodes, 1729 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 1730 .bcms = mmss_noc_bcms, 1731 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 1732 }; 1733 1734 static struct qcom_icc_bcm * const nsp_noc_bcms[] = { 1735 &bcm_co0, 1736 &bcm_co3, 1737 }; 1738 1739 static struct qcom_icc_node * const nsp_noc_nodes[] = { 1740 [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config, 1741 [MASTER_CDSP_PROC] = &qxm_nsp, 1742 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, 1743 [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, 1744 }; 1745 1746 static const struct qcom_icc_desc sm8350_compute_noc = { 1747 .nodes = nsp_noc_nodes, 1748 .num_nodes = ARRAY_SIZE(nsp_noc_nodes), 1749 .bcms = nsp_noc_bcms, 1750 .num_bcms = ARRAY_SIZE(nsp_noc_bcms), 1751 }; 1752 1753 static struct qcom_icc_bcm * const system_noc_bcms[] = { 1754 &bcm_sn0, 1755 &bcm_sn2, 1756 &bcm_sn7, 1757 &bcm_sn8, 1758 }; 1759 1760 static struct qcom_icc_node * const system_noc_nodes[] = { 1761 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, 1762 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, 1763 [MASTER_SNOC_CFG] = &qnm_snoc_cfg, 1764 [MASTER_PIMEM] = &qxm_pimem, 1765 [MASTER_GIC] = &xm_gic, 1766 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, 1767 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 1768 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 1769 }; 1770 1771 static const struct qcom_icc_desc sm8350_system_noc = { 1772 .nodes = system_noc_nodes, 1773 .num_nodes = ARRAY_SIZE(system_noc_nodes), 1774 .bcms = system_noc_bcms, 1775 .num_bcms = ARRAY_SIZE(system_noc_bcms), 1776 }; 1777 1778 static const struct of_device_id qnoc_of_match[] = { 1779 { .compatible = "qcom,sm8350-aggre1-noc", .data = &sm8350_aggre1_noc}, 1780 { .compatible = "qcom,sm8350-aggre2-noc", .data = &sm8350_aggre2_noc}, 1781 { .compatible = "qcom,sm8350-config-noc", .data = &sm8350_config_noc}, 1782 { .compatible = "qcom,sm8350-dc-noc", .data = &sm8350_dc_noc}, 1783 { .compatible = "qcom,sm8350-gem-noc", .data = &sm8350_gem_noc}, 1784 { .compatible = "qcom,sm8350-lpass-ag-noc", .data = &sm8350_lpass_ag_noc}, 1785 { .compatible = "qcom,sm8350-mc-virt", .data = &sm8350_mc_virt}, 1786 { .compatible = "qcom,sm8350-mmss-noc", .data = &sm8350_mmss_noc}, 1787 { .compatible = "qcom,sm8350-compute-noc", .data = &sm8350_compute_noc}, 1788 { .compatible = "qcom,sm8350-system-noc", .data = &sm8350_system_noc}, 1789 { } 1790 }; 1791 MODULE_DEVICE_TABLE(of, qnoc_of_match); 1792 1793 static struct platform_driver qnoc_driver = { 1794 .probe = qcom_icc_rpmh_probe, 1795 .remove = qcom_icc_rpmh_remove, 1796 .driver = { 1797 .name = "qnoc-sm8350", 1798 .of_match_table = qnoc_of_match, 1799 .sync_state = icc_sync_state, 1800 }, 1801 }; 1802 module_platform_driver(qnoc_driver); 1803 1804 MODULE_DESCRIPTION("SM8350 NoC driver"); 1805 MODULE_LICENSE("GPL v2"); 1806