16df5b349SJonathan Marek /* SPDX-License-Identifier: GPL-2.0 */ 26df5b349SJonathan Marek /* 36df5b349SJonathan Marek * Qualcomm #define SM8250 interconnect IDs 46df5b349SJonathan Marek * 56df5b349SJonathan Marek * Copyright (c) 2020, The Linux Foundation. All rights reserved. 66df5b349SJonathan Marek */ 76df5b349SJonathan Marek 86df5b349SJonathan Marek #ifndef __DRIVERS_INTERCONNECT_QCOM_SM8250_H 96df5b349SJonathan Marek #define __DRIVERS_INTERCONNECT_QCOM_SM8250_H 106df5b349SJonathan Marek 116df5b349SJonathan Marek #define SM8250_A1NOC_SNOC_MAS 0 126df5b349SJonathan Marek #define SM8250_A1NOC_SNOC_SLV 1 136df5b349SJonathan Marek #define SM8250_A2NOC_SNOC_MAS 2 146df5b349SJonathan Marek #define SM8250_A2NOC_SNOC_SLV 3 156df5b349SJonathan Marek #define SM8250_MASTER_A1NOC_CFG 4 166df5b349SJonathan Marek #define SM8250_MASTER_A2NOC_CFG 5 176df5b349SJonathan Marek #define SM8250_MASTER_AMPSS_M0 6 186df5b349SJonathan Marek #define SM8250_MASTER_ANOC_PCIE_GEM_NOC 7 196df5b349SJonathan Marek #define SM8250_MASTER_CAMNOC_HF 8 206df5b349SJonathan Marek #define SM8250_MASTER_CAMNOC_ICP 9 216df5b349SJonathan Marek #define SM8250_MASTER_CAMNOC_SF 10 226df5b349SJonathan Marek #define SM8250_MASTER_CNOC_A2NOC 11 236df5b349SJonathan Marek #define SM8250_MASTER_CNOC_DC_NOC 12 246df5b349SJonathan Marek #define SM8250_MASTER_CNOC_MNOC_CFG 13 256df5b349SJonathan Marek #define SM8250_MASTER_COMPUTE_NOC 14 266df5b349SJonathan Marek #define SM8250_MASTER_CRYPTO_CORE_0 15 276df5b349SJonathan Marek #define SM8250_MASTER_GEM_NOC_CFG 16 286df5b349SJonathan Marek #define SM8250_MASTER_GEM_NOC_PCIE_SNOC 17 296df5b349SJonathan Marek #define SM8250_MASTER_GEM_NOC_SNOC 18 306df5b349SJonathan Marek #define SM8250_MASTER_GIC 19 316df5b349SJonathan Marek #define SM8250_MASTER_GPU_TCU 20 326df5b349SJonathan Marek #define SM8250_MASTER_GRAPHICS_3D 21 336df5b349SJonathan Marek #define SM8250_MASTER_IPA 22 3410d13cb5SDmitry Baryshkov /* 23 was used by MASTER_IPA_CORE, now represented as RPMh clock */ 356df5b349SJonathan Marek #define SM8250_MASTER_LLCC 24 366df5b349SJonathan Marek #define SM8250_MASTER_MDP_PORT0 25 376df5b349SJonathan Marek #define SM8250_MASTER_MDP_PORT1 26 386df5b349SJonathan Marek #define SM8250_MASTER_MNOC_HF_MEM_NOC 27 396df5b349SJonathan Marek #define SM8250_MASTER_MNOC_SF_MEM_NOC 28 406df5b349SJonathan Marek #define SM8250_MASTER_NPU 29 416df5b349SJonathan Marek #define SM8250_MASTER_NPU_CDP 30 426df5b349SJonathan Marek #define SM8250_MASTER_NPU_NOC_CFG 31 436df5b349SJonathan Marek #define SM8250_MASTER_NPU_SYS 32 446df5b349SJonathan Marek #define SM8250_MASTER_PCIE 33 456df5b349SJonathan Marek #define SM8250_MASTER_PCIE_1 34 466df5b349SJonathan Marek #define SM8250_MASTER_PCIE_2 35 476df5b349SJonathan Marek #define SM8250_MASTER_PIMEM 36 486df5b349SJonathan Marek #define SM8250_MASTER_QDSS_BAM 37 496df5b349SJonathan Marek #define SM8250_MASTER_QDSS_DAP 38 506df5b349SJonathan Marek #define SM8250_MASTER_QDSS_ETR 39 516df5b349SJonathan Marek #define SM8250_MASTER_QSPI_0 40 526df5b349SJonathan Marek #define SM8250_MASTER_QUP_0 41 536df5b349SJonathan Marek #define SM8250_MASTER_QUP_1 42 546df5b349SJonathan Marek #define SM8250_MASTER_QUP_2 43 556df5b349SJonathan Marek #define SM8250_MASTER_ROTATOR 44 566df5b349SJonathan Marek #define SM8250_MASTER_SDCC_2 45 576df5b349SJonathan Marek #define SM8250_MASTER_SDCC_4 46 586df5b349SJonathan Marek #define SM8250_MASTER_SNOC_CFG 47 596df5b349SJonathan Marek #define SM8250_MASTER_SNOC_GC_MEM_NOC 48 606df5b349SJonathan Marek #define SM8250_MASTER_SNOC_SF_MEM_NOC 49 616df5b349SJonathan Marek #define SM8250_MASTER_SYS_TCU 50 626df5b349SJonathan Marek #define SM8250_MASTER_TSIF 51 636df5b349SJonathan Marek #define SM8250_MASTER_UFS_CARD 52 646df5b349SJonathan Marek #define SM8250_MASTER_UFS_MEM 53 656df5b349SJonathan Marek #define SM8250_MASTER_USB3 54 666df5b349SJonathan Marek #define SM8250_MASTER_USB3_1 55 676df5b349SJonathan Marek #define SM8250_MASTER_VIDEO_P0 56 686df5b349SJonathan Marek #define SM8250_MASTER_VIDEO_P1 57 696df5b349SJonathan Marek #define SM8250_MASTER_VIDEO_PROC 58 706df5b349SJonathan Marek #define SM8250_SLAVE_A1NOC_CFG 59 716df5b349SJonathan Marek #define SM8250_SLAVE_A2NOC_CFG 60 726df5b349SJonathan Marek #define SM8250_SLAVE_AHB2PHY_NORTH 61 736df5b349SJonathan Marek #define SM8250_SLAVE_AHB2PHY_SOUTH 62 746df5b349SJonathan Marek #define SM8250_SLAVE_ANOC_PCIE_GEM_NOC 63 756df5b349SJonathan Marek #define SM8250_SLAVE_ANOC_PCIE_GEM_NOC_1 64 766df5b349SJonathan Marek #define SM8250_SLAVE_AOSS 65 776df5b349SJonathan Marek #define SM8250_SLAVE_APPSS 66 786df5b349SJonathan Marek #define SM8250_SLAVE_CAMERA_CFG 67 796df5b349SJonathan Marek #define SM8250_SLAVE_CDSP_CFG 68 806df5b349SJonathan Marek #define SM8250_SLAVE_CDSP_MEM_NOC 69 816df5b349SJonathan Marek #define SM8250_SLAVE_CLK_CTL 70 826df5b349SJonathan Marek #define SM8250_SLAVE_CNOC_A2NOC 71 836df5b349SJonathan Marek #define SM8250_SLAVE_CNOC_DDRSS 72 846df5b349SJonathan Marek #define SM8250_SLAVE_CNOC_MNOC_CFG 73 856df5b349SJonathan Marek #define SM8250_SLAVE_CRYPTO_0_CFG 74 866df5b349SJonathan Marek #define SM8250_SLAVE_CX_RDPM 75 876df5b349SJonathan Marek #define SM8250_SLAVE_DCC_CFG 76 886df5b349SJonathan Marek #define SM8250_SLAVE_DISPLAY_CFG 77 896df5b349SJonathan Marek #define SM8250_SLAVE_EBI_CH0 78 906df5b349SJonathan Marek #define SM8250_SLAVE_GEM_NOC_CFG 79 916df5b349SJonathan Marek #define SM8250_SLAVE_GEM_NOC_SNOC 80 926df5b349SJonathan Marek #define SM8250_SLAVE_GRAPHICS_3D_CFG 81 936df5b349SJonathan Marek #define SM8250_SLAVE_IMEM_CFG 82 946df5b349SJonathan Marek #define SM8250_SLAVE_IPA_CFG 83 9510d13cb5SDmitry Baryshkov /* 84 was used by SLAVE_IPA_CORE, now represented as RPMh clock */ 966df5b349SJonathan Marek #define SM8250_SLAVE_IPC_ROUTER_CFG 85 976df5b349SJonathan Marek #define SM8250_SLAVE_ISENSE_CFG 86 986df5b349SJonathan Marek #define SM8250_SLAVE_LLCC 87 996df5b349SJonathan Marek #define SM8250_SLAVE_LLCC_CFG 88 1006df5b349SJonathan Marek #define SM8250_SLAVE_LPASS 89 1016df5b349SJonathan Marek #define SM8250_SLAVE_MEM_NOC_PCIE_SNOC 90 1026df5b349SJonathan Marek #define SM8250_SLAVE_MNOC_HF_MEM_NOC 91 1036df5b349SJonathan Marek #define SM8250_SLAVE_MNOC_SF_MEM_NOC 92 1046df5b349SJonathan Marek #define SM8250_SLAVE_NPU_CAL_DP0 93 1056df5b349SJonathan Marek #define SM8250_SLAVE_NPU_CAL_DP1 94 1066df5b349SJonathan Marek #define SM8250_SLAVE_NPU_CFG 95 1076df5b349SJonathan Marek #define SM8250_SLAVE_NPU_COMPUTE_NOC 96 1086df5b349SJonathan Marek #define SM8250_SLAVE_NPU_CP 97 1096df5b349SJonathan Marek #define SM8250_SLAVE_NPU_DPM 98 1106df5b349SJonathan Marek #define SM8250_SLAVE_NPU_INT_DMA_BWMON_CFG 99 1116df5b349SJonathan Marek #define SM8250_SLAVE_NPU_LLM_CFG 100 1126df5b349SJonathan Marek #define SM8250_SLAVE_NPU_TCM 101 1136df5b349SJonathan Marek #define SM8250_SLAVE_OCIMEM 102 1146df5b349SJonathan Marek #define SM8250_SLAVE_PCIE_0 103 1156df5b349SJonathan Marek #define SM8250_SLAVE_PCIE_0_CFG 104 1166df5b349SJonathan Marek #define SM8250_SLAVE_PCIE_1 105 1176df5b349SJonathan Marek #define SM8250_SLAVE_PCIE_1_CFG 106 1186df5b349SJonathan Marek #define SM8250_SLAVE_PCIE_2 107 1196df5b349SJonathan Marek #define SM8250_SLAVE_PCIE_2_CFG 108 1206df5b349SJonathan Marek #define SM8250_SLAVE_PDM 109 1216df5b349SJonathan Marek #define SM8250_SLAVE_PIMEM 110 1226df5b349SJonathan Marek #define SM8250_SLAVE_PIMEM_CFG 111 1236df5b349SJonathan Marek #define SM8250_SLAVE_PRNG 112 1246df5b349SJonathan Marek #define SM8250_SLAVE_QDSS_CFG 113 1256df5b349SJonathan Marek #define SM8250_SLAVE_QDSS_STM 114 1266df5b349SJonathan Marek #define SM8250_SLAVE_QSPI_0 115 1276df5b349SJonathan Marek #define SM8250_SLAVE_QUP_0 116 1286df5b349SJonathan Marek #define SM8250_SLAVE_QUP_1 117 1296df5b349SJonathan Marek #define SM8250_SLAVE_QUP_2 118 1306df5b349SJonathan Marek #define SM8250_SLAVE_RBCPR_CX_CFG 119 1316df5b349SJonathan Marek #define SM8250_SLAVE_RBCPR_MMCX_CFG 120 1326df5b349SJonathan Marek #define SM8250_SLAVE_RBCPR_MX_CFG 121 1336df5b349SJonathan Marek #define SM8250_SLAVE_SDCC_2 122 1346df5b349SJonathan Marek #define SM8250_SLAVE_SDCC_4 123 1356df5b349SJonathan Marek #define SM8250_SLAVE_SERVICE_A1NOC 124 1366df5b349SJonathan Marek #define SM8250_SLAVE_SERVICE_A2NOC 125 1376df5b349SJonathan Marek #define SM8250_SLAVE_SERVICE_CNOC 126 1386df5b349SJonathan Marek #define SM8250_SLAVE_SERVICE_GEM_NOC 127 1396df5b349SJonathan Marek #define SM8250_SLAVE_SERVICE_GEM_NOC_1 128 1406df5b349SJonathan Marek #define SM8250_SLAVE_SERVICE_GEM_NOC_2 129 1416df5b349SJonathan Marek #define SM8250_SLAVE_SERVICE_MNOC 130 1426df5b349SJonathan Marek #define SM8250_SLAVE_SERVICE_NPU_NOC 131 1436df5b349SJonathan Marek #define SM8250_SLAVE_SERVICE_SNOC 132 1446df5b349SJonathan Marek #define SM8250_SLAVE_SNOC_CFG 133 1456df5b349SJonathan Marek #define SM8250_SLAVE_SNOC_GEM_NOC_GC 134 1466df5b349SJonathan Marek #define SM8250_SLAVE_SNOC_GEM_NOC_SF 135 1476df5b349SJonathan Marek #define SM8250_SLAVE_TCSR 136 1486df5b349SJonathan Marek #define SM8250_SLAVE_TCU 137 1496df5b349SJonathan Marek #define SM8250_SLAVE_TLMM_NORTH 138 1506df5b349SJonathan Marek #define SM8250_SLAVE_TLMM_SOUTH 139 1516df5b349SJonathan Marek #define SM8250_SLAVE_TLMM_WEST 140 1526df5b349SJonathan Marek #define SM8250_SLAVE_TSIF 141 1536df5b349SJonathan Marek #define SM8250_SLAVE_UFS_CARD_CFG 142 1546df5b349SJonathan Marek #define SM8250_SLAVE_UFS_MEM_CFG 143 1556df5b349SJonathan Marek #define SM8250_SLAVE_USB3 144 1566df5b349SJonathan Marek #define SM8250_SLAVE_USB3_1 145 1576df5b349SJonathan Marek #define SM8250_SLAVE_VENUS_CFG 146 1586df5b349SJonathan Marek #define SM8250_SLAVE_VSENSE_CTRL_CFG 147 1596df5b349SJonathan Marek #define SM8250_SNOC_CNOC_MAS 148 1606df5b349SJonathan Marek #define SM8250_SNOC_CNOC_SLV 149 161*cde2f928SKonrad Dybcio #define SM8250_MASTER_QUP_CORE_0 150 162*cde2f928SKonrad Dybcio #define SM8250_MASTER_QUP_CORE_1 151 163*cde2f928SKonrad Dybcio #define SM8250_MASTER_QUP_CORE_2 152 164*cde2f928SKonrad Dybcio #define SM8250_SLAVE_QUP_CORE_0 153 165*cde2f928SKonrad Dybcio #define SM8250_SLAVE_QUP_CORE_1 154 166*cde2f928SKonrad Dybcio #define SM8250_SLAVE_QUP_CORE_2 155 1676df5b349SJonathan Marek 1686df5b349SJonathan Marek #endif 169