1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 * 5 */ 6 7 #include <linux/device.h> 8 #include <linux/interconnect.h> 9 #include <linux/interconnect-provider.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include <dt-bindings/interconnect/qcom,sm8250.h> 13 14 #include "bcm-voter.h" 15 #include "icc-rpmh.h" 16 17 static struct qcom_icc_node qhm_a1noc_cfg; 18 static struct qcom_icc_node qhm_qspi; 19 static struct qcom_icc_node qhm_qup1; 20 static struct qcom_icc_node qhm_qup2; 21 static struct qcom_icc_node qhm_tsif; 22 static struct qcom_icc_node xm_pcie3_modem; 23 static struct qcom_icc_node xm_sdc4; 24 static struct qcom_icc_node xm_ufs_mem; 25 static struct qcom_icc_node xm_usb3_0; 26 static struct qcom_icc_node xm_usb3_1; 27 static struct qcom_icc_node qhm_a2noc_cfg; 28 static struct qcom_icc_node qhm_qdss_bam; 29 static struct qcom_icc_node qhm_qup0; 30 static struct qcom_icc_node qnm_cnoc; 31 static struct qcom_icc_node qxm_crypto; 32 static struct qcom_icc_node qxm_ipa; 33 static struct qcom_icc_node xm_pcie3_0; 34 static struct qcom_icc_node xm_pcie3_1; 35 static struct qcom_icc_node xm_qdss_etr; 36 static struct qcom_icc_node xm_sdc2; 37 static struct qcom_icc_node xm_ufs_card; 38 static struct qcom_icc_node qnm_npu; 39 static struct qcom_icc_node qnm_snoc; 40 static struct qcom_icc_node xm_qdss_dap; 41 static struct qcom_icc_node qhm_cnoc_dc_noc; 42 static struct qcom_icc_node alm_gpu_tcu; 43 static struct qcom_icc_node alm_sys_tcu; 44 static struct qcom_icc_node chm_apps; 45 static struct qcom_icc_node qhm_gemnoc_cfg; 46 static struct qcom_icc_node qnm_cmpnoc; 47 static struct qcom_icc_node qnm_gpu; 48 static struct qcom_icc_node qnm_mnoc_hf; 49 static struct qcom_icc_node qnm_mnoc_sf; 50 static struct qcom_icc_node qnm_pcie; 51 static struct qcom_icc_node qnm_snoc_gc; 52 static struct qcom_icc_node qnm_snoc_sf; 53 static struct qcom_icc_node llcc_mc; 54 static struct qcom_icc_node qhm_mnoc_cfg; 55 static struct qcom_icc_node qnm_camnoc_hf; 56 static struct qcom_icc_node qnm_camnoc_icp; 57 static struct qcom_icc_node qnm_camnoc_sf; 58 static struct qcom_icc_node qnm_video0; 59 static struct qcom_icc_node qnm_video1; 60 static struct qcom_icc_node qnm_video_cvp; 61 static struct qcom_icc_node qxm_mdp0; 62 static struct qcom_icc_node qxm_mdp1; 63 static struct qcom_icc_node qxm_rot; 64 static struct qcom_icc_node amm_npu_sys; 65 static struct qcom_icc_node amm_npu_sys_cdp_w; 66 static struct qcom_icc_node qhm_cfg; 67 static struct qcom_icc_node qhm_snoc_cfg; 68 static struct qcom_icc_node qnm_aggre1_noc; 69 static struct qcom_icc_node qnm_aggre2_noc; 70 static struct qcom_icc_node qnm_gemnoc; 71 static struct qcom_icc_node qnm_gemnoc_pcie; 72 static struct qcom_icc_node qxm_pimem; 73 static struct qcom_icc_node xm_gic; 74 static struct qcom_icc_node qns_a1noc_snoc; 75 static struct qcom_icc_node qns_pcie_modem_mem_noc; 76 static struct qcom_icc_node srvc_aggre1_noc; 77 static struct qcom_icc_node qns_a2noc_snoc; 78 static struct qcom_icc_node qns_pcie_mem_noc; 79 static struct qcom_icc_node srvc_aggre2_noc; 80 static struct qcom_icc_node qns_cdsp_mem_noc; 81 static struct qcom_icc_node qhs_a1_noc_cfg; 82 static struct qcom_icc_node qhs_a2_noc_cfg; 83 static struct qcom_icc_node qhs_ahb2phy0; 84 static struct qcom_icc_node qhs_ahb2phy1; 85 static struct qcom_icc_node qhs_aoss; 86 static struct qcom_icc_node qhs_camera_cfg; 87 static struct qcom_icc_node qhs_clk_ctl; 88 static struct qcom_icc_node qhs_compute_dsp; 89 static struct qcom_icc_node qhs_cpr_cx; 90 static struct qcom_icc_node qhs_cpr_mmcx; 91 static struct qcom_icc_node qhs_cpr_mx; 92 static struct qcom_icc_node qhs_crypto0_cfg; 93 static struct qcom_icc_node qhs_cx_rdpm; 94 static struct qcom_icc_node qhs_dcc_cfg; 95 static struct qcom_icc_node qhs_ddrss_cfg; 96 static struct qcom_icc_node qhs_display_cfg; 97 static struct qcom_icc_node qhs_gpuss_cfg; 98 static struct qcom_icc_node qhs_imem_cfg; 99 static struct qcom_icc_node qhs_ipa; 100 static struct qcom_icc_node qhs_ipc_router; 101 static struct qcom_icc_node qhs_lpass_cfg; 102 static struct qcom_icc_node qhs_mnoc_cfg; 103 static struct qcom_icc_node qhs_npu_cfg; 104 static struct qcom_icc_node qhs_pcie0_cfg; 105 static struct qcom_icc_node qhs_pcie1_cfg; 106 static struct qcom_icc_node qhs_pcie_modem_cfg; 107 static struct qcom_icc_node qhs_pdm; 108 static struct qcom_icc_node qhs_pimem_cfg; 109 static struct qcom_icc_node qhs_prng; 110 static struct qcom_icc_node qhs_qdss_cfg; 111 static struct qcom_icc_node qhs_qspi; 112 static struct qcom_icc_node qhs_qup0; 113 static struct qcom_icc_node qhs_qup1; 114 static struct qcom_icc_node qhs_qup2; 115 static struct qcom_icc_node qhs_sdc2; 116 static struct qcom_icc_node qhs_sdc4; 117 static struct qcom_icc_node qhs_snoc_cfg; 118 static struct qcom_icc_node qhs_tcsr; 119 static struct qcom_icc_node qhs_tlmm0; 120 static struct qcom_icc_node qhs_tlmm1; 121 static struct qcom_icc_node qhs_tlmm2; 122 static struct qcom_icc_node qhs_tsif; 123 static struct qcom_icc_node qhs_ufs_card_cfg; 124 static struct qcom_icc_node qhs_ufs_mem_cfg; 125 static struct qcom_icc_node qhs_usb3_0; 126 static struct qcom_icc_node qhs_usb3_1; 127 static struct qcom_icc_node qhs_venus_cfg; 128 static struct qcom_icc_node qhs_vsense_ctrl_cfg; 129 static struct qcom_icc_node qns_cnoc_a2noc; 130 static struct qcom_icc_node srvc_cnoc; 131 static struct qcom_icc_node qhs_llcc; 132 static struct qcom_icc_node qhs_memnoc; 133 static struct qcom_icc_node qns_gem_noc_snoc; 134 static struct qcom_icc_node qns_llcc; 135 static struct qcom_icc_node qns_sys_pcie; 136 static struct qcom_icc_node srvc_even_gemnoc; 137 static struct qcom_icc_node srvc_odd_gemnoc; 138 static struct qcom_icc_node srvc_sys_gemnoc; 139 static struct qcom_icc_node ebi; 140 static struct qcom_icc_node qns_mem_noc_hf; 141 static struct qcom_icc_node qns_mem_noc_sf; 142 static struct qcom_icc_node srvc_mnoc; 143 static struct qcom_icc_node qhs_cal_dp0; 144 static struct qcom_icc_node qhs_cal_dp1; 145 static struct qcom_icc_node qhs_cp; 146 static struct qcom_icc_node qhs_dma_bwmon; 147 static struct qcom_icc_node qhs_dpm; 148 static struct qcom_icc_node qhs_isense; 149 static struct qcom_icc_node qhs_llm; 150 static struct qcom_icc_node qhs_tcm; 151 static struct qcom_icc_node qns_npu_sys; 152 static struct qcom_icc_node srvc_noc; 153 static struct qcom_icc_node qhs_apss; 154 static struct qcom_icc_node qns_cnoc; 155 static struct qcom_icc_node qns_gemnoc_gc; 156 static struct qcom_icc_node qns_gemnoc_sf; 157 static struct qcom_icc_node qxs_imem; 158 static struct qcom_icc_node qxs_pimem; 159 static struct qcom_icc_node srvc_snoc; 160 static struct qcom_icc_node xs_pcie_0; 161 static struct qcom_icc_node xs_pcie_1; 162 static struct qcom_icc_node xs_pcie_modem; 163 static struct qcom_icc_node xs_qdss_stm; 164 static struct qcom_icc_node xs_sys_tcu_cfg; 165 static struct qcom_icc_node qup0_core_master; 166 static struct qcom_icc_node qup1_core_master; 167 static struct qcom_icc_node qup2_core_master; 168 static struct qcom_icc_node qup0_core_slave; 169 static struct qcom_icc_node qup1_core_slave; 170 static struct qcom_icc_node qup2_core_slave; 171 172 static struct qcom_icc_node qhm_a1noc_cfg = { 173 .name = "qhm_a1noc_cfg", 174 .channels = 1, 175 .buswidth = 4, 176 .num_links = 1, 177 .link_nodes = { &srvc_aggre1_noc }, 178 }; 179 180 static struct qcom_icc_node qhm_qspi = { 181 .name = "qhm_qspi", 182 .channels = 1, 183 .buswidth = 4, 184 .num_links = 1, 185 .link_nodes = { &qns_a1noc_snoc }, 186 }; 187 188 static struct qcom_icc_node qhm_qup1 = { 189 .name = "qhm_qup1", 190 .channels = 1, 191 .buswidth = 4, 192 .num_links = 1, 193 .link_nodes = { &qns_a1noc_snoc }, 194 }; 195 196 static struct qcom_icc_node qhm_qup2 = { 197 .name = "qhm_qup2", 198 .channels = 1, 199 .buswidth = 4, 200 .num_links = 1, 201 .link_nodes = { &qns_a1noc_snoc }, 202 }; 203 204 static struct qcom_icc_node qhm_tsif = { 205 .name = "qhm_tsif", 206 .channels = 1, 207 .buswidth = 4, 208 .num_links = 1, 209 .link_nodes = { &qns_a1noc_snoc }, 210 }; 211 212 static struct qcom_icc_node xm_pcie3_modem = { 213 .name = "xm_pcie3_modem", 214 .channels = 1, 215 .buswidth = 8, 216 .num_links = 1, 217 .link_nodes = { &qns_pcie_modem_mem_noc }, 218 }; 219 220 static struct qcom_icc_node xm_sdc4 = { 221 .name = "xm_sdc4", 222 .channels = 1, 223 .buswidth = 8, 224 .num_links = 1, 225 .link_nodes = { &qns_a1noc_snoc }, 226 }; 227 228 static struct qcom_icc_node xm_ufs_mem = { 229 .name = "xm_ufs_mem", 230 .channels = 1, 231 .buswidth = 8, 232 .num_links = 1, 233 .link_nodes = { &qns_a1noc_snoc }, 234 }; 235 236 static struct qcom_icc_node xm_usb3_0 = { 237 .name = "xm_usb3_0", 238 .channels = 1, 239 .buswidth = 8, 240 .num_links = 1, 241 .link_nodes = { &qns_a1noc_snoc }, 242 }; 243 244 static struct qcom_icc_node xm_usb3_1 = { 245 .name = "xm_usb3_1", 246 .channels = 1, 247 .buswidth = 8, 248 .num_links = 1, 249 .link_nodes = { &qns_a1noc_snoc }, 250 }; 251 252 static struct qcom_icc_node qhm_a2noc_cfg = { 253 .name = "qhm_a2noc_cfg", 254 .channels = 1, 255 .buswidth = 4, 256 .num_links = 1, 257 .link_nodes = { &srvc_aggre2_noc }, 258 }; 259 260 static struct qcom_icc_node qhm_qdss_bam = { 261 .name = "qhm_qdss_bam", 262 .channels = 1, 263 .buswidth = 4, 264 .num_links = 1, 265 .link_nodes = { &qns_a2noc_snoc }, 266 }; 267 268 static struct qcom_icc_node qhm_qup0 = { 269 .name = "qhm_qup0", 270 .channels = 1, 271 .buswidth = 4, 272 .num_links = 1, 273 .link_nodes = { &qns_a2noc_snoc }, 274 }; 275 276 static struct qcom_icc_node qnm_cnoc = { 277 .name = "qnm_cnoc", 278 .channels = 1, 279 .buswidth = 8, 280 .num_links = 1, 281 .link_nodes = { &qns_a2noc_snoc }, 282 }; 283 284 static struct qcom_icc_node qxm_crypto = { 285 .name = "qxm_crypto", 286 .channels = 1, 287 .buswidth = 8, 288 .num_links = 1, 289 .link_nodes = { &qns_a2noc_snoc }, 290 }; 291 292 static struct qcom_icc_node qxm_ipa = { 293 .name = "qxm_ipa", 294 .channels = 1, 295 .buswidth = 8, 296 .num_links = 1, 297 .link_nodes = { &qns_a2noc_snoc }, 298 }; 299 300 static struct qcom_icc_node xm_pcie3_0 = { 301 .name = "xm_pcie3_0", 302 .channels = 1, 303 .buswidth = 8, 304 .num_links = 1, 305 .link_nodes = { &qns_pcie_mem_noc }, 306 }; 307 308 static struct qcom_icc_node xm_pcie3_1 = { 309 .name = "xm_pcie3_1", 310 .channels = 1, 311 .buswidth = 8, 312 .num_links = 1, 313 .link_nodes = { &qns_pcie_mem_noc }, 314 }; 315 316 static struct qcom_icc_node xm_qdss_etr = { 317 .name = "xm_qdss_etr", 318 .channels = 1, 319 .buswidth = 8, 320 .num_links = 1, 321 .link_nodes = { &qns_a2noc_snoc }, 322 }; 323 324 static struct qcom_icc_node xm_sdc2 = { 325 .name = "xm_sdc2", 326 .channels = 1, 327 .buswidth = 8, 328 .num_links = 1, 329 .link_nodes = { &qns_a2noc_snoc }, 330 }; 331 332 static struct qcom_icc_node xm_ufs_card = { 333 .name = "xm_ufs_card", 334 .channels = 1, 335 .buswidth = 8, 336 .num_links = 1, 337 .link_nodes = { &qns_a2noc_snoc }, 338 }; 339 340 static struct qcom_icc_node qnm_npu = { 341 .name = "qnm_npu", 342 .channels = 2, 343 .buswidth = 32, 344 .num_links = 1, 345 .link_nodes = { &qns_cdsp_mem_noc }, 346 }; 347 348 static struct qcom_icc_node qnm_snoc = { 349 .name = "qnm_snoc", 350 .channels = 1, 351 .buswidth = 8, 352 .num_links = 49, 353 .link_nodes = { &qhs_compute_dsp, 354 &qhs_camera_cfg, 355 &qhs_tlmm1, 356 &qhs_tlmm0, 357 &qhs_sdc4, 358 &qhs_tlmm2, 359 &qhs_sdc2, 360 &qhs_mnoc_cfg, 361 &qhs_ufs_mem_cfg, 362 &qhs_snoc_cfg, 363 &qhs_pdm, 364 &qhs_cx_rdpm, 365 &qhs_pcie1_cfg, 366 &qhs_a2_noc_cfg, 367 &qhs_qdss_cfg, 368 &qhs_display_cfg, 369 &qhs_pcie_modem_cfg, 370 &qhs_tcsr, 371 &qhs_dcc_cfg, 372 &qhs_ddrss_cfg, 373 &qhs_ipc_router, 374 &qhs_pcie0_cfg, 375 &qhs_cpr_mmcx, 376 &qhs_npu_cfg, 377 &qhs_ahb2phy0, 378 &qhs_ahb2phy1, 379 &qhs_gpuss_cfg, 380 &qhs_venus_cfg, 381 &qhs_tsif, 382 &qhs_ipa, 383 &qhs_imem_cfg, 384 &qhs_usb3_0, 385 &srvc_cnoc, 386 &qhs_ufs_card_cfg, 387 &qhs_usb3_1, 388 &qhs_lpass_cfg, 389 &qhs_cpr_cx, 390 &qhs_a1_noc_cfg, 391 &qhs_aoss, 392 &qhs_prng, 393 &qhs_vsense_ctrl_cfg, 394 &qhs_qspi, 395 &qhs_crypto0_cfg, 396 &qhs_pimem_cfg, 397 &qhs_cpr_mx, 398 &qhs_qup0, 399 &qhs_qup1, 400 &qhs_qup2, 401 &qhs_clk_ctl }, 402 }; 403 404 static struct qcom_icc_node xm_qdss_dap = { 405 .name = "xm_qdss_dap", 406 .channels = 1, 407 .buswidth = 8, 408 .num_links = 50, 409 .link_nodes = { &qhs_compute_dsp, 410 &qhs_camera_cfg, 411 &qhs_tlmm1, 412 &qhs_tlmm0, 413 &qhs_sdc4, 414 &qhs_tlmm2, 415 &qhs_sdc2, 416 &qhs_mnoc_cfg, 417 &qhs_ufs_mem_cfg, 418 &qhs_snoc_cfg, 419 &qhs_pdm, 420 &qhs_cx_rdpm, 421 &qhs_pcie1_cfg, 422 &qhs_a2_noc_cfg, 423 &qhs_qdss_cfg, 424 &qhs_display_cfg, 425 &qhs_pcie_modem_cfg, 426 &qhs_tcsr, 427 &qhs_dcc_cfg, 428 &qhs_ddrss_cfg, 429 &qhs_ipc_router, 430 &qns_cnoc_a2noc, 431 &qhs_pcie0_cfg, 432 &qhs_cpr_mmcx, 433 &qhs_npu_cfg, 434 &qhs_ahb2phy0, 435 &qhs_ahb2phy1, 436 &qhs_gpuss_cfg, 437 &qhs_venus_cfg, 438 &qhs_tsif, 439 &qhs_ipa, 440 &qhs_imem_cfg, 441 &qhs_usb3_0, 442 &srvc_cnoc, 443 &qhs_ufs_card_cfg, 444 &qhs_usb3_1, 445 &qhs_lpass_cfg, 446 &qhs_cpr_cx, 447 &qhs_a1_noc_cfg, 448 &qhs_aoss, 449 &qhs_prng, 450 &qhs_vsense_ctrl_cfg, 451 &qhs_qspi, 452 &qhs_crypto0_cfg, 453 &qhs_pimem_cfg, 454 &qhs_cpr_mx, 455 &qhs_qup0, 456 &qhs_qup1, 457 &qhs_qup2, 458 &qhs_clk_ctl }, 459 }; 460 461 static struct qcom_icc_node qhm_cnoc_dc_noc = { 462 .name = "qhm_cnoc_dc_noc", 463 .channels = 1, 464 .buswidth = 4, 465 .num_links = 2, 466 .link_nodes = { &qhs_memnoc, 467 &qhs_llcc }, 468 }; 469 470 static struct qcom_icc_node alm_gpu_tcu = { 471 .name = "alm_gpu_tcu", 472 .channels = 1, 473 .buswidth = 8, 474 .num_links = 2, 475 .link_nodes = { &qns_llcc, 476 &qns_gem_noc_snoc }, 477 }; 478 479 static struct qcom_icc_node alm_sys_tcu = { 480 .name = "alm_sys_tcu", 481 .channels = 1, 482 .buswidth = 8, 483 .num_links = 2, 484 .link_nodes = { &qns_llcc, 485 &qns_gem_noc_snoc }, 486 }; 487 488 static struct qcom_icc_node chm_apps = { 489 .name = "chm_apps", 490 .channels = 2, 491 .buswidth = 32, 492 .num_links = 3, 493 .link_nodes = { &qns_llcc, 494 &qns_gem_noc_snoc, 495 &qns_sys_pcie }, 496 }; 497 498 static struct qcom_icc_node qhm_gemnoc_cfg = { 499 .name = "qhm_gemnoc_cfg", 500 .channels = 1, 501 .buswidth = 4, 502 .num_links = 3, 503 .link_nodes = { &srvc_odd_gemnoc, 504 &srvc_even_gemnoc, 505 &srvc_sys_gemnoc }, 506 }; 507 508 static struct qcom_icc_node qnm_cmpnoc = { 509 .name = "qnm_cmpnoc", 510 .channels = 2, 511 .buswidth = 32, 512 .num_links = 2, 513 .link_nodes = { &qns_llcc, 514 &qns_gem_noc_snoc }, 515 }; 516 517 static struct qcom_icc_node qnm_gpu = { 518 .name = "qnm_gpu", 519 .channels = 2, 520 .buswidth = 32, 521 .num_links = 2, 522 .link_nodes = { &qns_llcc, 523 &qns_gem_noc_snoc }, 524 }; 525 526 static struct qcom_icc_node qnm_mnoc_hf = { 527 .name = "qnm_mnoc_hf", 528 .channels = 2, 529 .buswidth = 32, 530 .num_links = 1, 531 .link_nodes = { &qns_llcc }, 532 }; 533 534 static struct qcom_icc_node qnm_mnoc_sf = { 535 .name = "qnm_mnoc_sf", 536 .channels = 2, 537 .buswidth = 32, 538 .num_links = 2, 539 .link_nodes = { &qns_llcc, 540 &qns_gem_noc_snoc }, 541 }; 542 543 static struct qcom_icc_node qnm_pcie = { 544 .name = "qnm_pcie", 545 .channels = 1, 546 .buswidth = 16, 547 .num_links = 2, 548 .link_nodes = { &qns_llcc, 549 &qns_gem_noc_snoc }, 550 }; 551 552 static struct qcom_icc_node qnm_snoc_gc = { 553 .name = "qnm_snoc_gc", 554 .channels = 1, 555 .buswidth = 8, 556 .num_links = 1, 557 .link_nodes = { &qns_llcc }, 558 }; 559 560 static struct qcom_icc_node qnm_snoc_sf = { 561 .name = "qnm_snoc_sf", 562 .channels = 1, 563 .buswidth = 16, 564 .num_links = 3, 565 .link_nodes = { &qns_llcc, 566 &qns_gem_noc_snoc, 567 &qns_sys_pcie }, 568 }; 569 570 static struct qcom_icc_node llcc_mc = { 571 .name = "llcc_mc", 572 .channels = 4, 573 .buswidth = 4, 574 .num_links = 1, 575 .link_nodes = { &ebi }, 576 }; 577 578 static struct qcom_icc_node qhm_mnoc_cfg = { 579 .name = "qhm_mnoc_cfg", 580 .channels = 1, 581 .buswidth = 4, 582 .num_links = 1, 583 .link_nodes = { &srvc_mnoc }, 584 }; 585 586 static struct qcom_icc_node qnm_camnoc_hf = { 587 .name = "qnm_camnoc_hf", 588 .channels = 2, 589 .buswidth = 32, 590 .num_links = 1, 591 .link_nodes = { &qns_mem_noc_hf }, 592 }; 593 594 static struct qcom_icc_node qnm_camnoc_icp = { 595 .name = "qnm_camnoc_icp", 596 .channels = 1, 597 .buswidth = 8, 598 .num_links = 1, 599 .link_nodes = { &qns_mem_noc_sf }, 600 }; 601 602 static struct qcom_icc_node qnm_camnoc_sf = { 603 .name = "qnm_camnoc_sf", 604 .channels = 2, 605 .buswidth = 32, 606 .num_links = 1, 607 .link_nodes = { &qns_mem_noc_sf }, 608 }; 609 610 static struct qcom_icc_node qnm_video0 = { 611 .name = "qnm_video0", 612 .channels = 1, 613 .buswidth = 32, 614 .num_links = 1, 615 .link_nodes = { &qns_mem_noc_sf }, 616 }; 617 618 static struct qcom_icc_node qnm_video1 = { 619 .name = "qnm_video1", 620 .channels = 1, 621 .buswidth = 32, 622 .num_links = 1, 623 .link_nodes = { &qns_mem_noc_sf }, 624 }; 625 626 static struct qcom_icc_node qnm_video_cvp = { 627 .name = "qnm_video_cvp", 628 .channels = 1, 629 .buswidth = 32, 630 .num_links = 1, 631 .link_nodes = { &qns_mem_noc_sf }, 632 }; 633 634 static struct qcom_icc_node qxm_mdp0 = { 635 .name = "qxm_mdp0", 636 .channels = 1, 637 .buswidth = 32, 638 .num_links = 1, 639 .link_nodes = { &qns_mem_noc_hf }, 640 }; 641 642 static struct qcom_icc_node qxm_mdp1 = { 643 .name = "qxm_mdp1", 644 .channels = 1, 645 .buswidth = 32, 646 .num_links = 1, 647 .link_nodes = { &qns_mem_noc_hf }, 648 }; 649 650 static struct qcom_icc_node qxm_rot = { 651 .name = "qxm_rot", 652 .channels = 1, 653 .buswidth = 32, 654 .num_links = 1, 655 .link_nodes = { &qns_mem_noc_sf }, 656 }; 657 658 static struct qcom_icc_node amm_npu_sys = { 659 .name = "amm_npu_sys", 660 .channels = 4, 661 .buswidth = 32, 662 .num_links = 1, 663 .link_nodes = { &qns_npu_sys }, 664 }; 665 666 static struct qcom_icc_node amm_npu_sys_cdp_w = { 667 .name = "amm_npu_sys_cdp_w", 668 .channels = 2, 669 .buswidth = 16, 670 .num_links = 1, 671 .link_nodes = { &qns_npu_sys }, 672 }; 673 674 static struct qcom_icc_node qhm_cfg = { 675 .name = "qhm_cfg", 676 .channels = 1, 677 .buswidth = 4, 678 .num_links = 9, 679 .link_nodes = { &srvc_noc, 680 &qhs_isense, 681 &qhs_llm, 682 &qhs_dma_bwmon, 683 &qhs_cp, 684 &qhs_tcm, 685 &qhs_cal_dp0, 686 &qhs_cal_dp1, 687 &qhs_dpm }, 688 }; 689 690 static struct qcom_icc_node qhm_snoc_cfg = { 691 .name = "qhm_snoc_cfg", 692 .channels = 1, 693 .buswidth = 4, 694 .num_links = 1, 695 .link_nodes = { &srvc_snoc }, 696 }; 697 698 static struct qcom_icc_node qnm_aggre1_noc = { 699 .name = "qnm_aggre1_noc", 700 .channels = 1, 701 .buswidth = 16, 702 .num_links = 1, 703 .link_nodes = { &qns_gemnoc_sf }, 704 }; 705 706 static struct qcom_icc_node qnm_aggre2_noc = { 707 .name = "qnm_aggre2_noc", 708 .channels = 1, 709 .buswidth = 16, 710 .num_links = 1, 711 .link_nodes = { &qns_gemnoc_sf }, 712 }; 713 714 static struct qcom_icc_node qnm_gemnoc = { 715 .name = "qnm_gemnoc", 716 .channels = 1, 717 .buswidth = 16, 718 .num_links = 6, 719 .link_nodes = { &qxs_pimem, 720 &qxs_imem, 721 &qhs_apss, 722 &qns_cnoc, 723 &xs_sys_tcu_cfg, 724 &xs_qdss_stm }, 725 }; 726 727 static struct qcom_icc_node qnm_gemnoc_pcie = { 728 .name = "qnm_gemnoc_pcie", 729 .channels = 1, 730 .buswidth = 8, 731 .num_links = 3, 732 .link_nodes = { &xs_pcie_modem, 733 &xs_pcie_0, 734 &xs_pcie_1 }, 735 }; 736 737 static struct qcom_icc_node qxm_pimem = { 738 .name = "qxm_pimem", 739 .channels = 1, 740 .buswidth = 8, 741 .num_links = 1, 742 .link_nodes = { &qns_gemnoc_gc }, 743 }; 744 745 static struct qcom_icc_node xm_gic = { 746 .name = "xm_gic", 747 .channels = 1, 748 .buswidth = 8, 749 .num_links = 1, 750 .link_nodes = { &qns_gemnoc_gc }, 751 }; 752 753 static struct qcom_icc_node qns_a1noc_snoc = { 754 .name = "qns_a1noc_snoc", 755 .channels = 1, 756 .buswidth = 16, 757 .num_links = 1, 758 .link_nodes = { &qnm_aggre1_noc }, 759 }; 760 761 static struct qcom_icc_node qns_pcie_modem_mem_noc = { 762 .name = "qns_pcie_modem_mem_noc", 763 .channels = 1, 764 .buswidth = 16, 765 .num_links = 1, 766 .link_nodes = { &qnm_pcie }, 767 }; 768 769 static struct qcom_icc_node srvc_aggre1_noc = { 770 .name = "srvc_aggre1_noc", 771 .channels = 1, 772 .buswidth = 4, 773 }; 774 775 static struct qcom_icc_node qns_a2noc_snoc = { 776 .name = "qns_a2noc_snoc", 777 .channels = 1, 778 .buswidth = 16, 779 .num_links = 1, 780 .link_nodes = { &qnm_aggre2_noc }, 781 }; 782 783 static struct qcom_icc_node qns_pcie_mem_noc = { 784 .name = "qns_pcie_mem_noc", 785 .channels = 1, 786 .buswidth = 16, 787 .num_links = 1, 788 .link_nodes = { &qnm_pcie }, 789 }; 790 791 static struct qcom_icc_node srvc_aggre2_noc = { 792 .name = "srvc_aggre2_noc", 793 .channels = 1, 794 .buswidth = 4, 795 }; 796 797 static struct qcom_icc_node qns_cdsp_mem_noc = { 798 .name = "qns_cdsp_mem_noc", 799 .channels = 2, 800 .buswidth = 32, 801 .num_links = 1, 802 .link_nodes = { &qnm_cmpnoc }, 803 }; 804 805 static struct qcom_icc_node qhs_a1_noc_cfg = { 806 .name = "qhs_a1_noc_cfg", 807 .channels = 1, 808 .buswidth = 4, 809 .num_links = 1, 810 .link_nodes = { &qhm_a1noc_cfg }, 811 }; 812 813 static struct qcom_icc_node qhs_a2_noc_cfg = { 814 .name = "qhs_a2_noc_cfg", 815 .channels = 1, 816 .buswidth = 4, 817 .num_links = 1, 818 .link_nodes = { &qhm_a2noc_cfg }, 819 }; 820 821 static struct qcom_icc_node qhs_ahb2phy0 = { 822 .name = "qhs_ahb2phy0", 823 .channels = 1, 824 .buswidth = 4, 825 }; 826 827 static struct qcom_icc_node qhs_ahb2phy1 = { 828 .name = "qhs_ahb2phy1", 829 .channels = 1, 830 .buswidth = 4, 831 }; 832 833 static struct qcom_icc_node qhs_aoss = { 834 .name = "qhs_aoss", 835 .channels = 1, 836 .buswidth = 4, 837 }; 838 839 static struct qcom_icc_node qhs_camera_cfg = { 840 .name = "qhs_camera_cfg", 841 .channels = 1, 842 .buswidth = 4, 843 }; 844 845 static struct qcom_icc_node qhs_clk_ctl = { 846 .name = "qhs_clk_ctl", 847 .channels = 1, 848 .buswidth = 4, 849 }; 850 851 static struct qcom_icc_node qhs_compute_dsp = { 852 .name = "qhs_compute_dsp", 853 .channels = 1, 854 .buswidth = 4, 855 }; 856 857 static struct qcom_icc_node qhs_cpr_cx = { 858 .name = "qhs_cpr_cx", 859 .channels = 1, 860 .buswidth = 4, 861 }; 862 863 static struct qcom_icc_node qhs_cpr_mmcx = { 864 .name = "qhs_cpr_mmcx", 865 .channels = 1, 866 .buswidth = 4, 867 }; 868 869 static struct qcom_icc_node qhs_cpr_mx = { 870 .name = "qhs_cpr_mx", 871 .channels = 1, 872 .buswidth = 4, 873 }; 874 875 static struct qcom_icc_node qhs_crypto0_cfg = { 876 .name = "qhs_crypto0_cfg", 877 .channels = 1, 878 .buswidth = 4, 879 }; 880 881 static struct qcom_icc_node qhs_cx_rdpm = { 882 .name = "qhs_cx_rdpm", 883 .channels = 1, 884 .buswidth = 4, 885 }; 886 887 static struct qcom_icc_node qhs_dcc_cfg = { 888 .name = "qhs_dcc_cfg", 889 .channels = 1, 890 .buswidth = 4, 891 }; 892 893 static struct qcom_icc_node qhs_ddrss_cfg = { 894 .name = "qhs_ddrss_cfg", 895 .channels = 1, 896 .buswidth = 4, 897 .num_links = 1, 898 .link_nodes = { &qhm_cnoc_dc_noc }, 899 }; 900 901 static struct qcom_icc_node qhs_display_cfg = { 902 .name = "qhs_display_cfg", 903 .channels = 1, 904 .buswidth = 4, 905 }; 906 907 static struct qcom_icc_node qhs_gpuss_cfg = { 908 .name = "qhs_gpuss_cfg", 909 .channels = 1, 910 .buswidth = 8, 911 }; 912 913 static struct qcom_icc_node qhs_imem_cfg = { 914 .name = "qhs_imem_cfg", 915 .channels = 1, 916 .buswidth = 4, 917 }; 918 919 static struct qcom_icc_node qhs_ipa = { 920 .name = "qhs_ipa", 921 .channels = 1, 922 .buswidth = 4, 923 }; 924 925 static struct qcom_icc_node qhs_ipc_router = { 926 .name = "qhs_ipc_router", 927 .channels = 1, 928 .buswidth = 4, 929 }; 930 931 static struct qcom_icc_node qhs_lpass_cfg = { 932 .name = "qhs_lpass_cfg", 933 .channels = 1, 934 .buswidth = 4, 935 }; 936 937 static struct qcom_icc_node qhs_mnoc_cfg = { 938 .name = "qhs_mnoc_cfg", 939 .channels = 1, 940 .buswidth = 4, 941 .num_links = 1, 942 .link_nodes = { &qhm_mnoc_cfg }, 943 }; 944 945 static struct qcom_icc_node qhs_npu_cfg = { 946 .name = "qhs_npu_cfg", 947 .channels = 1, 948 .buswidth = 4, 949 .num_links = 1, 950 .link_nodes = { &qhm_cfg }, 951 }; 952 953 static struct qcom_icc_node qhs_pcie0_cfg = { 954 .name = "qhs_pcie0_cfg", 955 .channels = 1, 956 .buswidth = 4, 957 }; 958 959 static struct qcom_icc_node qhs_pcie1_cfg = { 960 .name = "qhs_pcie1_cfg", 961 .channels = 1, 962 .buswidth = 4, 963 }; 964 965 static struct qcom_icc_node qhs_pcie_modem_cfg = { 966 .name = "qhs_pcie_modem_cfg", 967 .channels = 1, 968 .buswidth = 4, 969 }; 970 971 static struct qcom_icc_node qhs_pdm = { 972 .name = "qhs_pdm", 973 .channels = 1, 974 .buswidth = 4, 975 }; 976 977 static struct qcom_icc_node qhs_pimem_cfg = { 978 .name = "qhs_pimem_cfg", 979 .channels = 1, 980 .buswidth = 4, 981 }; 982 983 static struct qcom_icc_node qhs_prng = { 984 .name = "qhs_prng", 985 .channels = 1, 986 .buswidth = 4, 987 }; 988 989 static struct qcom_icc_node qhs_qdss_cfg = { 990 .name = "qhs_qdss_cfg", 991 .channels = 1, 992 .buswidth = 4, 993 }; 994 995 static struct qcom_icc_node qhs_qspi = { 996 .name = "qhs_qspi", 997 .channels = 1, 998 .buswidth = 4, 999 }; 1000 1001 static struct qcom_icc_node qhs_qup0 = { 1002 .name = "qhs_qup0", 1003 .channels = 1, 1004 .buswidth = 4, 1005 }; 1006 1007 static struct qcom_icc_node qhs_qup1 = { 1008 .name = "qhs_qup1", 1009 .channels = 1, 1010 .buswidth = 4, 1011 }; 1012 1013 static struct qcom_icc_node qhs_qup2 = { 1014 .name = "qhs_qup2", 1015 .channels = 1, 1016 .buswidth = 4, 1017 }; 1018 1019 static struct qcom_icc_node qhs_sdc2 = { 1020 .name = "qhs_sdc2", 1021 .channels = 1, 1022 .buswidth = 4, 1023 }; 1024 1025 static struct qcom_icc_node qhs_sdc4 = { 1026 .name = "qhs_sdc4", 1027 .channels = 1, 1028 .buswidth = 4, 1029 }; 1030 1031 static struct qcom_icc_node qhs_snoc_cfg = { 1032 .name = "qhs_snoc_cfg", 1033 .channels = 1, 1034 .buswidth = 4, 1035 .num_links = 1, 1036 .link_nodes = { &qhm_snoc_cfg }, 1037 }; 1038 1039 static struct qcom_icc_node qhs_tcsr = { 1040 .name = "qhs_tcsr", 1041 .channels = 1, 1042 .buswidth = 4, 1043 }; 1044 1045 static struct qcom_icc_node qhs_tlmm0 = { 1046 .name = "qhs_tlmm0", 1047 .channels = 1, 1048 .buswidth = 4, 1049 }; 1050 1051 static struct qcom_icc_node qhs_tlmm1 = { 1052 .name = "qhs_tlmm1", 1053 .channels = 1, 1054 .buswidth = 4, 1055 }; 1056 1057 static struct qcom_icc_node qhs_tlmm2 = { 1058 .name = "qhs_tlmm2", 1059 .channels = 1, 1060 .buswidth = 4, 1061 }; 1062 1063 static struct qcom_icc_node qhs_tsif = { 1064 .name = "qhs_tsif", 1065 .channels = 1, 1066 .buswidth = 4, 1067 }; 1068 1069 static struct qcom_icc_node qhs_ufs_card_cfg = { 1070 .name = "qhs_ufs_card_cfg", 1071 .channels = 1, 1072 .buswidth = 4, 1073 }; 1074 1075 static struct qcom_icc_node qhs_ufs_mem_cfg = { 1076 .name = "qhs_ufs_mem_cfg", 1077 .channels = 1, 1078 .buswidth = 4, 1079 }; 1080 1081 static struct qcom_icc_node qhs_usb3_0 = { 1082 .name = "qhs_usb3_0", 1083 .channels = 1, 1084 .buswidth = 4, 1085 }; 1086 1087 static struct qcom_icc_node qhs_usb3_1 = { 1088 .name = "qhs_usb3_1", 1089 .channels = 1, 1090 .buswidth = 4, 1091 }; 1092 1093 static struct qcom_icc_node qhs_venus_cfg = { 1094 .name = "qhs_venus_cfg", 1095 .channels = 1, 1096 .buswidth = 4, 1097 }; 1098 1099 static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 1100 .name = "qhs_vsense_ctrl_cfg", 1101 .channels = 1, 1102 .buswidth = 4, 1103 }; 1104 1105 static struct qcom_icc_node qns_cnoc_a2noc = { 1106 .name = "qns_cnoc_a2noc", 1107 .channels = 1, 1108 .buswidth = 8, 1109 .num_links = 1, 1110 .link_nodes = { &qnm_cnoc }, 1111 }; 1112 1113 static struct qcom_icc_node srvc_cnoc = { 1114 .name = "srvc_cnoc", 1115 .channels = 1, 1116 .buswidth = 4, 1117 }; 1118 1119 static struct qcom_icc_node qhs_llcc = { 1120 .name = "qhs_llcc", 1121 .channels = 1, 1122 .buswidth = 4, 1123 }; 1124 1125 static struct qcom_icc_node qhs_memnoc = { 1126 .name = "qhs_memnoc", 1127 .channels = 1, 1128 .buswidth = 4, 1129 .num_links = 1, 1130 .link_nodes = { &qhm_gemnoc_cfg }, 1131 }; 1132 1133 static struct qcom_icc_node qns_gem_noc_snoc = { 1134 .name = "qns_gem_noc_snoc", 1135 .channels = 1, 1136 .buswidth = 16, 1137 .num_links = 1, 1138 .link_nodes = { &qnm_gemnoc }, 1139 }; 1140 1141 static struct qcom_icc_node qns_llcc = { 1142 .name = "qns_llcc", 1143 .channels = 4, 1144 .buswidth = 16, 1145 .num_links = 1, 1146 .link_nodes = { &llcc_mc }, 1147 }; 1148 1149 static struct qcom_icc_node qns_sys_pcie = { 1150 .name = "qns_sys_pcie", 1151 .channels = 1, 1152 .buswidth = 8, 1153 .num_links = 1, 1154 .link_nodes = { &qnm_gemnoc_pcie }, 1155 }; 1156 1157 static struct qcom_icc_node srvc_even_gemnoc = { 1158 .name = "srvc_even_gemnoc", 1159 .channels = 1, 1160 .buswidth = 4, 1161 }; 1162 1163 static struct qcom_icc_node srvc_odd_gemnoc = { 1164 .name = "srvc_odd_gemnoc", 1165 .channels = 1, 1166 .buswidth = 4, 1167 }; 1168 1169 static struct qcom_icc_node srvc_sys_gemnoc = { 1170 .name = "srvc_sys_gemnoc", 1171 .channels = 1, 1172 .buswidth = 4, 1173 }; 1174 1175 static struct qcom_icc_node ebi = { 1176 .name = "ebi", 1177 .channels = 4, 1178 .buswidth = 4, 1179 }; 1180 1181 static struct qcom_icc_node qns_mem_noc_hf = { 1182 .name = "qns_mem_noc_hf", 1183 .channels = 2, 1184 .buswidth = 32, 1185 .num_links = 1, 1186 .link_nodes = { &qnm_mnoc_hf }, 1187 }; 1188 1189 static struct qcom_icc_node qns_mem_noc_sf = { 1190 .name = "qns_mem_noc_sf", 1191 .channels = 2, 1192 .buswidth = 32, 1193 .num_links = 1, 1194 .link_nodes = { &qnm_mnoc_sf }, 1195 }; 1196 1197 static struct qcom_icc_node srvc_mnoc = { 1198 .name = "srvc_mnoc", 1199 .channels = 1, 1200 .buswidth = 4, 1201 }; 1202 1203 static struct qcom_icc_node qhs_cal_dp0 = { 1204 .name = "qhs_cal_dp0", 1205 .channels = 1, 1206 .buswidth = 4, 1207 }; 1208 1209 static struct qcom_icc_node qhs_cal_dp1 = { 1210 .name = "qhs_cal_dp1", 1211 .channels = 1, 1212 .buswidth = 4, 1213 }; 1214 1215 static struct qcom_icc_node qhs_cp = { 1216 .name = "qhs_cp", 1217 .channels = 1, 1218 .buswidth = 4, 1219 }; 1220 1221 static struct qcom_icc_node qhs_dma_bwmon = { 1222 .name = "qhs_dma_bwmon", 1223 .channels = 1, 1224 .buswidth = 4, 1225 }; 1226 1227 static struct qcom_icc_node qhs_dpm = { 1228 .name = "qhs_dpm", 1229 .channels = 1, 1230 .buswidth = 4, 1231 }; 1232 1233 static struct qcom_icc_node qhs_isense = { 1234 .name = "qhs_isense", 1235 .channels = 1, 1236 .buswidth = 4, 1237 }; 1238 1239 static struct qcom_icc_node qhs_llm = { 1240 .name = "qhs_llm", 1241 .channels = 1, 1242 .buswidth = 4, 1243 }; 1244 1245 static struct qcom_icc_node qhs_tcm = { 1246 .name = "qhs_tcm", 1247 .channels = 1, 1248 .buswidth = 4, 1249 }; 1250 1251 static struct qcom_icc_node qns_npu_sys = { 1252 .name = "qns_npu_sys", 1253 .channels = 2, 1254 .buswidth = 32, 1255 }; 1256 1257 static struct qcom_icc_node srvc_noc = { 1258 .name = "srvc_noc", 1259 .channels = 1, 1260 .buswidth = 4, 1261 }; 1262 1263 static struct qcom_icc_node qhs_apss = { 1264 .name = "qhs_apss", 1265 .channels = 1, 1266 .buswidth = 8, 1267 }; 1268 1269 static struct qcom_icc_node qns_cnoc = { 1270 .name = "qns_cnoc", 1271 .channels = 1, 1272 .buswidth = 8, 1273 .num_links = 1, 1274 .link_nodes = { &qnm_snoc }, 1275 }; 1276 1277 static struct qcom_icc_node qns_gemnoc_gc = { 1278 .name = "qns_gemnoc_gc", 1279 .channels = 1, 1280 .buswidth = 8, 1281 .num_links = 1, 1282 .link_nodes = { &qnm_snoc_gc }, 1283 }; 1284 1285 static struct qcom_icc_node qns_gemnoc_sf = { 1286 .name = "qns_gemnoc_sf", 1287 .channels = 1, 1288 .buswidth = 16, 1289 .num_links = 1, 1290 .link_nodes = { &qnm_snoc_sf }, 1291 }; 1292 1293 static struct qcom_icc_node qxs_imem = { 1294 .name = "qxs_imem", 1295 .channels = 1, 1296 .buswidth = 8, 1297 }; 1298 1299 static struct qcom_icc_node qxs_pimem = { 1300 .name = "qxs_pimem", 1301 .channels = 1, 1302 .buswidth = 8, 1303 }; 1304 1305 static struct qcom_icc_node srvc_snoc = { 1306 .name = "srvc_snoc", 1307 .channels = 1, 1308 .buswidth = 4, 1309 }; 1310 1311 static struct qcom_icc_node xs_pcie_0 = { 1312 .name = "xs_pcie_0", 1313 .channels = 1, 1314 .buswidth = 8, 1315 }; 1316 1317 static struct qcom_icc_node xs_pcie_1 = { 1318 .name = "xs_pcie_1", 1319 .channels = 1, 1320 .buswidth = 8, 1321 }; 1322 1323 static struct qcom_icc_node xs_pcie_modem = { 1324 .name = "xs_pcie_modem", 1325 .channels = 1, 1326 .buswidth = 8, 1327 }; 1328 1329 static struct qcom_icc_node xs_qdss_stm = { 1330 .name = "xs_qdss_stm", 1331 .channels = 1, 1332 .buswidth = 4, 1333 }; 1334 1335 static struct qcom_icc_node xs_sys_tcu_cfg = { 1336 .name = "xs_sys_tcu_cfg", 1337 .channels = 1, 1338 .buswidth = 8, 1339 }; 1340 1341 static struct qcom_icc_node qup0_core_master = { 1342 .name = "qup0_core_master", 1343 .channels = 1, 1344 .buswidth = 4, 1345 .num_links = 1, 1346 .link_nodes = { &qup0_core_slave }, 1347 }; 1348 1349 static struct qcom_icc_node qup1_core_master = { 1350 .name = "qup1_core_master", 1351 .channels = 1, 1352 .buswidth = 4, 1353 .num_links = 1, 1354 .link_nodes = { &qup1_core_slave }, 1355 }; 1356 1357 static struct qcom_icc_node qup2_core_master = { 1358 .name = "qup2_core_master", 1359 .channels = 1, 1360 .buswidth = 4, 1361 .num_links = 1, 1362 .link_nodes = { &qup2_core_slave }, 1363 }; 1364 1365 static struct qcom_icc_node qup0_core_slave = { 1366 .name = "qup0_core_slave", 1367 .channels = 1, 1368 .buswidth = 4, 1369 }; 1370 1371 static struct qcom_icc_node qup1_core_slave = { 1372 .name = "qup1_core_slave", 1373 .channels = 1, 1374 .buswidth = 4, 1375 }; 1376 1377 static struct qcom_icc_node qup2_core_slave = { 1378 .name = "qup2_core_slave", 1379 .channels = 1, 1380 .buswidth = 4, 1381 }; 1382 1383 static struct qcom_icc_bcm bcm_acv = { 1384 .name = "ACV", 1385 .enable_mask = BIT(3), 1386 .keepalive = false, 1387 .num_nodes = 1, 1388 .nodes = { &ebi }, 1389 }; 1390 1391 static struct qcom_icc_bcm bcm_mc0 = { 1392 .name = "MC0", 1393 .keepalive = true, 1394 .num_nodes = 1, 1395 .nodes = { &ebi }, 1396 }; 1397 1398 static struct qcom_icc_bcm bcm_sh0 = { 1399 .name = "SH0", 1400 .keepalive = true, 1401 .num_nodes = 1, 1402 .nodes = { &qns_llcc }, 1403 }; 1404 1405 static struct qcom_icc_bcm bcm_mm0 = { 1406 .name = "MM0", 1407 .keepalive = true, 1408 .num_nodes = 1, 1409 .nodes = { &qns_mem_noc_hf }, 1410 }; 1411 1412 static struct qcom_icc_bcm bcm_ce0 = { 1413 .name = "CE0", 1414 .keepalive = false, 1415 .num_nodes = 1, 1416 .nodes = { &qxm_crypto }, 1417 }; 1418 1419 static struct qcom_icc_bcm bcm_mm1 = { 1420 .name = "MM1", 1421 .keepalive = false, 1422 .num_nodes = 3, 1423 .nodes = { &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1 }, 1424 }; 1425 1426 static struct qcom_icc_bcm bcm_sh2 = { 1427 .name = "SH2", 1428 .keepalive = false, 1429 .num_nodes = 2, 1430 .nodes = { &alm_gpu_tcu, &alm_sys_tcu }, 1431 }; 1432 1433 static struct qcom_icc_bcm bcm_mm2 = { 1434 .name = "MM2", 1435 .keepalive = false, 1436 .num_nodes = 1, 1437 .nodes = { &qns_mem_noc_sf }, 1438 }; 1439 1440 static struct qcom_icc_bcm bcm_qup0 = { 1441 .name = "QUP0", 1442 .keepalive = false, 1443 .num_nodes = 3, 1444 .nodes = { &qup0_core_master, &qup1_core_master, &qup2_core_master }, 1445 }; 1446 1447 static struct qcom_icc_bcm bcm_sh3 = { 1448 .name = "SH3", 1449 .keepalive = false, 1450 .num_nodes = 1, 1451 .nodes = { &qnm_cmpnoc }, 1452 }; 1453 1454 static struct qcom_icc_bcm bcm_mm3 = { 1455 .name = "MM3", 1456 .keepalive = false, 1457 .num_nodes = 5, 1458 .nodes = { &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &qnm_video_cvp }, 1459 }; 1460 1461 static struct qcom_icc_bcm bcm_sh4 = { 1462 .name = "SH4", 1463 .keepalive = false, 1464 .num_nodes = 1, 1465 .nodes = { &chm_apps }, 1466 }; 1467 1468 static struct qcom_icc_bcm bcm_sn0 = { 1469 .name = "SN0", 1470 .keepalive = true, 1471 .num_nodes = 1, 1472 .nodes = { &qns_gemnoc_sf }, 1473 }; 1474 1475 static struct qcom_icc_bcm bcm_co0 = { 1476 .name = "CO0", 1477 .keepalive = false, 1478 .num_nodes = 1, 1479 .nodes = { &qns_cdsp_mem_noc }, 1480 }; 1481 1482 static struct qcom_icc_bcm bcm_cn0 = { 1483 .name = "CN0", 1484 .keepalive = true, 1485 .num_nodes = 52, 1486 .nodes = { &qnm_snoc, 1487 &xm_qdss_dap, 1488 &qhs_a1_noc_cfg, 1489 &qhs_a2_noc_cfg, 1490 &qhs_ahb2phy0, 1491 &qhs_ahb2phy1, 1492 &qhs_aoss, 1493 &qhs_camera_cfg, 1494 &qhs_clk_ctl, 1495 &qhs_compute_dsp, 1496 &qhs_cpr_cx, 1497 &qhs_cpr_mmcx, 1498 &qhs_cpr_mx, 1499 &qhs_crypto0_cfg, 1500 &qhs_cx_rdpm, 1501 &qhs_dcc_cfg, 1502 &qhs_ddrss_cfg, 1503 &qhs_display_cfg, 1504 &qhs_gpuss_cfg, 1505 &qhs_imem_cfg, 1506 &qhs_ipa, 1507 &qhs_ipc_router, 1508 &qhs_lpass_cfg, 1509 &qhs_mnoc_cfg, 1510 &qhs_npu_cfg, 1511 &qhs_pcie0_cfg, 1512 &qhs_pcie1_cfg, 1513 &qhs_pcie_modem_cfg, 1514 &qhs_pdm, 1515 &qhs_pimem_cfg, 1516 &qhs_prng, 1517 &qhs_qdss_cfg, 1518 &qhs_qspi, 1519 &qhs_qup0, 1520 &qhs_qup1, 1521 &qhs_qup2, 1522 &qhs_sdc2, 1523 &qhs_sdc4, 1524 &qhs_snoc_cfg, 1525 &qhs_tcsr, 1526 &qhs_tlmm0, 1527 &qhs_tlmm1, 1528 &qhs_tlmm2, 1529 &qhs_tsif, 1530 &qhs_ufs_card_cfg, 1531 &qhs_ufs_mem_cfg, 1532 &qhs_usb3_0, 1533 &qhs_usb3_1, 1534 &qhs_venus_cfg, 1535 &qhs_vsense_ctrl_cfg, 1536 &qns_cnoc_a2noc, 1537 &srvc_cnoc 1538 }, 1539 }; 1540 1541 static struct qcom_icc_bcm bcm_sn1 = { 1542 .name = "SN1", 1543 .keepalive = false, 1544 .num_nodes = 1, 1545 .nodes = { &qxs_imem }, 1546 }; 1547 1548 static struct qcom_icc_bcm bcm_sn2 = { 1549 .name = "SN2", 1550 .keepalive = false, 1551 .num_nodes = 1, 1552 .nodes = { &qns_gemnoc_gc }, 1553 }; 1554 1555 static struct qcom_icc_bcm bcm_co2 = { 1556 .name = "CO2", 1557 .keepalive = false, 1558 .num_nodes = 1, 1559 .nodes = { &qnm_npu }, 1560 }; 1561 1562 static struct qcom_icc_bcm bcm_sn3 = { 1563 .name = "SN3", 1564 .keepalive = false, 1565 .num_nodes = 1, 1566 .nodes = { &qxs_pimem }, 1567 }; 1568 1569 static struct qcom_icc_bcm bcm_sn4 = { 1570 .name = "SN4", 1571 .keepalive = false, 1572 .num_nodes = 1, 1573 .nodes = { &xs_qdss_stm }, 1574 }; 1575 1576 static struct qcom_icc_bcm bcm_sn5 = { 1577 .name = "SN5", 1578 .keepalive = false, 1579 .num_nodes = 1, 1580 .nodes = { &xs_pcie_modem }, 1581 }; 1582 1583 static struct qcom_icc_bcm bcm_sn6 = { 1584 .name = "SN6", 1585 .keepalive = false, 1586 .num_nodes = 2, 1587 .nodes = { &xs_pcie_0, &xs_pcie_1 }, 1588 }; 1589 1590 static struct qcom_icc_bcm bcm_sn7 = { 1591 .name = "SN7", 1592 .keepalive = false, 1593 .num_nodes = 1, 1594 .nodes = { &qnm_aggre1_noc }, 1595 }; 1596 1597 static struct qcom_icc_bcm bcm_sn8 = { 1598 .name = "SN8", 1599 .keepalive = false, 1600 .num_nodes = 1, 1601 .nodes = { &qnm_aggre2_noc }, 1602 }; 1603 1604 static struct qcom_icc_bcm bcm_sn9 = { 1605 .name = "SN9", 1606 .keepalive = false, 1607 .num_nodes = 1, 1608 .nodes = { &qnm_gemnoc_pcie }, 1609 }; 1610 1611 static struct qcom_icc_bcm bcm_sn11 = { 1612 .name = "SN11", 1613 .keepalive = false, 1614 .num_nodes = 1, 1615 .nodes = { &qnm_gemnoc }, 1616 }; 1617 1618 static struct qcom_icc_bcm bcm_sn12 = { 1619 .name = "SN12", 1620 .keepalive = false, 1621 .num_nodes = 2, 1622 .nodes = { &qns_pcie_modem_mem_noc, &qns_pcie_mem_noc }, 1623 }; 1624 1625 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 1626 &bcm_sn12, 1627 }; 1628 1629 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1630 [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg, 1631 [MASTER_QSPI_0] = &qhm_qspi, 1632 [MASTER_QUP_1] = &qhm_qup1, 1633 [MASTER_QUP_2] = &qhm_qup2, 1634 [MASTER_TSIF] = &qhm_tsif, 1635 [MASTER_PCIE_2] = &xm_pcie3_modem, 1636 [MASTER_SDCC_4] = &xm_sdc4, 1637 [MASTER_UFS_MEM] = &xm_ufs_mem, 1638 [MASTER_USB3] = &xm_usb3_0, 1639 [MASTER_USB3_1] = &xm_usb3_1, 1640 [A1NOC_SNOC_SLV] = &qns_a1noc_snoc, 1641 [SLAVE_ANOC_PCIE_GEM_NOC_1] = &qns_pcie_modem_mem_noc, 1642 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, 1643 }; 1644 1645 static const struct qcom_icc_desc sm8250_aggre1_noc = { 1646 .nodes = aggre1_noc_nodes, 1647 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 1648 .bcms = aggre1_noc_bcms, 1649 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 1650 }; 1651 1652 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 1653 &bcm_ce0, 1654 &bcm_sn12, 1655 }; 1656 1657 static struct qcom_icc_bcm * const qup_virt_bcms[] = { 1658 &bcm_qup0, 1659 }; 1660 1661 static struct qcom_icc_node * const qup_virt_nodes[] = { 1662 [MASTER_QUP_CORE_0] = &qup0_core_master, 1663 [MASTER_QUP_CORE_1] = &qup1_core_master, 1664 [MASTER_QUP_CORE_2] = &qup2_core_master, 1665 [SLAVE_QUP_CORE_0] = &qup0_core_slave, 1666 [SLAVE_QUP_CORE_1] = &qup1_core_slave, 1667 [SLAVE_QUP_CORE_2] = &qup2_core_slave, 1668 }; 1669 1670 static const struct qcom_icc_desc sm8250_qup_virt = { 1671 .nodes = qup_virt_nodes, 1672 .num_nodes = ARRAY_SIZE(qup_virt_nodes), 1673 .bcms = qup_virt_bcms, 1674 .num_bcms = ARRAY_SIZE(qup_virt_bcms), 1675 }; 1676 1677 static struct qcom_icc_node * const aggre2_noc_nodes[] = { 1678 [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg, 1679 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 1680 [MASTER_QUP_0] = &qhm_qup0, 1681 [MASTER_CNOC_A2NOC] = &qnm_cnoc, 1682 [MASTER_CRYPTO_CORE_0] = &qxm_crypto, 1683 [MASTER_IPA] = &qxm_ipa, 1684 [MASTER_PCIE] = &xm_pcie3_0, 1685 [MASTER_PCIE_1] = &xm_pcie3_1, 1686 [MASTER_QDSS_ETR] = &xm_qdss_etr, 1687 [MASTER_SDCC_2] = &xm_sdc2, 1688 [MASTER_UFS_CARD] = &xm_ufs_card, 1689 [A2NOC_SNOC_SLV] = &qns_a2noc_snoc, 1690 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, 1691 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, 1692 }; 1693 1694 static const struct qcom_icc_desc sm8250_aggre2_noc = { 1695 .nodes = aggre2_noc_nodes, 1696 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 1697 .bcms = aggre2_noc_bcms, 1698 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 1699 }; 1700 1701 static struct qcom_icc_bcm * const compute_noc_bcms[] = { 1702 &bcm_co0, 1703 &bcm_co2, 1704 }; 1705 1706 static struct qcom_icc_node * const compute_noc_nodes[] = { 1707 [MASTER_NPU] = &qnm_npu, 1708 [SLAVE_CDSP_MEM_NOC] = &qns_cdsp_mem_noc, 1709 }; 1710 1711 static const struct qcom_icc_desc sm8250_compute_noc = { 1712 .nodes = compute_noc_nodes, 1713 .num_nodes = ARRAY_SIZE(compute_noc_nodes), 1714 .bcms = compute_noc_bcms, 1715 .num_bcms = ARRAY_SIZE(compute_noc_bcms), 1716 }; 1717 1718 static struct qcom_icc_bcm * const config_noc_bcms[] = { 1719 &bcm_cn0, 1720 }; 1721 1722 static struct qcom_icc_node * const config_noc_nodes[] = { 1723 [SNOC_CNOC_MAS] = &qnm_snoc, 1724 [MASTER_QDSS_DAP] = &xm_qdss_dap, 1725 [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg, 1726 [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg, 1727 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, 1728 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1, 1729 [SLAVE_AOSS] = &qhs_aoss, 1730 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 1731 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1732 [SLAVE_CDSP_CFG] = &qhs_compute_dsp, 1733 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 1734 [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx, 1735 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, 1736 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1737 [SLAVE_CX_RDPM] = &qhs_cx_rdpm, 1738 [SLAVE_DCC_CFG] = &qhs_dcc_cfg, 1739 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg, 1740 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 1741 [SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg, 1742 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1743 [SLAVE_IPA_CFG] = &qhs_ipa, 1744 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, 1745 [SLAVE_LPASS] = &qhs_lpass_cfg, 1746 [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg, 1747 [SLAVE_NPU_CFG] = &qhs_npu_cfg, 1748 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, 1749 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, 1750 [SLAVE_PCIE_2_CFG] = &qhs_pcie_modem_cfg, 1751 [SLAVE_PDM] = &qhs_pdm, 1752 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 1753 [SLAVE_PRNG] = &qhs_prng, 1754 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1755 [SLAVE_QSPI_0] = &qhs_qspi, 1756 [SLAVE_QUP_0] = &qhs_qup0, 1757 [SLAVE_QUP_1] = &qhs_qup1, 1758 [SLAVE_QUP_2] = &qhs_qup2, 1759 [SLAVE_SDCC_2] = &qhs_sdc2, 1760 [SLAVE_SDCC_4] = &qhs_sdc4, 1761 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, 1762 [SLAVE_TCSR] = &qhs_tcsr, 1763 [SLAVE_TLMM_NORTH] = &qhs_tlmm0, 1764 [SLAVE_TLMM_SOUTH] = &qhs_tlmm1, 1765 [SLAVE_TLMM_WEST] = &qhs_tlmm2, 1766 [SLAVE_TSIF] = &qhs_tsif, 1767 [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg, 1768 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 1769 [SLAVE_USB3] = &qhs_usb3_0, 1770 [SLAVE_USB3_1] = &qhs_usb3_1, 1771 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1772 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 1773 [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc, 1774 [SLAVE_SERVICE_CNOC] = &srvc_cnoc, 1775 }; 1776 1777 static const struct qcom_icc_desc sm8250_config_noc = { 1778 .nodes = config_noc_nodes, 1779 .num_nodes = ARRAY_SIZE(config_noc_nodes), 1780 .bcms = config_noc_bcms, 1781 .num_bcms = ARRAY_SIZE(config_noc_bcms), 1782 }; 1783 1784 static struct qcom_icc_bcm * const dc_noc_bcms[] = { 1785 }; 1786 1787 static struct qcom_icc_node * const dc_noc_nodes[] = { 1788 [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc, 1789 [SLAVE_LLCC_CFG] = &qhs_llcc, 1790 [SLAVE_GEM_NOC_CFG] = &qhs_memnoc, 1791 }; 1792 1793 static const struct qcom_icc_desc sm8250_dc_noc = { 1794 .nodes = dc_noc_nodes, 1795 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 1796 .bcms = dc_noc_bcms, 1797 .num_bcms = ARRAY_SIZE(dc_noc_bcms), 1798 }; 1799 1800 static struct qcom_icc_bcm * const gem_noc_bcms[] = { 1801 &bcm_sh0, 1802 &bcm_sh2, 1803 &bcm_sh3, 1804 &bcm_sh4, 1805 }; 1806 1807 static struct qcom_icc_node * const gem_noc_nodes[] = { 1808 [MASTER_GPU_TCU] = &alm_gpu_tcu, 1809 [MASTER_SYS_TCU] = &alm_sys_tcu, 1810 [MASTER_AMPSS_M0] = &chm_apps, 1811 [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg, 1812 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc, 1813 [MASTER_GRAPHICS_3D] = &qnm_gpu, 1814 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 1815 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 1816 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, 1817 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 1818 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 1819 [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc, 1820 [SLAVE_LLCC] = &qns_llcc, 1821 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_sys_pcie, 1822 [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc, 1823 [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc, 1824 [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc, 1825 }; 1826 1827 static const struct qcom_icc_desc sm8250_gem_noc = { 1828 .nodes = gem_noc_nodes, 1829 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 1830 .bcms = gem_noc_bcms, 1831 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 1832 }; 1833 1834 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 1835 &bcm_acv, 1836 &bcm_mc0, 1837 }; 1838 1839 static struct qcom_icc_node * const mc_virt_nodes[] = { 1840 [MASTER_LLCC] = &llcc_mc, 1841 [SLAVE_EBI_CH0] = &ebi, 1842 }; 1843 1844 static const struct qcom_icc_desc sm8250_mc_virt = { 1845 .nodes = mc_virt_nodes, 1846 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 1847 .bcms = mc_virt_bcms, 1848 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 1849 }; 1850 1851 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 1852 &bcm_mm0, 1853 &bcm_mm1, 1854 &bcm_mm2, 1855 &bcm_mm3, 1856 }; 1857 1858 static struct qcom_icc_node * const mmss_noc_nodes[] = { 1859 [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg, 1860 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, 1861 [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp, 1862 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, 1863 [MASTER_VIDEO_P0] = &qnm_video0, 1864 [MASTER_VIDEO_P1] = &qnm_video1, 1865 [MASTER_VIDEO_PROC] = &qnm_video_cvp, 1866 [MASTER_MDP_PORT0] = &qxm_mdp0, 1867 [MASTER_MDP_PORT1] = &qxm_mdp1, 1868 [MASTER_ROTATOR] = &qxm_rot, 1869 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 1870 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, 1871 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 1872 }; 1873 1874 static const struct qcom_icc_desc sm8250_mmss_noc = { 1875 .nodes = mmss_noc_nodes, 1876 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 1877 .bcms = mmss_noc_bcms, 1878 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 1879 }; 1880 1881 static struct qcom_icc_bcm * const npu_noc_bcms[] = { 1882 }; 1883 1884 static struct qcom_icc_node * const npu_noc_nodes[] = { 1885 [MASTER_NPU_SYS] = &amm_npu_sys, 1886 [MASTER_NPU_CDP] = &amm_npu_sys_cdp_w, 1887 [MASTER_NPU_NOC_CFG] = &qhm_cfg, 1888 [SLAVE_NPU_CAL_DP0] = &qhs_cal_dp0, 1889 [SLAVE_NPU_CAL_DP1] = &qhs_cal_dp1, 1890 [SLAVE_NPU_CP] = &qhs_cp, 1891 [SLAVE_NPU_INT_DMA_BWMON_CFG] = &qhs_dma_bwmon, 1892 [SLAVE_NPU_DPM] = &qhs_dpm, 1893 [SLAVE_ISENSE_CFG] = &qhs_isense, 1894 [SLAVE_NPU_LLM_CFG] = &qhs_llm, 1895 [SLAVE_NPU_TCM] = &qhs_tcm, 1896 [SLAVE_NPU_COMPUTE_NOC] = &qns_npu_sys, 1897 [SLAVE_SERVICE_NPU_NOC] = &srvc_noc, 1898 }; 1899 1900 static const struct qcom_icc_desc sm8250_npu_noc = { 1901 .nodes = npu_noc_nodes, 1902 .num_nodes = ARRAY_SIZE(npu_noc_nodes), 1903 .bcms = npu_noc_bcms, 1904 .num_bcms = ARRAY_SIZE(npu_noc_bcms), 1905 }; 1906 1907 static struct qcom_icc_bcm * const system_noc_bcms[] = { 1908 &bcm_sn0, 1909 &bcm_sn1, 1910 &bcm_sn11, 1911 &bcm_sn2, 1912 &bcm_sn3, 1913 &bcm_sn4, 1914 &bcm_sn5, 1915 &bcm_sn6, 1916 &bcm_sn7, 1917 &bcm_sn8, 1918 &bcm_sn9, 1919 }; 1920 1921 static struct qcom_icc_node * const system_noc_nodes[] = { 1922 [MASTER_SNOC_CFG] = &qhm_snoc_cfg, 1923 [A1NOC_SNOC_MAS] = &qnm_aggre1_noc, 1924 [A2NOC_SNOC_MAS] = &qnm_aggre2_noc, 1925 [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc, 1926 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, 1927 [MASTER_PIMEM] = &qxm_pimem, 1928 [MASTER_GIC] = &xm_gic, 1929 [SLAVE_APPSS] = &qhs_apss, 1930 [SNOC_CNOC_SLV] = &qns_cnoc, 1931 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, 1932 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 1933 [SLAVE_OCIMEM] = &qxs_imem, 1934 [SLAVE_PIMEM] = &qxs_pimem, 1935 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 1936 [SLAVE_PCIE_0] = &xs_pcie_0, 1937 [SLAVE_PCIE_1] = &xs_pcie_1, 1938 [SLAVE_PCIE_2] = &xs_pcie_modem, 1939 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1940 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1941 }; 1942 1943 static const struct qcom_icc_desc sm8250_system_noc = { 1944 .nodes = system_noc_nodes, 1945 .num_nodes = ARRAY_SIZE(system_noc_nodes), 1946 .bcms = system_noc_bcms, 1947 .num_bcms = ARRAY_SIZE(system_noc_bcms), 1948 }; 1949 1950 static const struct of_device_id qnoc_of_match[] = { 1951 { .compatible = "qcom,sm8250-aggre1-noc", 1952 .data = &sm8250_aggre1_noc}, 1953 { .compatible = "qcom,sm8250-aggre2-noc", 1954 .data = &sm8250_aggre2_noc}, 1955 { .compatible = "qcom,sm8250-compute-noc", 1956 .data = &sm8250_compute_noc}, 1957 { .compatible = "qcom,sm8250-config-noc", 1958 .data = &sm8250_config_noc}, 1959 { .compatible = "qcom,sm8250-dc-noc", 1960 .data = &sm8250_dc_noc}, 1961 { .compatible = "qcom,sm8250-gem-noc", 1962 .data = &sm8250_gem_noc}, 1963 { .compatible = "qcom,sm8250-mc-virt", 1964 .data = &sm8250_mc_virt}, 1965 { .compatible = "qcom,sm8250-mmss-noc", 1966 .data = &sm8250_mmss_noc}, 1967 { .compatible = "qcom,sm8250-npu-noc", 1968 .data = &sm8250_npu_noc}, 1969 { .compatible = "qcom,sm8250-qup-virt", 1970 .data = &sm8250_qup_virt }, 1971 { .compatible = "qcom,sm8250-system-noc", 1972 .data = &sm8250_system_noc}, 1973 { } 1974 }; 1975 MODULE_DEVICE_TABLE(of, qnoc_of_match); 1976 1977 static struct platform_driver qnoc_driver = { 1978 .probe = qcom_icc_rpmh_probe, 1979 .remove = qcom_icc_rpmh_remove, 1980 .driver = { 1981 .name = "qnoc-sm8250", 1982 .of_match_table = qnoc_of_match, 1983 .sync_state = icc_sync_state, 1984 }, 1985 }; 1986 module_platform_driver(qnoc_driver); 1987 1988 MODULE_DESCRIPTION("Qualcomm SM8250 NoC driver"); 1989 MODULE_LICENSE("GPL v2"); 1990