1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 * 5 */ 6 7 #include <linux/device.h> 8 #include <linux/interconnect.h> 9 #include <linux/interconnect-provider.h> 10 #include <linux/mod_devicetable.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <dt-bindings/interconnect/qcom,sm8150.h> 14 15 #include "bcm-voter.h" 16 #include "icc-rpmh.h" 17 18 static struct qcom_icc_node qhm_a1noc_cfg; 19 static struct qcom_icc_node qhm_qup0; 20 static struct qcom_icc_node xm_emac; 21 static struct qcom_icc_node xm_ufs_mem; 22 static struct qcom_icc_node xm_usb3_0; 23 static struct qcom_icc_node xm_usb3_1; 24 static struct qcom_icc_node qhm_a2noc_cfg; 25 static struct qcom_icc_node qhm_qdss_bam; 26 static struct qcom_icc_node qhm_qspi; 27 static struct qcom_icc_node qhm_qup1; 28 static struct qcom_icc_node qhm_qup2; 29 static struct qcom_icc_node qhm_sensorss_ahb; 30 static struct qcom_icc_node qhm_tsif; 31 static struct qcom_icc_node qnm_cnoc; 32 static struct qcom_icc_node qxm_crypto; 33 static struct qcom_icc_node qxm_ipa; 34 static struct qcom_icc_node xm_pcie3_0; 35 static struct qcom_icc_node xm_pcie3_1; 36 static struct qcom_icc_node xm_qdss_etr; 37 static struct qcom_icc_node xm_sdc2; 38 static struct qcom_icc_node xm_sdc4; 39 static struct qcom_icc_node qxm_camnoc_hf0_uncomp; 40 static struct qcom_icc_node qxm_camnoc_hf1_uncomp; 41 static struct qcom_icc_node qxm_camnoc_sf_uncomp; 42 static struct qcom_icc_node qnm_npu; 43 static struct qcom_icc_node qhm_spdm; 44 static struct qcom_icc_node qnm_snoc; 45 static struct qcom_icc_node xm_qdss_dap; 46 static struct qcom_icc_node qhm_cnoc_dc_noc; 47 static struct qcom_icc_node acm_apps; 48 static struct qcom_icc_node acm_gpu_tcu; 49 static struct qcom_icc_node acm_sys_tcu; 50 static struct qcom_icc_node qhm_gemnoc_cfg; 51 static struct qcom_icc_node qnm_cmpnoc; 52 static struct qcom_icc_node qnm_gpu; 53 static struct qcom_icc_node qnm_mnoc_hf; 54 static struct qcom_icc_node qnm_mnoc_sf; 55 static struct qcom_icc_node qnm_pcie; 56 static struct qcom_icc_node qnm_snoc_gc; 57 static struct qcom_icc_node qnm_snoc_sf; 58 static struct qcom_icc_node qxm_ecc; 59 static struct qcom_icc_node llcc_mc; 60 static struct qcom_icc_node qhm_mnoc_cfg; 61 static struct qcom_icc_node qxm_camnoc_hf0; 62 static struct qcom_icc_node qxm_camnoc_hf1; 63 static struct qcom_icc_node qxm_camnoc_sf; 64 static struct qcom_icc_node qxm_mdp0; 65 static struct qcom_icc_node qxm_mdp1; 66 static struct qcom_icc_node qxm_rot; 67 static struct qcom_icc_node qxm_venus0; 68 static struct qcom_icc_node qxm_venus1; 69 static struct qcom_icc_node qxm_venus_arm9; 70 static struct qcom_icc_node qhm_snoc_cfg; 71 static struct qcom_icc_node qnm_aggre1_noc; 72 static struct qcom_icc_node qnm_aggre2_noc; 73 static struct qcom_icc_node qnm_gemnoc; 74 static struct qcom_icc_node qxm_pimem; 75 static struct qcom_icc_node xm_gic; 76 static struct qcom_icc_node qns_a1noc_snoc; 77 static struct qcom_icc_node srvc_aggre1_noc; 78 static struct qcom_icc_node qns_a2noc_snoc; 79 static struct qcom_icc_node qns_pcie_mem_noc; 80 static struct qcom_icc_node srvc_aggre2_noc; 81 static struct qcom_icc_node qns_camnoc_uncomp; 82 static struct qcom_icc_node qns_cdsp_mem_noc; 83 static struct qcom_icc_node qhs_a1_noc_cfg; 84 static struct qcom_icc_node qhs_a2_noc_cfg; 85 static struct qcom_icc_node qhs_ahb2phy_south; 86 static struct qcom_icc_node qhs_aop; 87 static struct qcom_icc_node qhs_aoss; 88 static struct qcom_icc_node qhs_camera_cfg; 89 static struct qcom_icc_node qhs_clk_ctl; 90 static struct qcom_icc_node qhs_compute_dsp; 91 static struct qcom_icc_node qhs_cpr_cx; 92 static struct qcom_icc_node qhs_cpr_mmcx; 93 static struct qcom_icc_node qhs_cpr_mx; 94 static struct qcom_icc_node qhs_crypto0_cfg; 95 static struct qcom_icc_node qhs_ddrss_cfg; 96 static struct qcom_icc_node qhs_display_cfg; 97 static struct qcom_icc_node qhs_emac_cfg; 98 static struct qcom_icc_node qhs_glm; 99 static struct qcom_icc_node qhs_gpuss_cfg; 100 static struct qcom_icc_node qhs_imem_cfg; 101 static struct qcom_icc_node qhs_ipa; 102 static struct qcom_icc_node qhs_mnoc_cfg; 103 static struct qcom_icc_node qhs_npu_cfg; 104 static struct qcom_icc_node qhs_pcie0_cfg; 105 static struct qcom_icc_node qhs_pcie1_cfg; 106 static struct qcom_icc_node qhs_phy_refgen_north; 107 static struct qcom_icc_node qhs_pimem_cfg; 108 static struct qcom_icc_node qhs_prng; 109 static struct qcom_icc_node qhs_qdss_cfg; 110 static struct qcom_icc_node qhs_qspi; 111 static struct qcom_icc_node qhs_qupv3_east; 112 static struct qcom_icc_node qhs_qupv3_north; 113 static struct qcom_icc_node qhs_qupv3_south; 114 static struct qcom_icc_node qhs_sdc2; 115 static struct qcom_icc_node qhs_sdc4; 116 static struct qcom_icc_node qhs_snoc_cfg; 117 static struct qcom_icc_node qhs_spdm; 118 static struct qcom_icc_node qhs_spss_cfg; 119 static struct qcom_icc_node qhs_ssc_cfg; 120 static struct qcom_icc_node qhs_tcsr; 121 static struct qcom_icc_node qhs_tlmm_east; 122 static struct qcom_icc_node qhs_tlmm_north; 123 static struct qcom_icc_node qhs_tlmm_south; 124 static struct qcom_icc_node qhs_tlmm_west; 125 static struct qcom_icc_node qhs_tsif; 126 static struct qcom_icc_node qhs_ufs_card_cfg; 127 static struct qcom_icc_node qhs_ufs_mem_cfg; 128 static struct qcom_icc_node qhs_usb3_0; 129 static struct qcom_icc_node qhs_usb3_1; 130 static struct qcom_icc_node qhs_venus_cfg; 131 static struct qcom_icc_node qhs_vsense_ctrl_cfg; 132 static struct qcom_icc_node qns_cnoc_a2noc; 133 static struct qcom_icc_node srvc_cnoc; 134 static struct qcom_icc_node qhs_llcc; 135 static struct qcom_icc_node qhs_memnoc; 136 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; 137 static struct qcom_icc_node qns_ecc; 138 static struct qcom_icc_node qns_gem_noc_snoc; 139 static struct qcom_icc_node qns_llcc; 140 static struct qcom_icc_node srvc_gemnoc; 141 static struct qcom_icc_node ebi; 142 static struct qcom_icc_node qns2_mem_noc; 143 static struct qcom_icc_node qns_mem_noc_hf; 144 static struct qcom_icc_node srvc_mnoc; 145 static struct qcom_icc_node qhs_apss; 146 static struct qcom_icc_node qns_cnoc; 147 static struct qcom_icc_node qns_gemnoc_gc; 148 static struct qcom_icc_node qns_gemnoc_sf; 149 static struct qcom_icc_node qxs_imem; 150 static struct qcom_icc_node qxs_pimem; 151 static struct qcom_icc_node srvc_snoc; 152 static struct qcom_icc_node xs_pcie_0; 153 static struct qcom_icc_node xs_pcie_1; 154 static struct qcom_icc_node xs_qdss_stm; 155 static struct qcom_icc_node xs_sys_tcu_cfg; 156 157 static struct qcom_icc_node qhm_a1noc_cfg = { 158 .name = "qhm_a1noc_cfg", 159 .channels = 1, 160 .buswidth = 4, 161 .num_links = 1, 162 .link_nodes = { &srvc_aggre1_noc }, 163 }; 164 165 static struct qcom_icc_node qhm_qup0 = { 166 .name = "qhm_qup0", 167 .channels = 1, 168 .buswidth = 4, 169 .num_links = 1, 170 .link_nodes = { &qns_a1noc_snoc }, 171 }; 172 173 static struct qcom_icc_node xm_emac = { 174 .name = "xm_emac", 175 .channels = 1, 176 .buswidth = 8, 177 .num_links = 1, 178 .link_nodes = { &qns_a1noc_snoc }, 179 }; 180 181 static struct qcom_icc_node xm_ufs_mem = { 182 .name = "xm_ufs_mem", 183 .channels = 1, 184 .buswidth = 8, 185 .num_links = 1, 186 .link_nodes = { &qns_a1noc_snoc }, 187 }; 188 189 static struct qcom_icc_node xm_usb3_0 = { 190 .name = "xm_usb3_0", 191 .channels = 1, 192 .buswidth = 8, 193 .num_links = 1, 194 .link_nodes = { &qns_a1noc_snoc }, 195 }; 196 197 static struct qcom_icc_node xm_usb3_1 = { 198 .name = "xm_usb3_1", 199 .channels = 1, 200 .buswidth = 8, 201 .num_links = 1, 202 .link_nodes = { &qns_a1noc_snoc }, 203 }; 204 205 static struct qcom_icc_node qhm_a2noc_cfg = { 206 .name = "qhm_a2noc_cfg", 207 .channels = 1, 208 .buswidth = 4, 209 .num_links = 1, 210 .link_nodes = { &srvc_aggre2_noc }, 211 }; 212 213 static struct qcom_icc_node qhm_qdss_bam = { 214 .name = "qhm_qdss_bam", 215 .channels = 1, 216 .buswidth = 4, 217 .num_links = 1, 218 .link_nodes = { &qns_a2noc_snoc }, 219 }; 220 221 static struct qcom_icc_node qhm_qspi = { 222 .name = "qhm_qspi", 223 .channels = 1, 224 .buswidth = 4, 225 .num_links = 1, 226 .link_nodes = { &qns_a2noc_snoc }, 227 }; 228 229 static struct qcom_icc_node qhm_qup1 = { 230 .name = "qhm_qup1", 231 .channels = 1, 232 .buswidth = 4, 233 .num_links = 1, 234 .link_nodes = { &qns_a2noc_snoc }, 235 }; 236 237 static struct qcom_icc_node qhm_qup2 = { 238 .name = "qhm_qup2", 239 .channels = 1, 240 .buswidth = 4, 241 .num_links = 1, 242 .link_nodes = { &qns_a2noc_snoc }, 243 }; 244 245 static struct qcom_icc_node qhm_sensorss_ahb = { 246 .name = "qhm_sensorss_ahb", 247 .channels = 1, 248 .buswidth = 4, 249 .num_links = 1, 250 .link_nodes = { &qns_a2noc_snoc }, 251 }; 252 253 static struct qcom_icc_node qhm_tsif = { 254 .name = "qhm_tsif", 255 .channels = 1, 256 .buswidth = 4, 257 .num_links = 1, 258 .link_nodes = { &qns_a2noc_snoc }, 259 }; 260 261 static struct qcom_icc_node qnm_cnoc = { 262 .name = "qnm_cnoc", 263 .channels = 1, 264 .buswidth = 8, 265 .num_links = 1, 266 .link_nodes = { &qns_a2noc_snoc }, 267 }; 268 269 static struct qcom_icc_node qxm_crypto = { 270 .name = "qxm_crypto", 271 .channels = 1, 272 .buswidth = 8, 273 .num_links = 1, 274 .link_nodes = { &qns_a2noc_snoc }, 275 }; 276 277 static struct qcom_icc_node qxm_ipa = { 278 .name = "qxm_ipa", 279 .channels = 1, 280 .buswidth = 8, 281 .num_links = 1, 282 .link_nodes = { &qns_a2noc_snoc }, 283 }; 284 285 static struct qcom_icc_node xm_pcie3_0 = { 286 .name = "xm_pcie3_0", 287 .channels = 1, 288 .buswidth = 8, 289 .num_links = 1, 290 .link_nodes = { &qns_pcie_mem_noc }, 291 }; 292 293 static struct qcom_icc_node xm_pcie3_1 = { 294 .name = "xm_pcie3_1", 295 .channels = 1, 296 .buswidth = 8, 297 .num_links = 1, 298 .link_nodes = { &qns_pcie_mem_noc }, 299 }; 300 301 static struct qcom_icc_node xm_qdss_etr = { 302 .name = "xm_qdss_etr", 303 .channels = 1, 304 .buswidth = 8, 305 .num_links = 1, 306 .link_nodes = { &qns_a2noc_snoc }, 307 }; 308 309 static struct qcom_icc_node xm_sdc2 = { 310 .name = "xm_sdc2", 311 .channels = 1, 312 .buswidth = 8, 313 .num_links = 1, 314 .link_nodes = { &qns_a2noc_snoc }, 315 }; 316 317 static struct qcom_icc_node xm_sdc4 = { 318 .name = "xm_sdc4", 319 .channels = 1, 320 .buswidth = 8, 321 .num_links = 1, 322 .link_nodes = { &qns_a2noc_snoc }, 323 }; 324 325 static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { 326 .name = "qxm_camnoc_hf0_uncomp", 327 .channels = 1, 328 .buswidth = 32, 329 .num_links = 1, 330 .link_nodes = { &qns_camnoc_uncomp }, 331 }; 332 333 static struct qcom_icc_node qxm_camnoc_hf1_uncomp = { 334 .name = "qxm_camnoc_hf1_uncomp", 335 .channels = 1, 336 .buswidth = 32, 337 .num_links = 1, 338 .link_nodes = { &qns_camnoc_uncomp }, 339 }; 340 341 static struct qcom_icc_node qxm_camnoc_sf_uncomp = { 342 .name = "qxm_camnoc_sf_uncomp", 343 .channels = 1, 344 .buswidth = 32, 345 .num_links = 1, 346 .link_nodes = { &qns_camnoc_uncomp }, 347 }; 348 349 static struct qcom_icc_node qnm_npu = { 350 .name = "qnm_npu", 351 .channels = 1, 352 .buswidth = 32, 353 .num_links = 1, 354 .link_nodes = { &qns_cdsp_mem_noc }, 355 }; 356 357 static struct qcom_icc_node qhm_spdm = { 358 .name = "qhm_spdm", 359 .channels = 1, 360 .buswidth = 4, 361 .num_links = 1, 362 .link_nodes = { &qns_cnoc_a2noc }, 363 }; 364 365 static struct qcom_icc_node qnm_snoc = { 366 .name = "qnm_snoc", 367 .channels = 1, 368 .buswidth = 8, 369 .num_links = 50, 370 .link_nodes = { &qhs_tlmm_south, 371 &qhs_compute_dsp, 372 &qhs_spss_cfg, 373 &qhs_camera_cfg, 374 &qhs_sdc4, 375 &qhs_sdc2, 376 &qhs_mnoc_cfg, 377 &qhs_emac_cfg, 378 &qhs_ufs_mem_cfg, 379 &qhs_tlmm_east, 380 &qhs_ssc_cfg, 381 &qhs_snoc_cfg, 382 &qhs_phy_refgen_north, 383 &qhs_qupv3_south, 384 &qhs_glm, 385 &qhs_pcie1_cfg, 386 &qhs_a2_noc_cfg, 387 &qhs_qdss_cfg, 388 &qhs_display_cfg, 389 &qhs_tcsr, 390 &qhs_ddrss_cfg, 391 &qhs_cpr_mmcx, 392 &qhs_npu_cfg, 393 &qhs_pcie0_cfg, 394 &qhs_gpuss_cfg, 395 &qhs_venus_cfg, 396 &qhs_tsif, 397 &qhs_ipa, 398 &qhs_clk_ctl, 399 &qhs_aop, 400 &qhs_qupv3_north, 401 &qhs_ahb2phy_south, 402 &qhs_usb3_1, 403 &srvc_cnoc, 404 &qhs_ufs_card_cfg, 405 &qhs_qupv3_east, 406 &qhs_cpr_cx, 407 &qhs_tlmm_west, 408 &qhs_a1_noc_cfg, 409 &qhs_aoss, 410 &qhs_prng, 411 &qhs_vsense_ctrl_cfg, 412 &qhs_qspi, 413 &qhs_usb3_0, 414 &qhs_spdm, 415 &qhs_crypto0_cfg, 416 &qhs_pimem_cfg, 417 &qhs_tlmm_north, 418 &qhs_cpr_mx, 419 &qhs_imem_cfg }, 420 }; 421 422 static struct qcom_icc_node xm_qdss_dap = { 423 .name = "xm_qdss_dap", 424 .channels = 1, 425 .buswidth = 8, 426 .num_links = 51, 427 .link_nodes = { &qhs_tlmm_south, 428 &qhs_compute_dsp, 429 &qhs_spss_cfg, 430 &qhs_camera_cfg, 431 &qhs_sdc4, 432 &qhs_sdc2, 433 &qhs_mnoc_cfg, 434 &qhs_emac_cfg, 435 &qhs_ufs_mem_cfg, 436 &qhs_tlmm_east, 437 &qhs_ssc_cfg, 438 &qhs_snoc_cfg, 439 &qhs_phy_refgen_north, 440 &qhs_qupv3_south, 441 &qhs_glm, 442 &qhs_pcie1_cfg, 443 &qhs_a2_noc_cfg, 444 &qhs_qdss_cfg, 445 &qhs_display_cfg, 446 &qhs_tcsr, 447 &qhs_ddrss_cfg, 448 &qns_cnoc_a2noc, 449 &qhs_cpr_mmcx, 450 &qhs_npu_cfg, 451 &qhs_pcie0_cfg, 452 &qhs_gpuss_cfg, 453 &qhs_venus_cfg, 454 &qhs_tsif, 455 &qhs_ipa, 456 &qhs_clk_ctl, 457 &qhs_aop, 458 &qhs_qupv3_north, 459 &qhs_ahb2phy_south, 460 &qhs_usb3_1, 461 &srvc_cnoc, 462 &qhs_ufs_card_cfg, 463 &qhs_qupv3_east, 464 &qhs_cpr_cx, 465 &qhs_tlmm_west, 466 &qhs_a1_noc_cfg, 467 &qhs_aoss, 468 &qhs_prng, 469 &qhs_vsense_ctrl_cfg, 470 &qhs_qspi, 471 &qhs_usb3_0, 472 &qhs_spdm, 473 &qhs_crypto0_cfg, 474 &qhs_pimem_cfg, 475 &qhs_tlmm_north, 476 &qhs_cpr_mx, 477 &qhs_imem_cfg }, 478 }; 479 480 static struct qcom_icc_node qhm_cnoc_dc_noc = { 481 .name = "qhm_cnoc_dc_noc", 482 .channels = 1, 483 .buswidth = 4, 484 .num_links = 2, 485 .link_nodes = { &qhs_memnoc, 486 &qhs_llcc }, 487 }; 488 489 static struct qcom_icc_node acm_apps = { 490 .name = "acm_apps", 491 .channels = 2, 492 .buswidth = 32, 493 .num_links = 3, 494 .link_nodes = { &qns_ecc, 495 &qns_llcc, 496 &qns_gem_noc_snoc }, 497 }; 498 499 static struct qcom_icc_node acm_gpu_tcu = { 500 .name = "acm_gpu_tcu", 501 .channels = 1, 502 .buswidth = 8, 503 .num_links = 2, 504 .link_nodes = { &qns_llcc, 505 &qns_gem_noc_snoc }, 506 }; 507 508 static struct qcom_icc_node acm_sys_tcu = { 509 .name = "acm_sys_tcu", 510 .channels = 1, 511 .buswidth = 8, 512 .num_links = 2, 513 .link_nodes = { &qns_llcc, 514 &qns_gem_noc_snoc }, 515 }; 516 517 static struct qcom_icc_node qhm_gemnoc_cfg = { 518 .name = "qhm_gemnoc_cfg", 519 .channels = 1, 520 .buswidth = 4, 521 .num_links = 2, 522 .link_nodes = { &srvc_gemnoc, 523 &qhs_mdsp_ms_mpu_cfg }, 524 }; 525 526 static struct qcom_icc_node qnm_cmpnoc = { 527 .name = "qnm_cmpnoc", 528 .channels = 2, 529 .buswidth = 32, 530 .num_links = 3, 531 .link_nodes = { &qns_ecc, 532 &qns_llcc, 533 &qns_gem_noc_snoc }, 534 }; 535 536 static struct qcom_icc_node qnm_gpu = { 537 .name = "qnm_gpu", 538 .channels = 2, 539 .buswidth = 32, 540 .num_links = 2, 541 .link_nodes = { &qns_llcc, 542 &qns_gem_noc_snoc }, 543 }; 544 545 static struct qcom_icc_node qnm_mnoc_hf = { 546 .name = "qnm_mnoc_hf", 547 .channels = 2, 548 .buswidth = 32, 549 .num_links = 1, 550 .link_nodes = { &qns_llcc }, 551 }; 552 553 static struct qcom_icc_node qnm_mnoc_sf = { 554 .name = "qnm_mnoc_sf", 555 .channels = 1, 556 .buswidth = 32, 557 .num_links = 2, 558 .link_nodes = { &qns_llcc, 559 &qns_gem_noc_snoc }, 560 }; 561 562 static struct qcom_icc_node qnm_pcie = { 563 .name = "qnm_pcie", 564 .channels = 1, 565 .buswidth = 16, 566 .num_links = 2, 567 .link_nodes = { &qns_llcc, 568 &qns_gem_noc_snoc }, 569 }; 570 571 static struct qcom_icc_node qnm_snoc_gc = { 572 .name = "qnm_snoc_gc", 573 .channels = 1, 574 .buswidth = 8, 575 .num_links = 1, 576 .link_nodes = { &qns_llcc }, 577 }; 578 579 static struct qcom_icc_node qnm_snoc_sf = { 580 .name = "qnm_snoc_sf", 581 .channels = 1, 582 .buswidth = 16, 583 .num_links = 1, 584 .link_nodes = { &qns_llcc }, 585 }; 586 587 static struct qcom_icc_node qxm_ecc = { 588 .name = "qxm_ecc", 589 .channels = 2, 590 .buswidth = 32, 591 .num_links = 1, 592 .link_nodes = { &qns_llcc }, 593 }; 594 595 static struct qcom_icc_node llcc_mc = { 596 .name = "llcc_mc", 597 .channels = 4, 598 .buswidth = 4, 599 .num_links = 1, 600 .link_nodes = { &ebi }, 601 }; 602 603 static struct qcom_icc_node qhm_mnoc_cfg = { 604 .name = "qhm_mnoc_cfg", 605 .channels = 1, 606 .buswidth = 4, 607 .num_links = 1, 608 .link_nodes = { &srvc_mnoc }, 609 }; 610 611 static struct qcom_icc_node qxm_camnoc_hf0 = { 612 .name = "qxm_camnoc_hf0", 613 .channels = 1, 614 .buswidth = 32, 615 .num_links = 1, 616 .link_nodes = { &qns_mem_noc_hf }, 617 }; 618 619 static struct qcom_icc_node qxm_camnoc_hf1 = { 620 .name = "qxm_camnoc_hf1", 621 .channels = 1, 622 .buswidth = 32, 623 .num_links = 1, 624 .link_nodes = { &qns_mem_noc_hf }, 625 }; 626 627 static struct qcom_icc_node qxm_camnoc_sf = { 628 .name = "qxm_camnoc_sf", 629 .channels = 1, 630 .buswidth = 32, 631 .num_links = 1, 632 .link_nodes = { &qns2_mem_noc }, 633 }; 634 635 static struct qcom_icc_node qxm_mdp0 = { 636 .name = "qxm_mdp0", 637 .channels = 1, 638 .buswidth = 32, 639 .num_links = 1, 640 .link_nodes = { &qns_mem_noc_hf }, 641 }; 642 643 static struct qcom_icc_node qxm_mdp1 = { 644 .name = "qxm_mdp1", 645 .channels = 1, 646 .buswidth = 32, 647 .num_links = 1, 648 .link_nodes = { &qns_mem_noc_hf }, 649 }; 650 651 static struct qcom_icc_node qxm_rot = { 652 .name = "qxm_rot", 653 .channels = 1, 654 .buswidth = 32, 655 .num_links = 1, 656 .link_nodes = { &qns2_mem_noc }, 657 }; 658 659 static struct qcom_icc_node qxm_venus0 = { 660 .name = "qxm_venus0", 661 .channels = 1, 662 .buswidth = 32, 663 .num_links = 1, 664 .link_nodes = { &qns2_mem_noc }, 665 }; 666 667 static struct qcom_icc_node qxm_venus1 = { 668 .name = "qxm_venus1", 669 .channels = 1, 670 .buswidth = 32, 671 .num_links = 1, 672 .link_nodes = { &qns2_mem_noc }, 673 }; 674 675 static struct qcom_icc_node qxm_venus_arm9 = { 676 .name = "qxm_venus_arm9", 677 .channels = 1, 678 .buswidth = 8, 679 .num_links = 1, 680 .link_nodes = { &qns2_mem_noc }, 681 }; 682 683 static struct qcom_icc_node qhm_snoc_cfg = { 684 .name = "qhm_snoc_cfg", 685 .channels = 1, 686 .buswidth = 4, 687 .num_links = 1, 688 .link_nodes = { &srvc_snoc }, 689 }; 690 691 static struct qcom_icc_node qnm_aggre1_noc = { 692 .name = "qnm_aggre1_noc", 693 .channels = 1, 694 .buswidth = 16, 695 .num_links = 6, 696 .link_nodes = { &qns_gemnoc_sf, 697 &qxs_pimem, 698 &qxs_imem, 699 &qhs_apss, 700 &qns_cnoc, 701 &xs_qdss_stm }, 702 }; 703 704 static struct qcom_icc_node qnm_aggre2_noc = { 705 .name = "qnm_aggre2_noc", 706 .channels = 1, 707 .buswidth = 16, 708 .num_links = 9, 709 .link_nodes = { &qns_gemnoc_sf, 710 &qxs_pimem, 711 &qxs_imem, 712 &qhs_apss, 713 &qns_cnoc, 714 &xs_pcie_0, 715 &xs_pcie_1, 716 &xs_sys_tcu_cfg, 717 &xs_qdss_stm }, 718 }; 719 720 static struct qcom_icc_node qnm_gemnoc = { 721 .name = "qnm_gemnoc", 722 .channels = 1, 723 .buswidth = 8, 724 .num_links = 6, 725 .link_nodes = { &qxs_pimem, 726 &qxs_imem, 727 &qhs_apss, 728 &qns_cnoc, 729 &xs_sys_tcu_cfg, 730 &xs_qdss_stm }, 731 }; 732 733 static struct qcom_icc_node qxm_pimem = { 734 .name = "qxm_pimem", 735 .channels = 1, 736 .buswidth = 8, 737 .num_links = 2, 738 .link_nodes = { &qns_gemnoc_gc, 739 &qxs_imem }, 740 }; 741 742 static struct qcom_icc_node xm_gic = { 743 .name = "xm_gic", 744 .channels = 1, 745 .buswidth = 8, 746 .num_links = 2, 747 .link_nodes = { &qns_gemnoc_gc, 748 &qxs_imem }, 749 }; 750 751 static struct qcom_icc_node qns_a1noc_snoc = { 752 .name = "qns_a1noc_snoc", 753 .channels = 1, 754 .buswidth = 16, 755 .num_links = 1, 756 .link_nodes = { &qnm_aggre1_noc }, 757 }; 758 759 static struct qcom_icc_node srvc_aggre1_noc = { 760 .name = "srvc_aggre1_noc", 761 .channels = 1, 762 .buswidth = 4, 763 }; 764 765 static struct qcom_icc_node qns_a2noc_snoc = { 766 .name = "qns_a2noc_snoc", 767 .channels = 1, 768 .buswidth = 16, 769 .num_links = 1, 770 .link_nodes = { &qnm_aggre2_noc }, 771 }; 772 773 static struct qcom_icc_node qns_pcie_mem_noc = { 774 .name = "qns_pcie_mem_noc", 775 .channels = 1, 776 .buswidth = 16, 777 .num_links = 1, 778 .link_nodes = { &qnm_pcie }, 779 }; 780 781 static struct qcom_icc_node srvc_aggre2_noc = { 782 .name = "srvc_aggre2_noc", 783 .channels = 1, 784 .buswidth = 4, 785 }; 786 787 static struct qcom_icc_node qns_camnoc_uncomp = { 788 .name = "qns_camnoc_uncomp", 789 .channels = 1, 790 .buswidth = 32, 791 }; 792 793 static struct qcom_icc_node qns_cdsp_mem_noc = { 794 .name = "qns_cdsp_mem_noc", 795 .channels = 2, 796 .buswidth = 32, 797 .num_links = 1, 798 .link_nodes = { &qnm_cmpnoc }, 799 }; 800 801 static struct qcom_icc_node qhs_a1_noc_cfg = { 802 .name = "qhs_a1_noc_cfg", 803 .channels = 1, 804 .buswidth = 4, 805 .num_links = 1, 806 .link_nodes = { &qhm_a1noc_cfg }, 807 }; 808 809 static struct qcom_icc_node qhs_a2_noc_cfg = { 810 .name = "qhs_a2_noc_cfg", 811 .channels = 1, 812 .buswidth = 4, 813 .num_links = 1, 814 .link_nodes = { &qhm_a2noc_cfg }, 815 }; 816 817 static struct qcom_icc_node qhs_ahb2phy_south = { 818 .name = "qhs_ahb2phy_south", 819 .channels = 1, 820 .buswidth = 4, 821 }; 822 823 static struct qcom_icc_node qhs_aop = { 824 .name = "qhs_aop", 825 .channels = 1, 826 .buswidth = 4, 827 }; 828 829 static struct qcom_icc_node qhs_aoss = { 830 .name = "qhs_aoss", 831 .channels = 1, 832 .buswidth = 4, 833 }; 834 835 static struct qcom_icc_node qhs_camera_cfg = { 836 .name = "qhs_camera_cfg", 837 .channels = 1, 838 .buswidth = 4, 839 }; 840 841 static struct qcom_icc_node qhs_clk_ctl = { 842 .name = "qhs_clk_ctl", 843 .channels = 1, 844 .buswidth = 4, 845 }; 846 847 static struct qcom_icc_node qhs_compute_dsp = { 848 .name = "qhs_compute_dsp", 849 .channels = 1, 850 .buswidth = 4, 851 }; 852 853 static struct qcom_icc_node qhs_cpr_cx = { 854 .name = "qhs_cpr_cx", 855 .channels = 1, 856 .buswidth = 4, 857 }; 858 859 static struct qcom_icc_node qhs_cpr_mmcx = { 860 .name = "qhs_cpr_mmcx", 861 .channels = 1, 862 .buswidth = 4, 863 }; 864 865 static struct qcom_icc_node qhs_cpr_mx = { 866 .name = "qhs_cpr_mx", 867 .channels = 1, 868 .buswidth = 4, 869 }; 870 871 static struct qcom_icc_node qhs_crypto0_cfg = { 872 .name = "qhs_crypto0_cfg", 873 .channels = 1, 874 .buswidth = 4, 875 }; 876 877 static struct qcom_icc_node qhs_ddrss_cfg = { 878 .name = "qhs_ddrss_cfg", 879 .channels = 1, 880 .buswidth = 4, 881 .num_links = 1, 882 .link_nodes = { &qhm_cnoc_dc_noc }, 883 }; 884 885 static struct qcom_icc_node qhs_display_cfg = { 886 .name = "qhs_display_cfg", 887 .channels = 1, 888 .buswidth = 4, 889 }; 890 891 static struct qcom_icc_node qhs_emac_cfg = { 892 .name = "qhs_emac_cfg", 893 .channels = 1, 894 .buswidth = 4, 895 }; 896 897 static struct qcom_icc_node qhs_glm = { 898 .name = "qhs_glm", 899 .channels = 1, 900 .buswidth = 4, 901 }; 902 903 static struct qcom_icc_node qhs_gpuss_cfg = { 904 .name = "qhs_gpuss_cfg", 905 .channels = 1, 906 .buswidth = 8, 907 }; 908 909 static struct qcom_icc_node qhs_imem_cfg = { 910 .name = "qhs_imem_cfg", 911 .channels = 1, 912 .buswidth = 4, 913 }; 914 915 static struct qcom_icc_node qhs_ipa = { 916 .name = "qhs_ipa", 917 .channels = 1, 918 .buswidth = 4, 919 }; 920 921 static struct qcom_icc_node qhs_mnoc_cfg = { 922 .name = "qhs_mnoc_cfg", 923 .channels = 1, 924 .buswidth = 4, 925 .num_links = 1, 926 .link_nodes = { &qhm_mnoc_cfg }, 927 }; 928 929 static struct qcom_icc_node qhs_npu_cfg = { 930 .name = "qhs_npu_cfg", 931 .channels = 1, 932 .buswidth = 4, 933 }; 934 935 static struct qcom_icc_node qhs_pcie0_cfg = { 936 .name = "qhs_pcie0_cfg", 937 .channels = 1, 938 .buswidth = 4, 939 }; 940 941 static struct qcom_icc_node qhs_pcie1_cfg = { 942 .name = "qhs_pcie1_cfg", 943 .channels = 1, 944 .buswidth = 4, 945 }; 946 947 static struct qcom_icc_node qhs_phy_refgen_north = { 948 .name = "qhs_phy_refgen_north", 949 .channels = 1, 950 .buswidth = 4, 951 }; 952 953 static struct qcom_icc_node qhs_pimem_cfg = { 954 .name = "qhs_pimem_cfg", 955 .channels = 1, 956 .buswidth = 4, 957 }; 958 959 static struct qcom_icc_node qhs_prng = { 960 .name = "qhs_prng", 961 .channels = 1, 962 .buswidth = 4, 963 }; 964 965 static struct qcom_icc_node qhs_qdss_cfg = { 966 .name = "qhs_qdss_cfg", 967 .channels = 1, 968 .buswidth = 4, 969 }; 970 971 static struct qcom_icc_node qhs_qspi = { 972 .name = "qhs_qspi", 973 .channels = 1, 974 .buswidth = 4, 975 }; 976 977 static struct qcom_icc_node qhs_qupv3_east = { 978 .name = "qhs_qupv3_east", 979 .channels = 1, 980 .buswidth = 4, 981 }; 982 983 static struct qcom_icc_node qhs_qupv3_north = { 984 .name = "qhs_qupv3_north", 985 .channels = 1, 986 .buswidth = 4, 987 }; 988 989 static struct qcom_icc_node qhs_qupv3_south = { 990 .name = "qhs_qupv3_south", 991 .channels = 1, 992 .buswidth = 4, 993 }; 994 995 static struct qcom_icc_node qhs_sdc2 = { 996 .name = "qhs_sdc2", 997 .channels = 1, 998 .buswidth = 4, 999 }; 1000 1001 static struct qcom_icc_node qhs_sdc4 = { 1002 .name = "qhs_sdc4", 1003 .channels = 1, 1004 .buswidth = 4, 1005 }; 1006 1007 static struct qcom_icc_node qhs_snoc_cfg = { 1008 .name = "qhs_snoc_cfg", 1009 .channels = 1, 1010 .buswidth = 4, 1011 .num_links = 1, 1012 .link_nodes = { &qhm_snoc_cfg }, 1013 }; 1014 1015 static struct qcom_icc_node qhs_spdm = { 1016 .name = "qhs_spdm", 1017 .channels = 1, 1018 .buswidth = 4, 1019 }; 1020 1021 static struct qcom_icc_node qhs_spss_cfg = { 1022 .name = "qhs_spss_cfg", 1023 .channels = 1, 1024 .buswidth = 4, 1025 }; 1026 1027 static struct qcom_icc_node qhs_ssc_cfg = { 1028 .name = "qhs_ssc_cfg", 1029 .channels = 1, 1030 .buswidth = 4, 1031 }; 1032 1033 static struct qcom_icc_node qhs_tcsr = { 1034 .name = "qhs_tcsr", 1035 .channels = 1, 1036 .buswidth = 4, 1037 }; 1038 1039 static struct qcom_icc_node qhs_tlmm_east = { 1040 .name = "qhs_tlmm_east", 1041 .channels = 1, 1042 .buswidth = 4, 1043 }; 1044 1045 static struct qcom_icc_node qhs_tlmm_north = { 1046 .name = "qhs_tlmm_north", 1047 .channels = 1, 1048 .buswidth = 4, 1049 }; 1050 1051 static struct qcom_icc_node qhs_tlmm_south = { 1052 .name = "qhs_tlmm_south", 1053 .channels = 1, 1054 .buswidth = 4, 1055 }; 1056 1057 static struct qcom_icc_node qhs_tlmm_west = { 1058 .name = "qhs_tlmm_west", 1059 .channels = 1, 1060 .buswidth = 4, 1061 }; 1062 1063 static struct qcom_icc_node qhs_tsif = { 1064 .name = "qhs_tsif", 1065 .channels = 1, 1066 .buswidth = 4, 1067 }; 1068 1069 static struct qcom_icc_node qhs_ufs_card_cfg = { 1070 .name = "qhs_ufs_card_cfg", 1071 .channels = 1, 1072 .buswidth = 4, 1073 }; 1074 1075 static struct qcom_icc_node qhs_ufs_mem_cfg = { 1076 .name = "qhs_ufs_mem_cfg", 1077 .channels = 1, 1078 .buswidth = 4, 1079 }; 1080 1081 static struct qcom_icc_node qhs_usb3_0 = { 1082 .name = "qhs_usb3_0", 1083 .channels = 1, 1084 .buswidth = 4, 1085 }; 1086 1087 static struct qcom_icc_node qhs_usb3_1 = { 1088 .name = "qhs_usb3_1", 1089 .channels = 1, 1090 .buswidth = 4, 1091 }; 1092 1093 static struct qcom_icc_node qhs_venus_cfg = { 1094 .name = "qhs_venus_cfg", 1095 .channels = 1, 1096 .buswidth = 4, 1097 }; 1098 1099 static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 1100 .name = "qhs_vsense_ctrl_cfg", 1101 .channels = 1, 1102 .buswidth = 4, 1103 }; 1104 1105 static struct qcom_icc_node qns_cnoc_a2noc = { 1106 .name = "qns_cnoc_a2noc", 1107 .channels = 1, 1108 .buswidth = 8, 1109 .num_links = 1, 1110 .link_nodes = { &qnm_cnoc }, 1111 }; 1112 1113 static struct qcom_icc_node srvc_cnoc = { 1114 .name = "srvc_cnoc", 1115 .channels = 1, 1116 .buswidth = 4, 1117 }; 1118 1119 static struct qcom_icc_node qhs_llcc = { 1120 .name = "qhs_llcc", 1121 .channels = 1, 1122 .buswidth = 4, 1123 }; 1124 1125 static struct qcom_icc_node qhs_memnoc = { 1126 .name = "qhs_memnoc", 1127 .channels = 1, 1128 .buswidth = 4, 1129 .num_links = 1, 1130 .link_nodes = { &qhm_gemnoc_cfg }, 1131 }; 1132 1133 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { 1134 .name = "qhs_mdsp_ms_mpu_cfg", 1135 .channels = 1, 1136 .buswidth = 4, 1137 }; 1138 1139 static struct qcom_icc_node qns_ecc = { 1140 .name = "qns_ecc", 1141 .channels = 1, 1142 .buswidth = 32, 1143 }; 1144 1145 static struct qcom_icc_node qns_gem_noc_snoc = { 1146 .name = "qns_gem_noc_snoc", 1147 .channels = 1, 1148 .buswidth = 8, 1149 .num_links = 1, 1150 .link_nodes = { &qnm_gemnoc }, 1151 }; 1152 1153 static struct qcom_icc_node qns_llcc = { 1154 .name = "qns_llcc", 1155 .channels = 4, 1156 .buswidth = 16, 1157 .num_links = 1, 1158 .link_nodes = { &llcc_mc }, 1159 }; 1160 1161 static struct qcom_icc_node srvc_gemnoc = { 1162 .name = "srvc_gemnoc", 1163 .channels = 1, 1164 .buswidth = 4, 1165 }; 1166 1167 static struct qcom_icc_node ebi = { 1168 .name = "ebi", 1169 .channels = 4, 1170 .buswidth = 4, 1171 }; 1172 1173 static struct qcom_icc_node qns2_mem_noc = { 1174 .name = "qns2_mem_noc", 1175 .channels = 1, 1176 .buswidth = 32, 1177 .num_links = 1, 1178 .link_nodes = { &qnm_mnoc_sf }, 1179 }; 1180 1181 static struct qcom_icc_node qns_mem_noc_hf = { 1182 .name = "qns_mem_noc_hf", 1183 .channels = 2, 1184 .buswidth = 32, 1185 .num_links = 1, 1186 .link_nodes = { &qnm_mnoc_hf }, 1187 }; 1188 1189 static struct qcom_icc_node srvc_mnoc = { 1190 .name = "srvc_mnoc", 1191 .channels = 1, 1192 .buswidth = 4, 1193 }; 1194 1195 static struct qcom_icc_node qhs_apss = { 1196 .name = "qhs_apss", 1197 .channels = 1, 1198 .buswidth = 8, 1199 }; 1200 1201 static struct qcom_icc_node qns_cnoc = { 1202 .name = "qns_cnoc", 1203 .channels = 1, 1204 .buswidth = 8, 1205 .num_links = 1, 1206 .link_nodes = { &qnm_snoc }, 1207 }; 1208 1209 static struct qcom_icc_node qns_gemnoc_gc = { 1210 .name = "qns_gemnoc_gc", 1211 .channels = 1, 1212 .buswidth = 8, 1213 .num_links = 1, 1214 .link_nodes = { &qnm_snoc_gc }, 1215 }; 1216 1217 static struct qcom_icc_node qns_gemnoc_sf = { 1218 .name = "qns_gemnoc_sf", 1219 .channels = 1, 1220 .buswidth = 16, 1221 .num_links = 1, 1222 .link_nodes = { &qnm_snoc_sf }, 1223 }; 1224 1225 static struct qcom_icc_node qxs_imem = { 1226 .name = "qxs_imem", 1227 .channels = 1, 1228 .buswidth = 8, 1229 }; 1230 1231 static struct qcom_icc_node qxs_pimem = { 1232 .name = "qxs_pimem", 1233 .channels = 1, 1234 .buswidth = 8, 1235 }; 1236 1237 static struct qcom_icc_node srvc_snoc = { 1238 .name = "srvc_snoc", 1239 .channels = 1, 1240 .buswidth = 4, 1241 }; 1242 1243 static struct qcom_icc_node xs_pcie_0 = { 1244 .name = "xs_pcie_0", 1245 .channels = 1, 1246 .buswidth = 8, 1247 }; 1248 1249 static struct qcom_icc_node xs_pcie_1 = { 1250 .name = "xs_pcie_1", 1251 .channels = 1, 1252 .buswidth = 8, 1253 }; 1254 1255 static struct qcom_icc_node xs_qdss_stm = { 1256 .name = "xs_qdss_stm", 1257 .channels = 1, 1258 .buswidth = 4, 1259 }; 1260 1261 static struct qcom_icc_node xs_sys_tcu_cfg = { 1262 .name = "xs_sys_tcu_cfg", 1263 .channels = 1, 1264 .buswidth = 8, 1265 }; 1266 1267 static struct qcom_icc_bcm bcm_acv = { 1268 .name = "ACV", 1269 .enable_mask = BIT(3), 1270 .keepalive = false, 1271 .num_nodes = 1, 1272 .nodes = { &ebi }, 1273 }; 1274 1275 static struct qcom_icc_bcm bcm_mc0 = { 1276 .name = "MC0", 1277 .keepalive = true, 1278 .num_nodes = 1, 1279 .nodes = { &ebi }, 1280 }; 1281 1282 static struct qcom_icc_bcm bcm_sh0 = { 1283 .name = "SH0", 1284 .keepalive = true, 1285 .num_nodes = 1, 1286 .nodes = { &qns_llcc }, 1287 }; 1288 1289 static struct qcom_icc_bcm bcm_mm0 = { 1290 .name = "MM0", 1291 .keepalive = true, 1292 .num_nodes = 1, 1293 .nodes = { &qns_mem_noc_hf }, 1294 }; 1295 1296 static struct qcom_icc_bcm bcm_mm1 = { 1297 .name = "MM1", 1298 .keepalive = false, 1299 .num_nodes = 7, 1300 .nodes = { &qxm_camnoc_hf0_uncomp, 1301 &qxm_camnoc_hf1_uncomp, 1302 &qxm_camnoc_sf_uncomp, 1303 &qxm_camnoc_hf0, 1304 &qxm_camnoc_hf1, 1305 &qxm_mdp0, 1306 &qxm_mdp1 1307 }, 1308 }; 1309 1310 static struct qcom_icc_bcm bcm_sh2 = { 1311 .name = "SH2", 1312 .keepalive = false, 1313 .num_nodes = 1, 1314 .nodes = { &qns_gem_noc_snoc }, 1315 }; 1316 1317 static struct qcom_icc_bcm bcm_mm2 = { 1318 .name = "MM2", 1319 .keepalive = false, 1320 .num_nodes = 2, 1321 .nodes = { &qxm_camnoc_sf, &qns2_mem_noc }, 1322 }; 1323 1324 static struct qcom_icc_bcm bcm_sh3 = { 1325 .name = "SH3", 1326 .keepalive = false, 1327 .num_nodes = 2, 1328 .nodes = { &acm_gpu_tcu, &acm_sys_tcu }, 1329 }; 1330 1331 static struct qcom_icc_bcm bcm_mm3 = { 1332 .name = "MM3", 1333 .keepalive = false, 1334 .num_nodes = 4, 1335 .nodes = { &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9 }, 1336 }; 1337 1338 static struct qcom_icc_bcm bcm_sh4 = { 1339 .name = "SH4", 1340 .keepalive = false, 1341 .num_nodes = 1, 1342 .nodes = { &qnm_cmpnoc }, 1343 }; 1344 1345 static struct qcom_icc_bcm bcm_sh5 = { 1346 .name = "SH5", 1347 .keepalive = false, 1348 .num_nodes = 1, 1349 .nodes = { &acm_apps }, 1350 }; 1351 1352 static struct qcom_icc_bcm bcm_sn0 = { 1353 .name = "SN0", 1354 .keepalive = true, 1355 .num_nodes = 1, 1356 .nodes = { &qns_gemnoc_sf }, 1357 }; 1358 1359 static struct qcom_icc_bcm bcm_co0 = { 1360 .name = "CO0", 1361 .keepalive = false, 1362 .num_nodes = 1, 1363 .nodes = { &qns_cdsp_mem_noc }, 1364 }; 1365 1366 static struct qcom_icc_bcm bcm_ce0 = { 1367 .name = "CE0", 1368 .keepalive = false, 1369 .num_nodes = 1, 1370 .nodes = { &qxm_crypto }, 1371 }; 1372 1373 static struct qcom_icc_bcm bcm_sn1 = { 1374 .name = "SN1", 1375 .keepalive = false, 1376 .num_nodes = 1, 1377 .nodes = { &qxs_imem }, 1378 }; 1379 1380 static struct qcom_icc_bcm bcm_co1 = { 1381 .name = "CO1", 1382 .keepalive = false, 1383 .num_nodes = 1, 1384 .nodes = { &qnm_npu }, 1385 }; 1386 1387 static struct qcom_icc_bcm bcm_cn0 = { 1388 .name = "CN0", 1389 .keepalive = true, 1390 .num_nodes = 53, 1391 .nodes = { &qhm_spdm, 1392 &qnm_snoc, 1393 &qhs_a1_noc_cfg, 1394 &qhs_a2_noc_cfg, 1395 &qhs_ahb2phy_south, 1396 &qhs_aop, 1397 &qhs_aoss, 1398 &qhs_camera_cfg, 1399 &qhs_clk_ctl, 1400 &qhs_compute_dsp, 1401 &qhs_cpr_cx, 1402 &qhs_cpr_mmcx, 1403 &qhs_cpr_mx, 1404 &qhs_crypto0_cfg, 1405 &qhs_ddrss_cfg, 1406 &qhs_display_cfg, 1407 &qhs_emac_cfg, 1408 &qhs_glm, 1409 &qhs_gpuss_cfg, 1410 &qhs_imem_cfg, 1411 &qhs_ipa, 1412 &qhs_mnoc_cfg, 1413 &qhs_npu_cfg, 1414 &qhs_pcie0_cfg, 1415 &qhs_pcie1_cfg, 1416 &qhs_phy_refgen_north, 1417 &qhs_pimem_cfg, 1418 &qhs_prng, 1419 &qhs_qdss_cfg, 1420 &qhs_qspi, 1421 &qhs_qupv3_east, 1422 &qhs_qupv3_north, 1423 &qhs_qupv3_south, 1424 &qhs_sdc2, 1425 &qhs_sdc4, 1426 &qhs_snoc_cfg, 1427 &qhs_spdm, 1428 &qhs_spss_cfg, 1429 &qhs_ssc_cfg, 1430 &qhs_tcsr, 1431 &qhs_tlmm_east, 1432 &qhs_tlmm_north, 1433 &qhs_tlmm_south, 1434 &qhs_tlmm_west, 1435 &qhs_tsif, 1436 &qhs_ufs_card_cfg, 1437 &qhs_ufs_mem_cfg, 1438 &qhs_usb3_0, 1439 &qhs_usb3_1, 1440 &qhs_venus_cfg, 1441 &qhs_vsense_ctrl_cfg, 1442 &qns_cnoc_a2noc, 1443 &srvc_cnoc 1444 }, 1445 }; 1446 1447 static struct qcom_icc_bcm bcm_qup0 = { 1448 .name = "QUP0", 1449 .keepalive = false, 1450 .num_nodes = 3, 1451 .nodes = { &qhm_qup0, &qhm_qup1, &qhm_qup2 }, 1452 }; 1453 1454 static struct qcom_icc_bcm bcm_sn2 = { 1455 .name = "SN2", 1456 .keepalive = false, 1457 .num_nodes = 1, 1458 .nodes = { &qns_gemnoc_gc }, 1459 }; 1460 1461 static struct qcom_icc_bcm bcm_sn3 = { 1462 .name = "SN3", 1463 .keepalive = false, 1464 .num_nodes = 3, 1465 .nodes = { &srvc_aggre1_noc, &srvc_aggre2_noc, &qns_cnoc }, 1466 }; 1467 1468 static struct qcom_icc_bcm bcm_sn4 = { 1469 .name = "SN4", 1470 .keepalive = false, 1471 .num_nodes = 1, 1472 .nodes = { &qxs_pimem }, 1473 }; 1474 1475 static struct qcom_icc_bcm bcm_sn5 = { 1476 .name = "SN5", 1477 .keepalive = false, 1478 .num_nodes = 1, 1479 .nodes = { &xs_qdss_stm }, 1480 }; 1481 1482 static struct qcom_icc_bcm bcm_sn8 = { 1483 .name = "SN8", 1484 .keepalive = false, 1485 .num_nodes = 2, 1486 .nodes = { &xs_pcie_0, &xs_pcie_1 }, 1487 }; 1488 1489 static struct qcom_icc_bcm bcm_sn9 = { 1490 .name = "SN9", 1491 .keepalive = false, 1492 .num_nodes = 1, 1493 .nodes = { &qnm_aggre1_noc }, 1494 }; 1495 1496 static struct qcom_icc_bcm bcm_sn11 = { 1497 .name = "SN11", 1498 .keepalive = false, 1499 .num_nodes = 1, 1500 .nodes = { &qnm_aggre2_noc }, 1501 }; 1502 1503 static struct qcom_icc_bcm bcm_sn12 = { 1504 .name = "SN12", 1505 .keepalive = false, 1506 .num_nodes = 2, 1507 .nodes = { &qxm_pimem, &xm_gic }, 1508 }; 1509 1510 static struct qcom_icc_bcm bcm_sn14 = { 1511 .name = "SN14", 1512 .keepalive = false, 1513 .num_nodes = 1, 1514 .nodes = { &qns_pcie_mem_noc }, 1515 }; 1516 1517 static struct qcom_icc_bcm bcm_sn15 = { 1518 .name = "SN15", 1519 .keepalive = false, 1520 .num_nodes = 1, 1521 .nodes = { &qnm_gemnoc }, 1522 }; 1523 1524 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 1525 &bcm_qup0, 1526 &bcm_sn3, 1527 }; 1528 1529 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1530 [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg, 1531 [MASTER_QUP_0] = &qhm_qup0, 1532 [MASTER_EMAC] = &xm_emac, 1533 [MASTER_UFS_MEM] = &xm_ufs_mem, 1534 [MASTER_USB3] = &xm_usb3_0, 1535 [MASTER_USB3_1] = &xm_usb3_1, 1536 [A1NOC_SNOC_SLV] = &qns_a1noc_snoc, 1537 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, 1538 }; 1539 1540 static const struct qcom_icc_desc sm8150_aggre1_noc = { 1541 .nodes = aggre1_noc_nodes, 1542 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 1543 .bcms = aggre1_noc_bcms, 1544 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 1545 }; 1546 1547 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 1548 &bcm_ce0, 1549 &bcm_qup0, 1550 &bcm_sn14, 1551 &bcm_sn3, 1552 }; 1553 1554 static struct qcom_icc_node * const aggre2_noc_nodes[] = { 1555 [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg, 1556 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 1557 [MASTER_QSPI] = &qhm_qspi, 1558 [MASTER_QUP_1] = &qhm_qup1, 1559 [MASTER_QUP_2] = &qhm_qup2, 1560 [MASTER_SENSORS_AHB] = &qhm_sensorss_ahb, 1561 [MASTER_TSIF] = &qhm_tsif, 1562 [MASTER_CNOC_A2NOC] = &qnm_cnoc, 1563 [MASTER_CRYPTO_CORE_0] = &qxm_crypto, 1564 [MASTER_IPA] = &qxm_ipa, 1565 [MASTER_PCIE] = &xm_pcie3_0, 1566 [MASTER_PCIE_1] = &xm_pcie3_1, 1567 [MASTER_QDSS_ETR] = &xm_qdss_etr, 1568 [MASTER_SDCC_2] = &xm_sdc2, 1569 [MASTER_SDCC_4] = &xm_sdc4, 1570 [A2NOC_SNOC_SLV] = &qns_a2noc_snoc, 1571 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, 1572 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, 1573 }; 1574 1575 static const struct qcom_icc_desc sm8150_aggre2_noc = { 1576 .nodes = aggre2_noc_nodes, 1577 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 1578 .bcms = aggre2_noc_bcms, 1579 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 1580 }; 1581 1582 static struct qcom_icc_bcm * const camnoc_virt_bcms[] = { 1583 &bcm_mm1, 1584 }; 1585 1586 static struct qcom_icc_node * const camnoc_virt_nodes[] = { 1587 [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp, 1588 [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp, 1589 [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp, 1590 [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp, 1591 }; 1592 1593 static const struct qcom_icc_desc sm8150_camnoc_virt = { 1594 .nodes = camnoc_virt_nodes, 1595 .num_nodes = ARRAY_SIZE(camnoc_virt_nodes), 1596 .bcms = camnoc_virt_bcms, 1597 .num_bcms = ARRAY_SIZE(camnoc_virt_bcms), 1598 }; 1599 1600 static struct qcom_icc_bcm * const compute_noc_bcms[] = { 1601 &bcm_co0, 1602 &bcm_co1, 1603 }; 1604 1605 static struct qcom_icc_node * const compute_noc_nodes[] = { 1606 [MASTER_NPU] = &qnm_npu, 1607 [SLAVE_CDSP_MEM_NOC] = &qns_cdsp_mem_noc, 1608 }; 1609 1610 static const struct qcom_icc_desc sm8150_compute_noc = { 1611 .nodes = compute_noc_nodes, 1612 .num_nodes = ARRAY_SIZE(compute_noc_nodes), 1613 .bcms = compute_noc_bcms, 1614 .num_bcms = ARRAY_SIZE(compute_noc_bcms), 1615 }; 1616 1617 static struct qcom_icc_bcm * const config_noc_bcms[] = { 1618 &bcm_cn0, 1619 }; 1620 1621 static struct qcom_icc_node * const config_noc_nodes[] = { 1622 [MASTER_SPDM] = &qhm_spdm, 1623 [SNOC_CNOC_MAS] = &qnm_snoc, 1624 [MASTER_QDSS_DAP] = &xm_qdss_dap, 1625 [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg, 1626 [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg, 1627 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy_south, 1628 [SLAVE_AOP] = &qhs_aop, 1629 [SLAVE_AOSS] = &qhs_aoss, 1630 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 1631 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1632 [SLAVE_CDSP_CFG] = &qhs_compute_dsp, 1633 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 1634 [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx, 1635 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, 1636 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1637 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg, 1638 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 1639 [SLAVE_EMAC_CFG] = &qhs_emac_cfg, 1640 [SLAVE_GLM] = &qhs_glm, 1641 [SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg, 1642 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1643 [SLAVE_IPA_CFG] = &qhs_ipa, 1644 [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg, 1645 [SLAVE_NPU_CFG] = &qhs_npu_cfg, 1646 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, 1647 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, 1648 [SLAVE_NORTH_PHY_CFG] = &qhs_phy_refgen_north, 1649 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 1650 [SLAVE_PRNG] = &qhs_prng, 1651 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1652 [SLAVE_QSPI] = &qhs_qspi, 1653 [SLAVE_QUP_2] = &qhs_qupv3_east, 1654 [SLAVE_QUP_1] = &qhs_qupv3_north, 1655 [SLAVE_QUP_0] = &qhs_qupv3_south, 1656 [SLAVE_SDCC_2] = &qhs_sdc2, 1657 [SLAVE_SDCC_4] = &qhs_sdc4, 1658 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, 1659 [SLAVE_SPDM_WRAPPER] = &qhs_spdm, 1660 [SLAVE_SPSS_CFG] = &qhs_spss_cfg, 1661 [SLAVE_SSC_CFG] = &qhs_ssc_cfg, 1662 [SLAVE_TCSR] = &qhs_tcsr, 1663 [SLAVE_TLMM_EAST] = &qhs_tlmm_east, 1664 [SLAVE_TLMM_NORTH] = &qhs_tlmm_north, 1665 [SLAVE_TLMM_SOUTH] = &qhs_tlmm_south, 1666 [SLAVE_TLMM_WEST] = &qhs_tlmm_west, 1667 [SLAVE_TSIF] = &qhs_tsif, 1668 [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg, 1669 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 1670 [SLAVE_USB3] = &qhs_usb3_0, 1671 [SLAVE_USB3_1] = &qhs_usb3_1, 1672 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1673 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 1674 [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc, 1675 [SLAVE_SERVICE_CNOC] = &srvc_cnoc, 1676 }; 1677 1678 static const struct qcom_icc_desc sm8150_config_noc = { 1679 .nodes = config_noc_nodes, 1680 .num_nodes = ARRAY_SIZE(config_noc_nodes), 1681 .bcms = config_noc_bcms, 1682 .num_bcms = ARRAY_SIZE(config_noc_bcms), 1683 }; 1684 1685 static struct qcom_icc_bcm * const dc_noc_bcms[] = { 1686 }; 1687 1688 static struct qcom_icc_node * const dc_noc_nodes[] = { 1689 [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc, 1690 [SLAVE_LLCC_CFG] = &qhs_llcc, 1691 [SLAVE_GEM_NOC_CFG] = &qhs_memnoc, 1692 }; 1693 1694 static const struct qcom_icc_desc sm8150_dc_noc = { 1695 .nodes = dc_noc_nodes, 1696 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 1697 .bcms = dc_noc_bcms, 1698 .num_bcms = ARRAY_SIZE(dc_noc_bcms), 1699 }; 1700 1701 static struct qcom_icc_bcm * const gem_noc_bcms[] = { 1702 &bcm_sh0, 1703 &bcm_sh2, 1704 &bcm_sh3, 1705 &bcm_sh4, 1706 &bcm_sh5, 1707 }; 1708 1709 static struct qcom_icc_node * const gem_noc_nodes[] = { 1710 [MASTER_AMPSS_M0] = &acm_apps, 1711 [MASTER_GPU_TCU] = &acm_gpu_tcu, 1712 [MASTER_SYS_TCU] = &acm_sys_tcu, 1713 [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg, 1714 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc, 1715 [MASTER_GRAPHICS_3D] = &qnm_gpu, 1716 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 1717 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 1718 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_pcie, 1719 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 1720 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 1721 [MASTER_ECC] = &qxm_ecc, 1722 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg, 1723 [SLAVE_ECC] = &qns_ecc, 1724 [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc, 1725 [SLAVE_LLCC] = &qns_llcc, 1726 [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc, 1727 }; 1728 1729 static const struct qcom_icc_desc sm8150_gem_noc = { 1730 .nodes = gem_noc_nodes, 1731 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 1732 .bcms = gem_noc_bcms, 1733 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 1734 }; 1735 1736 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 1737 &bcm_acv, 1738 &bcm_mc0, 1739 }; 1740 1741 static struct qcom_icc_node * const mc_virt_nodes[] = { 1742 [MASTER_LLCC] = &llcc_mc, 1743 [SLAVE_EBI_CH0] = &ebi, 1744 }; 1745 1746 static const struct qcom_icc_desc sm8150_mc_virt = { 1747 .nodes = mc_virt_nodes, 1748 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 1749 .bcms = mc_virt_bcms, 1750 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 1751 }; 1752 1753 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 1754 &bcm_mm0, 1755 &bcm_mm1, 1756 &bcm_mm2, 1757 &bcm_mm3, 1758 }; 1759 1760 static struct qcom_icc_node * const mmss_noc_nodes[] = { 1761 [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg, 1762 [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0, 1763 [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1, 1764 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf, 1765 [MASTER_MDP_PORT0] = &qxm_mdp0, 1766 [MASTER_MDP_PORT1] = &qxm_mdp1, 1767 [MASTER_ROTATOR] = &qxm_rot, 1768 [MASTER_VIDEO_P0] = &qxm_venus0, 1769 [MASTER_VIDEO_P1] = &qxm_venus1, 1770 [MASTER_VIDEO_PROC] = &qxm_venus_arm9, 1771 [SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc, 1772 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 1773 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 1774 }; 1775 1776 static const struct qcom_icc_desc sm8150_mmss_noc = { 1777 .nodes = mmss_noc_nodes, 1778 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 1779 .bcms = mmss_noc_bcms, 1780 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 1781 }; 1782 1783 static struct qcom_icc_bcm * const system_noc_bcms[] = { 1784 &bcm_sn0, 1785 &bcm_sn1, 1786 &bcm_sn11, 1787 &bcm_sn12, 1788 &bcm_sn15, 1789 &bcm_sn2, 1790 &bcm_sn3, 1791 &bcm_sn4, 1792 &bcm_sn5, 1793 &bcm_sn8, 1794 &bcm_sn9, 1795 }; 1796 1797 static struct qcom_icc_node * const system_noc_nodes[] = { 1798 [MASTER_SNOC_CFG] = &qhm_snoc_cfg, 1799 [A1NOC_SNOC_MAS] = &qnm_aggre1_noc, 1800 [A2NOC_SNOC_MAS] = &qnm_aggre2_noc, 1801 [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc, 1802 [MASTER_PIMEM] = &qxm_pimem, 1803 [MASTER_GIC] = &xm_gic, 1804 [SLAVE_APPSS] = &qhs_apss, 1805 [SNOC_CNOC_SLV] = &qns_cnoc, 1806 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, 1807 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 1808 [SLAVE_OCIMEM] = &qxs_imem, 1809 [SLAVE_PIMEM] = &qxs_pimem, 1810 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 1811 [SLAVE_PCIE_0] = &xs_pcie_0, 1812 [SLAVE_PCIE_1] = &xs_pcie_1, 1813 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1814 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1815 }; 1816 1817 static const struct qcom_icc_desc sm8150_system_noc = { 1818 .nodes = system_noc_nodes, 1819 .num_nodes = ARRAY_SIZE(system_noc_nodes), 1820 .bcms = system_noc_bcms, 1821 .num_bcms = ARRAY_SIZE(system_noc_bcms), 1822 }; 1823 1824 static const struct of_device_id qnoc_of_match[] = { 1825 { .compatible = "qcom,sm8150-aggre1-noc", 1826 .data = &sm8150_aggre1_noc}, 1827 { .compatible = "qcom,sm8150-aggre2-noc", 1828 .data = &sm8150_aggre2_noc}, 1829 { .compatible = "qcom,sm8150-camnoc-virt", 1830 .data = &sm8150_camnoc_virt}, 1831 { .compatible = "qcom,sm8150-compute-noc", 1832 .data = &sm8150_compute_noc}, 1833 { .compatible = "qcom,sm8150-config-noc", 1834 .data = &sm8150_config_noc}, 1835 { .compatible = "qcom,sm8150-dc-noc", 1836 .data = &sm8150_dc_noc}, 1837 { .compatible = "qcom,sm8150-gem-noc", 1838 .data = &sm8150_gem_noc}, 1839 { .compatible = "qcom,sm8150-mc-virt", 1840 .data = &sm8150_mc_virt}, 1841 { .compatible = "qcom,sm8150-mmss-noc", 1842 .data = &sm8150_mmss_noc}, 1843 { .compatible = "qcom,sm8150-system-noc", 1844 .data = &sm8150_system_noc}, 1845 { } 1846 }; 1847 MODULE_DEVICE_TABLE(of, qnoc_of_match); 1848 1849 static struct platform_driver qnoc_driver = { 1850 .probe = qcom_icc_rpmh_probe, 1851 .remove = qcom_icc_rpmh_remove, 1852 .driver = { 1853 .name = "qnoc-sm8150", 1854 .of_match_table = qnoc_of_match, 1855 }, 1856 }; 1857 module_platform_driver(qnoc_driver); 1858 1859 MODULE_DESCRIPTION("Qualcomm SM8150 NoC driver"); 1860 MODULE_LICENSE("GPL v2"); 1861