1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 * 5 */ 6 7 #include <linux/device.h> 8 #include <linux/interconnect.h> 9 #include <linux/interconnect-provider.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include <dt-bindings/interconnect/qcom,sm8150.h> 13 14 #include "bcm-voter.h" 15 #include "icc-rpmh.h" 16 17 static struct qcom_icc_node qhm_a1noc_cfg; 18 static struct qcom_icc_node qhm_qup0; 19 static struct qcom_icc_node xm_emac; 20 static struct qcom_icc_node xm_ufs_mem; 21 static struct qcom_icc_node xm_usb3_0; 22 static struct qcom_icc_node xm_usb3_1; 23 static struct qcom_icc_node qhm_a2noc_cfg; 24 static struct qcom_icc_node qhm_qdss_bam; 25 static struct qcom_icc_node qhm_qspi; 26 static struct qcom_icc_node qhm_qup1; 27 static struct qcom_icc_node qhm_qup2; 28 static struct qcom_icc_node qhm_sensorss_ahb; 29 static struct qcom_icc_node qhm_tsif; 30 static struct qcom_icc_node qnm_cnoc; 31 static struct qcom_icc_node qxm_crypto; 32 static struct qcom_icc_node qxm_ipa; 33 static struct qcom_icc_node xm_pcie3_0; 34 static struct qcom_icc_node xm_pcie3_1; 35 static struct qcom_icc_node xm_qdss_etr; 36 static struct qcom_icc_node xm_sdc2; 37 static struct qcom_icc_node xm_sdc4; 38 static struct qcom_icc_node qxm_camnoc_hf0_uncomp; 39 static struct qcom_icc_node qxm_camnoc_hf1_uncomp; 40 static struct qcom_icc_node qxm_camnoc_sf_uncomp; 41 static struct qcom_icc_node qnm_npu; 42 static struct qcom_icc_node qhm_spdm; 43 static struct qcom_icc_node qnm_snoc; 44 static struct qcom_icc_node xm_qdss_dap; 45 static struct qcom_icc_node qhm_cnoc_dc_noc; 46 static struct qcom_icc_node acm_apps; 47 static struct qcom_icc_node acm_gpu_tcu; 48 static struct qcom_icc_node acm_sys_tcu; 49 static struct qcom_icc_node qhm_gemnoc_cfg; 50 static struct qcom_icc_node qnm_cmpnoc; 51 static struct qcom_icc_node qnm_gpu; 52 static struct qcom_icc_node qnm_mnoc_hf; 53 static struct qcom_icc_node qnm_mnoc_sf; 54 static struct qcom_icc_node qnm_pcie; 55 static struct qcom_icc_node qnm_snoc_gc; 56 static struct qcom_icc_node qnm_snoc_sf; 57 static struct qcom_icc_node qxm_ecc; 58 static struct qcom_icc_node llcc_mc; 59 static struct qcom_icc_node qhm_mnoc_cfg; 60 static struct qcom_icc_node qxm_camnoc_hf0; 61 static struct qcom_icc_node qxm_camnoc_hf1; 62 static struct qcom_icc_node qxm_camnoc_sf; 63 static struct qcom_icc_node qxm_mdp0; 64 static struct qcom_icc_node qxm_mdp1; 65 static struct qcom_icc_node qxm_rot; 66 static struct qcom_icc_node qxm_venus0; 67 static struct qcom_icc_node qxm_venus1; 68 static struct qcom_icc_node qxm_venus_arm9; 69 static struct qcom_icc_node qhm_snoc_cfg; 70 static struct qcom_icc_node qnm_aggre1_noc; 71 static struct qcom_icc_node qnm_aggre2_noc; 72 static struct qcom_icc_node qnm_gemnoc; 73 static struct qcom_icc_node qxm_pimem; 74 static struct qcom_icc_node xm_gic; 75 static struct qcom_icc_node qns_a1noc_snoc; 76 static struct qcom_icc_node srvc_aggre1_noc; 77 static struct qcom_icc_node qns_a2noc_snoc; 78 static struct qcom_icc_node qns_pcie_mem_noc; 79 static struct qcom_icc_node srvc_aggre2_noc; 80 static struct qcom_icc_node qns_camnoc_uncomp; 81 static struct qcom_icc_node qns_cdsp_mem_noc; 82 static struct qcom_icc_node qhs_a1_noc_cfg; 83 static struct qcom_icc_node qhs_a2_noc_cfg; 84 static struct qcom_icc_node qhs_ahb2phy_south; 85 static struct qcom_icc_node qhs_aop; 86 static struct qcom_icc_node qhs_aoss; 87 static struct qcom_icc_node qhs_camera_cfg; 88 static struct qcom_icc_node qhs_clk_ctl; 89 static struct qcom_icc_node qhs_compute_dsp; 90 static struct qcom_icc_node qhs_cpr_cx; 91 static struct qcom_icc_node qhs_cpr_mmcx; 92 static struct qcom_icc_node qhs_cpr_mx; 93 static struct qcom_icc_node qhs_crypto0_cfg; 94 static struct qcom_icc_node qhs_ddrss_cfg; 95 static struct qcom_icc_node qhs_display_cfg; 96 static struct qcom_icc_node qhs_emac_cfg; 97 static struct qcom_icc_node qhs_glm; 98 static struct qcom_icc_node qhs_gpuss_cfg; 99 static struct qcom_icc_node qhs_imem_cfg; 100 static struct qcom_icc_node qhs_ipa; 101 static struct qcom_icc_node qhs_mnoc_cfg; 102 static struct qcom_icc_node qhs_npu_cfg; 103 static struct qcom_icc_node qhs_pcie0_cfg; 104 static struct qcom_icc_node qhs_pcie1_cfg; 105 static struct qcom_icc_node qhs_phy_refgen_north; 106 static struct qcom_icc_node qhs_pimem_cfg; 107 static struct qcom_icc_node qhs_prng; 108 static struct qcom_icc_node qhs_qdss_cfg; 109 static struct qcom_icc_node qhs_qspi; 110 static struct qcom_icc_node qhs_qupv3_east; 111 static struct qcom_icc_node qhs_qupv3_north; 112 static struct qcom_icc_node qhs_qupv3_south; 113 static struct qcom_icc_node qhs_sdc2; 114 static struct qcom_icc_node qhs_sdc4; 115 static struct qcom_icc_node qhs_snoc_cfg; 116 static struct qcom_icc_node qhs_spdm; 117 static struct qcom_icc_node qhs_spss_cfg; 118 static struct qcom_icc_node qhs_ssc_cfg; 119 static struct qcom_icc_node qhs_tcsr; 120 static struct qcom_icc_node qhs_tlmm_east; 121 static struct qcom_icc_node qhs_tlmm_north; 122 static struct qcom_icc_node qhs_tlmm_south; 123 static struct qcom_icc_node qhs_tlmm_west; 124 static struct qcom_icc_node qhs_tsif; 125 static struct qcom_icc_node qhs_ufs_card_cfg; 126 static struct qcom_icc_node qhs_ufs_mem_cfg; 127 static struct qcom_icc_node qhs_usb3_0; 128 static struct qcom_icc_node qhs_usb3_1; 129 static struct qcom_icc_node qhs_venus_cfg; 130 static struct qcom_icc_node qhs_vsense_ctrl_cfg; 131 static struct qcom_icc_node qns_cnoc_a2noc; 132 static struct qcom_icc_node srvc_cnoc; 133 static struct qcom_icc_node qhs_llcc; 134 static struct qcom_icc_node qhs_memnoc; 135 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; 136 static struct qcom_icc_node qns_ecc; 137 static struct qcom_icc_node qns_gem_noc_snoc; 138 static struct qcom_icc_node qns_llcc; 139 static struct qcom_icc_node srvc_gemnoc; 140 static struct qcom_icc_node ebi; 141 static struct qcom_icc_node qns2_mem_noc; 142 static struct qcom_icc_node qns_mem_noc_hf; 143 static struct qcom_icc_node srvc_mnoc; 144 static struct qcom_icc_node qhs_apss; 145 static struct qcom_icc_node qns_cnoc; 146 static struct qcom_icc_node qns_gemnoc_gc; 147 static struct qcom_icc_node qns_gemnoc_sf; 148 static struct qcom_icc_node qxs_imem; 149 static struct qcom_icc_node qxs_pimem; 150 static struct qcom_icc_node srvc_snoc; 151 static struct qcom_icc_node xs_pcie_0; 152 static struct qcom_icc_node xs_pcie_1; 153 static struct qcom_icc_node xs_qdss_stm; 154 static struct qcom_icc_node xs_sys_tcu_cfg; 155 156 static struct qcom_icc_node qhm_a1noc_cfg = { 157 .name = "qhm_a1noc_cfg", 158 .channels = 1, 159 .buswidth = 4, 160 .num_links = 1, 161 .link_nodes = { &srvc_aggre1_noc }, 162 }; 163 164 static struct qcom_icc_node qhm_qup0 = { 165 .name = "qhm_qup0", 166 .channels = 1, 167 .buswidth = 4, 168 .num_links = 1, 169 .link_nodes = { &qns_a1noc_snoc }, 170 }; 171 172 static struct qcom_icc_node xm_emac = { 173 .name = "xm_emac", 174 .channels = 1, 175 .buswidth = 8, 176 .num_links = 1, 177 .link_nodes = { &qns_a1noc_snoc }, 178 }; 179 180 static struct qcom_icc_node xm_ufs_mem = { 181 .name = "xm_ufs_mem", 182 .channels = 1, 183 .buswidth = 8, 184 .num_links = 1, 185 .link_nodes = { &qns_a1noc_snoc }, 186 }; 187 188 static struct qcom_icc_node xm_usb3_0 = { 189 .name = "xm_usb3_0", 190 .channels = 1, 191 .buswidth = 8, 192 .num_links = 1, 193 .link_nodes = { &qns_a1noc_snoc }, 194 }; 195 196 static struct qcom_icc_node xm_usb3_1 = { 197 .name = "xm_usb3_1", 198 .channels = 1, 199 .buswidth = 8, 200 .num_links = 1, 201 .link_nodes = { &qns_a1noc_snoc }, 202 }; 203 204 static struct qcom_icc_node qhm_a2noc_cfg = { 205 .name = "qhm_a2noc_cfg", 206 .channels = 1, 207 .buswidth = 4, 208 .num_links = 1, 209 .link_nodes = { &srvc_aggre2_noc }, 210 }; 211 212 static struct qcom_icc_node qhm_qdss_bam = { 213 .name = "qhm_qdss_bam", 214 .channels = 1, 215 .buswidth = 4, 216 .num_links = 1, 217 .link_nodes = { &qns_a2noc_snoc }, 218 }; 219 220 static struct qcom_icc_node qhm_qspi = { 221 .name = "qhm_qspi", 222 .channels = 1, 223 .buswidth = 4, 224 .num_links = 1, 225 .link_nodes = { &qns_a2noc_snoc }, 226 }; 227 228 static struct qcom_icc_node qhm_qup1 = { 229 .name = "qhm_qup1", 230 .channels = 1, 231 .buswidth = 4, 232 .num_links = 1, 233 .link_nodes = { &qns_a2noc_snoc }, 234 }; 235 236 static struct qcom_icc_node qhm_qup2 = { 237 .name = "qhm_qup2", 238 .channels = 1, 239 .buswidth = 4, 240 .num_links = 1, 241 .link_nodes = { &qns_a2noc_snoc }, 242 }; 243 244 static struct qcom_icc_node qhm_sensorss_ahb = { 245 .name = "qhm_sensorss_ahb", 246 .channels = 1, 247 .buswidth = 4, 248 .num_links = 1, 249 .link_nodes = { &qns_a2noc_snoc }, 250 }; 251 252 static struct qcom_icc_node qhm_tsif = { 253 .name = "qhm_tsif", 254 .channels = 1, 255 .buswidth = 4, 256 .num_links = 1, 257 .link_nodes = { &qns_a2noc_snoc }, 258 }; 259 260 static struct qcom_icc_node qnm_cnoc = { 261 .name = "qnm_cnoc", 262 .channels = 1, 263 .buswidth = 8, 264 .num_links = 1, 265 .link_nodes = { &qns_a2noc_snoc }, 266 }; 267 268 static struct qcom_icc_node qxm_crypto = { 269 .name = "qxm_crypto", 270 .channels = 1, 271 .buswidth = 8, 272 .num_links = 1, 273 .link_nodes = { &qns_a2noc_snoc }, 274 }; 275 276 static struct qcom_icc_node qxm_ipa = { 277 .name = "qxm_ipa", 278 .channels = 1, 279 .buswidth = 8, 280 .num_links = 1, 281 .link_nodes = { &qns_a2noc_snoc }, 282 }; 283 284 static struct qcom_icc_node xm_pcie3_0 = { 285 .name = "xm_pcie3_0", 286 .channels = 1, 287 .buswidth = 8, 288 .num_links = 1, 289 .link_nodes = { &qns_pcie_mem_noc }, 290 }; 291 292 static struct qcom_icc_node xm_pcie3_1 = { 293 .name = "xm_pcie3_1", 294 .channels = 1, 295 .buswidth = 8, 296 .num_links = 1, 297 .link_nodes = { &qns_pcie_mem_noc }, 298 }; 299 300 static struct qcom_icc_node xm_qdss_etr = { 301 .name = "xm_qdss_etr", 302 .channels = 1, 303 .buswidth = 8, 304 .num_links = 1, 305 .link_nodes = { &qns_a2noc_snoc }, 306 }; 307 308 static struct qcom_icc_node xm_sdc2 = { 309 .name = "xm_sdc2", 310 .channels = 1, 311 .buswidth = 8, 312 .num_links = 1, 313 .link_nodes = { &qns_a2noc_snoc }, 314 }; 315 316 static struct qcom_icc_node xm_sdc4 = { 317 .name = "xm_sdc4", 318 .channels = 1, 319 .buswidth = 8, 320 .num_links = 1, 321 .link_nodes = { &qns_a2noc_snoc }, 322 }; 323 324 static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { 325 .name = "qxm_camnoc_hf0_uncomp", 326 .channels = 1, 327 .buswidth = 32, 328 .num_links = 1, 329 .link_nodes = { &qns_camnoc_uncomp }, 330 }; 331 332 static struct qcom_icc_node qxm_camnoc_hf1_uncomp = { 333 .name = "qxm_camnoc_hf1_uncomp", 334 .channels = 1, 335 .buswidth = 32, 336 .num_links = 1, 337 .link_nodes = { &qns_camnoc_uncomp }, 338 }; 339 340 static struct qcom_icc_node qxm_camnoc_sf_uncomp = { 341 .name = "qxm_camnoc_sf_uncomp", 342 .channels = 1, 343 .buswidth = 32, 344 .num_links = 1, 345 .link_nodes = { &qns_camnoc_uncomp }, 346 }; 347 348 static struct qcom_icc_node qnm_npu = { 349 .name = "qnm_npu", 350 .channels = 1, 351 .buswidth = 32, 352 .num_links = 1, 353 .link_nodes = { &qns_cdsp_mem_noc }, 354 }; 355 356 static struct qcom_icc_node qhm_spdm = { 357 .name = "qhm_spdm", 358 .channels = 1, 359 .buswidth = 4, 360 .num_links = 1, 361 .link_nodes = { &qns_cnoc_a2noc }, 362 }; 363 364 static struct qcom_icc_node qnm_snoc = { 365 .name = "qnm_snoc", 366 .channels = 1, 367 .buswidth = 8, 368 .num_links = 50, 369 .link_nodes = { &qhs_tlmm_south, 370 &qhs_compute_dsp, 371 &qhs_spss_cfg, 372 &qhs_camera_cfg, 373 &qhs_sdc4, 374 &qhs_sdc2, 375 &qhs_mnoc_cfg, 376 &qhs_emac_cfg, 377 &qhs_ufs_mem_cfg, 378 &qhs_tlmm_east, 379 &qhs_ssc_cfg, 380 &qhs_snoc_cfg, 381 &qhs_phy_refgen_north, 382 &qhs_qupv3_south, 383 &qhs_glm, 384 &qhs_pcie1_cfg, 385 &qhs_a2_noc_cfg, 386 &qhs_qdss_cfg, 387 &qhs_display_cfg, 388 &qhs_tcsr, 389 &qhs_ddrss_cfg, 390 &qhs_cpr_mmcx, 391 &qhs_npu_cfg, 392 &qhs_pcie0_cfg, 393 &qhs_gpuss_cfg, 394 &qhs_venus_cfg, 395 &qhs_tsif, 396 &qhs_ipa, 397 &qhs_clk_ctl, 398 &qhs_aop, 399 &qhs_qupv3_north, 400 &qhs_ahb2phy_south, 401 &qhs_usb3_1, 402 &srvc_cnoc, 403 &qhs_ufs_card_cfg, 404 &qhs_qupv3_east, 405 &qhs_cpr_cx, 406 &qhs_tlmm_west, 407 &qhs_a1_noc_cfg, 408 &qhs_aoss, 409 &qhs_prng, 410 &qhs_vsense_ctrl_cfg, 411 &qhs_qspi, 412 &qhs_usb3_0, 413 &qhs_spdm, 414 &qhs_crypto0_cfg, 415 &qhs_pimem_cfg, 416 &qhs_tlmm_north, 417 &qhs_cpr_mx, 418 &qhs_imem_cfg }, 419 }; 420 421 static struct qcom_icc_node xm_qdss_dap = { 422 .name = "xm_qdss_dap", 423 .channels = 1, 424 .buswidth = 8, 425 .num_links = 51, 426 .link_nodes = { &qhs_tlmm_south, 427 &qhs_compute_dsp, 428 &qhs_spss_cfg, 429 &qhs_camera_cfg, 430 &qhs_sdc4, 431 &qhs_sdc2, 432 &qhs_mnoc_cfg, 433 &qhs_emac_cfg, 434 &qhs_ufs_mem_cfg, 435 &qhs_tlmm_east, 436 &qhs_ssc_cfg, 437 &qhs_snoc_cfg, 438 &qhs_phy_refgen_north, 439 &qhs_qupv3_south, 440 &qhs_glm, 441 &qhs_pcie1_cfg, 442 &qhs_a2_noc_cfg, 443 &qhs_qdss_cfg, 444 &qhs_display_cfg, 445 &qhs_tcsr, 446 &qhs_ddrss_cfg, 447 &qns_cnoc_a2noc, 448 &qhs_cpr_mmcx, 449 &qhs_npu_cfg, 450 &qhs_pcie0_cfg, 451 &qhs_gpuss_cfg, 452 &qhs_venus_cfg, 453 &qhs_tsif, 454 &qhs_ipa, 455 &qhs_clk_ctl, 456 &qhs_aop, 457 &qhs_qupv3_north, 458 &qhs_ahb2phy_south, 459 &qhs_usb3_1, 460 &srvc_cnoc, 461 &qhs_ufs_card_cfg, 462 &qhs_qupv3_east, 463 &qhs_cpr_cx, 464 &qhs_tlmm_west, 465 &qhs_a1_noc_cfg, 466 &qhs_aoss, 467 &qhs_prng, 468 &qhs_vsense_ctrl_cfg, 469 &qhs_qspi, 470 &qhs_usb3_0, 471 &qhs_spdm, 472 &qhs_crypto0_cfg, 473 &qhs_pimem_cfg, 474 &qhs_tlmm_north, 475 &qhs_cpr_mx, 476 &qhs_imem_cfg }, 477 }; 478 479 static struct qcom_icc_node qhm_cnoc_dc_noc = { 480 .name = "qhm_cnoc_dc_noc", 481 .channels = 1, 482 .buswidth = 4, 483 .num_links = 2, 484 .link_nodes = { &qhs_memnoc, 485 &qhs_llcc }, 486 }; 487 488 static struct qcom_icc_node acm_apps = { 489 .name = "acm_apps", 490 .channels = 2, 491 .buswidth = 32, 492 .num_links = 3, 493 .link_nodes = { &qns_ecc, 494 &qns_llcc, 495 &qns_gem_noc_snoc }, 496 }; 497 498 static struct qcom_icc_node acm_gpu_tcu = { 499 .name = "acm_gpu_tcu", 500 .channels = 1, 501 .buswidth = 8, 502 .num_links = 2, 503 .link_nodes = { &qns_llcc, 504 &qns_gem_noc_snoc }, 505 }; 506 507 static struct qcom_icc_node acm_sys_tcu = { 508 .name = "acm_sys_tcu", 509 .channels = 1, 510 .buswidth = 8, 511 .num_links = 2, 512 .link_nodes = { &qns_llcc, 513 &qns_gem_noc_snoc }, 514 }; 515 516 static struct qcom_icc_node qhm_gemnoc_cfg = { 517 .name = "qhm_gemnoc_cfg", 518 .channels = 1, 519 .buswidth = 4, 520 .num_links = 2, 521 .link_nodes = { &srvc_gemnoc, 522 &qhs_mdsp_ms_mpu_cfg }, 523 }; 524 525 static struct qcom_icc_node qnm_cmpnoc = { 526 .name = "qnm_cmpnoc", 527 .channels = 2, 528 .buswidth = 32, 529 .num_links = 3, 530 .link_nodes = { &qns_ecc, 531 &qns_llcc, 532 &qns_gem_noc_snoc }, 533 }; 534 535 static struct qcom_icc_node qnm_gpu = { 536 .name = "qnm_gpu", 537 .channels = 2, 538 .buswidth = 32, 539 .num_links = 2, 540 .link_nodes = { &qns_llcc, 541 &qns_gem_noc_snoc }, 542 }; 543 544 static struct qcom_icc_node qnm_mnoc_hf = { 545 .name = "qnm_mnoc_hf", 546 .channels = 2, 547 .buswidth = 32, 548 .num_links = 1, 549 .link_nodes = { &qns_llcc }, 550 }; 551 552 static struct qcom_icc_node qnm_mnoc_sf = { 553 .name = "qnm_mnoc_sf", 554 .channels = 1, 555 .buswidth = 32, 556 .num_links = 2, 557 .link_nodes = { &qns_llcc, 558 &qns_gem_noc_snoc }, 559 }; 560 561 static struct qcom_icc_node qnm_pcie = { 562 .name = "qnm_pcie", 563 .channels = 1, 564 .buswidth = 16, 565 .num_links = 2, 566 .link_nodes = { &qns_llcc, 567 &qns_gem_noc_snoc }, 568 }; 569 570 static struct qcom_icc_node qnm_snoc_gc = { 571 .name = "qnm_snoc_gc", 572 .channels = 1, 573 .buswidth = 8, 574 .num_links = 1, 575 .link_nodes = { &qns_llcc }, 576 }; 577 578 static struct qcom_icc_node qnm_snoc_sf = { 579 .name = "qnm_snoc_sf", 580 .channels = 1, 581 .buswidth = 16, 582 .num_links = 1, 583 .link_nodes = { &qns_llcc }, 584 }; 585 586 static struct qcom_icc_node qxm_ecc = { 587 .name = "qxm_ecc", 588 .channels = 2, 589 .buswidth = 32, 590 .num_links = 1, 591 .link_nodes = { &qns_llcc }, 592 }; 593 594 static struct qcom_icc_node llcc_mc = { 595 .name = "llcc_mc", 596 .channels = 4, 597 .buswidth = 4, 598 .num_links = 1, 599 .link_nodes = { &ebi }, 600 }; 601 602 static struct qcom_icc_node qhm_mnoc_cfg = { 603 .name = "qhm_mnoc_cfg", 604 .channels = 1, 605 .buswidth = 4, 606 .num_links = 1, 607 .link_nodes = { &srvc_mnoc }, 608 }; 609 610 static struct qcom_icc_node qxm_camnoc_hf0 = { 611 .name = "qxm_camnoc_hf0", 612 .channels = 1, 613 .buswidth = 32, 614 .num_links = 1, 615 .link_nodes = { &qns_mem_noc_hf }, 616 }; 617 618 static struct qcom_icc_node qxm_camnoc_hf1 = { 619 .name = "qxm_camnoc_hf1", 620 .channels = 1, 621 .buswidth = 32, 622 .num_links = 1, 623 .link_nodes = { &qns_mem_noc_hf }, 624 }; 625 626 static struct qcom_icc_node qxm_camnoc_sf = { 627 .name = "qxm_camnoc_sf", 628 .channels = 1, 629 .buswidth = 32, 630 .num_links = 1, 631 .link_nodes = { &qns2_mem_noc }, 632 }; 633 634 static struct qcom_icc_node qxm_mdp0 = { 635 .name = "qxm_mdp0", 636 .channels = 1, 637 .buswidth = 32, 638 .num_links = 1, 639 .link_nodes = { &qns_mem_noc_hf }, 640 }; 641 642 static struct qcom_icc_node qxm_mdp1 = { 643 .name = "qxm_mdp1", 644 .channels = 1, 645 .buswidth = 32, 646 .num_links = 1, 647 .link_nodes = { &qns_mem_noc_hf }, 648 }; 649 650 static struct qcom_icc_node qxm_rot = { 651 .name = "qxm_rot", 652 .channels = 1, 653 .buswidth = 32, 654 .num_links = 1, 655 .link_nodes = { &qns2_mem_noc }, 656 }; 657 658 static struct qcom_icc_node qxm_venus0 = { 659 .name = "qxm_venus0", 660 .channels = 1, 661 .buswidth = 32, 662 .num_links = 1, 663 .link_nodes = { &qns2_mem_noc }, 664 }; 665 666 static struct qcom_icc_node qxm_venus1 = { 667 .name = "qxm_venus1", 668 .channels = 1, 669 .buswidth = 32, 670 .num_links = 1, 671 .link_nodes = { &qns2_mem_noc }, 672 }; 673 674 static struct qcom_icc_node qxm_venus_arm9 = { 675 .name = "qxm_venus_arm9", 676 .channels = 1, 677 .buswidth = 8, 678 .num_links = 1, 679 .link_nodes = { &qns2_mem_noc }, 680 }; 681 682 static struct qcom_icc_node qhm_snoc_cfg = { 683 .name = "qhm_snoc_cfg", 684 .channels = 1, 685 .buswidth = 4, 686 .num_links = 1, 687 .link_nodes = { &srvc_snoc }, 688 }; 689 690 static struct qcom_icc_node qnm_aggre1_noc = { 691 .name = "qnm_aggre1_noc", 692 .channels = 1, 693 .buswidth = 16, 694 .num_links = 6, 695 .link_nodes = { &qns_gemnoc_sf, 696 &qxs_pimem, 697 &qxs_imem, 698 &qhs_apss, 699 &qns_cnoc, 700 &xs_qdss_stm }, 701 }; 702 703 static struct qcom_icc_node qnm_aggre2_noc = { 704 .name = "qnm_aggre2_noc", 705 .channels = 1, 706 .buswidth = 16, 707 .num_links = 9, 708 .link_nodes = { &qns_gemnoc_sf, 709 &qxs_pimem, 710 &qxs_imem, 711 &qhs_apss, 712 &qns_cnoc, 713 &xs_pcie_0, 714 &xs_pcie_1, 715 &xs_sys_tcu_cfg, 716 &xs_qdss_stm }, 717 }; 718 719 static struct qcom_icc_node qnm_gemnoc = { 720 .name = "qnm_gemnoc", 721 .channels = 1, 722 .buswidth = 8, 723 .num_links = 6, 724 .link_nodes = { &qxs_pimem, 725 &qxs_imem, 726 &qhs_apss, 727 &qns_cnoc, 728 &xs_sys_tcu_cfg, 729 &xs_qdss_stm }, 730 }; 731 732 static struct qcom_icc_node qxm_pimem = { 733 .name = "qxm_pimem", 734 .channels = 1, 735 .buswidth = 8, 736 .num_links = 2, 737 .link_nodes = { &qns_gemnoc_gc, 738 &qxs_imem }, 739 }; 740 741 static struct qcom_icc_node xm_gic = { 742 .name = "xm_gic", 743 .channels = 1, 744 .buswidth = 8, 745 .num_links = 2, 746 .link_nodes = { &qns_gemnoc_gc, 747 &qxs_imem }, 748 }; 749 750 static struct qcom_icc_node qns_a1noc_snoc = { 751 .name = "qns_a1noc_snoc", 752 .channels = 1, 753 .buswidth = 16, 754 .num_links = 1, 755 .link_nodes = { &qnm_aggre1_noc }, 756 }; 757 758 static struct qcom_icc_node srvc_aggre1_noc = { 759 .name = "srvc_aggre1_noc", 760 .channels = 1, 761 .buswidth = 4, 762 }; 763 764 static struct qcom_icc_node qns_a2noc_snoc = { 765 .name = "qns_a2noc_snoc", 766 .channels = 1, 767 .buswidth = 16, 768 .num_links = 1, 769 .link_nodes = { &qnm_aggre2_noc }, 770 }; 771 772 static struct qcom_icc_node qns_pcie_mem_noc = { 773 .name = "qns_pcie_mem_noc", 774 .channels = 1, 775 .buswidth = 16, 776 .num_links = 1, 777 .link_nodes = { &qnm_pcie }, 778 }; 779 780 static struct qcom_icc_node srvc_aggre2_noc = { 781 .name = "srvc_aggre2_noc", 782 .channels = 1, 783 .buswidth = 4, 784 }; 785 786 static struct qcom_icc_node qns_camnoc_uncomp = { 787 .name = "qns_camnoc_uncomp", 788 .channels = 1, 789 .buswidth = 32, 790 }; 791 792 static struct qcom_icc_node qns_cdsp_mem_noc = { 793 .name = "qns_cdsp_mem_noc", 794 .channels = 2, 795 .buswidth = 32, 796 .num_links = 1, 797 .link_nodes = { &qnm_cmpnoc }, 798 }; 799 800 static struct qcom_icc_node qhs_a1_noc_cfg = { 801 .name = "qhs_a1_noc_cfg", 802 .channels = 1, 803 .buswidth = 4, 804 .num_links = 1, 805 .link_nodes = { &qhm_a1noc_cfg }, 806 }; 807 808 static struct qcom_icc_node qhs_a2_noc_cfg = { 809 .name = "qhs_a2_noc_cfg", 810 .channels = 1, 811 .buswidth = 4, 812 .num_links = 1, 813 .link_nodes = { &qhm_a2noc_cfg }, 814 }; 815 816 static struct qcom_icc_node qhs_ahb2phy_south = { 817 .name = "qhs_ahb2phy_south", 818 .channels = 1, 819 .buswidth = 4, 820 }; 821 822 static struct qcom_icc_node qhs_aop = { 823 .name = "qhs_aop", 824 .channels = 1, 825 .buswidth = 4, 826 }; 827 828 static struct qcom_icc_node qhs_aoss = { 829 .name = "qhs_aoss", 830 .channels = 1, 831 .buswidth = 4, 832 }; 833 834 static struct qcom_icc_node qhs_camera_cfg = { 835 .name = "qhs_camera_cfg", 836 .channels = 1, 837 .buswidth = 4, 838 }; 839 840 static struct qcom_icc_node qhs_clk_ctl = { 841 .name = "qhs_clk_ctl", 842 .channels = 1, 843 .buswidth = 4, 844 }; 845 846 static struct qcom_icc_node qhs_compute_dsp = { 847 .name = "qhs_compute_dsp", 848 .channels = 1, 849 .buswidth = 4, 850 }; 851 852 static struct qcom_icc_node qhs_cpr_cx = { 853 .name = "qhs_cpr_cx", 854 .channels = 1, 855 .buswidth = 4, 856 }; 857 858 static struct qcom_icc_node qhs_cpr_mmcx = { 859 .name = "qhs_cpr_mmcx", 860 .channels = 1, 861 .buswidth = 4, 862 }; 863 864 static struct qcom_icc_node qhs_cpr_mx = { 865 .name = "qhs_cpr_mx", 866 .channels = 1, 867 .buswidth = 4, 868 }; 869 870 static struct qcom_icc_node qhs_crypto0_cfg = { 871 .name = "qhs_crypto0_cfg", 872 .channels = 1, 873 .buswidth = 4, 874 }; 875 876 static struct qcom_icc_node qhs_ddrss_cfg = { 877 .name = "qhs_ddrss_cfg", 878 .channels = 1, 879 .buswidth = 4, 880 .num_links = 1, 881 .link_nodes = { &qhm_cnoc_dc_noc }, 882 }; 883 884 static struct qcom_icc_node qhs_display_cfg = { 885 .name = "qhs_display_cfg", 886 .channels = 1, 887 .buswidth = 4, 888 }; 889 890 static struct qcom_icc_node qhs_emac_cfg = { 891 .name = "qhs_emac_cfg", 892 .channels = 1, 893 .buswidth = 4, 894 }; 895 896 static struct qcom_icc_node qhs_glm = { 897 .name = "qhs_glm", 898 .channels = 1, 899 .buswidth = 4, 900 }; 901 902 static struct qcom_icc_node qhs_gpuss_cfg = { 903 .name = "qhs_gpuss_cfg", 904 .channels = 1, 905 .buswidth = 8, 906 }; 907 908 static struct qcom_icc_node qhs_imem_cfg = { 909 .name = "qhs_imem_cfg", 910 .channels = 1, 911 .buswidth = 4, 912 }; 913 914 static struct qcom_icc_node qhs_ipa = { 915 .name = "qhs_ipa", 916 .channels = 1, 917 .buswidth = 4, 918 }; 919 920 static struct qcom_icc_node qhs_mnoc_cfg = { 921 .name = "qhs_mnoc_cfg", 922 .channels = 1, 923 .buswidth = 4, 924 .num_links = 1, 925 .link_nodes = { &qhm_mnoc_cfg }, 926 }; 927 928 static struct qcom_icc_node qhs_npu_cfg = { 929 .name = "qhs_npu_cfg", 930 .channels = 1, 931 .buswidth = 4, 932 }; 933 934 static struct qcom_icc_node qhs_pcie0_cfg = { 935 .name = "qhs_pcie0_cfg", 936 .channels = 1, 937 .buswidth = 4, 938 }; 939 940 static struct qcom_icc_node qhs_pcie1_cfg = { 941 .name = "qhs_pcie1_cfg", 942 .channels = 1, 943 .buswidth = 4, 944 }; 945 946 static struct qcom_icc_node qhs_phy_refgen_north = { 947 .name = "qhs_phy_refgen_north", 948 .channels = 1, 949 .buswidth = 4, 950 }; 951 952 static struct qcom_icc_node qhs_pimem_cfg = { 953 .name = "qhs_pimem_cfg", 954 .channels = 1, 955 .buswidth = 4, 956 }; 957 958 static struct qcom_icc_node qhs_prng = { 959 .name = "qhs_prng", 960 .channels = 1, 961 .buswidth = 4, 962 }; 963 964 static struct qcom_icc_node qhs_qdss_cfg = { 965 .name = "qhs_qdss_cfg", 966 .channels = 1, 967 .buswidth = 4, 968 }; 969 970 static struct qcom_icc_node qhs_qspi = { 971 .name = "qhs_qspi", 972 .channels = 1, 973 .buswidth = 4, 974 }; 975 976 static struct qcom_icc_node qhs_qupv3_east = { 977 .name = "qhs_qupv3_east", 978 .channels = 1, 979 .buswidth = 4, 980 }; 981 982 static struct qcom_icc_node qhs_qupv3_north = { 983 .name = "qhs_qupv3_north", 984 .channels = 1, 985 .buswidth = 4, 986 }; 987 988 static struct qcom_icc_node qhs_qupv3_south = { 989 .name = "qhs_qupv3_south", 990 .channels = 1, 991 .buswidth = 4, 992 }; 993 994 static struct qcom_icc_node qhs_sdc2 = { 995 .name = "qhs_sdc2", 996 .channels = 1, 997 .buswidth = 4, 998 }; 999 1000 static struct qcom_icc_node qhs_sdc4 = { 1001 .name = "qhs_sdc4", 1002 .channels = 1, 1003 .buswidth = 4, 1004 }; 1005 1006 static struct qcom_icc_node qhs_snoc_cfg = { 1007 .name = "qhs_snoc_cfg", 1008 .channels = 1, 1009 .buswidth = 4, 1010 .num_links = 1, 1011 .link_nodes = { &qhm_snoc_cfg }, 1012 }; 1013 1014 static struct qcom_icc_node qhs_spdm = { 1015 .name = "qhs_spdm", 1016 .channels = 1, 1017 .buswidth = 4, 1018 }; 1019 1020 static struct qcom_icc_node qhs_spss_cfg = { 1021 .name = "qhs_spss_cfg", 1022 .channels = 1, 1023 .buswidth = 4, 1024 }; 1025 1026 static struct qcom_icc_node qhs_ssc_cfg = { 1027 .name = "qhs_ssc_cfg", 1028 .channels = 1, 1029 .buswidth = 4, 1030 }; 1031 1032 static struct qcom_icc_node qhs_tcsr = { 1033 .name = "qhs_tcsr", 1034 .channels = 1, 1035 .buswidth = 4, 1036 }; 1037 1038 static struct qcom_icc_node qhs_tlmm_east = { 1039 .name = "qhs_tlmm_east", 1040 .channels = 1, 1041 .buswidth = 4, 1042 }; 1043 1044 static struct qcom_icc_node qhs_tlmm_north = { 1045 .name = "qhs_tlmm_north", 1046 .channels = 1, 1047 .buswidth = 4, 1048 }; 1049 1050 static struct qcom_icc_node qhs_tlmm_south = { 1051 .name = "qhs_tlmm_south", 1052 .channels = 1, 1053 .buswidth = 4, 1054 }; 1055 1056 static struct qcom_icc_node qhs_tlmm_west = { 1057 .name = "qhs_tlmm_west", 1058 .channels = 1, 1059 .buswidth = 4, 1060 }; 1061 1062 static struct qcom_icc_node qhs_tsif = { 1063 .name = "qhs_tsif", 1064 .channels = 1, 1065 .buswidth = 4, 1066 }; 1067 1068 static struct qcom_icc_node qhs_ufs_card_cfg = { 1069 .name = "qhs_ufs_card_cfg", 1070 .channels = 1, 1071 .buswidth = 4, 1072 }; 1073 1074 static struct qcom_icc_node qhs_ufs_mem_cfg = { 1075 .name = "qhs_ufs_mem_cfg", 1076 .channels = 1, 1077 .buswidth = 4, 1078 }; 1079 1080 static struct qcom_icc_node qhs_usb3_0 = { 1081 .name = "qhs_usb3_0", 1082 .channels = 1, 1083 .buswidth = 4, 1084 }; 1085 1086 static struct qcom_icc_node qhs_usb3_1 = { 1087 .name = "qhs_usb3_1", 1088 .channels = 1, 1089 .buswidth = 4, 1090 }; 1091 1092 static struct qcom_icc_node qhs_venus_cfg = { 1093 .name = "qhs_venus_cfg", 1094 .channels = 1, 1095 .buswidth = 4, 1096 }; 1097 1098 static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 1099 .name = "qhs_vsense_ctrl_cfg", 1100 .channels = 1, 1101 .buswidth = 4, 1102 }; 1103 1104 static struct qcom_icc_node qns_cnoc_a2noc = { 1105 .name = "qns_cnoc_a2noc", 1106 .channels = 1, 1107 .buswidth = 8, 1108 .num_links = 1, 1109 .link_nodes = { &qnm_cnoc }, 1110 }; 1111 1112 static struct qcom_icc_node srvc_cnoc = { 1113 .name = "srvc_cnoc", 1114 .channels = 1, 1115 .buswidth = 4, 1116 }; 1117 1118 static struct qcom_icc_node qhs_llcc = { 1119 .name = "qhs_llcc", 1120 .channels = 1, 1121 .buswidth = 4, 1122 }; 1123 1124 static struct qcom_icc_node qhs_memnoc = { 1125 .name = "qhs_memnoc", 1126 .channels = 1, 1127 .buswidth = 4, 1128 .num_links = 1, 1129 .link_nodes = { &qhm_gemnoc_cfg }, 1130 }; 1131 1132 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { 1133 .name = "qhs_mdsp_ms_mpu_cfg", 1134 .channels = 1, 1135 .buswidth = 4, 1136 }; 1137 1138 static struct qcom_icc_node qns_ecc = { 1139 .name = "qns_ecc", 1140 .channels = 1, 1141 .buswidth = 32, 1142 }; 1143 1144 static struct qcom_icc_node qns_gem_noc_snoc = { 1145 .name = "qns_gem_noc_snoc", 1146 .channels = 1, 1147 .buswidth = 8, 1148 .num_links = 1, 1149 .link_nodes = { &qnm_gemnoc }, 1150 }; 1151 1152 static struct qcom_icc_node qns_llcc = { 1153 .name = "qns_llcc", 1154 .channels = 4, 1155 .buswidth = 16, 1156 .num_links = 1, 1157 .link_nodes = { &llcc_mc }, 1158 }; 1159 1160 static struct qcom_icc_node srvc_gemnoc = { 1161 .name = "srvc_gemnoc", 1162 .channels = 1, 1163 .buswidth = 4, 1164 }; 1165 1166 static struct qcom_icc_node ebi = { 1167 .name = "ebi", 1168 .channels = 4, 1169 .buswidth = 4, 1170 }; 1171 1172 static struct qcom_icc_node qns2_mem_noc = { 1173 .name = "qns2_mem_noc", 1174 .channels = 1, 1175 .buswidth = 32, 1176 .num_links = 1, 1177 .link_nodes = { &qnm_mnoc_sf }, 1178 }; 1179 1180 static struct qcom_icc_node qns_mem_noc_hf = { 1181 .name = "qns_mem_noc_hf", 1182 .channels = 2, 1183 .buswidth = 32, 1184 .num_links = 1, 1185 .link_nodes = { &qnm_mnoc_hf }, 1186 }; 1187 1188 static struct qcom_icc_node srvc_mnoc = { 1189 .name = "srvc_mnoc", 1190 .channels = 1, 1191 .buswidth = 4, 1192 }; 1193 1194 static struct qcom_icc_node qhs_apss = { 1195 .name = "qhs_apss", 1196 .channels = 1, 1197 .buswidth = 8, 1198 }; 1199 1200 static struct qcom_icc_node qns_cnoc = { 1201 .name = "qns_cnoc", 1202 .channels = 1, 1203 .buswidth = 8, 1204 .num_links = 1, 1205 .link_nodes = { &qnm_snoc }, 1206 }; 1207 1208 static struct qcom_icc_node qns_gemnoc_gc = { 1209 .name = "qns_gemnoc_gc", 1210 .channels = 1, 1211 .buswidth = 8, 1212 .num_links = 1, 1213 .link_nodes = { &qnm_snoc_gc }, 1214 }; 1215 1216 static struct qcom_icc_node qns_gemnoc_sf = { 1217 .name = "qns_gemnoc_sf", 1218 .channels = 1, 1219 .buswidth = 16, 1220 .num_links = 1, 1221 .link_nodes = { &qnm_snoc_sf }, 1222 }; 1223 1224 static struct qcom_icc_node qxs_imem = { 1225 .name = "qxs_imem", 1226 .channels = 1, 1227 .buswidth = 8, 1228 }; 1229 1230 static struct qcom_icc_node qxs_pimem = { 1231 .name = "qxs_pimem", 1232 .channels = 1, 1233 .buswidth = 8, 1234 }; 1235 1236 static struct qcom_icc_node srvc_snoc = { 1237 .name = "srvc_snoc", 1238 .channels = 1, 1239 .buswidth = 4, 1240 }; 1241 1242 static struct qcom_icc_node xs_pcie_0 = { 1243 .name = "xs_pcie_0", 1244 .channels = 1, 1245 .buswidth = 8, 1246 }; 1247 1248 static struct qcom_icc_node xs_pcie_1 = { 1249 .name = "xs_pcie_1", 1250 .channels = 1, 1251 .buswidth = 8, 1252 }; 1253 1254 static struct qcom_icc_node xs_qdss_stm = { 1255 .name = "xs_qdss_stm", 1256 .channels = 1, 1257 .buswidth = 4, 1258 }; 1259 1260 static struct qcom_icc_node xs_sys_tcu_cfg = { 1261 .name = "xs_sys_tcu_cfg", 1262 .channels = 1, 1263 .buswidth = 8, 1264 }; 1265 1266 static struct qcom_icc_bcm bcm_acv = { 1267 .name = "ACV", 1268 .enable_mask = BIT(3), 1269 .keepalive = false, 1270 .num_nodes = 1, 1271 .nodes = { &ebi }, 1272 }; 1273 1274 static struct qcom_icc_bcm bcm_mc0 = { 1275 .name = "MC0", 1276 .keepalive = true, 1277 .num_nodes = 1, 1278 .nodes = { &ebi }, 1279 }; 1280 1281 static struct qcom_icc_bcm bcm_sh0 = { 1282 .name = "SH0", 1283 .keepalive = true, 1284 .num_nodes = 1, 1285 .nodes = { &qns_llcc }, 1286 }; 1287 1288 static struct qcom_icc_bcm bcm_mm0 = { 1289 .name = "MM0", 1290 .keepalive = true, 1291 .num_nodes = 1, 1292 .nodes = { &qns_mem_noc_hf }, 1293 }; 1294 1295 static struct qcom_icc_bcm bcm_mm1 = { 1296 .name = "MM1", 1297 .keepalive = false, 1298 .num_nodes = 7, 1299 .nodes = { &qxm_camnoc_hf0_uncomp, 1300 &qxm_camnoc_hf1_uncomp, 1301 &qxm_camnoc_sf_uncomp, 1302 &qxm_camnoc_hf0, 1303 &qxm_camnoc_hf1, 1304 &qxm_mdp0, 1305 &qxm_mdp1 1306 }, 1307 }; 1308 1309 static struct qcom_icc_bcm bcm_sh2 = { 1310 .name = "SH2", 1311 .keepalive = false, 1312 .num_nodes = 1, 1313 .nodes = { &qns_gem_noc_snoc }, 1314 }; 1315 1316 static struct qcom_icc_bcm bcm_mm2 = { 1317 .name = "MM2", 1318 .keepalive = false, 1319 .num_nodes = 2, 1320 .nodes = { &qxm_camnoc_sf, &qns2_mem_noc }, 1321 }; 1322 1323 static struct qcom_icc_bcm bcm_sh3 = { 1324 .name = "SH3", 1325 .keepalive = false, 1326 .num_nodes = 2, 1327 .nodes = { &acm_gpu_tcu, &acm_sys_tcu }, 1328 }; 1329 1330 static struct qcom_icc_bcm bcm_mm3 = { 1331 .name = "MM3", 1332 .keepalive = false, 1333 .num_nodes = 4, 1334 .nodes = { &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9 }, 1335 }; 1336 1337 static struct qcom_icc_bcm bcm_sh4 = { 1338 .name = "SH4", 1339 .keepalive = false, 1340 .num_nodes = 1, 1341 .nodes = { &qnm_cmpnoc }, 1342 }; 1343 1344 static struct qcom_icc_bcm bcm_sh5 = { 1345 .name = "SH5", 1346 .keepalive = false, 1347 .num_nodes = 1, 1348 .nodes = { &acm_apps }, 1349 }; 1350 1351 static struct qcom_icc_bcm bcm_sn0 = { 1352 .name = "SN0", 1353 .keepalive = true, 1354 .num_nodes = 1, 1355 .nodes = { &qns_gemnoc_sf }, 1356 }; 1357 1358 static struct qcom_icc_bcm bcm_co0 = { 1359 .name = "CO0", 1360 .keepalive = false, 1361 .num_nodes = 1, 1362 .nodes = { &qns_cdsp_mem_noc }, 1363 }; 1364 1365 static struct qcom_icc_bcm bcm_ce0 = { 1366 .name = "CE0", 1367 .keepalive = false, 1368 .num_nodes = 1, 1369 .nodes = { &qxm_crypto }, 1370 }; 1371 1372 static struct qcom_icc_bcm bcm_sn1 = { 1373 .name = "SN1", 1374 .keepalive = false, 1375 .num_nodes = 1, 1376 .nodes = { &qxs_imem }, 1377 }; 1378 1379 static struct qcom_icc_bcm bcm_co1 = { 1380 .name = "CO1", 1381 .keepalive = false, 1382 .num_nodes = 1, 1383 .nodes = { &qnm_npu }, 1384 }; 1385 1386 static struct qcom_icc_bcm bcm_cn0 = { 1387 .name = "CN0", 1388 .keepalive = true, 1389 .num_nodes = 53, 1390 .nodes = { &qhm_spdm, 1391 &qnm_snoc, 1392 &qhs_a1_noc_cfg, 1393 &qhs_a2_noc_cfg, 1394 &qhs_ahb2phy_south, 1395 &qhs_aop, 1396 &qhs_aoss, 1397 &qhs_camera_cfg, 1398 &qhs_clk_ctl, 1399 &qhs_compute_dsp, 1400 &qhs_cpr_cx, 1401 &qhs_cpr_mmcx, 1402 &qhs_cpr_mx, 1403 &qhs_crypto0_cfg, 1404 &qhs_ddrss_cfg, 1405 &qhs_display_cfg, 1406 &qhs_emac_cfg, 1407 &qhs_glm, 1408 &qhs_gpuss_cfg, 1409 &qhs_imem_cfg, 1410 &qhs_ipa, 1411 &qhs_mnoc_cfg, 1412 &qhs_npu_cfg, 1413 &qhs_pcie0_cfg, 1414 &qhs_pcie1_cfg, 1415 &qhs_phy_refgen_north, 1416 &qhs_pimem_cfg, 1417 &qhs_prng, 1418 &qhs_qdss_cfg, 1419 &qhs_qspi, 1420 &qhs_qupv3_east, 1421 &qhs_qupv3_north, 1422 &qhs_qupv3_south, 1423 &qhs_sdc2, 1424 &qhs_sdc4, 1425 &qhs_snoc_cfg, 1426 &qhs_spdm, 1427 &qhs_spss_cfg, 1428 &qhs_ssc_cfg, 1429 &qhs_tcsr, 1430 &qhs_tlmm_east, 1431 &qhs_tlmm_north, 1432 &qhs_tlmm_south, 1433 &qhs_tlmm_west, 1434 &qhs_tsif, 1435 &qhs_ufs_card_cfg, 1436 &qhs_ufs_mem_cfg, 1437 &qhs_usb3_0, 1438 &qhs_usb3_1, 1439 &qhs_venus_cfg, 1440 &qhs_vsense_ctrl_cfg, 1441 &qns_cnoc_a2noc, 1442 &srvc_cnoc 1443 }, 1444 }; 1445 1446 static struct qcom_icc_bcm bcm_qup0 = { 1447 .name = "QUP0", 1448 .keepalive = false, 1449 .num_nodes = 3, 1450 .nodes = { &qhm_qup0, &qhm_qup1, &qhm_qup2 }, 1451 }; 1452 1453 static struct qcom_icc_bcm bcm_sn2 = { 1454 .name = "SN2", 1455 .keepalive = false, 1456 .num_nodes = 1, 1457 .nodes = { &qns_gemnoc_gc }, 1458 }; 1459 1460 static struct qcom_icc_bcm bcm_sn3 = { 1461 .name = "SN3", 1462 .keepalive = false, 1463 .num_nodes = 3, 1464 .nodes = { &srvc_aggre1_noc, &srvc_aggre2_noc, &qns_cnoc }, 1465 }; 1466 1467 static struct qcom_icc_bcm bcm_sn4 = { 1468 .name = "SN4", 1469 .keepalive = false, 1470 .num_nodes = 1, 1471 .nodes = { &qxs_pimem }, 1472 }; 1473 1474 static struct qcom_icc_bcm bcm_sn5 = { 1475 .name = "SN5", 1476 .keepalive = false, 1477 .num_nodes = 1, 1478 .nodes = { &xs_qdss_stm }, 1479 }; 1480 1481 static struct qcom_icc_bcm bcm_sn8 = { 1482 .name = "SN8", 1483 .keepalive = false, 1484 .num_nodes = 2, 1485 .nodes = { &xs_pcie_0, &xs_pcie_1 }, 1486 }; 1487 1488 static struct qcom_icc_bcm bcm_sn9 = { 1489 .name = "SN9", 1490 .keepalive = false, 1491 .num_nodes = 1, 1492 .nodes = { &qnm_aggre1_noc }, 1493 }; 1494 1495 static struct qcom_icc_bcm bcm_sn11 = { 1496 .name = "SN11", 1497 .keepalive = false, 1498 .num_nodes = 1, 1499 .nodes = { &qnm_aggre2_noc }, 1500 }; 1501 1502 static struct qcom_icc_bcm bcm_sn12 = { 1503 .name = "SN12", 1504 .keepalive = false, 1505 .num_nodes = 2, 1506 .nodes = { &qxm_pimem, &xm_gic }, 1507 }; 1508 1509 static struct qcom_icc_bcm bcm_sn14 = { 1510 .name = "SN14", 1511 .keepalive = false, 1512 .num_nodes = 1, 1513 .nodes = { &qns_pcie_mem_noc }, 1514 }; 1515 1516 static struct qcom_icc_bcm bcm_sn15 = { 1517 .name = "SN15", 1518 .keepalive = false, 1519 .num_nodes = 1, 1520 .nodes = { &qnm_gemnoc }, 1521 }; 1522 1523 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 1524 &bcm_qup0, 1525 &bcm_sn3, 1526 }; 1527 1528 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1529 [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg, 1530 [MASTER_QUP_0] = &qhm_qup0, 1531 [MASTER_EMAC] = &xm_emac, 1532 [MASTER_UFS_MEM] = &xm_ufs_mem, 1533 [MASTER_USB3] = &xm_usb3_0, 1534 [MASTER_USB3_1] = &xm_usb3_1, 1535 [A1NOC_SNOC_SLV] = &qns_a1noc_snoc, 1536 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, 1537 }; 1538 1539 static const struct qcom_icc_desc sm8150_aggre1_noc = { 1540 .nodes = aggre1_noc_nodes, 1541 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 1542 .bcms = aggre1_noc_bcms, 1543 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 1544 }; 1545 1546 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 1547 &bcm_ce0, 1548 &bcm_qup0, 1549 &bcm_sn14, 1550 &bcm_sn3, 1551 }; 1552 1553 static struct qcom_icc_node * const aggre2_noc_nodes[] = { 1554 [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg, 1555 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 1556 [MASTER_QSPI] = &qhm_qspi, 1557 [MASTER_QUP_1] = &qhm_qup1, 1558 [MASTER_QUP_2] = &qhm_qup2, 1559 [MASTER_SENSORS_AHB] = &qhm_sensorss_ahb, 1560 [MASTER_TSIF] = &qhm_tsif, 1561 [MASTER_CNOC_A2NOC] = &qnm_cnoc, 1562 [MASTER_CRYPTO_CORE_0] = &qxm_crypto, 1563 [MASTER_IPA] = &qxm_ipa, 1564 [MASTER_PCIE] = &xm_pcie3_0, 1565 [MASTER_PCIE_1] = &xm_pcie3_1, 1566 [MASTER_QDSS_ETR] = &xm_qdss_etr, 1567 [MASTER_SDCC_2] = &xm_sdc2, 1568 [MASTER_SDCC_4] = &xm_sdc4, 1569 [A2NOC_SNOC_SLV] = &qns_a2noc_snoc, 1570 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, 1571 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, 1572 }; 1573 1574 static const struct qcom_icc_desc sm8150_aggre2_noc = { 1575 .nodes = aggre2_noc_nodes, 1576 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 1577 .bcms = aggre2_noc_bcms, 1578 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 1579 }; 1580 1581 static struct qcom_icc_bcm * const camnoc_virt_bcms[] = { 1582 &bcm_mm1, 1583 }; 1584 1585 static struct qcom_icc_node * const camnoc_virt_nodes[] = { 1586 [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp, 1587 [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp, 1588 [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp, 1589 [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp, 1590 }; 1591 1592 static const struct qcom_icc_desc sm8150_camnoc_virt = { 1593 .nodes = camnoc_virt_nodes, 1594 .num_nodes = ARRAY_SIZE(camnoc_virt_nodes), 1595 .bcms = camnoc_virt_bcms, 1596 .num_bcms = ARRAY_SIZE(camnoc_virt_bcms), 1597 }; 1598 1599 static struct qcom_icc_bcm * const compute_noc_bcms[] = { 1600 &bcm_co0, 1601 &bcm_co1, 1602 }; 1603 1604 static struct qcom_icc_node * const compute_noc_nodes[] = { 1605 [MASTER_NPU] = &qnm_npu, 1606 [SLAVE_CDSP_MEM_NOC] = &qns_cdsp_mem_noc, 1607 }; 1608 1609 static const struct qcom_icc_desc sm8150_compute_noc = { 1610 .nodes = compute_noc_nodes, 1611 .num_nodes = ARRAY_SIZE(compute_noc_nodes), 1612 .bcms = compute_noc_bcms, 1613 .num_bcms = ARRAY_SIZE(compute_noc_bcms), 1614 }; 1615 1616 static struct qcom_icc_bcm * const config_noc_bcms[] = { 1617 &bcm_cn0, 1618 }; 1619 1620 static struct qcom_icc_node * const config_noc_nodes[] = { 1621 [MASTER_SPDM] = &qhm_spdm, 1622 [SNOC_CNOC_MAS] = &qnm_snoc, 1623 [MASTER_QDSS_DAP] = &xm_qdss_dap, 1624 [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg, 1625 [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg, 1626 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy_south, 1627 [SLAVE_AOP] = &qhs_aop, 1628 [SLAVE_AOSS] = &qhs_aoss, 1629 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 1630 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1631 [SLAVE_CDSP_CFG] = &qhs_compute_dsp, 1632 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 1633 [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx, 1634 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, 1635 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1636 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg, 1637 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 1638 [SLAVE_EMAC_CFG] = &qhs_emac_cfg, 1639 [SLAVE_GLM] = &qhs_glm, 1640 [SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg, 1641 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1642 [SLAVE_IPA_CFG] = &qhs_ipa, 1643 [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg, 1644 [SLAVE_NPU_CFG] = &qhs_npu_cfg, 1645 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, 1646 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, 1647 [SLAVE_NORTH_PHY_CFG] = &qhs_phy_refgen_north, 1648 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 1649 [SLAVE_PRNG] = &qhs_prng, 1650 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1651 [SLAVE_QSPI] = &qhs_qspi, 1652 [SLAVE_QUP_2] = &qhs_qupv3_east, 1653 [SLAVE_QUP_1] = &qhs_qupv3_north, 1654 [SLAVE_QUP_0] = &qhs_qupv3_south, 1655 [SLAVE_SDCC_2] = &qhs_sdc2, 1656 [SLAVE_SDCC_4] = &qhs_sdc4, 1657 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, 1658 [SLAVE_SPDM_WRAPPER] = &qhs_spdm, 1659 [SLAVE_SPSS_CFG] = &qhs_spss_cfg, 1660 [SLAVE_SSC_CFG] = &qhs_ssc_cfg, 1661 [SLAVE_TCSR] = &qhs_tcsr, 1662 [SLAVE_TLMM_EAST] = &qhs_tlmm_east, 1663 [SLAVE_TLMM_NORTH] = &qhs_tlmm_north, 1664 [SLAVE_TLMM_SOUTH] = &qhs_tlmm_south, 1665 [SLAVE_TLMM_WEST] = &qhs_tlmm_west, 1666 [SLAVE_TSIF] = &qhs_tsif, 1667 [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg, 1668 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 1669 [SLAVE_USB3] = &qhs_usb3_0, 1670 [SLAVE_USB3_1] = &qhs_usb3_1, 1671 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1672 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 1673 [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc, 1674 [SLAVE_SERVICE_CNOC] = &srvc_cnoc, 1675 }; 1676 1677 static const struct qcom_icc_desc sm8150_config_noc = { 1678 .nodes = config_noc_nodes, 1679 .num_nodes = ARRAY_SIZE(config_noc_nodes), 1680 .bcms = config_noc_bcms, 1681 .num_bcms = ARRAY_SIZE(config_noc_bcms), 1682 }; 1683 1684 static struct qcom_icc_bcm * const dc_noc_bcms[] = { 1685 }; 1686 1687 static struct qcom_icc_node * const dc_noc_nodes[] = { 1688 [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc, 1689 [SLAVE_LLCC_CFG] = &qhs_llcc, 1690 [SLAVE_GEM_NOC_CFG] = &qhs_memnoc, 1691 }; 1692 1693 static const struct qcom_icc_desc sm8150_dc_noc = { 1694 .nodes = dc_noc_nodes, 1695 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 1696 .bcms = dc_noc_bcms, 1697 .num_bcms = ARRAY_SIZE(dc_noc_bcms), 1698 }; 1699 1700 static struct qcom_icc_bcm * const gem_noc_bcms[] = { 1701 &bcm_sh0, 1702 &bcm_sh2, 1703 &bcm_sh3, 1704 &bcm_sh4, 1705 &bcm_sh5, 1706 }; 1707 1708 static struct qcom_icc_node * const gem_noc_nodes[] = { 1709 [MASTER_AMPSS_M0] = &acm_apps, 1710 [MASTER_GPU_TCU] = &acm_gpu_tcu, 1711 [MASTER_SYS_TCU] = &acm_sys_tcu, 1712 [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg, 1713 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc, 1714 [MASTER_GRAPHICS_3D] = &qnm_gpu, 1715 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 1716 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 1717 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_pcie, 1718 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 1719 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 1720 [MASTER_ECC] = &qxm_ecc, 1721 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg, 1722 [SLAVE_ECC] = &qns_ecc, 1723 [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc, 1724 [SLAVE_LLCC] = &qns_llcc, 1725 [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc, 1726 }; 1727 1728 static const struct qcom_icc_desc sm8150_gem_noc = { 1729 .nodes = gem_noc_nodes, 1730 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 1731 .bcms = gem_noc_bcms, 1732 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 1733 }; 1734 1735 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 1736 &bcm_acv, 1737 &bcm_mc0, 1738 }; 1739 1740 static struct qcom_icc_node * const mc_virt_nodes[] = { 1741 [MASTER_LLCC] = &llcc_mc, 1742 [SLAVE_EBI_CH0] = &ebi, 1743 }; 1744 1745 static const struct qcom_icc_desc sm8150_mc_virt = { 1746 .nodes = mc_virt_nodes, 1747 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 1748 .bcms = mc_virt_bcms, 1749 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 1750 }; 1751 1752 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 1753 &bcm_mm0, 1754 &bcm_mm1, 1755 &bcm_mm2, 1756 &bcm_mm3, 1757 }; 1758 1759 static struct qcom_icc_node * const mmss_noc_nodes[] = { 1760 [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg, 1761 [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0, 1762 [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1, 1763 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf, 1764 [MASTER_MDP_PORT0] = &qxm_mdp0, 1765 [MASTER_MDP_PORT1] = &qxm_mdp1, 1766 [MASTER_ROTATOR] = &qxm_rot, 1767 [MASTER_VIDEO_P0] = &qxm_venus0, 1768 [MASTER_VIDEO_P1] = &qxm_venus1, 1769 [MASTER_VIDEO_PROC] = &qxm_venus_arm9, 1770 [SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc, 1771 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 1772 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 1773 }; 1774 1775 static const struct qcom_icc_desc sm8150_mmss_noc = { 1776 .nodes = mmss_noc_nodes, 1777 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 1778 .bcms = mmss_noc_bcms, 1779 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 1780 }; 1781 1782 static struct qcom_icc_bcm * const system_noc_bcms[] = { 1783 &bcm_sn0, 1784 &bcm_sn1, 1785 &bcm_sn11, 1786 &bcm_sn12, 1787 &bcm_sn15, 1788 &bcm_sn2, 1789 &bcm_sn3, 1790 &bcm_sn4, 1791 &bcm_sn5, 1792 &bcm_sn8, 1793 &bcm_sn9, 1794 }; 1795 1796 static struct qcom_icc_node * const system_noc_nodes[] = { 1797 [MASTER_SNOC_CFG] = &qhm_snoc_cfg, 1798 [A1NOC_SNOC_MAS] = &qnm_aggre1_noc, 1799 [A2NOC_SNOC_MAS] = &qnm_aggre2_noc, 1800 [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc, 1801 [MASTER_PIMEM] = &qxm_pimem, 1802 [MASTER_GIC] = &xm_gic, 1803 [SLAVE_APPSS] = &qhs_apss, 1804 [SNOC_CNOC_SLV] = &qns_cnoc, 1805 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, 1806 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 1807 [SLAVE_OCIMEM] = &qxs_imem, 1808 [SLAVE_PIMEM] = &qxs_pimem, 1809 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 1810 [SLAVE_PCIE_0] = &xs_pcie_0, 1811 [SLAVE_PCIE_1] = &xs_pcie_1, 1812 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1813 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1814 }; 1815 1816 static const struct qcom_icc_desc sm8150_system_noc = { 1817 .nodes = system_noc_nodes, 1818 .num_nodes = ARRAY_SIZE(system_noc_nodes), 1819 .bcms = system_noc_bcms, 1820 .num_bcms = ARRAY_SIZE(system_noc_bcms), 1821 }; 1822 1823 static const struct of_device_id qnoc_of_match[] = { 1824 { .compatible = "qcom,sm8150-aggre1-noc", 1825 .data = &sm8150_aggre1_noc}, 1826 { .compatible = "qcom,sm8150-aggre2-noc", 1827 .data = &sm8150_aggre2_noc}, 1828 { .compatible = "qcom,sm8150-camnoc-virt", 1829 .data = &sm8150_camnoc_virt}, 1830 { .compatible = "qcom,sm8150-compute-noc", 1831 .data = &sm8150_compute_noc}, 1832 { .compatible = "qcom,sm8150-config-noc", 1833 .data = &sm8150_config_noc}, 1834 { .compatible = "qcom,sm8150-dc-noc", 1835 .data = &sm8150_dc_noc}, 1836 { .compatible = "qcom,sm8150-gem-noc", 1837 .data = &sm8150_gem_noc}, 1838 { .compatible = "qcom,sm8150-mc-virt", 1839 .data = &sm8150_mc_virt}, 1840 { .compatible = "qcom,sm8150-mmss-noc", 1841 .data = &sm8150_mmss_noc}, 1842 { .compatible = "qcom,sm8150-system-noc", 1843 .data = &sm8150_system_noc}, 1844 { } 1845 }; 1846 MODULE_DEVICE_TABLE(of, qnoc_of_match); 1847 1848 static struct platform_driver qnoc_driver = { 1849 .probe = qcom_icc_rpmh_probe, 1850 .remove = qcom_icc_rpmh_remove, 1851 .driver = { 1852 .name = "qnoc-sm8150", 1853 .of_match_table = qnoc_of_match, 1854 }, 1855 }; 1856 module_platform_driver(qnoc_driver); 1857 1858 MODULE_DESCRIPTION("Qualcomm SM8150 NoC driver"); 1859 MODULE_LICENSE("GPL v2"); 1860