1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com> 5 */ 6 7 #include <linux/device.h> 8 #include <linux/interconnect.h> 9 #include <linux/interconnect-provider.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include <dt-bindings/interconnect/qcom,sm7150-rpmh.h> 13 14 #include "bcm-voter.h" 15 #include "icc-rpmh.h" 16 17 static struct qcom_icc_node qhm_a1noc_cfg; 18 static struct qcom_icc_node qhm_qup_center; 19 static struct qcom_icc_node qhm_tsif; 20 static struct qcom_icc_node xm_emmc; 21 static struct qcom_icc_node xm_sdc2; 22 static struct qcom_icc_node xm_sdc4; 23 static struct qcom_icc_node xm_ufs_mem; 24 static struct qcom_icc_node qhm_a2noc_cfg; 25 static struct qcom_icc_node qhm_qdss_bam; 26 static struct qcom_icc_node qhm_qup_north; 27 static struct qcom_icc_node qnm_cnoc; 28 static struct qcom_icc_node qxm_crypto; 29 static struct qcom_icc_node qxm_ipa; 30 static struct qcom_icc_node xm_pcie3_0; 31 static struct qcom_icc_node xm_qdss_etr; 32 static struct qcom_icc_node xm_usb3_0; 33 static struct qcom_icc_node qxm_camnoc_hf0_uncomp; 34 static struct qcom_icc_node qxm_camnoc_rt_uncomp; 35 static struct qcom_icc_node qxm_camnoc_sf_uncomp; 36 static struct qcom_icc_node qxm_camnoc_nrt_uncomp; 37 static struct qcom_icc_node qnm_npu; 38 static struct qcom_icc_node qhm_spdm; 39 static struct qcom_icc_node qnm_snoc; 40 static struct qcom_icc_node xm_qdss_dap; 41 static struct qcom_icc_node qhm_cnoc_dc_noc; 42 static struct qcom_icc_node acm_apps; 43 static struct qcom_icc_node acm_sys_tcu; 44 static struct qcom_icc_node qhm_gemnoc_cfg; 45 static struct qcom_icc_node qnm_cmpnoc; 46 static struct qcom_icc_node qnm_mnoc_hf; 47 static struct qcom_icc_node qnm_mnoc_sf; 48 static struct qcom_icc_node qnm_pcie; 49 static struct qcom_icc_node qnm_snoc_gc; 50 static struct qcom_icc_node qnm_snoc_sf; 51 static struct qcom_icc_node qxm_gpu; 52 static struct qcom_icc_node llcc_mc; 53 static struct qcom_icc_node qhm_mnoc_cfg; 54 static struct qcom_icc_node qxm_camnoc_hf; 55 static struct qcom_icc_node qxm_camnoc_nrt; 56 static struct qcom_icc_node qxm_camnoc_rt; 57 static struct qcom_icc_node qxm_camnoc_sf; 58 static struct qcom_icc_node qxm_mdp0; 59 static struct qcom_icc_node qxm_mdp1; 60 static struct qcom_icc_node qxm_rot; 61 static struct qcom_icc_node qxm_venus0; 62 static struct qcom_icc_node qxm_venus1; 63 static struct qcom_icc_node qxm_venus_arm9; 64 static struct qcom_icc_node qhm_snoc_cfg; 65 static struct qcom_icc_node qnm_aggre1_noc; 66 static struct qcom_icc_node qnm_aggre2_noc; 67 static struct qcom_icc_node qnm_gemnoc; 68 static struct qcom_icc_node qxm_pimem; 69 static struct qcom_icc_node xm_gic; 70 static struct qcom_icc_node qns_a1noc_snoc; 71 static struct qcom_icc_node srvc_aggre1_noc; 72 static struct qcom_icc_node qns_a2noc_snoc; 73 static struct qcom_icc_node qns_pcie_gemnoc; 74 static struct qcom_icc_node srvc_aggre2_noc; 75 static struct qcom_icc_node qns_camnoc_uncomp; 76 static struct qcom_icc_node qns_cdsp_gemnoc; 77 static struct qcom_icc_node qhs_a1_noc_cfg; 78 static struct qcom_icc_node qhs_a2_noc_cfg; 79 static struct qcom_icc_node qhs_ahb2phy_north; 80 static struct qcom_icc_node qhs_ahb2phy_south; 81 static struct qcom_icc_node qhs_ahb2phy_west; 82 static struct qcom_icc_node qhs_aop; 83 static struct qcom_icc_node qhs_aoss; 84 static struct qcom_icc_node qhs_camera_cfg; 85 static struct qcom_icc_node qhs_camera_nrt_thrott_cfg; 86 static struct qcom_icc_node qhs_camera_rt_throttle_cfg; 87 static struct qcom_icc_node qhs_clk_ctl; 88 static struct qcom_icc_node qhs_compute_dsp_cfg; 89 static struct qcom_icc_node qhs_cpr_cx; 90 static struct qcom_icc_node qhs_cpr_mx; 91 static struct qcom_icc_node qhs_crypto0_cfg; 92 static struct qcom_icc_node qhs_ddrss_cfg; 93 static struct qcom_icc_node qhs_display_cfg; 94 static struct qcom_icc_node qhs_display_throttle_cfg; 95 static struct qcom_icc_node qhs_emmc_cfg; 96 static struct qcom_icc_node qhs_glm; 97 static struct qcom_icc_node qhs_gpuss_cfg; 98 static struct qcom_icc_node qhs_imem_cfg; 99 static struct qcom_icc_node qhs_ipa; 100 static struct qcom_icc_node qhs_mnoc_cfg; 101 static struct qcom_icc_node qhs_pcie_cfg; 102 static struct qcom_icc_node qhs_pdm; 103 static struct qcom_icc_node qhs_pimem_cfg; 104 static struct qcom_icc_node qhs_prng; 105 static struct qcom_icc_node qhs_qdss_cfg; 106 static struct qcom_icc_node qhs_qupv3_center; 107 static struct qcom_icc_node qhs_qupv3_north; 108 static struct qcom_icc_node qhs_sdc2; 109 static struct qcom_icc_node qhs_sdc4; 110 static struct qcom_icc_node qhs_snoc_cfg; 111 static struct qcom_icc_node qhs_spdm; 112 static struct qcom_icc_node qhs_tcsr; 113 static struct qcom_icc_node qhs_tlmm_north; 114 static struct qcom_icc_node qhs_tlmm_south; 115 static struct qcom_icc_node qhs_tlmm_west; 116 static struct qcom_icc_node qhs_tsif; 117 static struct qcom_icc_node qhs_ufs_mem_cfg; 118 static struct qcom_icc_node qhs_usb3_0; 119 static struct qcom_icc_node qhs_venus_cfg; 120 static struct qcom_icc_node qhs_venus_cvp_throttle_cfg; 121 static struct qcom_icc_node qhs_venus_throttle_cfg; 122 static struct qcom_icc_node qhs_vsense_ctrl_cfg; 123 static struct qcom_icc_node qns_cnoc_a2noc; 124 static struct qcom_icc_node srvc_cnoc; 125 static struct qcom_icc_node qhs_gemnoc; 126 static struct qcom_icc_node qhs_llcc; 127 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; 128 static struct qcom_icc_node qns_gem_noc_snoc; 129 static struct qcom_icc_node qns_llcc; 130 static struct qcom_icc_node srvc_gemnoc; 131 static struct qcom_icc_node ebi; 132 static struct qcom_icc_node qns2_mem_noc; 133 static struct qcom_icc_node qns_mem_noc_hf; 134 static struct qcom_icc_node srvc_mnoc; 135 static struct qcom_icc_node qhs_apss; 136 static struct qcom_icc_node qns_cnoc; 137 static struct qcom_icc_node qns_gemnoc_gc; 138 static struct qcom_icc_node qns_gemnoc_sf; 139 static struct qcom_icc_node qxs_imem; 140 static struct qcom_icc_node qxs_pimem; 141 static struct qcom_icc_node srvc_snoc; 142 static struct qcom_icc_node xs_qdss_stm; 143 static struct qcom_icc_node xs_sys_tcu_cfg; 144 145 static struct qcom_icc_node qhm_a1noc_cfg = { 146 .name = "qhm_a1noc_cfg", 147 .channels = 1, 148 .buswidth = 4, 149 .num_links = 1, 150 .link_nodes = { &srvc_aggre1_noc }, 151 }; 152 153 static struct qcom_icc_node qhm_qup_center = { 154 .name = "qhm_qup_center", 155 .channels = 1, 156 .buswidth = 4, 157 .num_links = 1, 158 .link_nodes = { &qns_a1noc_snoc }, 159 }; 160 161 static struct qcom_icc_node qhm_tsif = { 162 .name = "qhm_tsif", 163 .channels = 1, 164 .buswidth = 4, 165 .num_links = 1, 166 .link_nodes = { &qns_a1noc_snoc }, 167 }; 168 169 static struct qcom_icc_node xm_emmc = { 170 .name = "xm_emmc", 171 .channels = 1, 172 .buswidth = 8, 173 .num_links = 1, 174 .link_nodes = { &qns_a1noc_snoc }, 175 }; 176 177 static struct qcom_icc_node xm_sdc2 = { 178 .name = "xm_sdc2", 179 .channels = 1, 180 .buswidth = 8, 181 .num_links = 1, 182 .link_nodes = { &qns_a1noc_snoc }, 183 }; 184 185 static struct qcom_icc_node xm_sdc4 = { 186 .name = "xm_sdc4", 187 .channels = 1, 188 .buswidth = 8, 189 .num_links = 1, 190 .link_nodes = { &qns_a1noc_snoc }, 191 }; 192 193 static struct qcom_icc_node xm_ufs_mem = { 194 .name = "xm_ufs_mem", 195 .channels = 1, 196 .buswidth = 8, 197 .num_links = 1, 198 .link_nodes = { &qns_a1noc_snoc }, 199 }; 200 201 static struct qcom_icc_node qhm_a2noc_cfg = { 202 .name = "qhm_a2noc_cfg", 203 .channels = 1, 204 .buswidth = 4, 205 .num_links = 1, 206 .link_nodes = { &srvc_aggre2_noc }, 207 }; 208 209 static struct qcom_icc_node qhm_qdss_bam = { 210 .name = "qhm_qdss_bam", 211 .channels = 1, 212 .buswidth = 4, 213 .num_links = 1, 214 .link_nodes = { &qns_a2noc_snoc }, 215 }; 216 217 static struct qcom_icc_node qhm_qup_north = { 218 .name = "qhm_qup_north", 219 .channels = 1, 220 .buswidth = 4, 221 .num_links = 1, 222 .link_nodes = { &qns_a2noc_snoc }, 223 }; 224 225 static struct qcom_icc_node qnm_cnoc = { 226 .name = "qnm_cnoc", 227 .channels = 1, 228 .buswidth = 8, 229 .num_links = 1, 230 .link_nodes = { &qns_a2noc_snoc }, 231 }; 232 233 static struct qcom_icc_node qxm_crypto = { 234 .name = "qxm_crypto", 235 .channels = 1, 236 .buswidth = 8, 237 .num_links = 1, 238 .link_nodes = { &qns_a2noc_snoc }, 239 }; 240 241 static struct qcom_icc_node qxm_ipa = { 242 .name = "qxm_ipa", 243 .channels = 1, 244 .buswidth = 8, 245 .num_links = 1, 246 .link_nodes = { &qns_a2noc_snoc }, 247 }; 248 249 static struct qcom_icc_node xm_pcie3_0 = { 250 .name = "xm_pcie3_0", 251 .channels = 1, 252 .buswidth = 8, 253 .num_links = 1, 254 .link_nodes = { &qns_pcie_gemnoc }, 255 }; 256 257 static struct qcom_icc_node xm_qdss_etr = { 258 .name = "xm_qdss_etr", 259 .channels = 1, 260 .buswidth = 8, 261 .num_links = 1, 262 .link_nodes = { &qns_a2noc_snoc }, 263 }; 264 265 static struct qcom_icc_node xm_usb3_0 = { 266 .name = "xm_usb3_0", 267 .channels = 1, 268 .buswidth = 8, 269 .num_links = 1, 270 .link_nodes = { &qns_a2noc_snoc }, 271 }; 272 273 static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { 274 .name = "qxm_camnoc_hf0_uncomp", 275 .channels = 2, 276 .buswidth = 32, 277 .num_links = 1, 278 .link_nodes = { &qns_camnoc_uncomp }, 279 }; 280 281 static struct qcom_icc_node qxm_camnoc_rt_uncomp = { 282 .name = "qxm_camnoc_rt_uncomp", 283 .channels = 1, 284 .buswidth = 32, 285 .num_links = 1, 286 .link_nodes = { &qns_camnoc_uncomp }, 287 }; 288 289 static struct qcom_icc_node qxm_camnoc_sf_uncomp = { 290 .name = "qxm_camnoc_sf_uncomp", 291 .channels = 1, 292 .buswidth = 32, 293 .num_links = 1, 294 .link_nodes = { &qns_camnoc_uncomp }, 295 }; 296 297 static struct qcom_icc_node qxm_camnoc_nrt_uncomp = { 298 .name = "qxm_camnoc_nrt_uncomp", 299 .channels = 1, 300 .buswidth = 32, 301 .num_links = 1, 302 .link_nodes = { &qns_camnoc_uncomp }, 303 }; 304 305 static struct qcom_icc_node qnm_npu = { 306 .name = "qnm_npu", 307 .channels = 1, 308 .buswidth = 32, 309 .num_links = 1, 310 .link_nodes = { &qns_cdsp_gemnoc }, 311 }; 312 313 static struct qcom_icc_node qhm_spdm = { 314 .name = "qhm_spdm", 315 .channels = 1, 316 .buswidth = 4, 317 .num_links = 1, 318 .link_nodes = { &qns_cnoc_a2noc }, 319 }; 320 321 static struct qcom_icc_node qnm_snoc = { 322 .name = "qnm_snoc", 323 .channels = 1, 324 .buswidth = 8, 325 .num_links = 47, 326 .link_nodes = { &qhs_tlmm_south, 327 &qhs_camera_cfg, 328 &qhs_sdc4, 329 &qhs_sdc2, 330 &qhs_mnoc_cfg, 331 &qhs_ufs_mem_cfg, 332 &qhs_qupv3_center, 333 &qhs_glm, 334 &qhs_pdm, 335 &qhs_camera_nrt_thrott_cfg, 336 &qhs_a2_noc_cfg, 337 &qhs_qdss_cfg, 338 &qhs_camera_rt_throttle_cfg, 339 &qhs_display_cfg, 340 &qhs_pcie_cfg, 341 &qhs_display_throttle_cfg, 342 &qhs_tcsr, 343 &qhs_venus_cvp_throttle_cfg, 344 &qhs_ddrss_cfg, 345 &qhs_ahb2phy_north, 346 &qhs_snoc_cfg, 347 &qhs_gpuss_cfg, 348 &qhs_venus_cfg, 349 &qhs_tsif, 350 &qhs_compute_dsp_cfg, 351 &qhs_clk_ctl, 352 &qhs_aop, 353 &qhs_qupv3_north, 354 &qhs_ahb2phy_south, 355 &srvc_cnoc, 356 &qhs_ahb2phy_west, 357 &qhs_usb3_0, 358 &qhs_venus_throttle_cfg, 359 &qhs_ipa, 360 &qhs_cpr_cx, 361 &qhs_tlmm_west, 362 &qhs_a1_noc_cfg, 363 &qhs_aoss, 364 &qhs_prng, 365 &qhs_vsense_ctrl_cfg, 366 &qhs_emmc_cfg, 367 &qhs_spdm, 368 &qhs_crypto0_cfg, 369 &qhs_pimem_cfg, 370 &qhs_tlmm_north, 371 &qhs_cpr_mx, 372 &qhs_imem_cfg }, 373 }; 374 375 static struct qcom_icc_node xm_qdss_dap = { 376 .name = "xm_qdss_dap", 377 .channels = 1, 378 .buswidth = 8, 379 .num_links = 48, 380 .link_nodes = { &qhs_tlmm_south, 381 &qhs_camera_cfg, 382 &qhs_sdc4, 383 &qhs_sdc2, 384 &qhs_mnoc_cfg, 385 &qhs_ufs_mem_cfg, 386 &qhs_qupv3_center, 387 &qhs_glm, 388 &qhs_pdm, 389 &qhs_camera_nrt_thrott_cfg, 390 &qhs_a2_noc_cfg, 391 &qhs_qdss_cfg, 392 &qhs_camera_rt_throttle_cfg, 393 &qhs_display_cfg, 394 &qhs_pcie_cfg, 395 &qhs_display_throttle_cfg, 396 &qhs_tcsr, 397 &qhs_venus_cvp_throttle_cfg, 398 &qhs_ddrss_cfg, 399 &qns_cnoc_a2noc, 400 &qhs_ahb2phy_north, 401 &qhs_snoc_cfg, 402 &qhs_gpuss_cfg, 403 &qhs_venus_cfg, 404 &qhs_tsif, 405 &qhs_compute_dsp_cfg, 406 &qhs_clk_ctl, 407 &qhs_aop, 408 &qhs_qupv3_north, 409 &qhs_ahb2phy_south, 410 &srvc_cnoc, 411 &qhs_ahb2phy_west, 412 &qhs_usb3_0, 413 &qhs_venus_throttle_cfg, 414 &qhs_ipa, 415 &qhs_cpr_cx, 416 &qhs_tlmm_west, 417 &qhs_a1_noc_cfg, 418 &qhs_aoss, 419 &qhs_prng, 420 &qhs_vsense_ctrl_cfg, 421 &qhs_emmc_cfg, 422 &qhs_spdm, 423 &qhs_crypto0_cfg, 424 &qhs_pimem_cfg, 425 &qhs_tlmm_north, 426 &qhs_cpr_mx, 427 &qhs_imem_cfg }, 428 }; 429 430 static struct qcom_icc_node qhm_cnoc_dc_noc = { 431 .name = "qhm_cnoc_dc_noc", 432 .channels = 1, 433 .buswidth = 4, 434 .num_links = 2, 435 .link_nodes = { &qhs_llcc, 436 &qhs_gemnoc }, 437 }; 438 439 static struct qcom_icc_node acm_apps = { 440 .name = "acm_apps", 441 .channels = 1, 442 .buswidth = 16, 443 .num_links = 2, 444 .link_nodes = { &qns_llcc, 445 &qns_gem_noc_snoc }, 446 }; 447 448 static struct qcom_icc_node acm_sys_tcu = { 449 .name = "acm_sys_tcu", 450 .channels = 1, 451 .buswidth = 8, 452 .num_links = 2, 453 .link_nodes = { &qns_llcc, 454 &qns_gem_noc_snoc }, 455 }; 456 457 static struct qcom_icc_node qhm_gemnoc_cfg = { 458 .name = "qhm_gemnoc_cfg", 459 .channels = 1, 460 .buswidth = 4, 461 .num_links = 2, 462 .link_nodes = { &srvc_gemnoc, 463 &qhs_mdsp_ms_mpu_cfg }, 464 }; 465 466 static struct qcom_icc_node qnm_cmpnoc = { 467 .name = "qnm_cmpnoc", 468 .channels = 1, 469 .buswidth = 32, 470 .num_links = 2, 471 .link_nodes = { &qns_llcc, 472 &qns_gem_noc_snoc }, 473 }; 474 475 static struct qcom_icc_node qnm_mnoc_hf = { 476 .name = "qnm_mnoc_hf", 477 .channels = 2, 478 .buswidth = 32, 479 .num_links = 1, 480 .link_nodes = { &qns_llcc }, 481 }; 482 483 static struct qcom_icc_node qnm_mnoc_sf = { 484 .name = "qnm_mnoc_sf", 485 .channels = 1, 486 .buswidth = 32, 487 .num_links = 2, 488 .link_nodes = { &qns_llcc, 489 &qns_gem_noc_snoc }, 490 }; 491 492 static struct qcom_icc_node qnm_pcie = { 493 .name = "qnm_pcie", 494 .channels = 1, 495 .buswidth = 8, 496 .num_links = 2, 497 .link_nodes = { &qns_llcc, 498 &qns_gem_noc_snoc }, 499 }; 500 501 static struct qcom_icc_node qnm_snoc_gc = { 502 .name = "qnm_snoc_gc", 503 .channels = 1, 504 .buswidth = 8, 505 .num_links = 1, 506 .link_nodes = { &qns_llcc }, 507 }; 508 509 static struct qcom_icc_node qnm_snoc_sf = { 510 .name = "qnm_snoc_sf", 511 .channels = 1, 512 .buswidth = 16, 513 .num_links = 1, 514 .link_nodes = { &qns_llcc }, 515 }; 516 517 static struct qcom_icc_node qxm_gpu = { 518 .name = "qxm_gpu", 519 .channels = 2, 520 .buswidth = 32, 521 .num_links = 2, 522 .link_nodes = { &qns_llcc, 523 &qns_gem_noc_snoc }, 524 }; 525 526 static struct qcom_icc_node llcc_mc = { 527 .name = "llcc_mc", 528 .channels = 2, 529 .buswidth = 4, 530 .num_links = 1, 531 .link_nodes = { &ebi }, 532 }; 533 534 static struct qcom_icc_node qhm_mnoc_cfg = { 535 .name = "qhm_mnoc_cfg", 536 .channels = 1, 537 .buswidth = 4, 538 .num_links = 1, 539 .link_nodes = { &srvc_mnoc }, 540 }; 541 542 static struct qcom_icc_node qxm_camnoc_hf = { 543 .name = "qxm_camnoc_hf", 544 .channels = 2, 545 .buswidth = 32, 546 .num_links = 1, 547 .link_nodes = { &qns_mem_noc_hf }, 548 }; 549 550 static struct qcom_icc_node qxm_camnoc_nrt = { 551 .name = "qxm_camnoc_nrt", 552 .channels = 1, 553 .buswidth = 8, 554 .num_links = 1, 555 .link_nodes = { &qns2_mem_noc }, 556 }; 557 558 static struct qcom_icc_node qxm_camnoc_rt = { 559 .name = "qxm_camnoc_rt", 560 .channels = 1, 561 .buswidth = 32, 562 .num_links = 1, 563 .link_nodes = { &qns_mem_noc_hf }, 564 }; 565 566 static struct qcom_icc_node qxm_camnoc_sf = { 567 .name = "qxm_camnoc_sf", 568 .channels = 1, 569 .buswidth = 32, 570 .num_links = 1, 571 .link_nodes = { &qns2_mem_noc }, 572 }; 573 574 static struct qcom_icc_node qxm_mdp0 = { 575 .name = "qxm_mdp0", 576 .channels = 1, 577 .buswidth = 32, 578 .num_links = 1, 579 .link_nodes = { &qns_mem_noc_hf }, 580 }; 581 582 static struct qcom_icc_node qxm_mdp1 = { 583 .name = "qxm_mdp1", 584 .channels = 1, 585 .buswidth = 32, 586 .num_links = 1, 587 .link_nodes = { &qns_mem_noc_hf }, 588 }; 589 590 static struct qcom_icc_node qxm_rot = { 591 .name = "qxm_rot", 592 .channels = 1, 593 .buswidth = 32, 594 .num_links = 1, 595 .link_nodes = { &qns2_mem_noc }, 596 }; 597 598 static struct qcom_icc_node qxm_venus0 = { 599 .name = "qxm_venus0", 600 .channels = 1, 601 .buswidth = 32, 602 .num_links = 1, 603 .link_nodes = { &qns2_mem_noc }, 604 }; 605 606 static struct qcom_icc_node qxm_venus1 = { 607 .name = "qxm_venus1", 608 .channels = 1, 609 .buswidth = 32, 610 .num_links = 1, 611 .link_nodes = { &qns2_mem_noc }, 612 }; 613 614 static struct qcom_icc_node qxm_venus_arm9 = { 615 .name = "qxm_venus_arm9", 616 .channels = 1, 617 .buswidth = 8, 618 .num_links = 1, 619 .link_nodes = { &qns2_mem_noc }, 620 }; 621 622 static struct qcom_icc_node qhm_snoc_cfg = { 623 .name = "qhm_snoc_cfg", 624 .channels = 1, 625 .buswidth = 4, 626 .num_links = 1, 627 .link_nodes = { &srvc_snoc }, 628 }; 629 630 static struct qcom_icc_node qnm_aggre1_noc = { 631 .name = "qnm_aggre1_noc", 632 .channels = 1, 633 .buswidth = 16, 634 .num_links = 6, 635 .link_nodes = { &qns_gemnoc_sf, 636 &qxs_pimem, 637 &qxs_imem, 638 &qhs_apss, 639 &qns_cnoc, 640 &xs_qdss_stm }, 641 }; 642 643 static struct qcom_icc_node qnm_aggre2_noc = { 644 .name = "qnm_aggre2_noc", 645 .channels = 1, 646 .buswidth = 16, 647 .num_links = 7, 648 .link_nodes = { &qns_gemnoc_sf, 649 &qxs_pimem, 650 &qxs_imem, 651 &qhs_apss, 652 &qns_cnoc, 653 &xs_sys_tcu_cfg, 654 &xs_qdss_stm }, 655 }; 656 657 static struct qcom_icc_node qnm_gemnoc = { 658 .name = "qnm_gemnoc", 659 .channels = 1, 660 .buswidth = 8, 661 .num_links = 6, 662 .link_nodes = { &qxs_pimem, 663 &qxs_imem, 664 &qhs_apss, 665 &qns_cnoc, 666 &xs_sys_tcu_cfg, 667 &xs_qdss_stm }, 668 }; 669 670 static struct qcom_icc_node qxm_pimem = { 671 .name = "qxm_pimem", 672 .channels = 1, 673 .buswidth = 8, 674 .num_links = 2, 675 .link_nodes = { &qns_gemnoc_gc, 676 &qxs_imem }, 677 }; 678 679 static struct qcom_icc_node xm_gic = { 680 .name = "xm_gic", 681 .channels = 1, 682 .buswidth = 8, 683 .num_links = 2, 684 .link_nodes = { &qns_gemnoc_gc, 685 &qxs_imem }, 686 }; 687 688 static struct qcom_icc_node qns_a1noc_snoc = { 689 .name = "qns_a1noc_snoc", 690 .channels = 1, 691 .buswidth = 16, 692 .num_links = 1, 693 .link_nodes = { &qnm_aggre1_noc }, 694 }; 695 696 static struct qcom_icc_node srvc_aggre1_noc = { 697 .name = "srvc_aggre1_noc", 698 .channels = 1, 699 .buswidth = 4, 700 }; 701 702 static struct qcom_icc_node qns_a2noc_snoc = { 703 .name = "qns_a2noc_snoc", 704 .channels = 1, 705 .buswidth = 16, 706 .num_links = 1, 707 .link_nodes = { &qnm_aggre2_noc }, 708 }; 709 710 static struct qcom_icc_node qns_pcie_gemnoc = { 711 .name = "qns_pcie_gemnoc", 712 .channels = 1, 713 .buswidth = 8, 714 .num_links = 1, 715 .link_nodes = { &qnm_pcie }, 716 }; 717 718 static struct qcom_icc_node srvc_aggre2_noc = { 719 .name = "srvc_aggre2_noc", 720 .channels = 1, 721 .buswidth = 4, 722 }; 723 724 static struct qcom_icc_node qns_camnoc_uncomp = { 725 .name = "qns_camnoc_uncomp", 726 .channels = 1, 727 .buswidth = 32, 728 }; 729 730 static struct qcom_icc_node qns_cdsp_gemnoc = { 731 .name = "qns_cdsp_gemnoc", 732 .channels = 1, 733 .buswidth = 32, 734 .num_links = 1, 735 .link_nodes = { &qnm_cmpnoc }, 736 }; 737 738 static struct qcom_icc_node qhs_a1_noc_cfg = { 739 .name = "qhs_a1_noc_cfg", 740 .channels = 1, 741 .buswidth = 4, 742 .num_links = 1, 743 .link_nodes = { &qhm_a1noc_cfg }, 744 }; 745 746 static struct qcom_icc_node qhs_a2_noc_cfg = { 747 .name = "qhs_a2_noc_cfg", 748 .channels = 1, 749 .buswidth = 4, 750 .num_links = 1, 751 .link_nodes = { &qhm_a2noc_cfg }, 752 }; 753 754 static struct qcom_icc_node qhs_ahb2phy_north = { 755 .name = "qhs_ahb2phy_north", 756 .channels = 1, 757 .buswidth = 4, 758 }; 759 760 static struct qcom_icc_node qhs_ahb2phy_south = { 761 .name = "qhs_ahb2phy_south", 762 .channels = 1, 763 .buswidth = 4, 764 }; 765 766 static struct qcom_icc_node qhs_ahb2phy_west = { 767 .name = "qhs_ahb2phy_west", 768 .channels = 1, 769 .buswidth = 4, 770 }; 771 772 static struct qcom_icc_node qhs_aop = { 773 .name = "qhs_aop", 774 .channels = 1, 775 .buswidth = 4, 776 }; 777 778 static struct qcom_icc_node qhs_aoss = { 779 .name = "qhs_aoss", 780 .channels = 1, 781 .buswidth = 4, 782 }; 783 784 static struct qcom_icc_node qhs_camera_cfg = { 785 .name = "qhs_camera_cfg", 786 .channels = 1, 787 .buswidth = 4, 788 }; 789 790 static struct qcom_icc_node qhs_camera_nrt_thrott_cfg = { 791 .name = "qhs_camera_nrt_thrott_cfg", 792 .channels = 1, 793 .buswidth = 4, 794 }; 795 796 static struct qcom_icc_node qhs_camera_rt_throttle_cfg = { 797 .name = "qhs_camera_rt_throttle_cfg", 798 .channels = 1, 799 .buswidth = 4, 800 }; 801 802 static struct qcom_icc_node qhs_clk_ctl = { 803 .name = "qhs_clk_ctl", 804 .channels = 1, 805 .buswidth = 4, 806 }; 807 808 static struct qcom_icc_node qhs_compute_dsp_cfg = { 809 .name = "qhs_compute_dsp_cfg", 810 .channels = 1, 811 .buswidth = 4, 812 }; 813 814 static struct qcom_icc_node qhs_cpr_cx = { 815 .name = "qhs_cpr_cx", 816 .channels = 1, 817 .buswidth = 4, 818 }; 819 820 static struct qcom_icc_node qhs_cpr_mx = { 821 .name = "qhs_cpr_mx", 822 .channels = 1, 823 .buswidth = 4, 824 }; 825 826 static struct qcom_icc_node qhs_crypto0_cfg = { 827 .name = "qhs_crypto0_cfg", 828 .channels = 1, 829 .buswidth = 4, 830 }; 831 832 static struct qcom_icc_node qhs_ddrss_cfg = { 833 .name = "qhs_ddrss_cfg", 834 .channels = 1, 835 .buswidth = 4, 836 .num_links = 1, 837 .link_nodes = { &qhm_cnoc_dc_noc }, 838 }; 839 840 static struct qcom_icc_node qhs_display_cfg = { 841 .name = "qhs_display_cfg", 842 .channels = 1, 843 .buswidth = 4, 844 }; 845 846 static struct qcom_icc_node qhs_display_throttle_cfg = { 847 .name = "qhs_display_throttle_cfg", 848 .channels = 1, 849 .buswidth = 4, 850 }; 851 852 static struct qcom_icc_node qhs_emmc_cfg = { 853 .name = "qhs_emmc_cfg", 854 .channels = 1, 855 .buswidth = 4, 856 }; 857 858 static struct qcom_icc_node qhs_glm = { 859 .name = "qhs_glm", 860 .channels = 1, 861 .buswidth = 4, 862 }; 863 864 static struct qcom_icc_node qhs_gpuss_cfg = { 865 .name = "qhs_gpuss_cfg", 866 .channels = 1, 867 .buswidth = 8, 868 }; 869 870 static struct qcom_icc_node qhs_imem_cfg = { 871 .name = "qhs_imem_cfg", 872 .channels = 1, 873 .buswidth = 4, 874 }; 875 876 static struct qcom_icc_node qhs_ipa = { 877 .name = "qhs_ipa", 878 .channels = 1, 879 .buswidth = 4, 880 }; 881 882 static struct qcom_icc_node qhs_mnoc_cfg = { 883 .name = "qhs_mnoc_cfg", 884 .channels = 1, 885 .buswidth = 4, 886 .num_links = 1, 887 .link_nodes = { &qhm_mnoc_cfg }, 888 }; 889 890 static struct qcom_icc_node qhs_pcie_cfg = { 891 .name = "qhs_pcie_cfg", 892 .channels = 1, 893 .buswidth = 4, 894 }; 895 896 static struct qcom_icc_node qhs_pdm = { 897 .name = "qhs_pdm", 898 .channels = 1, 899 .buswidth = 4, 900 }; 901 902 static struct qcom_icc_node qhs_pimem_cfg = { 903 .name = "qhs_pimem_cfg", 904 .channels = 1, 905 .buswidth = 4, 906 }; 907 908 static struct qcom_icc_node qhs_prng = { 909 .name = "qhs_prng", 910 .channels = 1, 911 .buswidth = 4, 912 }; 913 914 static struct qcom_icc_node qhs_qdss_cfg = { 915 .name = "qhs_qdss_cfg", 916 .channels = 1, 917 .buswidth = 4, 918 }; 919 920 static struct qcom_icc_node qhs_qupv3_center = { 921 .name = "qhs_qupv3_center", 922 .channels = 1, 923 .buswidth = 4, 924 }; 925 926 static struct qcom_icc_node qhs_qupv3_north = { 927 .name = "qhs_qupv3_north", 928 .channels = 1, 929 .buswidth = 4, 930 }; 931 932 static struct qcom_icc_node qhs_sdc2 = { 933 .name = "qhs_sdc2", 934 .channels = 1, 935 .buswidth = 4, 936 }; 937 938 static struct qcom_icc_node qhs_sdc4 = { 939 .name = "qhs_sdc4", 940 .channels = 1, 941 .buswidth = 4, 942 }; 943 944 static struct qcom_icc_node qhs_snoc_cfg = { 945 .name = "qhs_snoc_cfg", 946 .channels = 1, 947 .buswidth = 4, 948 .num_links = 1, 949 .link_nodes = { &qhm_snoc_cfg }, 950 }; 951 952 static struct qcom_icc_node qhs_spdm = { 953 .name = "qhs_spdm", 954 .channels = 1, 955 .buswidth = 4, 956 }; 957 958 static struct qcom_icc_node qhs_tcsr = { 959 .name = "qhs_tcsr", 960 .channels = 1, 961 .buswidth = 4, 962 }; 963 964 static struct qcom_icc_node qhs_tlmm_north = { 965 .name = "qhs_tlmm_north", 966 .channels = 1, 967 .buswidth = 4, 968 }; 969 970 static struct qcom_icc_node qhs_tlmm_south = { 971 .name = "qhs_tlmm_south", 972 .channels = 1, 973 .buswidth = 4, 974 }; 975 976 static struct qcom_icc_node qhs_tlmm_west = { 977 .name = "qhs_tlmm_west", 978 .channels = 1, 979 .buswidth = 4, 980 }; 981 982 static struct qcom_icc_node qhs_tsif = { 983 .name = "qhs_tsif", 984 .channels = 1, 985 .buswidth = 4, 986 }; 987 988 static struct qcom_icc_node qhs_ufs_mem_cfg = { 989 .name = "qhs_ufs_mem_cfg", 990 .channels = 1, 991 .buswidth = 4, 992 }; 993 994 static struct qcom_icc_node qhs_usb3_0 = { 995 .name = "qhs_usb3_0", 996 .channels = 1, 997 .buswidth = 4, 998 }; 999 1000 static struct qcom_icc_node qhs_venus_cfg = { 1001 .name = "qhs_venus_cfg", 1002 .channels = 1, 1003 .buswidth = 4, 1004 }; 1005 1006 static struct qcom_icc_node qhs_venus_cvp_throttle_cfg = { 1007 .name = "qhs_venus_cvp_throttle_cfg", 1008 .channels = 1, 1009 .buswidth = 4, 1010 }; 1011 1012 static struct qcom_icc_node qhs_venus_throttle_cfg = { 1013 .name = "qhs_venus_throttle_cfg", 1014 .channels = 1, 1015 .buswidth = 4, 1016 }; 1017 1018 static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 1019 .name = "qhs_vsense_ctrl_cfg", 1020 .channels = 1, 1021 .buswidth = 4, 1022 }; 1023 1024 static struct qcom_icc_node qns_cnoc_a2noc = { 1025 .name = "qns_cnoc_a2noc", 1026 .channels = 1, 1027 .buswidth = 8, 1028 .num_links = 1, 1029 .link_nodes = { &qnm_cnoc }, 1030 }; 1031 1032 static struct qcom_icc_node srvc_cnoc = { 1033 .name = "srvc_cnoc", 1034 .channels = 1, 1035 .buswidth = 4, 1036 }; 1037 1038 static struct qcom_icc_node qhs_gemnoc = { 1039 .name = "qhs_gemnoc", 1040 .channels = 1, 1041 .buswidth = 4, 1042 .num_links = 1, 1043 .link_nodes = { &qhm_gemnoc_cfg }, 1044 }; 1045 1046 static struct qcom_icc_node qhs_llcc = { 1047 .name = "qhs_llcc", 1048 .channels = 1, 1049 .buswidth = 4, 1050 }; 1051 1052 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { 1053 .name = "qhs_mdsp_ms_mpu_cfg", 1054 .channels = 1, 1055 .buswidth = 4, 1056 }; 1057 1058 static struct qcom_icc_node qns_gem_noc_snoc = { 1059 .name = "qns_gem_noc_snoc", 1060 .channels = 1, 1061 .buswidth = 8, 1062 .num_links = 1, 1063 .link_nodes = { &qnm_gemnoc }, 1064 }; 1065 1066 static struct qcom_icc_node qns_llcc = { 1067 .name = "qns_llcc", 1068 .channels = 2, 1069 .buswidth = 16, 1070 .num_links = 1, 1071 .link_nodes = { &llcc_mc }, 1072 }; 1073 1074 static struct qcom_icc_node srvc_gemnoc = { 1075 .name = "srvc_gemnoc", 1076 .channels = 1, 1077 .buswidth = 4, 1078 }; 1079 1080 static struct qcom_icc_node ebi = { 1081 .name = "ebi", 1082 .channels = 2, 1083 .buswidth = 4, 1084 }; 1085 1086 static struct qcom_icc_node qns2_mem_noc = { 1087 .name = "qns2_mem_noc", 1088 .channels = 1, 1089 .buswidth = 32, 1090 .num_links = 1, 1091 .link_nodes = { &qnm_mnoc_sf }, 1092 }; 1093 1094 static struct qcom_icc_node qns_mem_noc_hf = { 1095 .name = "qns_mem_noc_hf", 1096 .channels = 2, 1097 .buswidth = 32, 1098 .num_links = 1, 1099 .link_nodes = { &qnm_mnoc_hf }, 1100 }; 1101 1102 static struct qcom_icc_node srvc_mnoc = { 1103 .name = "srvc_mnoc", 1104 .channels = 1, 1105 .buswidth = 4, 1106 }; 1107 1108 static struct qcom_icc_node qhs_apss = { 1109 .name = "qhs_apss", 1110 .channels = 1, 1111 .buswidth = 8, 1112 }; 1113 1114 static struct qcom_icc_node qns_cnoc = { 1115 .name = "qns_cnoc", 1116 .channels = 1, 1117 .buswidth = 8, 1118 .num_links = 1, 1119 .link_nodes = { &qnm_snoc }, 1120 }; 1121 1122 static struct qcom_icc_node qns_gemnoc_gc = { 1123 .name = "qns_gemnoc_gc", 1124 .channels = 1, 1125 .buswidth = 8, 1126 .num_links = 1, 1127 .link_nodes = { &qnm_snoc_gc }, 1128 }; 1129 1130 static struct qcom_icc_node qns_gemnoc_sf = { 1131 .name = "qns_gemnoc_sf", 1132 .channels = 1, 1133 .buswidth = 16, 1134 .num_links = 1, 1135 .link_nodes = { &qnm_snoc_sf }, 1136 }; 1137 1138 static struct qcom_icc_node qxs_imem = { 1139 .name = "qxs_imem", 1140 .channels = 1, 1141 .buswidth = 8, 1142 }; 1143 1144 static struct qcom_icc_node qxs_pimem = { 1145 .name = "qxs_pimem", 1146 .channels = 1, 1147 .buswidth = 8, 1148 }; 1149 1150 static struct qcom_icc_node srvc_snoc = { 1151 .name = "srvc_snoc", 1152 .channels = 1, 1153 .buswidth = 4, 1154 }; 1155 1156 static struct qcom_icc_node xs_qdss_stm = { 1157 .name = "xs_qdss_stm", 1158 .channels = 1, 1159 .buswidth = 4, 1160 }; 1161 1162 static struct qcom_icc_node xs_sys_tcu_cfg = { 1163 .name = "xs_sys_tcu_cfg", 1164 .channels = 1, 1165 .buswidth = 8, 1166 }; 1167 1168 static struct qcom_icc_bcm bcm_acv = { 1169 .name = "ACV", 1170 .enable_mask = BIT(3), 1171 .keepalive = false, 1172 .num_nodes = 1, 1173 .nodes = { &ebi }, 1174 }; 1175 1176 static struct qcom_icc_bcm bcm_mc0 = { 1177 .name = "MC0", 1178 .keepalive = true, 1179 .num_nodes = 1, 1180 .nodes = { &ebi }, 1181 }; 1182 1183 static struct qcom_icc_bcm bcm_sh0 = { 1184 .name = "SH0", 1185 .keepalive = true, 1186 .num_nodes = 1, 1187 .nodes = { &qns_llcc }, 1188 }; 1189 1190 static struct qcom_icc_bcm bcm_mm0 = { 1191 .name = "MM0", 1192 .keepalive = true, 1193 .num_nodes = 1, 1194 .nodes = { &qns_mem_noc_hf }, 1195 }; 1196 1197 static struct qcom_icc_bcm bcm_mm1 = { 1198 .name = "MM1", 1199 .keepalive = true, 1200 .num_nodes = 8, 1201 .nodes = { &qxm_camnoc_hf0_uncomp, 1202 &qxm_camnoc_rt_uncomp, 1203 &qxm_camnoc_sf_uncomp, 1204 &qxm_camnoc_nrt_uncomp, 1205 &qxm_camnoc_hf, 1206 &qxm_camnoc_rt, 1207 &qxm_mdp0, 1208 &qxm_mdp1 1209 }, 1210 }; 1211 1212 static struct qcom_icc_bcm bcm_sh2 = { 1213 .name = "SH2", 1214 .keepalive = false, 1215 .num_nodes = 1, 1216 .nodes = { &qns_gem_noc_snoc }, 1217 }; 1218 1219 static struct qcom_icc_bcm bcm_sh3 = { 1220 .name = "SH3", 1221 .keepalive = false, 1222 .num_nodes = 1, 1223 .nodes = { &acm_sys_tcu }, 1224 }; 1225 1226 static struct qcom_icc_bcm bcm_mm2 = { 1227 .name = "MM2", 1228 .keepalive = false, 1229 .num_nodes = 2, 1230 .nodes = { &qxm_camnoc_nrt, 1231 &qns2_mem_noc 1232 }, 1233 }; 1234 1235 static struct qcom_icc_bcm bcm_mm3 = { 1236 .name = "MM3", 1237 .keepalive = false, 1238 .num_nodes = 5, 1239 .nodes = { &qxm_camnoc_sf, 1240 &qxm_rot, 1241 &qxm_venus0, 1242 &qxm_venus1, 1243 &qxm_venus_arm9 1244 }, 1245 }; 1246 1247 static struct qcom_icc_bcm bcm_sh5 = { 1248 .name = "SH5", 1249 .keepalive = false, 1250 .num_nodes = 1, 1251 .nodes = { &acm_apps }, 1252 }; 1253 1254 static struct qcom_icc_bcm bcm_sn0 = { 1255 .name = "SN0", 1256 .keepalive = true, 1257 .num_nodes = 1, 1258 .nodes = { &qns_gemnoc_sf }, 1259 }; 1260 1261 static struct qcom_icc_bcm bcm_sh8 = { 1262 .name = "SH8", 1263 .keepalive = false, 1264 .num_nodes = 1, 1265 .nodes = { &qns_cdsp_gemnoc }, 1266 }; 1267 1268 static struct qcom_icc_bcm bcm_sh10 = { 1269 .name = "SH10", 1270 .keepalive = false, 1271 .num_nodes = 1, 1272 .nodes = { &qnm_npu }, 1273 }; 1274 1275 static struct qcom_icc_bcm bcm_ce0 = { 1276 .name = "CE0", 1277 .keepalive = false, 1278 .num_nodes = 1, 1279 .nodes = { &qxm_crypto }, 1280 }; 1281 1282 static struct qcom_icc_bcm bcm_cn0 = { 1283 .name = "CN0", 1284 .keepalive = true, 1285 .num_nodes = 54, 1286 .nodes = { &qhm_tsif, 1287 &xm_emmc, 1288 &xm_sdc2, 1289 &xm_sdc4, 1290 &qhm_spdm, 1291 &qnm_snoc, 1292 &qhs_a1_noc_cfg, 1293 &qhs_a2_noc_cfg, 1294 &qhs_ahb2phy_north, 1295 &qhs_ahb2phy_south, 1296 &qhs_ahb2phy_west, 1297 &qhs_aop, 1298 &qhs_aoss, 1299 &qhs_camera_cfg, 1300 &qhs_camera_nrt_thrott_cfg, 1301 &qhs_camera_rt_throttle_cfg, 1302 &qhs_clk_ctl, 1303 &qhs_compute_dsp_cfg, 1304 &qhs_cpr_cx, 1305 &qhs_cpr_mx, 1306 &qhs_crypto0_cfg, 1307 &qhs_ddrss_cfg, 1308 &qhs_display_cfg, 1309 &qhs_display_throttle_cfg, 1310 &qhs_emmc_cfg, 1311 &qhs_glm, 1312 &qhs_gpuss_cfg, 1313 &qhs_imem_cfg, 1314 &qhs_ipa, 1315 &qhs_mnoc_cfg, 1316 &qhs_pcie_cfg, 1317 &qhs_pdm, 1318 &qhs_pimem_cfg, 1319 &qhs_prng, 1320 &qhs_qdss_cfg, 1321 &qhs_qupv3_center, 1322 &qhs_qupv3_north, 1323 &qhs_sdc2, 1324 &qhs_sdc4, 1325 &qhs_snoc_cfg, 1326 &qhs_spdm, 1327 &qhs_tcsr, 1328 &qhs_tlmm_north, 1329 &qhs_tlmm_south, 1330 &qhs_tlmm_west, 1331 &qhs_tsif, 1332 &qhs_ufs_mem_cfg, 1333 &qhs_usb3_0, 1334 &qhs_venus_cfg, 1335 &qhs_venus_cvp_throttle_cfg, 1336 &qhs_venus_throttle_cfg, 1337 &qhs_vsense_ctrl_cfg, 1338 &qns_cnoc_a2noc, 1339 &srvc_cnoc 1340 }, 1341 }; 1342 1343 static struct qcom_icc_bcm bcm_qup0 = { 1344 .name = "QUP0", 1345 .keepalive = false, 1346 .num_nodes = 2, 1347 .nodes = { &qhm_qup_center, 1348 &qhm_qup_north 1349 }, 1350 }; 1351 1352 static struct qcom_icc_bcm bcm_sn1 = { 1353 .name = "SN1", 1354 .keepalive = false, 1355 .num_nodes = 1, 1356 .nodes = { &qxs_imem }, 1357 }; 1358 1359 static struct qcom_icc_bcm bcm_sn2 = { 1360 .name = "SN2", 1361 .keepalive = false, 1362 .num_nodes = 1, 1363 .nodes = { &qns_gemnoc_gc }, 1364 }; 1365 1366 static struct qcom_icc_bcm bcm_sn4 = { 1367 .name = "SN4", 1368 .keepalive = false, 1369 .num_nodes = 1, 1370 .nodes = { &qxs_pimem }, 1371 }; 1372 1373 static struct qcom_icc_bcm bcm_sn9 = { 1374 .name = "SN9", 1375 .keepalive = false, 1376 .num_nodes = 2, 1377 .nodes = { &qnm_aggre1_noc, 1378 &qns_a1noc_snoc 1379 }, 1380 }; 1381 1382 static struct qcom_icc_bcm bcm_sn11 = { 1383 .name = "SN11", 1384 .keepalive = false, 1385 .num_nodes = 2, 1386 .nodes = { &qnm_aggre2_noc, 1387 &qns_a2noc_snoc 1388 }, 1389 }; 1390 1391 static struct qcom_icc_bcm bcm_sn12 = { 1392 .name = "SN12", 1393 .keepalive = false, 1394 .num_nodes = 2, 1395 .nodes = { &qxm_pimem, 1396 &xm_gic 1397 }, 1398 }; 1399 1400 static struct qcom_icc_bcm bcm_sn14 = { 1401 .name = "SN14", 1402 .keepalive = false, 1403 .num_nodes = 1, 1404 .nodes = { &qns_pcie_gemnoc }, 1405 }; 1406 1407 static struct qcom_icc_bcm bcm_sn15 = { 1408 .name = "SN15", 1409 .keepalive = false, 1410 .num_nodes = 1, 1411 .nodes = { &qnm_gemnoc }, 1412 }; 1413 1414 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 1415 &bcm_cn0, 1416 &bcm_qup0, 1417 &bcm_sn9, 1418 }; 1419 1420 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1421 [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg, 1422 [MASTER_QUP_0] = &qhm_qup_center, 1423 [MASTER_TSIF] = &qhm_tsif, 1424 [MASTER_EMMC] = &xm_emmc, 1425 [MASTER_SDCC_2] = &xm_sdc2, 1426 [MASTER_SDCC_4] = &xm_sdc4, 1427 [MASTER_UFS_MEM] = &xm_ufs_mem, 1428 [A1NOC_SNOC_SLV] = &qns_a1noc_snoc, 1429 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, 1430 }; 1431 1432 static const struct qcom_icc_desc sm7150_aggre1_noc = { 1433 .nodes = aggre1_noc_nodes, 1434 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 1435 .bcms = aggre1_noc_bcms, 1436 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 1437 }; 1438 1439 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 1440 &bcm_ce0, 1441 &bcm_qup0, 1442 &bcm_sn11, 1443 &bcm_sn14, 1444 }; 1445 1446 static struct qcom_icc_node * const aggre2_noc_nodes[] = { 1447 [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg, 1448 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 1449 [MASTER_QUP_1] = &qhm_qup_north, 1450 [MASTER_CNOC_A2NOC] = &qnm_cnoc, 1451 [MASTER_CRYPTO_CORE_0] = &qxm_crypto, 1452 [MASTER_IPA] = &qxm_ipa, 1453 [MASTER_PCIE] = &xm_pcie3_0, 1454 [MASTER_QDSS_ETR] = &xm_qdss_etr, 1455 [MASTER_USB3] = &xm_usb3_0, 1456 [A2NOC_SNOC_SLV] = &qns_a2noc_snoc, 1457 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_gemnoc, 1458 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, 1459 }; 1460 1461 static const struct qcom_icc_desc sm7150_aggre2_noc = { 1462 .nodes = aggre2_noc_nodes, 1463 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 1464 .bcms = aggre2_noc_bcms, 1465 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 1466 }; 1467 1468 static struct qcom_icc_bcm * const camnoc_virt_bcms[] = { 1469 &bcm_mm1, 1470 }; 1471 1472 static struct qcom_icc_node * const camnoc_virt_nodes[] = { 1473 [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp, 1474 [MASTER_CAMNOC_RT_UNCOMP] = &qxm_camnoc_rt_uncomp, 1475 [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp, 1476 [MASTER_CAMNOC_NRT_UNCOMP] = &qxm_camnoc_nrt_uncomp, 1477 [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp, 1478 }; 1479 1480 static const struct qcom_icc_desc sm7150_camnoc_virt = { 1481 .nodes = camnoc_virt_nodes, 1482 .num_nodes = ARRAY_SIZE(camnoc_virt_nodes), 1483 .bcms = camnoc_virt_bcms, 1484 .num_bcms = ARRAY_SIZE(camnoc_virt_bcms), 1485 }; 1486 1487 static struct qcom_icc_bcm * const compute_noc_bcms[] = { 1488 &bcm_sh10, 1489 &bcm_sh8, 1490 }; 1491 1492 static struct qcom_icc_node * const compute_noc_nodes[] = { 1493 [MASTER_NPU] = &qnm_npu, 1494 [SLAVE_CDSP_GEM_NOC] = &qns_cdsp_gemnoc, 1495 }; 1496 1497 static const struct qcom_icc_desc sm7150_compute_noc = { 1498 .nodes = compute_noc_nodes, 1499 .num_nodes = ARRAY_SIZE(compute_noc_nodes), 1500 .bcms = compute_noc_bcms, 1501 .num_bcms = ARRAY_SIZE(compute_noc_bcms), 1502 }; 1503 1504 static struct qcom_icc_bcm * const config_noc_bcms[] = { 1505 &bcm_cn0, 1506 }; 1507 1508 static struct qcom_icc_node * const config_noc_nodes[] = { 1509 [MASTER_SPDM] = &qhm_spdm, 1510 [SNOC_CNOC_MAS] = &qnm_snoc, 1511 [MASTER_QDSS_DAP] = &xm_qdss_dap, 1512 [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg, 1513 [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg, 1514 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy_north, 1515 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy_south, 1516 [SLAVE_AHB2PHY_WEST] = &qhs_ahb2phy_west, 1517 [SLAVE_AOP] = &qhs_aop, 1518 [SLAVE_AOSS] = &qhs_aoss, 1519 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 1520 [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_thrott_cfg, 1521 [SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg, 1522 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1523 [SLAVE_CDSP_CFG] = &qhs_compute_dsp_cfg, 1524 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 1525 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, 1526 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1527 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg, 1528 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 1529 [SLAVE_DISPLAY_THROTTLE_CFG] = &qhs_display_throttle_cfg, 1530 [SLAVE_EMMC_CFG] = &qhs_emmc_cfg, 1531 [SLAVE_GLM] = &qhs_glm, 1532 [SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg, 1533 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1534 [SLAVE_IPA_CFG] = &qhs_ipa, 1535 [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg, 1536 [SLAVE_PCIE_CFG] = &qhs_pcie_cfg, 1537 [SLAVE_PDM] = &qhs_pdm, 1538 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 1539 [SLAVE_PRNG] = &qhs_prng, 1540 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1541 [SLAVE_QUP_0] = &qhs_qupv3_center, 1542 [SLAVE_QUP_1] = &qhs_qupv3_north, 1543 [SLAVE_SDCC_2] = &qhs_sdc2, 1544 [SLAVE_SDCC_4] = &qhs_sdc4, 1545 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, 1546 [SLAVE_SPDM_WRAPPER] = &qhs_spdm, 1547 [SLAVE_TCSR] = &qhs_tcsr, 1548 [SLAVE_TLMM_NORTH] = &qhs_tlmm_north, 1549 [SLAVE_TLMM_SOUTH] = &qhs_tlmm_south, 1550 [SLAVE_TLMM_WEST] = &qhs_tlmm_west, 1551 [SLAVE_TSIF] = &qhs_tsif, 1552 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 1553 [SLAVE_USB3] = &qhs_usb3_0, 1554 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1555 [SLAVE_VENUS_CVP_THROTTLE_CFG] = &qhs_venus_cvp_throttle_cfg, 1556 [SLAVE_VENUS_THROTTLE_CFG] = &qhs_venus_throttle_cfg, 1557 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 1558 [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc, 1559 [SLAVE_SERVICE_CNOC] = &srvc_cnoc, 1560 }; 1561 1562 static const struct qcom_icc_desc sm7150_config_noc = { 1563 .nodes = config_noc_nodes, 1564 .num_nodes = ARRAY_SIZE(config_noc_nodes), 1565 .bcms = config_noc_bcms, 1566 .num_bcms = ARRAY_SIZE(config_noc_bcms), 1567 }; 1568 1569 static struct qcom_icc_bcm * const dc_noc_bcms[] = { 1570 }; 1571 1572 static struct qcom_icc_node * const dc_noc_nodes[] = { 1573 [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc, 1574 [SLAVE_GEM_NOC_CFG] = &qhs_gemnoc, 1575 [SLAVE_LLCC_CFG] = &qhs_llcc, 1576 }; 1577 1578 static const struct qcom_icc_desc sm7150_dc_noc = { 1579 .nodes = dc_noc_nodes, 1580 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 1581 .bcms = dc_noc_bcms, 1582 .num_bcms = ARRAY_SIZE(dc_noc_bcms), 1583 }; 1584 1585 static struct qcom_icc_bcm * const gem_noc_bcms[] = { 1586 &bcm_sh0, 1587 &bcm_sh2, 1588 &bcm_sh3, 1589 &bcm_sh5, 1590 }; 1591 1592 static struct qcom_icc_node * const gem_noc_nodes[] = { 1593 [MASTER_AMPSS_M0] = &acm_apps, 1594 [MASTER_SYS_TCU] = &acm_sys_tcu, 1595 [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg, 1596 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc, 1597 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 1598 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 1599 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_pcie, 1600 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 1601 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 1602 [MASTER_GRAPHICS_3D] = &qxm_gpu, 1603 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg, 1604 [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc, 1605 [SLAVE_LLCC] = &qns_llcc, 1606 [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc, 1607 }; 1608 1609 static const struct qcom_icc_desc sm7150_gem_noc = { 1610 .nodes = gem_noc_nodes, 1611 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 1612 .bcms = gem_noc_bcms, 1613 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 1614 }; 1615 1616 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 1617 &bcm_acv, 1618 &bcm_mc0, 1619 }; 1620 1621 static struct qcom_icc_node * const mc_virt_nodes[] = { 1622 [MASTER_LLCC] = &llcc_mc, 1623 [SLAVE_EBI_CH0] = &ebi, 1624 }; 1625 1626 static const struct qcom_icc_desc sm7150_mc_virt = { 1627 .nodes = mc_virt_nodes, 1628 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 1629 .bcms = mc_virt_bcms, 1630 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 1631 }; 1632 1633 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 1634 &bcm_mm0, 1635 &bcm_mm1, 1636 &bcm_mm2, 1637 &bcm_mm3, 1638 }; 1639 1640 static struct qcom_icc_node * const mmss_noc_nodes[] = { 1641 [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg, 1642 [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf, 1643 [MASTER_CAMNOC_NRT] = &qxm_camnoc_nrt, 1644 [MASTER_CAMNOC_RT] = &qxm_camnoc_rt, 1645 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf, 1646 [MASTER_MDP_PORT0] = &qxm_mdp0, 1647 [MASTER_MDP_PORT1] = &qxm_mdp1, 1648 [MASTER_ROTATOR] = &qxm_rot, 1649 [MASTER_VIDEO_P0] = &qxm_venus0, 1650 [MASTER_VIDEO_P1] = &qxm_venus1, 1651 [MASTER_VIDEO_PROC] = &qxm_venus_arm9, 1652 [SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc, 1653 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 1654 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 1655 }; 1656 1657 static const struct qcom_icc_desc sm7150_mmss_noc = { 1658 .nodes = mmss_noc_nodes, 1659 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 1660 .bcms = mmss_noc_bcms, 1661 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 1662 }; 1663 1664 static struct qcom_icc_bcm * const system_noc_bcms[] = { 1665 &bcm_sn0, 1666 &bcm_sn1, 1667 &bcm_sn11, 1668 &bcm_sn12, 1669 &bcm_sn15, 1670 &bcm_sn2, 1671 &bcm_sn4, 1672 &bcm_sn9, 1673 }; 1674 1675 static struct qcom_icc_node * const system_noc_nodes[] = { 1676 [MASTER_SNOC_CFG] = &qhm_snoc_cfg, 1677 [A1NOC_SNOC_MAS] = &qnm_aggre1_noc, 1678 [A2NOC_SNOC_MAS] = &qnm_aggre2_noc, 1679 [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc, 1680 [MASTER_PIMEM] = &qxm_pimem, 1681 [MASTER_GIC] = &xm_gic, 1682 [SLAVE_APPSS] = &qhs_apss, 1683 [SNOC_CNOC_SLV] = &qns_cnoc, 1684 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, 1685 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 1686 [SLAVE_OCIMEM] = &qxs_imem, 1687 [SLAVE_PIMEM] = &qxs_pimem, 1688 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 1689 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1690 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1691 }; 1692 1693 static const struct qcom_icc_desc sm7150_system_noc = { 1694 .nodes = system_noc_nodes, 1695 .num_nodes = ARRAY_SIZE(system_noc_nodes), 1696 .bcms = system_noc_bcms, 1697 .num_bcms = ARRAY_SIZE(system_noc_bcms), 1698 }; 1699 1700 static const struct of_device_id qnoc_of_match[] = { 1701 { .compatible = "qcom,sm7150-aggre1-noc", .data = &sm7150_aggre1_noc }, 1702 { .compatible = "qcom,sm7150-aggre2-noc", .data = &sm7150_aggre2_noc }, 1703 { .compatible = "qcom,sm7150-camnoc-virt", .data = &sm7150_camnoc_virt }, 1704 { .compatible = "qcom,sm7150-compute-noc", .data = &sm7150_compute_noc }, 1705 { .compatible = "qcom,sm7150-config-noc", .data = &sm7150_config_noc }, 1706 { .compatible = "qcom,sm7150-dc-noc", .data = &sm7150_dc_noc }, 1707 { .compatible = "qcom,sm7150-gem-noc", .data = &sm7150_gem_noc }, 1708 { .compatible = "qcom,sm7150-mc-virt", .data = &sm7150_mc_virt }, 1709 { .compatible = "qcom,sm7150-mmss-noc", .data = &sm7150_mmss_noc }, 1710 { .compatible = "qcom,sm7150-system-noc", .data = &sm7150_system_noc }, 1711 { } 1712 }; 1713 MODULE_DEVICE_TABLE(of, qnoc_of_match); 1714 1715 static struct platform_driver qnoc_driver = { 1716 .probe = qcom_icc_rpmh_probe, 1717 .remove = qcom_icc_rpmh_remove, 1718 .driver = { 1719 .name = "qnoc-sm7150", 1720 .of_match_table = qnoc_of_match, 1721 .sync_state = icc_sync_state, 1722 }, 1723 }; 1724 1725 static int __init qnoc_driver_init(void) 1726 { 1727 return platform_driver_register(&qnoc_driver); 1728 } 1729 core_initcall(qnoc_driver_init); 1730 1731 static void __exit qnoc_driver_exit(void) 1732 { 1733 platform_driver_unregister(&qnoc_driver); 1734 } 1735 module_exit(qnoc_driver_exit); 1736 1737 MODULE_DESCRIPTION("Qualcomm SM7150 NoC driver"); 1738 MODULE_LICENSE("GPL"); 1739