1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2022 Luca Weiss <luca.weiss@fairphone.com> 4 */ 5 6 #include <linux/device.h> 7 #include <linux/interconnect.h> 8 #include <linux/interconnect-provider.h> 9 #include <linux/mod_devicetable.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include <dt-bindings/interconnect/qcom,sm6350.h> 13 14 #include "bcm-voter.h" 15 #include "icc-rpmh.h" 16 #include "sm6350.h" 17 18 DEFINE_QNODE(qhm_a1noc_cfg, SM6350_MASTER_A1NOC_CFG, 1, 4, SM6350_SLAVE_SERVICE_A1NOC); 19 DEFINE_QNODE(qhm_qup_0, SM6350_MASTER_QUP_0, 1, 4, SM6350_A1NOC_SNOC_SLV); 20 DEFINE_QNODE(xm_emmc, SM6350_MASTER_EMMC, 1, 8, SM6350_A1NOC_SNOC_SLV); 21 DEFINE_QNODE(xm_ufs_mem, SM6350_MASTER_UFS_MEM, 1, 8, SM6350_A1NOC_SNOC_SLV); 22 DEFINE_QNODE(qhm_a2noc_cfg, SM6350_MASTER_A2NOC_CFG, 1, 4, SM6350_SLAVE_SERVICE_A2NOC); 23 DEFINE_QNODE(qhm_qdss_bam, SM6350_MASTER_QDSS_BAM, 1, 4, SM6350_A2NOC_SNOC_SLV); 24 DEFINE_QNODE(qhm_qup_1, SM6350_MASTER_QUP_1, 1, 4, SM6350_A2NOC_SNOC_SLV); 25 DEFINE_QNODE(qxm_crypto, SM6350_MASTER_CRYPTO_CORE_0, 1, 8, SM6350_A2NOC_SNOC_SLV); 26 DEFINE_QNODE(qxm_ipa, SM6350_MASTER_IPA, 1, 8, SM6350_A2NOC_SNOC_SLV); 27 DEFINE_QNODE(xm_qdss_etr, SM6350_MASTER_QDSS_ETR, 1, 8, SM6350_A2NOC_SNOC_SLV); 28 DEFINE_QNODE(xm_sdc2, SM6350_MASTER_SDCC_2, 1, 8, SM6350_A2NOC_SNOC_SLV); 29 DEFINE_QNODE(xm_usb3_0, SM6350_MASTER_USB3, 1, 8, SM6350_A2NOC_SNOC_SLV); 30 DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SM6350_MASTER_CAMNOC_HF0_UNCOMP, 2, 32, SM6350_SLAVE_CAMNOC_UNCOMP); 31 DEFINE_QNODE(qxm_camnoc_icp_uncomp, SM6350_MASTER_CAMNOC_ICP_UNCOMP, 1, 32, SM6350_SLAVE_CAMNOC_UNCOMP); 32 DEFINE_QNODE(qxm_camnoc_sf_uncomp, SM6350_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SM6350_SLAVE_CAMNOC_UNCOMP); 33 DEFINE_QNODE(qup0_core_master, SM6350_MASTER_QUP_CORE_0, 1, 4, SM6350_SLAVE_QUP_CORE_0); 34 DEFINE_QNODE(qup1_core_master, SM6350_MASTER_QUP_CORE_1, 1, 4, SM6350_SLAVE_QUP_CORE_1); 35 DEFINE_QNODE(qnm_npu, SM6350_MASTER_NPU, 2, 32, SM6350_SLAVE_CDSP_GEM_NOC); 36 DEFINE_QNODE(qxm_npu_dsp, SM6350_MASTER_NPU_PROC, 1, 8, SM6350_SLAVE_CDSP_GEM_NOC); 37 DEFINE_QNODE(qnm_snoc, SM6350_SNOC_CNOC_MAS, 1, 8, SM6350_SLAVE_CAMERA_CFG, SM6350_SLAVE_SDCC_2, SM6350_SLAVE_CNOC_MNOC_CFG, SM6350_SLAVE_UFS_MEM_CFG, SM6350_SLAVE_QM_CFG, SM6350_SLAVE_SNOC_CFG, SM6350_SLAVE_QM_MPU_CFG, SM6350_SLAVE_GLM, SM6350_SLAVE_PDM, SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, SM6350_SLAVE_A2NOC_CFG, SM6350_SLAVE_QDSS_CFG, SM6350_SLAVE_VSENSE_CTRL_CFG, SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, SM6350_SLAVE_DISPLAY_CFG, SM6350_SLAVE_TCSR, SM6350_SLAVE_DCC_CFG, SM6350_SLAVE_CNOC_DDRSS, SM6350_SLAVE_DISPLAY_THROTTLE_CFG, SM6350_SLAVE_NPU_CFG, SM6350_SLAVE_AHB2PHY, SM6350_SLAVE_GRAPHICS_3D_CFG, SM6350_SLAVE_BOOT_ROM, SM6350_SLAVE_VENUS_CFG, SM6350_SLAVE_IPA_CFG, SM6350_SLAVE_SECURITY, SM6350_SLAVE_IMEM_CFG, SM6350_SLAVE_CNOC_MSS, SM6350_SLAVE_SERVICE_CNOC, SM6350_SLAVE_USB3, SM6350_SLAVE_VENUS_THROTTLE_CFG, SM6350_SLAVE_RBCPR_CX_CFG, SM6350_SLAVE_A1NOC_CFG, SM6350_SLAVE_AOSS, SM6350_SLAVE_PRNG, SM6350_SLAVE_EMMC_CFG, SM6350_SLAVE_CRYPTO_0_CFG, SM6350_SLAVE_PIMEM_CFG, SM6350_SLAVE_RBCPR_MX_CFG, SM6350_SLAVE_QUP_0, SM6350_SLAVE_QUP_1, SM6350_SLAVE_CLK_CTL); 38 DEFINE_QNODE(xm_qdss_dap, SM6350_MASTER_QDSS_DAP, 1, 8, SM6350_SLAVE_CAMERA_CFG, SM6350_SLAVE_SDCC_2, SM6350_SLAVE_CNOC_MNOC_CFG, SM6350_SLAVE_UFS_MEM_CFG, SM6350_SLAVE_QM_CFG, SM6350_SLAVE_SNOC_CFG, SM6350_SLAVE_QM_MPU_CFG, SM6350_SLAVE_GLM, SM6350_SLAVE_PDM, SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, SM6350_SLAVE_A2NOC_CFG, SM6350_SLAVE_QDSS_CFG, SM6350_SLAVE_VSENSE_CTRL_CFG, SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, SM6350_SLAVE_DISPLAY_CFG, SM6350_SLAVE_TCSR, SM6350_SLAVE_DCC_CFG, SM6350_SLAVE_CNOC_DDRSS, SM6350_SLAVE_DISPLAY_THROTTLE_CFG, SM6350_SLAVE_NPU_CFG, SM6350_SLAVE_AHB2PHY, SM6350_SLAVE_GRAPHICS_3D_CFG, SM6350_SLAVE_BOOT_ROM, SM6350_SLAVE_VENUS_CFG, SM6350_SLAVE_IPA_CFG, SM6350_SLAVE_SECURITY, SM6350_SLAVE_IMEM_CFG, SM6350_SLAVE_CNOC_MSS, SM6350_SLAVE_SERVICE_CNOC, SM6350_SLAVE_USB3, SM6350_SLAVE_VENUS_THROTTLE_CFG, SM6350_SLAVE_RBCPR_CX_CFG, SM6350_SLAVE_A1NOC_CFG, SM6350_SLAVE_AOSS, SM6350_SLAVE_PRNG, SM6350_SLAVE_EMMC_CFG, SM6350_SLAVE_CRYPTO_0_CFG, SM6350_SLAVE_PIMEM_CFG, SM6350_SLAVE_RBCPR_MX_CFG, SM6350_SLAVE_QUP_0, SM6350_SLAVE_QUP_1, SM6350_SLAVE_CLK_CTL); 39 DEFINE_QNODE(qhm_cnoc_dc_noc, SM6350_MASTER_CNOC_DC_NOC, 1, 4, SM6350_SLAVE_LLCC_CFG, SM6350_SLAVE_GEM_NOC_CFG); 40 DEFINE_QNODE(acm_apps, SM6350_MASTER_AMPSS_M0, 1, 16, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC); 41 DEFINE_QNODE(acm_sys_tcu, SM6350_MASTER_SYS_TCU, 1, 8, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC); 42 DEFINE_QNODE(qhm_gemnoc_cfg, SM6350_MASTER_GEM_NOC_CFG, 1, 4, SM6350_SLAVE_MCDMA_MS_MPU_CFG, SM6350_SLAVE_SERVICE_GEM_NOC, SM6350_SLAVE_MSS_PROC_MS_MPU_CFG); 43 DEFINE_QNODE(qnm_cmpnoc, SM6350_MASTER_COMPUTE_NOC, 1, 32, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC); 44 DEFINE_QNODE(qnm_mnoc_hf, SM6350_MASTER_MNOC_HF_MEM_NOC, 1, 32, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC); 45 DEFINE_QNODE(qnm_mnoc_sf, SM6350_MASTER_MNOC_SF_MEM_NOC, 1, 32, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC); 46 DEFINE_QNODE(qnm_snoc_gc, SM6350_MASTER_SNOC_GC_MEM_NOC, 1, 8, SM6350_SLAVE_LLCC); 47 DEFINE_QNODE(qnm_snoc_sf, SM6350_MASTER_SNOC_SF_MEM_NOC, 1, 16, SM6350_SLAVE_LLCC); 48 DEFINE_QNODE(qxm_gpu, SM6350_MASTER_GRAPHICS_3D, 2, 32, SM6350_SLAVE_LLCC, SM6350_SLAVE_GEM_NOC_SNOC); 49 DEFINE_QNODE(llcc_mc, SM6350_MASTER_LLCC, 2, 4, SM6350_SLAVE_EBI_CH0); 50 DEFINE_QNODE(qhm_mnoc_cfg, SM6350_MASTER_CNOC_MNOC_CFG, 1, 4, SM6350_SLAVE_SERVICE_MNOC); 51 DEFINE_QNODE(qnm_video0, SM6350_MASTER_VIDEO_P0, 1, 32, SM6350_SLAVE_MNOC_SF_MEM_NOC); 52 DEFINE_QNODE(qnm_video_cvp, SM6350_MASTER_VIDEO_PROC, 1, 8, SM6350_SLAVE_MNOC_SF_MEM_NOC); 53 DEFINE_QNODE(qxm_camnoc_hf, SM6350_MASTER_CAMNOC_HF, 2, 32, SM6350_SLAVE_MNOC_HF_MEM_NOC); 54 DEFINE_QNODE(qxm_camnoc_icp, SM6350_MASTER_CAMNOC_ICP, 1, 8, SM6350_SLAVE_MNOC_SF_MEM_NOC); 55 DEFINE_QNODE(qxm_camnoc_sf, SM6350_MASTER_CAMNOC_SF, 1, 32, SM6350_SLAVE_MNOC_SF_MEM_NOC); 56 DEFINE_QNODE(qxm_mdp0, SM6350_MASTER_MDP_PORT0, 1, 32, SM6350_SLAVE_MNOC_HF_MEM_NOC); 57 DEFINE_QNODE(amm_npu_sys, SM6350_MASTER_NPU_SYS, 2, 32, SM6350_SLAVE_NPU_COMPUTE_NOC); 58 DEFINE_QNODE(qhm_npu_cfg, SM6350_MASTER_NPU_NOC_CFG, 1, 4, SM6350_SLAVE_SERVICE_NPU_NOC, SM6350_SLAVE_ISENSE_CFG, SM6350_SLAVE_NPU_LLM_CFG, SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG, SM6350_SLAVE_NPU_CP, SM6350_SLAVE_NPU_TCM, SM6350_SLAVE_NPU_CAL_DP0, SM6350_SLAVE_NPU_DPM); 59 DEFINE_QNODE(qhm_snoc_cfg, SM6350_MASTER_SNOC_CFG, 1, 4, SM6350_SLAVE_SERVICE_SNOC); 60 DEFINE_QNODE(qnm_aggre1_noc, SM6350_A1NOC_SNOC_MAS, 1, 16, SM6350_SLAVE_SNOC_GEM_NOC_SF, SM6350_SLAVE_PIMEM, SM6350_SLAVE_OCIMEM, SM6350_SLAVE_APPSS, SM6350_SNOC_CNOC_SLV, SM6350_SLAVE_QDSS_STM); 61 DEFINE_QNODE(qnm_aggre2_noc, SM6350_A2NOC_SNOC_MAS, 1, 16, SM6350_SLAVE_SNOC_GEM_NOC_SF, SM6350_SLAVE_PIMEM, SM6350_SLAVE_OCIMEM, SM6350_SLAVE_APPSS, SM6350_SNOC_CNOC_SLV, SM6350_SLAVE_TCU, SM6350_SLAVE_QDSS_STM); 62 DEFINE_QNODE(qnm_gemnoc, SM6350_MASTER_GEM_NOC_SNOC, 1, 8, SM6350_SLAVE_PIMEM, SM6350_SLAVE_OCIMEM, SM6350_SLAVE_APPSS, SM6350_SNOC_CNOC_SLV, SM6350_SLAVE_TCU, SM6350_SLAVE_QDSS_STM); 63 DEFINE_QNODE(qxm_pimem, SM6350_MASTER_PIMEM, 1, 8, SM6350_SLAVE_SNOC_GEM_NOC_GC, SM6350_SLAVE_OCIMEM); 64 DEFINE_QNODE(xm_gic, SM6350_MASTER_GIC, 1, 8, SM6350_SLAVE_SNOC_GEM_NOC_GC); 65 DEFINE_QNODE(qns_a1noc_snoc, SM6350_A1NOC_SNOC_SLV, 1, 16, SM6350_A1NOC_SNOC_MAS); 66 DEFINE_QNODE(srvc_aggre1_noc, SM6350_SLAVE_SERVICE_A1NOC, 1, 4); 67 DEFINE_QNODE(qns_a2noc_snoc, SM6350_A2NOC_SNOC_SLV, 1, 16, SM6350_A2NOC_SNOC_MAS); 68 DEFINE_QNODE(srvc_aggre2_noc, SM6350_SLAVE_SERVICE_A2NOC, 1, 4); 69 DEFINE_QNODE(qns_camnoc_uncomp, SM6350_SLAVE_CAMNOC_UNCOMP, 1, 32); 70 DEFINE_QNODE(qup0_core_slave, SM6350_SLAVE_QUP_CORE_0, 1, 4); 71 DEFINE_QNODE(qup1_core_slave, SM6350_SLAVE_QUP_CORE_1, 1, 4); 72 DEFINE_QNODE(qns_cdsp_gemnoc, SM6350_SLAVE_CDSP_GEM_NOC, 1, 32, SM6350_MASTER_COMPUTE_NOC); 73 DEFINE_QNODE(qhs_a1_noc_cfg, SM6350_SLAVE_A1NOC_CFG, 1, 4, SM6350_MASTER_A1NOC_CFG); 74 DEFINE_QNODE(qhs_a2_noc_cfg, SM6350_SLAVE_A2NOC_CFG, 1, 4, SM6350_MASTER_A2NOC_CFG); 75 DEFINE_QNODE(qhs_ahb2phy0, SM6350_SLAVE_AHB2PHY, 1, 4); 76 DEFINE_QNODE(qhs_ahb2phy2, SM6350_SLAVE_AHB2PHY_2, 1, 4); 77 DEFINE_QNODE(qhs_aoss, SM6350_SLAVE_AOSS, 1, 4); 78 DEFINE_QNODE(qhs_boot_rom, SM6350_SLAVE_BOOT_ROM, 1, 4); 79 DEFINE_QNODE(qhs_camera_cfg, SM6350_SLAVE_CAMERA_CFG, 1, 4); 80 DEFINE_QNODE(qhs_camera_nrt_thrott_cfg, SM6350_SLAVE_CAMERA_NRT_THROTTLE_CFG, 1, 4); 81 DEFINE_QNODE(qhs_camera_rt_throttle_cfg, SM6350_SLAVE_CAMERA_RT_THROTTLE_CFG, 1, 4); 82 DEFINE_QNODE(qhs_clk_ctl, SM6350_SLAVE_CLK_CTL, 1, 4); 83 DEFINE_QNODE(qhs_cpr_cx, SM6350_SLAVE_RBCPR_CX_CFG, 1, 4); 84 DEFINE_QNODE(qhs_cpr_mx, SM6350_SLAVE_RBCPR_MX_CFG, 1, 4); 85 DEFINE_QNODE(qhs_crypto0_cfg, SM6350_SLAVE_CRYPTO_0_CFG, 1, 4); 86 DEFINE_QNODE(qhs_dcc_cfg, SM6350_SLAVE_DCC_CFG, 1, 4); 87 DEFINE_QNODE(qhs_ddrss_cfg, SM6350_SLAVE_CNOC_DDRSS, 1, 4, SM6350_MASTER_CNOC_DC_NOC); 88 DEFINE_QNODE(qhs_display_cfg, SM6350_SLAVE_DISPLAY_CFG, 1, 4); 89 DEFINE_QNODE(qhs_display_throttle_cfg, SM6350_SLAVE_DISPLAY_THROTTLE_CFG, 1, 4); 90 DEFINE_QNODE(qhs_emmc_cfg, SM6350_SLAVE_EMMC_CFG, 1, 4); 91 DEFINE_QNODE(qhs_glm, SM6350_SLAVE_GLM, 1, 4); 92 DEFINE_QNODE(qhs_gpuss_cfg, SM6350_SLAVE_GRAPHICS_3D_CFG, 1, 8); 93 DEFINE_QNODE(qhs_imem_cfg, SM6350_SLAVE_IMEM_CFG, 1, 4); 94 DEFINE_QNODE(qhs_ipa, SM6350_SLAVE_IPA_CFG, 1, 4); 95 DEFINE_QNODE(qhs_mnoc_cfg, SM6350_SLAVE_CNOC_MNOC_CFG, 1, 4, SM6350_MASTER_CNOC_MNOC_CFG); 96 DEFINE_QNODE(qhs_mss_cfg, SM6350_SLAVE_CNOC_MSS, 1, 4); 97 DEFINE_QNODE(qhs_npu_cfg, SM6350_SLAVE_NPU_CFG, 1, 4, SM6350_MASTER_NPU_NOC_CFG); 98 DEFINE_QNODE(qhs_pdm, SM6350_SLAVE_PDM, 1, 4); 99 DEFINE_QNODE(qhs_pimem_cfg, SM6350_SLAVE_PIMEM_CFG, 1, 4); 100 DEFINE_QNODE(qhs_prng, SM6350_SLAVE_PRNG, 1, 4); 101 DEFINE_QNODE(qhs_qdss_cfg, SM6350_SLAVE_QDSS_CFG, 1, 4); 102 DEFINE_QNODE(qhs_qm_cfg, SM6350_SLAVE_QM_CFG, 1, 4); 103 DEFINE_QNODE(qhs_qm_mpu_cfg, SM6350_SLAVE_QM_MPU_CFG, 1, 4); 104 DEFINE_QNODE(qhs_qup0, SM6350_SLAVE_QUP_0, 1, 4); 105 DEFINE_QNODE(qhs_qup1, SM6350_SLAVE_QUP_1, 1, 4); 106 DEFINE_QNODE(qhs_sdc2, SM6350_SLAVE_SDCC_2, 1, 4); 107 DEFINE_QNODE(qhs_security, SM6350_SLAVE_SECURITY, 1, 4); 108 DEFINE_QNODE(qhs_snoc_cfg, SM6350_SLAVE_SNOC_CFG, 1, 4, SM6350_MASTER_SNOC_CFG); 109 DEFINE_QNODE(qhs_tcsr, SM6350_SLAVE_TCSR, 1, 4); 110 DEFINE_QNODE(qhs_ufs_mem_cfg, SM6350_SLAVE_UFS_MEM_CFG, 1, 4); 111 DEFINE_QNODE(qhs_usb3_0, SM6350_SLAVE_USB3, 1, 4); 112 DEFINE_QNODE(qhs_venus_cfg, SM6350_SLAVE_VENUS_CFG, 1, 4); 113 DEFINE_QNODE(qhs_venus_throttle_cfg, SM6350_SLAVE_VENUS_THROTTLE_CFG, 1, 4); 114 DEFINE_QNODE(qhs_vsense_ctrl_cfg, SM6350_SLAVE_VSENSE_CTRL_CFG, 1, 4); 115 DEFINE_QNODE(srvc_cnoc, SM6350_SLAVE_SERVICE_CNOC, 1, 4); 116 DEFINE_QNODE(qhs_gemnoc, SM6350_SLAVE_GEM_NOC_CFG, 1, 4, SM6350_MASTER_GEM_NOC_CFG); 117 DEFINE_QNODE(qhs_llcc, SM6350_SLAVE_LLCC_CFG, 1, 4); 118 DEFINE_QNODE(qhs_mcdma_ms_mpu_cfg, SM6350_SLAVE_MCDMA_MS_MPU_CFG, 1, 4); 119 DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SM6350_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4); 120 DEFINE_QNODE(qns_gem_noc_snoc, SM6350_SLAVE_GEM_NOC_SNOC, 1, 8, SM6350_MASTER_GEM_NOC_SNOC); 121 DEFINE_QNODE(qns_llcc, SM6350_SLAVE_LLCC, 1, 16, SM6350_MASTER_LLCC); 122 DEFINE_QNODE(srvc_gemnoc, SM6350_SLAVE_SERVICE_GEM_NOC, 1, 4); 123 DEFINE_QNODE(ebi, SM6350_SLAVE_EBI_CH0, 2, 4); 124 DEFINE_QNODE(qns_mem_noc_hf, SM6350_SLAVE_MNOC_HF_MEM_NOC, 1, 32, SM6350_MASTER_MNOC_HF_MEM_NOC); 125 DEFINE_QNODE(qns_mem_noc_sf, SM6350_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SM6350_MASTER_MNOC_SF_MEM_NOC); 126 DEFINE_QNODE(srvc_mnoc, SM6350_SLAVE_SERVICE_MNOC, 1, 4); 127 DEFINE_QNODE(qhs_cal_dp0, SM6350_SLAVE_NPU_CAL_DP0, 1, 4); 128 DEFINE_QNODE(qhs_cp, SM6350_SLAVE_NPU_CP, 1, 4); 129 DEFINE_QNODE(qhs_dma_bwmon, SM6350_SLAVE_NPU_INT_DMA_BWMON_CFG, 1, 4); 130 DEFINE_QNODE(qhs_dpm, SM6350_SLAVE_NPU_DPM, 1, 4); 131 DEFINE_QNODE(qhs_isense, SM6350_SLAVE_ISENSE_CFG, 1, 4); 132 DEFINE_QNODE(qhs_llm, SM6350_SLAVE_NPU_LLM_CFG, 1, 4); 133 DEFINE_QNODE(qhs_tcm, SM6350_SLAVE_NPU_TCM, 1, 4); 134 DEFINE_QNODE(qns_npu_sys, SM6350_SLAVE_NPU_COMPUTE_NOC, 2, 32); 135 DEFINE_QNODE(srvc_noc, SM6350_SLAVE_SERVICE_NPU_NOC, 1, 4); 136 DEFINE_QNODE(qhs_apss, SM6350_SLAVE_APPSS, 1, 8); 137 DEFINE_QNODE(qns_cnoc, SM6350_SNOC_CNOC_SLV, 1, 8, SM6350_SNOC_CNOC_MAS); 138 DEFINE_QNODE(qns_gemnoc_gc, SM6350_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SM6350_MASTER_SNOC_GC_MEM_NOC); 139 DEFINE_QNODE(qns_gemnoc_sf, SM6350_SLAVE_SNOC_GEM_NOC_SF, 1, 16, SM6350_MASTER_SNOC_SF_MEM_NOC); 140 DEFINE_QNODE(qxs_imem, SM6350_SLAVE_OCIMEM, 1, 8); 141 DEFINE_QNODE(qxs_pimem, SM6350_SLAVE_PIMEM, 1, 8); 142 DEFINE_QNODE(srvc_snoc, SM6350_SLAVE_SERVICE_SNOC, 1, 4); 143 DEFINE_QNODE(xs_qdss_stm, SM6350_SLAVE_QDSS_STM, 1, 4); 144 DEFINE_QNODE(xs_sys_tcu_cfg, SM6350_SLAVE_TCU, 1, 8); 145 146 DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); 147 DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); 148 DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_aoss, &qhs_boot_rom, &qhs_camera_cfg, &qhs_camera_nrt_thrott_cfg, &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, &qhs_cpr_cx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_display_throttle_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_mss_cfg, &qhs_npu_cfg, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qm_cfg, &qhs_qm_mpu_cfg, &qhs_qup0, &qhs_qup1, &qhs_security, &qhs_snoc_cfg, &qhs_tcsr, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_venus_cfg, &qhs_venus_throttle_cfg, &qhs_vsense_ctrl_cfg, &srvc_cnoc); 149 DEFINE_QBCM(bcm_cn1, "CN1", false, &xm_emmc, &xm_sdc2, &qhs_ahb2phy2, &qhs_emmc_cfg, &qhs_pdm, &qhs_sdc2); 150 DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_gemnoc); 151 DEFINE_QBCM(bcm_co2, "CO2", false, &qnm_npu); 152 DEFINE_QBCM(bcm_co3, "CO3", false, &qxm_npu_dsp); 153 DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); 154 DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf); 155 DEFINE_QBCM(bcm_mm1, "MM1", true, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_icp_uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf, &qxm_mdp0); 156 DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf); 157 DEFINE_QBCM(bcm_mm3, "MM3", false, &qhm_mnoc_cfg, &qnm_video0, &qnm_video_cvp, &qxm_camnoc_sf); 158 DEFINE_QBCM(bcm_qup0, "QUP0", false, &qup0_core_master, &qup1_core_master, &qup0_core_slave, &qup1_core_slave); 159 DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); 160 DEFINE_QBCM(bcm_sh2, "SH2", false, &acm_sys_tcu); 161 DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc); 162 DEFINE_QBCM(bcm_sh4, "SH4", false, &acm_apps); 163 DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf); 164 DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); 165 DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc); 166 DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem); 167 DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm); 168 DEFINE_QBCM(bcm_sn5, "SN5", false, &qnm_aggre1_noc); 169 DEFINE_QBCM(bcm_sn6, "SN6", false, &qnm_aggre2_noc); 170 DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_gemnoc); 171 172 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 173 &bcm_cn1, 174 }; 175 176 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 177 [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg, 178 [MASTER_QUP_0] = &qhm_qup_0, 179 [MASTER_EMMC] = &xm_emmc, 180 [MASTER_UFS_MEM] = &xm_ufs_mem, 181 [A1NOC_SNOC_SLV] = &qns_a1noc_snoc, 182 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, 183 }; 184 185 static const struct qcom_icc_desc sm6350_aggre1_noc = { 186 .nodes = aggre1_noc_nodes, 187 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 188 .bcms = aggre1_noc_bcms, 189 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 190 }; 191 192 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 193 &bcm_ce0, 194 &bcm_cn1, 195 }; 196 197 static struct qcom_icc_node * const aggre2_noc_nodes[] = { 198 [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg, 199 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 200 [MASTER_QUP_1] = &qhm_qup_1, 201 [MASTER_CRYPTO_CORE_0] = &qxm_crypto, 202 [MASTER_IPA] = &qxm_ipa, 203 [MASTER_QDSS_ETR] = &xm_qdss_etr, 204 [MASTER_SDCC_2] = &xm_sdc2, 205 [MASTER_USB3] = &xm_usb3_0, 206 [A2NOC_SNOC_SLV] = &qns_a2noc_snoc, 207 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, 208 }; 209 210 static const struct qcom_icc_desc sm6350_aggre2_noc = { 211 .nodes = aggre2_noc_nodes, 212 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 213 .bcms = aggre2_noc_bcms, 214 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 215 }; 216 217 static struct qcom_icc_bcm * const clk_virt_bcms[] = { 218 &bcm_acv, 219 &bcm_mc0, 220 &bcm_mm1, 221 &bcm_qup0, 222 }; 223 224 static struct qcom_icc_node * const clk_virt_nodes[] = { 225 [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp, 226 [MASTER_CAMNOC_ICP_UNCOMP] = &qxm_camnoc_icp_uncomp, 227 [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp, 228 [MASTER_QUP_CORE_0] = &qup0_core_master, 229 [MASTER_QUP_CORE_1] = &qup1_core_master, 230 [MASTER_LLCC] = &llcc_mc, 231 [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp, 232 [SLAVE_QUP_CORE_0] = &qup0_core_slave, 233 [SLAVE_QUP_CORE_1] = &qup1_core_slave, 234 [SLAVE_EBI_CH0] = &ebi, 235 }; 236 237 static const struct qcom_icc_desc sm6350_clk_virt = { 238 .nodes = clk_virt_nodes, 239 .num_nodes = ARRAY_SIZE(clk_virt_nodes), 240 .bcms = clk_virt_bcms, 241 .num_bcms = ARRAY_SIZE(clk_virt_bcms), 242 }; 243 244 static struct qcom_icc_bcm * const compute_noc_bcms[] = { 245 &bcm_co0, 246 &bcm_co2, 247 &bcm_co3, 248 }; 249 250 static struct qcom_icc_node * const compute_noc_nodes[] = { 251 [MASTER_NPU] = &qnm_npu, 252 [MASTER_NPU_PROC] = &qxm_npu_dsp, 253 [SLAVE_CDSP_GEM_NOC] = &qns_cdsp_gemnoc, 254 }; 255 256 static const struct qcom_icc_desc sm6350_compute_noc = { 257 .nodes = compute_noc_nodes, 258 .num_nodes = ARRAY_SIZE(compute_noc_nodes), 259 .bcms = compute_noc_bcms, 260 .num_bcms = ARRAY_SIZE(compute_noc_bcms), 261 }; 262 263 static struct qcom_icc_bcm * const config_noc_bcms[] = { 264 &bcm_cn0, 265 &bcm_cn1, 266 }; 267 268 static struct qcom_icc_node * const config_noc_nodes[] = { 269 [SNOC_CNOC_MAS] = &qnm_snoc, 270 [MASTER_QDSS_DAP] = &xm_qdss_dap, 271 [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg, 272 [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg, 273 [SLAVE_AHB2PHY] = &qhs_ahb2phy0, 274 [SLAVE_AHB2PHY_2] = &qhs_ahb2phy2, 275 [SLAVE_AOSS] = &qhs_aoss, 276 [SLAVE_BOOT_ROM] = &qhs_boot_rom, 277 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 278 [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_thrott_cfg, 279 [SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg, 280 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 281 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 282 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, 283 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 284 [SLAVE_DCC_CFG] = &qhs_dcc_cfg, 285 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg, 286 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 287 [SLAVE_DISPLAY_THROTTLE_CFG] = &qhs_display_throttle_cfg, 288 [SLAVE_EMMC_CFG] = &qhs_emmc_cfg, 289 [SLAVE_GLM] = &qhs_glm, 290 [SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg, 291 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 292 [SLAVE_IPA_CFG] = &qhs_ipa, 293 [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg, 294 [SLAVE_CNOC_MSS] = &qhs_mss_cfg, 295 [SLAVE_NPU_CFG] = &qhs_npu_cfg, 296 [SLAVE_PDM] = &qhs_pdm, 297 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 298 [SLAVE_PRNG] = &qhs_prng, 299 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 300 [SLAVE_QM_CFG] = &qhs_qm_cfg, 301 [SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg, 302 [SLAVE_QUP_0] = &qhs_qup0, 303 [SLAVE_QUP_1] = &qhs_qup1, 304 [SLAVE_SDCC_2] = &qhs_sdc2, 305 [SLAVE_SECURITY] = &qhs_security, 306 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, 307 [SLAVE_TCSR] = &qhs_tcsr, 308 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 309 [SLAVE_USB3] = &qhs_usb3_0, 310 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 311 [SLAVE_VENUS_THROTTLE_CFG] = &qhs_venus_throttle_cfg, 312 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 313 [SLAVE_SERVICE_CNOC] = &srvc_cnoc, 314 }; 315 316 static const struct qcom_icc_desc sm6350_config_noc = { 317 .nodes = config_noc_nodes, 318 .num_nodes = ARRAY_SIZE(config_noc_nodes), 319 .bcms = config_noc_bcms, 320 .num_bcms = ARRAY_SIZE(config_noc_bcms), 321 }; 322 323 static struct qcom_icc_bcm * const dc_noc_bcms[] = { 324 }; 325 326 static struct qcom_icc_node * const dc_noc_nodes[] = { 327 [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc, 328 [SLAVE_GEM_NOC_CFG] = &qhs_gemnoc, 329 [SLAVE_LLCC_CFG] = &qhs_llcc, 330 }; 331 332 static const struct qcom_icc_desc sm6350_dc_noc = { 333 .nodes = dc_noc_nodes, 334 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 335 .bcms = dc_noc_bcms, 336 .num_bcms = ARRAY_SIZE(dc_noc_bcms), 337 }; 338 339 static struct qcom_icc_bcm * const gem_noc_bcms[] = { 340 &bcm_sh0, 341 &bcm_sh2, 342 &bcm_sh3, 343 &bcm_sh4, 344 }; 345 346 static struct qcom_icc_node * const gem_noc_nodes[] = { 347 [MASTER_AMPSS_M0] = &acm_apps, 348 [MASTER_SYS_TCU] = &acm_sys_tcu, 349 [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg, 350 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc, 351 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 352 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 353 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 354 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 355 [MASTER_GRAPHICS_3D] = &qxm_gpu, 356 [SLAVE_MCDMA_MS_MPU_CFG] = &qhs_mcdma_ms_mpu_cfg, 357 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg, 358 [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc, 359 [SLAVE_LLCC] = &qns_llcc, 360 [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc, 361 }; 362 363 static const struct qcom_icc_desc sm6350_gem_noc = { 364 .nodes = gem_noc_nodes, 365 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 366 .bcms = gem_noc_bcms, 367 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 368 }; 369 370 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 371 &bcm_mm0, 372 &bcm_mm1, 373 &bcm_mm2, 374 &bcm_mm3, 375 }; 376 377 static struct qcom_icc_node * const mmss_noc_nodes[] = { 378 [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg, 379 [MASTER_VIDEO_P0] = &qnm_video0, 380 [MASTER_VIDEO_PROC] = &qnm_video_cvp, 381 [MASTER_CAMNOC_HF] = &qxm_camnoc_hf, 382 [MASTER_CAMNOC_ICP] = &qxm_camnoc_icp, 383 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf, 384 [MASTER_MDP_PORT0] = &qxm_mdp0, 385 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 386 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, 387 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 388 }; 389 390 static const struct qcom_icc_desc sm6350_mmss_noc = { 391 .nodes = mmss_noc_nodes, 392 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 393 .bcms = mmss_noc_bcms, 394 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 395 }; 396 397 static struct qcom_icc_bcm * const npu_noc_bcms[] = { 398 }; 399 400 static struct qcom_icc_node * const npu_noc_nodes[] = { 401 [MASTER_NPU_SYS] = &amm_npu_sys, 402 [MASTER_NPU_NOC_CFG] = &qhm_npu_cfg, 403 [SLAVE_NPU_CAL_DP0] = &qhs_cal_dp0, 404 [SLAVE_NPU_CP] = &qhs_cp, 405 [SLAVE_NPU_INT_DMA_BWMON_CFG] = &qhs_dma_bwmon, 406 [SLAVE_NPU_DPM] = &qhs_dpm, 407 [SLAVE_ISENSE_CFG] = &qhs_isense, 408 [SLAVE_NPU_LLM_CFG] = &qhs_llm, 409 [SLAVE_NPU_TCM] = &qhs_tcm, 410 [SLAVE_NPU_COMPUTE_NOC] = &qns_npu_sys, 411 [SLAVE_SERVICE_NPU_NOC] = &srvc_noc, 412 }; 413 414 static const struct qcom_icc_desc sm6350_npu_noc = { 415 .nodes = npu_noc_nodes, 416 .num_nodes = ARRAY_SIZE(npu_noc_nodes), 417 .bcms = npu_noc_bcms, 418 .num_bcms = ARRAY_SIZE(npu_noc_bcms), 419 }; 420 421 static struct qcom_icc_bcm * const system_noc_bcms[] = { 422 &bcm_sn0, 423 &bcm_sn1, 424 &bcm_sn10, 425 &bcm_sn2, 426 &bcm_sn3, 427 &bcm_sn4, 428 &bcm_sn5, 429 &bcm_sn6, 430 }; 431 432 static struct qcom_icc_node * const system_noc_nodes[] = { 433 [MASTER_SNOC_CFG] = &qhm_snoc_cfg, 434 [A1NOC_SNOC_MAS] = &qnm_aggre1_noc, 435 [A2NOC_SNOC_MAS] = &qnm_aggre2_noc, 436 [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc, 437 [MASTER_PIMEM] = &qxm_pimem, 438 [MASTER_GIC] = &xm_gic, 439 [SLAVE_APPSS] = &qhs_apss, 440 [SNOC_CNOC_SLV] = &qns_cnoc, 441 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, 442 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 443 [SLAVE_OCIMEM] = &qxs_imem, 444 [SLAVE_PIMEM] = &qxs_pimem, 445 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 446 [SLAVE_QDSS_STM] = &xs_qdss_stm, 447 [SLAVE_TCU] = &xs_sys_tcu_cfg, 448 }; 449 450 static const struct qcom_icc_desc sm6350_system_noc = { 451 .nodes = system_noc_nodes, 452 .num_nodes = ARRAY_SIZE(system_noc_nodes), 453 .bcms = system_noc_bcms, 454 .num_bcms = ARRAY_SIZE(system_noc_bcms), 455 }; 456 457 static const struct of_device_id qnoc_of_match[] = { 458 { .compatible = "qcom,sm6350-aggre1-noc", 459 .data = &sm6350_aggre1_noc}, 460 { .compatible = "qcom,sm6350-aggre2-noc", 461 .data = &sm6350_aggre2_noc}, 462 { .compatible = "qcom,sm6350-clk-virt", 463 .data = &sm6350_clk_virt}, 464 { .compatible = "qcom,sm6350-compute-noc", 465 .data = &sm6350_compute_noc}, 466 { .compatible = "qcom,sm6350-config-noc", 467 .data = &sm6350_config_noc}, 468 { .compatible = "qcom,sm6350-dc-noc", 469 .data = &sm6350_dc_noc}, 470 { .compatible = "qcom,sm6350-gem-noc", 471 .data = &sm6350_gem_noc}, 472 { .compatible = "qcom,sm6350-mmss-noc", 473 .data = &sm6350_mmss_noc}, 474 { .compatible = "qcom,sm6350-npu-noc", 475 .data = &sm6350_npu_noc}, 476 { .compatible = "qcom,sm6350-system-noc", 477 .data = &sm6350_system_noc}, 478 { } 479 }; 480 MODULE_DEVICE_TABLE(of, qnoc_of_match); 481 482 static struct platform_driver qnoc_driver = { 483 .probe = qcom_icc_rpmh_probe, 484 .remove = qcom_icc_rpmh_remove, 485 .driver = { 486 .name = "qnoc-sm6350", 487 .of_match_table = qnoc_of_match, 488 .sync_state = icc_sync_state, 489 }, 490 }; 491 module_platform_driver(qnoc_driver); 492 493 MODULE_DESCRIPTION("Qualcomm SM6350 NoC driver"); 494 MODULE_LICENSE("GPL v2"); 495