1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2022 Luca Weiss <luca.weiss@fairphone.com> 4 */ 5 6 #include <linux/device.h> 7 #include <linux/interconnect.h> 8 #include <linux/interconnect-provider.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 #include <dt-bindings/interconnect/qcom,sm6350.h> 12 13 #include "bcm-voter.h" 14 #include "icc-rpmh.h" 15 16 static struct qcom_icc_node qhm_a1noc_cfg; 17 static struct qcom_icc_node qhm_qup_0; 18 static struct qcom_icc_node xm_emmc; 19 static struct qcom_icc_node xm_ufs_mem; 20 static struct qcom_icc_node qhm_a2noc_cfg; 21 static struct qcom_icc_node qhm_qdss_bam; 22 static struct qcom_icc_node qhm_qup_1; 23 static struct qcom_icc_node qxm_crypto; 24 static struct qcom_icc_node qxm_ipa; 25 static struct qcom_icc_node xm_qdss_etr; 26 static struct qcom_icc_node xm_sdc2; 27 static struct qcom_icc_node xm_usb3_0; 28 static struct qcom_icc_node qxm_camnoc_hf0_uncomp; 29 static struct qcom_icc_node qxm_camnoc_icp_uncomp; 30 static struct qcom_icc_node qxm_camnoc_sf_uncomp; 31 static struct qcom_icc_node qup0_core_master; 32 static struct qcom_icc_node qup1_core_master; 33 static struct qcom_icc_node qnm_npu; 34 static struct qcom_icc_node qxm_npu_dsp; 35 static struct qcom_icc_node qnm_snoc; 36 static struct qcom_icc_node xm_qdss_dap; 37 static struct qcom_icc_node qhm_cnoc_dc_noc; 38 static struct qcom_icc_node acm_apps; 39 static struct qcom_icc_node acm_sys_tcu; 40 static struct qcom_icc_node qhm_gemnoc_cfg; 41 static struct qcom_icc_node qnm_cmpnoc; 42 static struct qcom_icc_node qnm_mnoc_hf; 43 static struct qcom_icc_node qnm_mnoc_sf; 44 static struct qcom_icc_node qnm_snoc_gc; 45 static struct qcom_icc_node qnm_snoc_sf; 46 static struct qcom_icc_node qxm_gpu; 47 static struct qcom_icc_node llcc_mc; 48 static struct qcom_icc_node qhm_mnoc_cfg; 49 static struct qcom_icc_node qnm_video0; 50 static struct qcom_icc_node qnm_video_cvp; 51 static struct qcom_icc_node qxm_camnoc_hf; 52 static struct qcom_icc_node qxm_camnoc_icp; 53 static struct qcom_icc_node qxm_camnoc_sf; 54 static struct qcom_icc_node qxm_mdp0; 55 static struct qcom_icc_node amm_npu_sys; 56 static struct qcom_icc_node qhm_npu_cfg; 57 static struct qcom_icc_node qhm_snoc_cfg; 58 static struct qcom_icc_node qnm_aggre1_noc; 59 static struct qcom_icc_node qnm_aggre2_noc; 60 static struct qcom_icc_node qnm_gemnoc; 61 static struct qcom_icc_node qxm_pimem; 62 static struct qcom_icc_node xm_gic; 63 static struct qcom_icc_node qns_a1noc_snoc; 64 static struct qcom_icc_node srvc_aggre1_noc; 65 static struct qcom_icc_node qns_a2noc_snoc; 66 static struct qcom_icc_node srvc_aggre2_noc; 67 static struct qcom_icc_node qns_camnoc_uncomp; 68 static struct qcom_icc_node qup0_core_slave; 69 static struct qcom_icc_node qup1_core_slave; 70 static struct qcom_icc_node qns_cdsp_gemnoc; 71 static struct qcom_icc_node qhs_a1_noc_cfg; 72 static struct qcom_icc_node qhs_a2_noc_cfg; 73 static struct qcom_icc_node qhs_ahb2phy0; 74 static struct qcom_icc_node qhs_ahb2phy2; 75 static struct qcom_icc_node qhs_aoss; 76 static struct qcom_icc_node qhs_boot_rom; 77 static struct qcom_icc_node qhs_camera_cfg; 78 static struct qcom_icc_node qhs_camera_nrt_thrott_cfg; 79 static struct qcom_icc_node qhs_camera_rt_throttle_cfg; 80 static struct qcom_icc_node qhs_clk_ctl; 81 static struct qcom_icc_node qhs_cpr_cx; 82 static struct qcom_icc_node qhs_cpr_mx; 83 static struct qcom_icc_node qhs_crypto0_cfg; 84 static struct qcom_icc_node qhs_dcc_cfg; 85 static struct qcom_icc_node qhs_ddrss_cfg; 86 static struct qcom_icc_node qhs_display_cfg; 87 static struct qcom_icc_node qhs_display_throttle_cfg; 88 static struct qcom_icc_node qhs_emmc_cfg; 89 static struct qcom_icc_node qhs_glm; 90 static struct qcom_icc_node qhs_gpuss_cfg; 91 static struct qcom_icc_node qhs_imem_cfg; 92 static struct qcom_icc_node qhs_ipa; 93 static struct qcom_icc_node qhs_mnoc_cfg; 94 static struct qcom_icc_node qhs_mss_cfg; 95 static struct qcom_icc_node qhs_npu_cfg; 96 static struct qcom_icc_node qhs_pdm; 97 static struct qcom_icc_node qhs_pimem_cfg; 98 static struct qcom_icc_node qhs_prng; 99 static struct qcom_icc_node qhs_qdss_cfg; 100 static struct qcom_icc_node qhs_qm_cfg; 101 static struct qcom_icc_node qhs_qm_mpu_cfg; 102 static struct qcom_icc_node qhs_qup0; 103 static struct qcom_icc_node qhs_qup1; 104 static struct qcom_icc_node qhs_sdc2; 105 static struct qcom_icc_node qhs_security; 106 static struct qcom_icc_node qhs_snoc_cfg; 107 static struct qcom_icc_node qhs_tcsr; 108 static struct qcom_icc_node qhs_ufs_mem_cfg; 109 static struct qcom_icc_node qhs_usb3_0; 110 static struct qcom_icc_node qhs_venus_cfg; 111 static struct qcom_icc_node qhs_venus_throttle_cfg; 112 static struct qcom_icc_node qhs_vsense_ctrl_cfg; 113 static struct qcom_icc_node srvc_cnoc; 114 static struct qcom_icc_node qhs_gemnoc; 115 static struct qcom_icc_node qhs_llcc; 116 static struct qcom_icc_node qhs_mcdma_ms_mpu_cfg; 117 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; 118 static struct qcom_icc_node qns_gem_noc_snoc; 119 static struct qcom_icc_node qns_llcc; 120 static struct qcom_icc_node srvc_gemnoc; 121 static struct qcom_icc_node ebi; 122 static struct qcom_icc_node qns_mem_noc_hf; 123 static struct qcom_icc_node qns_mem_noc_sf; 124 static struct qcom_icc_node srvc_mnoc; 125 static struct qcom_icc_node qhs_cal_dp0; 126 static struct qcom_icc_node qhs_cp; 127 static struct qcom_icc_node qhs_dma_bwmon; 128 static struct qcom_icc_node qhs_dpm; 129 static struct qcom_icc_node qhs_isense; 130 static struct qcom_icc_node qhs_llm; 131 static struct qcom_icc_node qhs_tcm; 132 static struct qcom_icc_node qns_npu_sys; 133 static struct qcom_icc_node srvc_noc; 134 static struct qcom_icc_node qhs_apss; 135 static struct qcom_icc_node qns_cnoc; 136 static struct qcom_icc_node qns_gemnoc_gc; 137 static struct qcom_icc_node qns_gemnoc_sf; 138 static struct qcom_icc_node qxs_imem; 139 static struct qcom_icc_node qxs_pimem; 140 static struct qcom_icc_node srvc_snoc; 141 static struct qcom_icc_node xs_qdss_stm; 142 static struct qcom_icc_node xs_sys_tcu_cfg; 143 144 static struct qcom_icc_node qhm_a1noc_cfg = { 145 .name = "qhm_a1noc_cfg", 146 .channels = 1, 147 .buswidth = 4, 148 .num_links = 1, 149 .link_nodes = { &srvc_aggre1_noc }, 150 }; 151 152 static struct qcom_icc_qosbox qhm_qup_0_qos = { 153 .num_ports = 1, 154 .port_offsets = { 0xa000 }, 155 .prio = 2, 156 .urg_fwd = 0, 157 }; 158 159 static struct qcom_icc_node qhm_qup_0 = { 160 .name = "qhm_qup_0", 161 .channels = 1, 162 .buswidth = 4, 163 .qosbox = &qhm_qup_0_qos, 164 .num_links = 1, 165 .link_nodes = { &qns_a1noc_snoc }, 166 }; 167 168 static struct qcom_icc_qosbox xm_emmc_qos = { 169 .num_ports = 1, 170 .port_offsets = { 0x7000 }, 171 .prio = 2, 172 .urg_fwd = 0, 173 }; 174 175 static struct qcom_icc_node xm_emmc = { 176 .name = "xm_emmc", 177 .channels = 1, 178 .buswidth = 8, 179 .qosbox = &xm_emmc_qos, 180 .num_links = 1, 181 .link_nodes = { &qns_a1noc_snoc }, 182 }; 183 184 static struct qcom_icc_qosbox xm_ufs_mem_qos = { 185 .num_ports = 1, 186 .port_offsets = { 0x8000 }, 187 .prio = 4, 188 .urg_fwd = 0, 189 }; 190 191 static struct qcom_icc_node xm_ufs_mem = { 192 .name = "xm_ufs_mem", 193 .channels = 1, 194 .buswidth = 8, 195 .qosbox = &xm_ufs_mem_qos, 196 .num_links = 1, 197 .link_nodes = { &qns_a1noc_snoc }, 198 }; 199 200 static struct qcom_icc_node qhm_a2noc_cfg = { 201 .name = "qhm_a2noc_cfg", 202 .channels = 1, 203 .buswidth = 4, 204 .num_links = 1, 205 .link_nodes = { &srvc_aggre2_noc }, 206 }; 207 208 static struct qcom_icc_qosbox qhm_qdss_bam_qos = { 209 .num_ports = 1, 210 .port_offsets = { 0xb000 }, 211 .prio = 2, 212 .urg_fwd = 0, 213 }; 214 215 static struct qcom_icc_node qhm_qdss_bam = { 216 .name = "qhm_qdss_bam", 217 .channels = 1, 218 .buswidth = 4, 219 .qosbox = &qhm_qdss_bam_qos, 220 .num_links = 1, 221 .link_nodes = { &qns_a2noc_snoc }, 222 }; 223 224 static struct qcom_icc_qosbox qhm_qup_1_qos = { 225 .num_ports = 1, 226 .port_offsets = { 0x9000 }, 227 .prio = 2, 228 .urg_fwd = 0, 229 }; 230 static struct qcom_icc_node qhm_qup_1 = { 231 .name = "qhm_qup_1", 232 .channels = 1, 233 .buswidth = 4, 234 .qosbox = &qhm_qup_1_qos, 235 .num_links = 1, 236 .link_nodes = { &qns_a2noc_snoc }, 237 }; 238 239 static struct qcom_icc_qosbox qxm_crypto_qos = { 240 .num_ports = 1, 241 .port_offsets = { 0x6000 }, 242 .prio = 2, 243 .urg_fwd = 0, 244 }; 245 246 static struct qcom_icc_node qxm_crypto = { 247 .name = "qxm_crypto", 248 .channels = 1, 249 .buswidth = 8, 250 .qosbox = &qxm_crypto_qos, 251 .num_links = 1, 252 .link_nodes = { &qns_a2noc_snoc }, 253 }; 254 255 static struct qcom_icc_qosbox qxm_ipa_qos = { 256 .num_ports = 1, 257 .port_offsets = { 0x7000 }, 258 .prio = 2, 259 .urg_fwd = 0, 260 }; 261 262 static struct qcom_icc_node qxm_ipa = { 263 .name = "qxm_ipa", 264 .channels = 1, 265 .buswidth = 8, 266 .qosbox = &qxm_ipa_qos, 267 .num_links = 1, 268 .link_nodes = { &qns_a2noc_snoc }, 269 }; 270 271 static struct qcom_icc_qosbox xm_qdss_etr_qos = { 272 .num_ports = 1, 273 .port_offsets = { 0xc000 }, 274 .prio = 2, 275 .urg_fwd = 0, 276 }; 277 278 static struct qcom_icc_node xm_qdss_etr = { 279 .name = "xm_qdss_etr", 280 .channels = 1, 281 .buswidth = 8, 282 .qosbox = &xm_qdss_etr_qos, 283 .num_links = 1, 284 .link_nodes = { &qns_a2noc_snoc }, 285 }; 286 287 static struct qcom_icc_qosbox xm_sdc2_qos = { 288 .num_ports = 1, 289 .port_offsets = { 0x18000 }, 290 .prio = 2, 291 .urg_fwd = 0, 292 }; 293 294 static struct qcom_icc_node xm_sdc2 = { 295 .name = "xm_sdc2", 296 .channels = 1, 297 .buswidth = 8, 298 .qosbox = &xm_sdc2_qos, 299 .num_links = 1, 300 .link_nodes = { &qns_a2noc_snoc }, 301 }; 302 303 static struct qcom_icc_qosbox xm_usb3_0_qos = { 304 .num_ports = 1, 305 .port_offsets = { 0xd000 }, 306 .prio = 2, 307 .urg_fwd = 0, 308 }; 309 310 static struct qcom_icc_node xm_usb3_0 = { 311 .name = "xm_usb3_0", 312 .channels = 1, 313 .buswidth = 8, 314 .qosbox = &xm_usb3_0_qos, 315 .num_links = 1, 316 .link_nodes = { &qns_a2noc_snoc }, 317 }; 318 319 static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { 320 .name = "qxm_camnoc_hf0_uncomp", 321 .channels = 2, 322 .buswidth = 32, 323 .num_links = 1, 324 .link_nodes = { &qns_camnoc_uncomp }, 325 }; 326 327 static struct qcom_icc_node qxm_camnoc_icp_uncomp = { 328 .name = "qxm_camnoc_icp_uncomp", 329 .channels = 1, 330 .buswidth = 32, 331 .num_links = 1, 332 .link_nodes = { &qns_camnoc_uncomp }, 333 }; 334 335 static struct qcom_icc_node qxm_camnoc_sf_uncomp = { 336 .name = "qxm_camnoc_sf_uncomp", 337 .channels = 1, 338 .buswidth = 32, 339 .num_links = 1, 340 .link_nodes = { &qns_camnoc_uncomp }, 341 }; 342 343 static struct qcom_icc_node qup0_core_master = { 344 .name = "qup0_core_master", 345 .channels = 1, 346 .buswidth = 4, 347 .num_links = 1, 348 .link_nodes = { &qup0_core_slave }, 349 }; 350 351 static struct qcom_icc_node qup1_core_master = { 352 .name = "qup1_core_master", 353 .channels = 1, 354 .buswidth = 4, 355 .num_links = 1, 356 .link_nodes = { &qup1_core_slave }, 357 }; 358 359 static struct qcom_icc_qosbox qnm_npu_qos = { 360 .num_ports = 2, 361 .port_offsets = { 0xf000, 0x11000 }, 362 .prio = 0, 363 .urg_fwd = 1, 364 }; 365 366 static struct qcom_icc_node qnm_npu = { 367 .name = "qnm_npu", 368 .channels = 2, 369 .buswidth = 32, 370 .qosbox = &qnm_npu_qos, 371 .num_links = 1, 372 .link_nodes = { &qns_cdsp_gemnoc }, 373 }; 374 375 static struct qcom_icc_qosbox qxm_npu_dsp_qos = { 376 .num_ports = 1, 377 .port_offsets = { 0x13000 }, 378 .prio = 0, 379 .urg_fwd = 1, 380 }; 381 382 static struct qcom_icc_node qxm_npu_dsp = { 383 .name = "qxm_npu_dsp", 384 .channels = 1, 385 .buswidth = 8, 386 .qosbox = &qxm_npu_dsp_qos, 387 .num_links = 1, 388 .link_nodes = { &qns_cdsp_gemnoc }, 389 }; 390 391 static struct qcom_icc_node qnm_snoc = { 392 .name = "qnm_snoc", 393 .channels = 1, 394 .buswidth = 8, 395 .num_links = 42, 396 .link_nodes = { &qhs_camera_cfg, 397 &qhs_sdc2, 398 &qhs_mnoc_cfg, 399 &qhs_ufs_mem_cfg, 400 &qhs_qm_cfg, 401 &qhs_snoc_cfg, 402 &qhs_qm_mpu_cfg, 403 &qhs_glm, 404 &qhs_pdm, 405 &qhs_camera_nrt_thrott_cfg, 406 &qhs_a2_noc_cfg, 407 &qhs_qdss_cfg, 408 &qhs_vsense_ctrl_cfg, 409 &qhs_camera_rt_throttle_cfg, 410 &qhs_display_cfg, 411 &qhs_tcsr, 412 &qhs_dcc_cfg, 413 &qhs_ddrss_cfg, 414 &qhs_display_throttle_cfg, 415 &qhs_npu_cfg, 416 &qhs_ahb2phy0, 417 &qhs_gpuss_cfg, 418 &qhs_boot_rom, 419 &qhs_venus_cfg, 420 &qhs_ipa, 421 &qhs_security, 422 &qhs_imem_cfg, 423 &qhs_mss_cfg, 424 &srvc_cnoc, 425 &qhs_usb3_0, 426 &qhs_venus_throttle_cfg, 427 &qhs_cpr_cx, 428 &qhs_a1_noc_cfg, 429 &qhs_aoss, 430 &qhs_prng, 431 &qhs_emmc_cfg, 432 &qhs_crypto0_cfg, 433 &qhs_pimem_cfg, 434 &qhs_cpr_mx, 435 &qhs_qup0, 436 &qhs_qup1, 437 &qhs_clk_ctl }, 438 }; 439 440 static struct qcom_icc_node xm_qdss_dap = { 441 .name = "xm_qdss_dap", 442 .channels = 1, 443 .buswidth = 8, 444 .num_links = 42, 445 .link_nodes = { &qhs_camera_cfg, 446 &qhs_sdc2, 447 &qhs_mnoc_cfg, 448 &qhs_ufs_mem_cfg, 449 &qhs_qm_cfg, 450 &qhs_snoc_cfg, 451 &qhs_qm_mpu_cfg, 452 &qhs_glm, 453 &qhs_pdm, 454 &qhs_camera_nrt_thrott_cfg, 455 &qhs_a2_noc_cfg, 456 &qhs_qdss_cfg, 457 &qhs_vsense_ctrl_cfg, 458 &qhs_camera_rt_throttle_cfg, 459 &qhs_display_cfg, 460 &qhs_tcsr, 461 &qhs_dcc_cfg, 462 &qhs_ddrss_cfg, 463 &qhs_display_throttle_cfg, 464 &qhs_npu_cfg, 465 &qhs_ahb2phy0, 466 &qhs_gpuss_cfg, 467 &qhs_boot_rom, 468 &qhs_venus_cfg, 469 &qhs_ipa, 470 &qhs_security, 471 &qhs_imem_cfg, 472 &qhs_mss_cfg, 473 &srvc_cnoc, 474 &qhs_usb3_0, 475 &qhs_venus_throttle_cfg, 476 &qhs_cpr_cx, 477 &qhs_a1_noc_cfg, 478 &qhs_aoss, 479 &qhs_prng, 480 &qhs_emmc_cfg, 481 &qhs_crypto0_cfg, 482 &qhs_pimem_cfg, 483 &qhs_cpr_mx, 484 &qhs_qup0, 485 &qhs_qup1, 486 &qhs_clk_ctl }, 487 }; 488 489 static struct qcom_icc_node qhm_cnoc_dc_noc = { 490 .name = "qhm_cnoc_dc_noc", 491 .channels = 1, 492 .buswidth = 4, 493 .num_links = 2, 494 .link_nodes = { &qhs_llcc, 495 &qhs_gemnoc }, 496 }; 497 498 static struct qcom_icc_qosbox acm_apps_qos = { 499 .num_ports = 2, 500 .port_offsets = { 0x2f100, 0x2f000 }, 501 .prio = 0, 502 .urg_fwd = 0, 503 }; 504 505 static struct qcom_icc_node acm_apps = { 506 .name = "acm_apps", 507 .channels = 1, 508 .buswidth = 16, 509 .qosbox = &acm_apps_qos, 510 .num_links = 2, 511 .link_nodes = { &qns_llcc, 512 &qns_gem_noc_snoc }, 513 }; 514 515 static struct qcom_icc_qosbox acm_sys_tcu_qos = { 516 .num_ports = 1, 517 .port_offsets = { 0x35000 }, 518 .prio = 6, 519 .urg_fwd = 0, 520 }; 521 522 static struct qcom_icc_node acm_sys_tcu = { 523 .name = "acm_sys_tcu", 524 .channels = 1, 525 .buswidth = 8, 526 .qosbox = &acm_sys_tcu_qos, 527 .num_links = 2, 528 .link_nodes = { &qns_llcc, 529 &qns_gem_noc_snoc }, 530 }; 531 532 static struct qcom_icc_node qhm_gemnoc_cfg = { 533 .name = "qhm_gemnoc_cfg", 534 .channels = 1, 535 .buswidth = 4, 536 .num_links = 3, 537 .link_nodes = { &qhs_mcdma_ms_mpu_cfg, 538 &srvc_gemnoc, 539 &qhs_mdsp_ms_mpu_cfg }, 540 }; 541 542 static struct qcom_icc_qosbox qnm_cmpnoc_qos = { 543 .num_ports = 1, 544 .port_offsets = { 0x2e000 }, 545 .prio = 0, 546 .urg_fwd = 1, 547 }; 548 549 static struct qcom_icc_node qnm_cmpnoc = { 550 .name = "qnm_cmpnoc", 551 .channels = 1, 552 .buswidth = 32, 553 .qosbox = &qnm_cmpnoc_qos, 554 .num_links = 2, 555 .link_nodes = { &qns_llcc, 556 &qns_gem_noc_snoc }, 557 }; 558 559 static struct qcom_icc_qosbox qnm_mnoc_hf_qos = { 560 .num_ports = 1, 561 .port_offsets = { 0x30000 }, 562 .prio = 0, 563 .urg_fwd = 1, 564 }; 565 566 static struct qcom_icc_node qnm_mnoc_hf = { 567 .name = "qnm_mnoc_hf", 568 .channels = 1, 569 .buswidth = 32, 570 .qosbox = &qnm_mnoc_hf_qos, 571 .num_links = 2, 572 .link_nodes = { &qns_llcc, 573 &qns_gem_noc_snoc }, 574 }; 575 576 static struct qcom_icc_qosbox qnm_mnoc_sf_qos = { 577 .num_ports = 1, 578 .port_offsets = { 0x34000 }, 579 .prio = 0, 580 .urg_fwd = 1, 581 }; 582 583 static struct qcom_icc_node qnm_mnoc_sf = { 584 .name = "qnm_mnoc_sf", 585 .channels = 1, 586 .buswidth = 32, 587 .qosbox = &qnm_mnoc_sf_qos, 588 .num_links = 2, 589 .link_nodes = { &qns_llcc, 590 &qns_gem_noc_snoc }, 591 }; 592 593 static struct qcom_icc_qosbox qnm_snoc_gc_qos = { 594 .num_ports = 1, 595 .port_offsets = { 0x32000 }, 596 .prio = 0, 597 .urg_fwd = 1, 598 }; 599 600 static struct qcom_icc_node qnm_snoc_gc = { 601 .name = "qnm_snoc_gc", 602 .channels = 1, 603 .buswidth = 8, 604 .qosbox = &qnm_snoc_gc_qos, 605 .num_links = 1, 606 .link_nodes = { &qns_llcc }, 607 }; 608 609 static struct qcom_icc_qosbox qnm_snoc_sf_qos = { 610 .num_ports = 1, 611 .port_offsets = { 0x31000 }, 612 .prio = 0, 613 .urg_fwd = 1, 614 }; 615 616 static struct qcom_icc_node qnm_snoc_sf = { 617 .name = "qnm_snoc_sf", 618 .channels = 1, 619 .buswidth = 16, 620 .qosbox = &qnm_snoc_sf_qos, 621 .num_links = 1, 622 .link_nodes = { &qns_llcc }, 623 }; 624 625 static struct qcom_icc_qosbox qxm_gpu_qos = { 626 .num_ports = 2, 627 .port_offsets = { 0x33000, 0x33080 }, 628 .prio = 0, 629 .urg_fwd = 0, 630 }; 631 632 static struct qcom_icc_node qxm_gpu = { 633 .name = "qxm_gpu", 634 .channels = 2, 635 .buswidth = 32, 636 .qosbox = &qxm_gpu_qos, 637 .num_links = 2, 638 .link_nodes = { &qns_llcc, 639 &qns_gem_noc_snoc }, 640 }; 641 642 static struct qcom_icc_node llcc_mc = { 643 .name = "llcc_mc", 644 .channels = 2, 645 .buswidth = 4, 646 .num_links = 1, 647 .link_nodes = { &ebi }, 648 }; 649 650 static struct qcom_icc_node qhm_mnoc_cfg = { 651 .name = "qhm_mnoc_cfg", 652 .channels = 1, 653 .buswidth = 4, 654 .num_links = 1, 655 .link_nodes = { &srvc_mnoc }, 656 }; 657 658 static struct qcom_icc_qosbox qnm_video0_qos = { 659 .num_ports = 1, 660 .port_offsets = { 0xf000 }, 661 .prio = 2, 662 .urg_fwd = 1, 663 }; 664 665 static struct qcom_icc_node qnm_video0 = { 666 .name = "qnm_video0", 667 .channels = 1, 668 .buswidth = 32, 669 .qosbox = &qnm_video0_qos, 670 .num_links = 1, 671 .link_nodes = { &qns_mem_noc_sf }, 672 }; 673 674 static struct qcom_icc_qosbox qnm_video_cvp_qos = { 675 .num_ports = 1, 676 .port_offsets = { 0xe000 }, 677 .prio = 5, 678 .urg_fwd = 1, 679 }; 680 681 static struct qcom_icc_node qnm_video_cvp = { 682 .name = "qnm_video_cvp", 683 .channels = 1, 684 .buswidth = 8, 685 .qosbox = &qnm_video_cvp_qos, 686 .num_links = 1, 687 .link_nodes = { &qns_mem_noc_sf }, 688 }; 689 690 static struct qcom_icc_qosbox qxm_camnoc_hf_qos = { 691 .num_ports = 2, 692 .port_offsets = { 0xa000, 0xb000 }, 693 .prio = 3, 694 .urg_fwd = 1, 695 }; 696 697 static struct qcom_icc_node qxm_camnoc_hf = { 698 .name = "qxm_camnoc_hf", 699 .channels = 2, 700 .buswidth = 32, 701 .qosbox = &qxm_camnoc_hf_qos, 702 .num_links = 1, 703 .link_nodes = { &qns_mem_noc_hf }, 704 }; 705 706 static struct qcom_icc_qosbox qxm_camnoc_icp_qos = { 707 .num_ports = 1, 708 .port_offsets = { 0xd000 }, 709 .prio = 5, 710 .urg_fwd = 0, 711 }; 712 713 static struct qcom_icc_node qxm_camnoc_icp = { 714 .name = "qxm_camnoc_icp", 715 .channels = 1, 716 .buswidth = 8, 717 .qosbox = &qxm_camnoc_icp_qos, 718 .num_links = 1, 719 .link_nodes = { &qns_mem_noc_sf }, 720 }; 721 722 static struct qcom_icc_qosbox qxm_camnoc_sf_qos = { 723 .num_ports = 1, 724 .port_offsets = { 0x9000 }, 725 .prio = 3, 726 .urg_fwd = 1, 727 }; 728 729 static struct qcom_icc_node qxm_camnoc_sf = { 730 .name = "qxm_camnoc_sf", 731 .channels = 1, 732 .buswidth = 32, 733 .qosbox = &qxm_camnoc_sf_qos, 734 .num_links = 1, 735 .link_nodes = { &qns_mem_noc_sf }, 736 }; 737 738 static struct qcom_icc_qosbox qxm_mdp0_qos = { 739 .num_ports = 1, 740 .port_offsets = { 0xc000 }, 741 .prio = 3, 742 .urg_fwd = 1, 743 }; 744 745 static struct qcom_icc_node qxm_mdp0 = { 746 .name = "qxm_mdp0", 747 .channels = 1, 748 .buswidth = 32, 749 .qosbox = &qxm_mdp0_qos, 750 .num_links = 1, 751 .link_nodes = { &qns_mem_noc_hf }, 752 }; 753 754 static struct qcom_icc_node amm_npu_sys = { 755 .name = "amm_npu_sys", 756 .channels = 2, 757 .buswidth = 32, 758 .num_links = 1, 759 .link_nodes = { &qns_npu_sys }, 760 }; 761 762 static struct qcom_icc_node qhm_npu_cfg = { 763 .name = "qhm_npu_cfg", 764 .channels = 1, 765 .buswidth = 4, 766 .num_links = 8, 767 .link_nodes = { &srvc_noc, 768 &qhs_isense, 769 &qhs_llm, 770 &qhs_dma_bwmon, 771 &qhs_cp, 772 &qhs_tcm, 773 &qhs_cal_dp0, 774 &qhs_dpm }, 775 }; 776 777 static struct qcom_icc_node qhm_snoc_cfg = { 778 .name = "qhm_snoc_cfg", 779 .channels = 1, 780 .buswidth = 4, 781 .num_links = 1, 782 .link_nodes = { &srvc_snoc }, 783 }; 784 785 static struct qcom_icc_node qnm_aggre1_noc = { 786 .name = "qnm_aggre1_noc", 787 .channels = 1, 788 .buswidth = 16, 789 .num_links = 6, 790 .link_nodes = { &qns_gemnoc_sf, 791 &qxs_pimem, 792 &qxs_imem, 793 &qhs_apss, 794 &qns_cnoc, 795 &xs_qdss_stm }, 796 }; 797 798 static struct qcom_icc_node qnm_aggre2_noc = { 799 .name = "qnm_aggre2_noc", 800 .channels = 1, 801 .buswidth = 16, 802 .num_links = 7, 803 .link_nodes = { &qns_gemnoc_sf, 804 &qxs_pimem, 805 &qxs_imem, 806 &qhs_apss, 807 &qns_cnoc, 808 &xs_sys_tcu_cfg, 809 &xs_qdss_stm }, 810 }; 811 812 static struct qcom_icc_node qnm_gemnoc = { 813 .name = "qnm_gemnoc", 814 .channels = 1, 815 .buswidth = 8, 816 .num_links = 6, 817 .link_nodes = { &qxs_pimem, 818 &qxs_imem, 819 &qhs_apss, 820 &qns_cnoc, 821 &xs_sys_tcu_cfg, 822 &xs_qdss_stm }, 823 }; 824 825 static struct qcom_icc_qosbox qxm_pimem_qos = { 826 .num_ports = 1, 827 .port_offsets = { 0xd000 }, 828 .prio = 2, 829 .urg_fwd = 0, 830 }; 831 832 static struct qcom_icc_node qxm_pimem = { 833 .name = "qxm_pimem", 834 .channels = 1, 835 .buswidth = 8, 836 .qosbox = &qxm_pimem_qos, 837 .num_links = 2, 838 .link_nodes = { &qns_gemnoc_gc, 839 &qxs_imem }, 840 }; 841 842 static struct qcom_icc_qosbox xm_gic_qos = { 843 .num_ports = 1, 844 .port_offsets = { 0xb000 }, 845 .prio = 3, 846 .urg_fwd = 0, 847 }; 848 849 static struct qcom_icc_node xm_gic = { 850 .name = "xm_gic", 851 .channels = 1, 852 .buswidth = 8, 853 .qosbox = &xm_gic_qos, 854 .num_links = 1, 855 .link_nodes = { &qns_gemnoc_gc }, 856 }; 857 858 static struct qcom_icc_node qns_a1noc_snoc = { 859 .name = "qns_a1noc_snoc", 860 .channels = 1, 861 .buswidth = 16, 862 .num_links = 1, 863 .link_nodes = { &qnm_aggre1_noc }, 864 }; 865 866 static struct qcom_icc_node srvc_aggre1_noc = { 867 .name = "srvc_aggre1_noc", 868 .channels = 1, 869 .buswidth = 4, 870 }; 871 872 static struct qcom_icc_node qns_a2noc_snoc = { 873 .name = "qns_a2noc_snoc", 874 .channels = 1, 875 .buswidth = 16, 876 .num_links = 1, 877 .link_nodes = { &qnm_aggre2_noc }, 878 }; 879 880 static struct qcom_icc_node srvc_aggre2_noc = { 881 .name = "srvc_aggre2_noc", 882 .channels = 1, 883 .buswidth = 4, 884 }; 885 886 static struct qcom_icc_node qns_camnoc_uncomp = { 887 .name = "qns_camnoc_uncomp", 888 .channels = 1, 889 .buswidth = 32, 890 }; 891 892 static struct qcom_icc_node qup0_core_slave = { 893 .name = "qup0_core_slave", 894 .channels = 1, 895 .buswidth = 4, 896 }; 897 898 static struct qcom_icc_node qup1_core_slave = { 899 .name = "qup1_core_slave", 900 .channels = 1, 901 .buswidth = 4, 902 }; 903 904 static struct qcom_icc_node qns_cdsp_gemnoc = { 905 .name = "qns_cdsp_gemnoc", 906 .channels = 1, 907 .buswidth = 32, 908 .num_links = 1, 909 .link_nodes = { &qnm_cmpnoc }, 910 }; 911 912 static struct qcom_icc_node qhs_a1_noc_cfg = { 913 .name = "qhs_a1_noc_cfg", 914 .channels = 1, 915 .buswidth = 4, 916 .num_links = 1, 917 .link_nodes = { &qhm_a1noc_cfg }, 918 }; 919 920 static struct qcom_icc_node qhs_a2_noc_cfg = { 921 .name = "qhs_a2_noc_cfg", 922 .channels = 1, 923 .buswidth = 4, 924 .num_links = 1, 925 .link_nodes = { &qhm_a2noc_cfg }, 926 }; 927 928 static struct qcom_icc_node qhs_ahb2phy0 = { 929 .name = "qhs_ahb2phy0", 930 .channels = 1, 931 .buswidth = 4, 932 }; 933 934 static struct qcom_icc_node qhs_ahb2phy2 = { 935 .name = "qhs_ahb2phy2", 936 .channels = 1, 937 .buswidth = 4, 938 }; 939 940 static struct qcom_icc_node qhs_aoss = { 941 .name = "qhs_aoss", 942 .channels = 1, 943 .buswidth = 4, 944 }; 945 946 static struct qcom_icc_node qhs_boot_rom = { 947 .name = "qhs_boot_rom", 948 .channels = 1, 949 .buswidth = 4, 950 }; 951 952 static struct qcom_icc_node qhs_camera_cfg = { 953 .name = "qhs_camera_cfg", 954 .channels = 1, 955 .buswidth = 4, 956 }; 957 958 static struct qcom_icc_node qhs_camera_nrt_thrott_cfg = { 959 .name = "qhs_camera_nrt_thrott_cfg", 960 .channels = 1, 961 .buswidth = 4, 962 }; 963 964 static struct qcom_icc_node qhs_camera_rt_throttle_cfg = { 965 .name = "qhs_camera_rt_throttle_cfg", 966 .channels = 1, 967 .buswidth = 4, 968 }; 969 970 static struct qcom_icc_node qhs_clk_ctl = { 971 .name = "qhs_clk_ctl", 972 .channels = 1, 973 .buswidth = 4, 974 }; 975 976 static struct qcom_icc_node qhs_cpr_cx = { 977 .name = "qhs_cpr_cx", 978 .channels = 1, 979 .buswidth = 4, 980 }; 981 982 static struct qcom_icc_node qhs_cpr_mx = { 983 .name = "qhs_cpr_mx", 984 .channels = 1, 985 .buswidth = 4, 986 }; 987 988 static struct qcom_icc_node qhs_crypto0_cfg = { 989 .name = "qhs_crypto0_cfg", 990 .channels = 1, 991 .buswidth = 4, 992 }; 993 994 static struct qcom_icc_node qhs_dcc_cfg = { 995 .name = "qhs_dcc_cfg", 996 .channels = 1, 997 .buswidth = 4, 998 }; 999 1000 static struct qcom_icc_node qhs_ddrss_cfg = { 1001 .name = "qhs_ddrss_cfg", 1002 .channels = 1, 1003 .buswidth = 4, 1004 .num_links = 1, 1005 .link_nodes = { &qhm_cnoc_dc_noc }, 1006 }; 1007 1008 static struct qcom_icc_node qhs_display_cfg = { 1009 .name = "qhs_display_cfg", 1010 .channels = 1, 1011 .buswidth = 4, 1012 }; 1013 1014 static struct qcom_icc_node qhs_display_throttle_cfg = { 1015 .name = "qhs_display_throttle_cfg", 1016 .channels = 1, 1017 .buswidth = 4, 1018 }; 1019 1020 static struct qcom_icc_node qhs_emmc_cfg = { 1021 .name = "qhs_emmc_cfg", 1022 .channels = 1, 1023 .buswidth = 4, 1024 }; 1025 1026 static struct qcom_icc_node qhs_glm = { 1027 .name = "qhs_glm", 1028 .channels = 1, 1029 .buswidth = 4, 1030 }; 1031 1032 static struct qcom_icc_node qhs_gpuss_cfg = { 1033 .name = "qhs_gpuss_cfg", 1034 .channels = 1, 1035 .buswidth = 8, 1036 }; 1037 1038 static struct qcom_icc_node qhs_imem_cfg = { 1039 .name = "qhs_imem_cfg", 1040 .channels = 1, 1041 .buswidth = 4, 1042 }; 1043 1044 static struct qcom_icc_node qhs_ipa = { 1045 .name = "qhs_ipa", 1046 .channels = 1, 1047 .buswidth = 4, 1048 }; 1049 1050 static struct qcom_icc_node qhs_mnoc_cfg = { 1051 .name = "qhs_mnoc_cfg", 1052 .channels = 1, 1053 .buswidth = 4, 1054 .num_links = 1, 1055 .link_nodes = { &qhm_mnoc_cfg }, 1056 }; 1057 1058 static struct qcom_icc_node qhs_mss_cfg = { 1059 .name = "qhs_mss_cfg", 1060 .channels = 1, 1061 .buswidth = 4, 1062 }; 1063 1064 static struct qcom_icc_node qhs_npu_cfg = { 1065 .name = "qhs_npu_cfg", 1066 .channels = 1, 1067 .buswidth = 4, 1068 .num_links = 1, 1069 .link_nodes = { &qhm_npu_cfg }, 1070 }; 1071 1072 static struct qcom_icc_node qhs_pdm = { 1073 .name = "qhs_pdm", 1074 .channels = 1, 1075 .buswidth = 4, 1076 }; 1077 1078 static struct qcom_icc_node qhs_pimem_cfg = { 1079 .name = "qhs_pimem_cfg", 1080 .channels = 1, 1081 .buswidth = 4, 1082 }; 1083 1084 static struct qcom_icc_node qhs_prng = { 1085 .name = "qhs_prng", 1086 .channels = 1, 1087 .buswidth = 4, 1088 }; 1089 1090 static struct qcom_icc_node qhs_qdss_cfg = { 1091 .name = "qhs_qdss_cfg", 1092 .channels = 1, 1093 .buswidth = 4, 1094 }; 1095 1096 static struct qcom_icc_node qhs_qm_cfg = { 1097 .name = "qhs_qm_cfg", 1098 .channels = 1, 1099 .buswidth = 4, 1100 }; 1101 1102 static struct qcom_icc_node qhs_qm_mpu_cfg = { 1103 .name = "qhs_qm_mpu_cfg", 1104 .channels = 1, 1105 .buswidth = 4, 1106 }; 1107 1108 static struct qcom_icc_node qhs_qup0 = { 1109 .name = "qhs_qup0", 1110 .channels = 1, 1111 .buswidth = 4, 1112 }; 1113 1114 static struct qcom_icc_node qhs_qup1 = { 1115 .name = "qhs_qup1", 1116 .channels = 1, 1117 .buswidth = 4, 1118 }; 1119 1120 static struct qcom_icc_node qhs_sdc2 = { 1121 .name = "qhs_sdc2", 1122 .channels = 1, 1123 .buswidth = 4, 1124 }; 1125 1126 static struct qcom_icc_node qhs_security = { 1127 .name = "qhs_security", 1128 .channels = 1, 1129 .buswidth = 4, 1130 }; 1131 1132 static struct qcom_icc_node qhs_snoc_cfg = { 1133 .name = "qhs_snoc_cfg", 1134 .channels = 1, 1135 .buswidth = 4, 1136 .num_links = 1, 1137 .link_nodes = { &qhm_snoc_cfg }, 1138 }; 1139 1140 static struct qcom_icc_node qhs_tcsr = { 1141 .name = "qhs_tcsr", 1142 .channels = 1, 1143 .buswidth = 4, 1144 }; 1145 1146 static struct qcom_icc_node qhs_ufs_mem_cfg = { 1147 .name = "qhs_ufs_mem_cfg", 1148 .channels = 1, 1149 .buswidth = 4, 1150 }; 1151 1152 static struct qcom_icc_node qhs_usb3_0 = { 1153 .name = "qhs_usb3_0", 1154 .channels = 1, 1155 .buswidth = 4, 1156 }; 1157 1158 static struct qcom_icc_node qhs_venus_cfg = { 1159 .name = "qhs_venus_cfg", 1160 .channels = 1, 1161 .buswidth = 4, 1162 }; 1163 1164 static struct qcom_icc_node qhs_venus_throttle_cfg = { 1165 .name = "qhs_venus_throttle_cfg", 1166 .channels = 1, 1167 .buswidth = 4, 1168 }; 1169 1170 static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 1171 .name = "qhs_vsense_ctrl_cfg", 1172 .channels = 1, 1173 .buswidth = 4, 1174 }; 1175 1176 static struct qcom_icc_node srvc_cnoc = { 1177 .name = "srvc_cnoc", 1178 .channels = 1, 1179 .buswidth = 4, 1180 }; 1181 1182 static struct qcom_icc_node qhs_gemnoc = { 1183 .name = "qhs_gemnoc", 1184 .channels = 1, 1185 .buswidth = 4, 1186 .num_links = 1, 1187 .link_nodes = { &qhm_gemnoc_cfg }, 1188 }; 1189 1190 static struct qcom_icc_node qhs_llcc = { 1191 .name = "qhs_llcc", 1192 .channels = 1, 1193 .buswidth = 4, 1194 }; 1195 1196 static struct qcom_icc_node qhs_mcdma_ms_mpu_cfg = { 1197 .name = "qhs_mcdma_ms_mpu_cfg", 1198 .channels = 1, 1199 .buswidth = 4, 1200 }; 1201 1202 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { 1203 .name = "qhs_mdsp_ms_mpu_cfg", 1204 .channels = 1, 1205 .buswidth = 4, 1206 }; 1207 1208 static struct qcom_icc_node qns_gem_noc_snoc = { 1209 .name = "qns_gem_noc_snoc", 1210 .channels = 1, 1211 .buswidth = 8, 1212 .num_links = 1, 1213 .link_nodes = { &qnm_gemnoc }, 1214 }; 1215 1216 static struct qcom_icc_node qns_llcc = { 1217 .name = "qns_llcc", 1218 .channels = 1, 1219 .buswidth = 16, 1220 .num_links = 1, 1221 .link_nodes = { &llcc_mc }, 1222 }; 1223 1224 static struct qcom_icc_node srvc_gemnoc = { 1225 .name = "srvc_gemnoc", 1226 .channels = 1, 1227 .buswidth = 4, 1228 }; 1229 1230 static struct qcom_icc_node ebi = { 1231 .name = "ebi", 1232 .channels = 2, 1233 .buswidth = 4, 1234 }; 1235 1236 static struct qcom_icc_node qns_mem_noc_hf = { 1237 .name = "qns_mem_noc_hf", 1238 .channels = 1, 1239 .buswidth = 32, 1240 .num_links = 1, 1241 .link_nodes = { &qnm_mnoc_hf }, 1242 }; 1243 1244 static struct qcom_icc_node qns_mem_noc_sf = { 1245 .name = "qns_mem_noc_sf", 1246 .channels = 1, 1247 .buswidth = 32, 1248 .num_links = 1, 1249 .link_nodes = { &qnm_mnoc_sf }, 1250 }; 1251 1252 static struct qcom_icc_node srvc_mnoc = { 1253 .name = "srvc_mnoc", 1254 .channels = 1, 1255 .buswidth = 4, 1256 }; 1257 1258 static struct qcom_icc_node qhs_cal_dp0 = { 1259 .name = "qhs_cal_dp0", 1260 .channels = 1, 1261 .buswidth = 4, 1262 }; 1263 1264 static struct qcom_icc_node qhs_cp = { 1265 .name = "qhs_cp", 1266 .channels = 1, 1267 .buswidth = 4, 1268 }; 1269 1270 static struct qcom_icc_node qhs_dma_bwmon = { 1271 .name = "qhs_dma_bwmon", 1272 .channels = 1, 1273 .buswidth = 4, 1274 }; 1275 1276 static struct qcom_icc_node qhs_dpm = { 1277 .name = "qhs_dpm", 1278 .channels = 1, 1279 .buswidth = 4, 1280 }; 1281 1282 static struct qcom_icc_node qhs_isense = { 1283 .name = "qhs_isense", 1284 .channels = 1, 1285 .buswidth = 4, 1286 }; 1287 1288 static struct qcom_icc_node qhs_llm = { 1289 .name = "qhs_llm", 1290 .channels = 1, 1291 .buswidth = 4, 1292 }; 1293 1294 static struct qcom_icc_node qhs_tcm = { 1295 .name = "qhs_tcm", 1296 .channels = 1, 1297 .buswidth = 4, 1298 }; 1299 1300 static struct qcom_icc_node qns_npu_sys = { 1301 .name = "qns_npu_sys", 1302 .channels = 2, 1303 .buswidth = 32, 1304 }; 1305 1306 static struct qcom_icc_node srvc_noc = { 1307 .name = "srvc_noc", 1308 .channels = 1, 1309 .buswidth = 4, 1310 }; 1311 1312 static struct qcom_icc_node qhs_apss = { 1313 .name = "qhs_apss", 1314 .channels = 1, 1315 .buswidth = 8, 1316 }; 1317 1318 static struct qcom_icc_node qns_cnoc = { 1319 .name = "qns_cnoc", 1320 .channels = 1, 1321 .buswidth = 8, 1322 .num_links = 1, 1323 .link_nodes = { &qnm_snoc }, 1324 }; 1325 1326 static struct qcom_icc_node qns_gemnoc_gc = { 1327 .name = "qns_gemnoc_gc", 1328 .channels = 1, 1329 .buswidth = 8, 1330 .num_links = 1, 1331 .link_nodes = { &qnm_snoc_gc }, 1332 }; 1333 1334 static struct qcom_icc_node qns_gemnoc_sf = { 1335 .name = "qns_gemnoc_sf", 1336 .channels = 1, 1337 .buswidth = 16, 1338 .num_links = 1, 1339 .link_nodes = { &qnm_snoc_sf }, 1340 }; 1341 1342 static struct qcom_icc_node qxs_imem = { 1343 .name = "qxs_imem", 1344 .channels = 1, 1345 .buswidth = 8, 1346 }; 1347 1348 static struct qcom_icc_node qxs_pimem = { 1349 .name = "qxs_pimem", 1350 .channels = 1, 1351 .buswidth = 8, 1352 }; 1353 1354 static struct qcom_icc_node srvc_snoc = { 1355 .name = "srvc_snoc", 1356 .channels = 1, 1357 .buswidth = 4, 1358 }; 1359 1360 static struct qcom_icc_node xs_qdss_stm = { 1361 .name = "xs_qdss_stm", 1362 .channels = 1, 1363 .buswidth = 4, 1364 }; 1365 1366 static struct qcom_icc_node xs_sys_tcu_cfg = { 1367 .name = "xs_sys_tcu_cfg", 1368 .channels = 1, 1369 .buswidth = 8, 1370 }; 1371 1372 static struct qcom_icc_bcm bcm_acv = { 1373 .name = "ACV", 1374 .enable_mask = BIT(3), 1375 .keepalive = false, 1376 .num_nodes = 1, 1377 .nodes = { &ebi }, 1378 }; 1379 1380 static struct qcom_icc_bcm bcm_ce0 = { 1381 .name = "CE0", 1382 .keepalive = false, 1383 .num_nodes = 1, 1384 .nodes = { &qxm_crypto }, 1385 }; 1386 1387 static struct qcom_icc_bcm bcm_cn0 = { 1388 .name = "CN0", 1389 .keepalive = true, 1390 .num_nodes = 41, 1391 .nodes = { &qnm_snoc, 1392 &xm_qdss_dap, 1393 &qhs_a1_noc_cfg, 1394 &qhs_a2_noc_cfg, 1395 &qhs_ahb2phy0, 1396 &qhs_aoss, 1397 &qhs_boot_rom, 1398 &qhs_camera_cfg, 1399 &qhs_camera_nrt_thrott_cfg, 1400 &qhs_camera_rt_throttle_cfg, 1401 &qhs_clk_ctl, 1402 &qhs_cpr_cx, 1403 &qhs_cpr_mx, 1404 &qhs_crypto0_cfg, 1405 &qhs_dcc_cfg, 1406 &qhs_ddrss_cfg, 1407 &qhs_display_cfg, 1408 &qhs_display_throttle_cfg, 1409 &qhs_glm, 1410 &qhs_gpuss_cfg, 1411 &qhs_imem_cfg, 1412 &qhs_ipa, 1413 &qhs_mnoc_cfg, 1414 &qhs_mss_cfg, 1415 &qhs_npu_cfg, 1416 &qhs_pimem_cfg, 1417 &qhs_prng, 1418 &qhs_qdss_cfg, 1419 &qhs_qm_cfg, 1420 &qhs_qm_mpu_cfg, 1421 &qhs_qup0, 1422 &qhs_qup1, 1423 &qhs_security, 1424 &qhs_snoc_cfg, 1425 &qhs_tcsr, 1426 &qhs_ufs_mem_cfg, 1427 &qhs_usb3_0, 1428 &qhs_venus_cfg, 1429 &qhs_venus_throttle_cfg, 1430 &qhs_vsense_ctrl_cfg, 1431 &srvc_cnoc 1432 }, 1433 }; 1434 1435 static struct qcom_icc_bcm bcm_cn1 = { 1436 .name = "CN1", 1437 .keepalive = false, 1438 .num_nodes = 6, 1439 .nodes = { &xm_emmc, 1440 &xm_sdc2, 1441 &qhs_ahb2phy2, 1442 &qhs_emmc_cfg, 1443 &qhs_pdm, 1444 &qhs_sdc2 1445 }, 1446 }; 1447 1448 static struct qcom_icc_bcm bcm_co0 = { 1449 .name = "CO0", 1450 .keepalive = false, 1451 .num_nodes = 1, 1452 .nodes = { &qns_cdsp_gemnoc }, 1453 }; 1454 1455 static struct qcom_icc_bcm bcm_co2 = { 1456 .name = "CO2", 1457 .keepalive = false, 1458 .num_nodes = 1, 1459 .nodes = { &qnm_npu }, 1460 }; 1461 1462 static struct qcom_icc_bcm bcm_co3 = { 1463 .name = "CO3", 1464 .keepalive = false, 1465 .num_nodes = 1, 1466 .nodes = { &qxm_npu_dsp }, 1467 }; 1468 1469 static struct qcom_icc_bcm bcm_mc0 = { 1470 .name = "MC0", 1471 .keepalive = true, 1472 .num_nodes = 1, 1473 .nodes = { &ebi }, 1474 }; 1475 1476 static struct qcom_icc_bcm bcm_mm0 = { 1477 .name = "MM0", 1478 .keepalive = true, 1479 .num_nodes = 1, 1480 .nodes = { &qns_mem_noc_hf }, 1481 }; 1482 1483 static struct qcom_icc_bcm bcm_mm1 = { 1484 .name = "MM1", 1485 .keepalive = true, 1486 .num_nodes = 5, 1487 .nodes = { &qxm_camnoc_hf0_uncomp, 1488 &qxm_camnoc_icp_uncomp, 1489 &qxm_camnoc_sf_uncomp, 1490 &qxm_camnoc_hf, 1491 &qxm_mdp0 1492 }, 1493 }; 1494 1495 static struct qcom_icc_bcm bcm_mm2 = { 1496 .name = "MM2", 1497 .keepalive = false, 1498 .num_nodes = 1, 1499 .nodes = { &qns_mem_noc_sf }, 1500 }; 1501 1502 static struct qcom_icc_bcm bcm_mm3 = { 1503 .name = "MM3", 1504 .keepalive = false, 1505 .num_nodes = 4, 1506 .nodes = { &qhm_mnoc_cfg, &qnm_video0, &qnm_video_cvp, &qxm_camnoc_sf }, 1507 }; 1508 1509 static struct qcom_icc_bcm bcm_qup0 = { 1510 .name = "QUP0", 1511 .keepalive = false, 1512 .num_nodes = 4, 1513 .nodes = { &qup0_core_master, &qup1_core_master, &qup0_core_slave, &qup1_core_slave }, 1514 }; 1515 1516 static struct qcom_icc_bcm bcm_sh0 = { 1517 .name = "SH0", 1518 .keepalive = true, 1519 .num_nodes = 1, 1520 .nodes = { &qns_llcc }, 1521 }; 1522 1523 static struct qcom_icc_bcm bcm_sh2 = { 1524 .name = "SH2", 1525 .keepalive = false, 1526 .num_nodes = 1, 1527 .nodes = { &acm_sys_tcu }, 1528 }; 1529 1530 static struct qcom_icc_bcm bcm_sh3 = { 1531 .name = "SH3", 1532 .keepalive = false, 1533 .num_nodes = 1, 1534 .nodes = { &qnm_cmpnoc }, 1535 }; 1536 1537 static struct qcom_icc_bcm bcm_sh4 = { 1538 .name = "SH4", 1539 .keepalive = false, 1540 .num_nodes = 1, 1541 .nodes = { &acm_apps }, 1542 }; 1543 1544 static struct qcom_icc_bcm bcm_sn0 = { 1545 .name = "SN0", 1546 .keepalive = true, 1547 .num_nodes = 1, 1548 .nodes = { &qns_gemnoc_sf }, 1549 }; 1550 1551 static struct qcom_icc_bcm bcm_sn1 = { 1552 .name = "SN1", 1553 .keepalive = false, 1554 .num_nodes = 1, 1555 .nodes = { &qxs_imem }, 1556 }; 1557 1558 static struct qcom_icc_bcm bcm_sn2 = { 1559 .name = "SN2", 1560 .keepalive = false, 1561 .num_nodes = 1, 1562 .nodes = { &qns_gemnoc_gc }, 1563 }; 1564 1565 static struct qcom_icc_bcm bcm_sn3 = { 1566 .name = "SN3", 1567 .keepalive = false, 1568 .num_nodes = 1, 1569 .nodes = { &qxs_pimem }, 1570 }; 1571 1572 static struct qcom_icc_bcm bcm_sn4 = { 1573 .name = "SN4", 1574 .keepalive = false, 1575 .num_nodes = 1, 1576 .nodes = { &xs_qdss_stm }, 1577 }; 1578 1579 static struct qcom_icc_bcm bcm_sn5 = { 1580 .name = "SN5", 1581 .keepalive = false, 1582 .num_nodes = 1, 1583 .nodes = { &qnm_aggre1_noc }, 1584 }; 1585 1586 static struct qcom_icc_bcm bcm_sn6 = { 1587 .name = "SN6", 1588 .keepalive = false, 1589 .num_nodes = 1, 1590 .nodes = { &qnm_aggre2_noc }, 1591 }; 1592 1593 static struct qcom_icc_bcm bcm_sn10 = { 1594 .name = "SN10", 1595 .keepalive = false, 1596 .num_nodes = 1, 1597 .nodes = { &qnm_gemnoc }, 1598 }; 1599 1600 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 1601 &bcm_cn1, 1602 }; 1603 1604 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1605 [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg, 1606 [MASTER_QUP_0] = &qhm_qup_0, 1607 [MASTER_EMMC] = &xm_emmc, 1608 [MASTER_UFS_MEM] = &xm_ufs_mem, 1609 [A1NOC_SNOC_SLV] = &qns_a1noc_snoc, 1610 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, 1611 }; 1612 1613 static const struct regmap_config sm6350_aggre1_noc_regmap_config = { 1614 .reg_bits = 32, 1615 .reg_stride = 4, 1616 .val_bits = 32, 1617 .max_register = 0x15080, 1618 .fast_io = true, 1619 }; 1620 1621 static const struct qcom_icc_desc sm6350_aggre1_noc = { 1622 .config = &sm6350_aggre1_noc_regmap_config, 1623 .nodes = aggre1_noc_nodes, 1624 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 1625 .bcms = aggre1_noc_bcms, 1626 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 1627 .qos_requires_clocks = true, 1628 }; 1629 1630 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 1631 &bcm_ce0, 1632 &bcm_cn1, 1633 }; 1634 1635 static struct qcom_icc_node * const aggre2_noc_nodes[] = { 1636 [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg, 1637 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 1638 [MASTER_QUP_1] = &qhm_qup_1, 1639 [MASTER_CRYPTO_CORE_0] = &qxm_crypto, 1640 [MASTER_IPA] = &qxm_ipa, 1641 [MASTER_QDSS_ETR] = &xm_qdss_etr, 1642 [MASTER_SDCC_2] = &xm_sdc2, 1643 [MASTER_USB3] = &xm_usb3_0, 1644 [A2NOC_SNOC_SLV] = &qns_a2noc_snoc, 1645 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, 1646 }; 1647 1648 static const struct regmap_config sm6350_aggre2_noc_regmap_config = { 1649 .reg_bits = 32, 1650 .reg_stride = 4, 1651 .val_bits = 32, 1652 .max_register = 0x1f880, 1653 .fast_io = true, 1654 }; 1655 1656 static const struct qcom_icc_desc sm6350_aggre2_noc = { 1657 .config = &sm6350_aggre2_noc_regmap_config, 1658 .nodes = aggre2_noc_nodes, 1659 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 1660 .bcms = aggre2_noc_bcms, 1661 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 1662 .qos_requires_clocks = true, 1663 }; 1664 1665 static struct qcom_icc_bcm * const clk_virt_bcms[] = { 1666 &bcm_acv, 1667 &bcm_mc0, 1668 &bcm_mm1, 1669 &bcm_qup0, 1670 }; 1671 1672 static struct qcom_icc_node * const clk_virt_nodes[] = { 1673 [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp, 1674 [MASTER_CAMNOC_ICP_UNCOMP] = &qxm_camnoc_icp_uncomp, 1675 [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp, 1676 [MASTER_QUP_CORE_0] = &qup0_core_master, 1677 [MASTER_QUP_CORE_1] = &qup1_core_master, 1678 [MASTER_LLCC] = &llcc_mc, 1679 [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp, 1680 [SLAVE_QUP_CORE_0] = &qup0_core_slave, 1681 [SLAVE_QUP_CORE_1] = &qup1_core_slave, 1682 [SLAVE_EBI_CH0] = &ebi, 1683 }; 1684 1685 static const struct qcom_icc_desc sm6350_clk_virt = { 1686 .nodes = clk_virt_nodes, 1687 .num_nodes = ARRAY_SIZE(clk_virt_nodes), 1688 .bcms = clk_virt_bcms, 1689 .num_bcms = ARRAY_SIZE(clk_virt_bcms), 1690 }; 1691 1692 static struct qcom_icc_bcm * const compute_noc_bcms[] = { 1693 &bcm_co0, 1694 &bcm_co2, 1695 &bcm_co3, 1696 }; 1697 1698 static struct qcom_icc_node * const compute_noc_nodes[] = { 1699 [MASTER_NPU] = &qnm_npu, 1700 [MASTER_NPU_PROC] = &qxm_npu_dsp, 1701 [SLAVE_CDSP_GEM_NOC] = &qns_cdsp_gemnoc, 1702 }; 1703 1704 static const struct regmap_config sm6350_compute_noc_regmap_config = { 1705 .reg_bits = 32, 1706 .reg_stride = 4, 1707 .val_bits = 32, 1708 .max_register = 0x1f880, 1709 .fast_io = true, 1710 }; 1711 1712 static const struct qcom_icc_desc sm6350_compute_noc = { 1713 .config = &sm6350_compute_noc_regmap_config, 1714 .nodes = compute_noc_nodes, 1715 .num_nodes = ARRAY_SIZE(compute_noc_nodes), 1716 .bcms = compute_noc_bcms, 1717 .num_bcms = ARRAY_SIZE(compute_noc_bcms), 1718 }; 1719 1720 static struct qcom_icc_bcm * const config_noc_bcms[] = { 1721 &bcm_cn0, 1722 &bcm_cn1, 1723 }; 1724 1725 static struct qcom_icc_node * const config_noc_nodes[] = { 1726 [SNOC_CNOC_MAS] = &qnm_snoc, 1727 [MASTER_QDSS_DAP] = &xm_qdss_dap, 1728 [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg, 1729 [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg, 1730 [SLAVE_AHB2PHY] = &qhs_ahb2phy0, 1731 [SLAVE_AHB2PHY_2] = &qhs_ahb2phy2, 1732 [SLAVE_AOSS] = &qhs_aoss, 1733 [SLAVE_BOOT_ROM] = &qhs_boot_rom, 1734 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 1735 [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_thrott_cfg, 1736 [SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg, 1737 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1738 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 1739 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, 1740 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1741 [SLAVE_DCC_CFG] = &qhs_dcc_cfg, 1742 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg, 1743 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 1744 [SLAVE_DISPLAY_THROTTLE_CFG] = &qhs_display_throttle_cfg, 1745 [SLAVE_EMMC_CFG] = &qhs_emmc_cfg, 1746 [SLAVE_GLM] = &qhs_glm, 1747 [SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg, 1748 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1749 [SLAVE_IPA_CFG] = &qhs_ipa, 1750 [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg, 1751 [SLAVE_CNOC_MSS] = &qhs_mss_cfg, 1752 [SLAVE_NPU_CFG] = &qhs_npu_cfg, 1753 [SLAVE_PDM] = &qhs_pdm, 1754 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 1755 [SLAVE_PRNG] = &qhs_prng, 1756 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1757 [SLAVE_QM_CFG] = &qhs_qm_cfg, 1758 [SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg, 1759 [SLAVE_QUP_0] = &qhs_qup0, 1760 [SLAVE_QUP_1] = &qhs_qup1, 1761 [SLAVE_SDCC_2] = &qhs_sdc2, 1762 [SLAVE_SECURITY] = &qhs_security, 1763 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, 1764 [SLAVE_TCSR] = &qhs_tcsr, 1765 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 1766 [SLAVE_USB3] = &qhs_usb3_0, 1767 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1768 [SLAVE_VENUS_THROTTLE_CFG] = &qhs_venus_throttle_cfg, 1769 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 1770 [SLAVE_SERVICE_CNOC] = &srvc_cnoc, 1771 }; 1772 1773 static const struct qcom_icc_desc sm6350_config_noc = { 1774 .nodes = config_noc_nodes, 1775 .num_nodes = ARRAY_SIZE(config_noc_nodes), 1776 .bcms = config_noc_bcms, 1777 .num_bcms = ARRAY_SIZE(config_noc_bcms), 1778 }; 1779 1780 static struct qcom_icc_node * const dc_noc_nodes[] = { 1781 [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc, 1782 [SLAVE_GEM_NOC_CFG] = &qhs_gemnoc, 1783 [SLAVE_LLCC_CFG] = &qhs_llcc, 1784 }; 1785 1786 static const struct regmap_config sm6350_dc_noc_regmap_config = { 1787 .reg_bits = 32, 1788 .reg_stride = 4, 1789 .val_bits = 32, 1790 .max_register = 0x3200, 1791 .fast_io = true, 1792 }; 1793 1794 static const struct qcom_icc_desc sm6350_dc_noc = { 1795 .config = &sm6350_dc_noc_regmap_config, 1796 .nodes = dc_noc_nodes, 1797 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 1798 }; 1799 1800 static struct qcom_icc_bcm * const gem_noc_bcms[] = { 1801 &bcm_sh0, 1802 &bcm_sh2, 1803 &bcm_sh3, 1804 &bcm_sh4, 1805 }; 1806 1807 static struct qcom_icc_node * const gem_noc_nodes[] = { 1808 [MASTER_AMPSS_M0] = &acm_apps, 1809 [MASTER_SYS_TCU] = &acm_sys_tcu, 1810 [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg, 1811 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc, 1812 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 1813 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 1814 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 1815 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 1816 [MASTER_GRAPHICS_3D] = &qxm_gpu, 1817 [SLAVE_MCDMA_MS_MPU_CFG] = &qhs_mcdma_ms_mpu_cfg, 1818 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg, 1819 [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc, 1820 [SLAVE_LLCC] = &qns_llcc, 1821 [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc, 1822 }; 1823 1824 static const struct regmap_config sm6350_gem_noc_regmap_config = { 1825 .reg_bits = 32, 1826 .reg_stride = 4, 1827 .val_bits = 32, 1828 .max_register = 0x3e200, 1829 .fast_io = true, 1830 }; 1831 1832 static const struct qcom_icc_desc sm6350_gem_noc = { 1833 .config = &sm6350_gem_noc_regmap_config, 1834 .nodes = gem_noc_nodes, 1835 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 1836 .bcms = gem_noc_bcms, 1837 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 1838 }; 1839 1840 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 1841 &bcm_mm0, 1842 &bcm_mm1, 1843 &bcm_mm2, 1844 &bcm_mm3, 1845 }; 1846 1847 static struct qcom_icc_node * const mmss_noc_nodes[] = { 1848 [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg, 1849 [MASTER_VIDEO_P0] = &qnm_video0, 1850 [MASTER_VIDEO_PROC] = &qnm_video_cvp, 1851 [MASTER_CAMNOC_HF] = &qxm_camnoc_hf, 1852 [MASTER_CAMNOC_ICP] = &qxm_camnoc_icp, 1853 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf, 1854 [MASTER_MDP_PORT0] = &qxm_mdp0, 1855 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 1856 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, 1857 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 1858 }; 1859 1860 static const struct regmap_config sm6350_mmss_noc_regmap_config = { 1861 .reg_bits = 32, 1862 .reg_stride = 4, 1863 .val_bits = 32, 1864 .max_register = 0x1c100, 1865 .fast_io = true, 1866 }; 1867 1868 static const struct qcom_icc_desc sm6350_mmss_noc = { 1869 .config = &sm6350_mmss_noc_regmap_config, 1870 .nodes = mmss_noc_nodes, 1871 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 1872 .bcms = mmss_noc_bcms, 1873 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 1874 }; 1875 1876 static struct qcom_icc_node * const npu_noc_nodes[] = { 1877 [MASTER_NPU_SYS] = &amm_npu_sys, 1878 [MASTER_NPU_NOC_CFG] = &qhm_npu_cfg, 1879 [SLAVE_NPU_CAL_DP0] = &qhs_cal_dp0, 1880 [SLAVE_NPU_CP] = &qhs_cp, 1881 [SLAVE_NPU_INT_DMA_BWMON_CFG] = &qhs_dma_bwmon, 1882 [SLAVE_NPU_DPM] = &qhs_dpm, 1883 [SLAVE_ISENSE_CFG] = &qhs_isense, 1884 [SLAVE_NPU_LLM_CFG] = &qhs_llm, 1885 [SLAVE_NPU_TCM] = &qhs_tcm, 1886 [SLAVE_NPU_COMPUTE_NOC] = &qns_npu_sys, 1887 [SLAVE_SERVICE_NPU_NOC] = &srvc_noc, 1888 }; 1889 1890 static const struct qcom_icc_desc sm6350_npu_noc = { 1891 .nodes = npu_noc_nodes, 1892 .num_nodes = ARRAY_SIZE(npu_noc_nodes), 1893 }; 1894 1895 static struct qcom_icc_bcm * const system_noc_bcms[] = { 1896 &bcm_sn0, 1897 &bcm_sn1, 1898 &bcm_sn10, 1899 &bcm_sn2, 1900 &bcm_sn3, 1901 &bcm_sn4, 1902 &bcm_sn5, 1903 &bcm_sn6, 1904 }; 1905 1906 static struct qcom_icc_node * const system_noc_nodes[] = { 1907 [MASTER_SNOC_CFG] = &qhm_snoc_cfg, 1908 [A1NOC_SNOC_MAS] = &qnm_aggre1_noc, 1909 [A2NOC_SNOC_MAS] = &qnm_aggre2_noc, 1910 [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc, 1911 [MASTER_PIMEM] = &qxm_pimem, 1912 [MASTER_GIC] = &xm_gic, 1913 [SLAVE_APPSS] = &qhs_apss, 1914 [SNOC_CNOC_SLV] = &qns_cnoc, 1915 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, 1916 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 1917 [SLAVE_OCIMEM] = &qxs_imem, 1918 [SLAVE_PIMEM] = &qxs_pimem, 1919 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 1920 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1921 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1922 }; 1923 1924 static const struct regmap_config sm6350_system_noc_regmap_config = { 1925 .reg_bits = 32, 1926 .reg_stride = 4, 1927 .val_bits = 32, 1928 .max_register = 0x17080, 1929 .fast_io = true, 1930 }; 1931 1932 static const struct qcom_icc_desc sm6350_system_noc = { 1933 .config = &sm6350_system_noc_regmap_config, 1934 .nodes = system_noc_nodes, 1935 .num_nodes = ARRAY_SIZE(system_noc_nodes), 1936 .bcms = system_noc_bcms, 1937 .num_bcms = ARRAY_SIZE(system_noc_bcms), 1938 }; 1939 1940 static const struct of_device_id qnoc_of_match[] = { 1941 { .compatible = "qcom,sm6350-aggre1-noc", 1942 .data = &sm6350_aggre1_noc}, 1943 { .compatible = "qcom,sm6350-aggre2-noc", 1944 .data = &sm6350_aggre2_noc}, 1945 { .compatible = "qcom,sm6350-clk-virt", 1946 .data = &sm6350_clk_virt}, 1947 { .compatible = "qcom,sm6350-compute-noc", 1948 .data = &sm6350_compute_noc}, 1949 { .compatible = "qcom,sm6350-config-noc", 1950 .data = &sm6350_config_noc}, 1951 { .compatible = "qcom,sm6350-dc-noc", 1952 .data = &sm6350_dc_noc}, 1953 { .compatible = "qcom,sm6350-gem-noc", 1954 .data = &sm6350_gem_noc}, 1955 { .compatible = "qcom,sm6350-mmss-noc", 1956 .data = &sm6350_mmss_noc}, 1957 { .compatible = "qcom,sm6350-npu-noc", 1958 .data = &sm6350_npu_noc}, 1959 { .compatible = "qcom,sm6350-system-noc", 1960 .data = &sm6350_system_noc}, 1961 { } 1962 }; 1963 MODULE_DEVICE_TABLE(of, qnoc_of_match); 1964 1965 static struct platform_driver qnoc_driver = { 1966 .probe = qcom_icc_rpmh_probe, 1967 .remove = qcom_icc_rpmh_remove, 1968 .driver = { 1969 .name = "qnoc-sm6350", 1970 .of_match_table = qnoc_of_match, 1971 .sync_state = icc_sync_state, 1972 }, 1973 }; 1974 module_platform_driver(qnoc_driver); 1975 1976 MODULE_DESCRIPTION("Qualcomm SM6350 NoC driver"); 1977 MODULE_LICENSE("GPL v2"); 1978