1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 5 * Copyright (c) 2023, Linaro Limited 6 */ 7 8 #include <dt-bindings/interconnect/qcom,sm6115.h> 9 #include <linux/device.h> 10 #include <linux/interconnect-provider.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 15 #include "icc-rpm.h" 16 17 static const char * const snoc_intf_clocks[] = { 18 "cpu_axi", 19 "ufs_axi", 20 "usb_axi", 21 "ipa", /* Required by qxm_ipa */ 22 }; 23 24 static const char * const cnoc_intf_clocks[] = { 25 "usb_axi", 26 }; 27 28 enum { 29 SM6115_MASTER_AMPSS_M0, 30 SM6115_MASTER_ANOC_SNOC, 31 SM6115_MASTER_BIMC_SNOC, 32 SM6115_MASTER_CAMNOC_HF, 33 SM6115_MASTER_CAMNOC_SF, 34 SM6115_MASTER_CRYPTO_CORE0, 35 SM6115_MASTER_GRAPHICS_3D, 36 SM6115_MASTER_IPA, 37 SM6115_MASTER_MDP_PORT0, 38 SM6115_MASTER_PIMEM, 39 SM6115_MASTER_QDSS_BAM, 40 SM6115_MASTER_QDSS_DAP, 41 SM6115_MASTER_QDSS_ETR, 42 SM6115_MASTER_QPIC, 43 SM6115_MASTER_QUP_0, 44 SM6115_MASTER_QUP_CORE_0, 45 SM6115_MASTER_SDCC_1, 46 SM6115_MASTER_SDCC_2, 47 SM6115_MASTER_SNOC_BIMC_NRT, 48 SM6115_MASTER_SNOC_BIMC_RT, 49 SM6115_MASTER_SNOC_BIMC, 50 SM6115_MASTER_SNOC_CFG, 51 SM6115_MASTER_SNOC_CNOC, 52 SM6115_MASTER_TCU_0, 53 SM6115_MASTER_TIC, 54 SM6115_MASTER_USB3, 55 SM6115_MASTER_VIDEO_P0, 56 SM6115_MASTER_VIDEO_PROC, 57 58 SM6115_SLAVE_AHB2PHY_USB, 59 SM6115_SLAVE_ANOC_SNOC, 60 SM6115_SLAVE_APPSS, 61 SM6115_SLAVE_APSS_THROTTLE_CFG, 62 SM6115_SLAVE_BIMC_CFG, 63 SM6115_SLAVE_BIMC_SNOC, 64 SM6115_SLAVE_BOOT_ROM, 65 SM6115_SLAVE_CAMERA_CFG, 66 SM6115_SLAVE_CAMERA_NRT_THROTTLE_CFG, 67 SM6115_SLAVE_CAMERA_RT_THROTTLE_CFG, 68 SM6115_SLAVE_CLK_CTL, 69 SM6115_SLAVE_CNOC_MSS, 70 SM6115_SLAVE_CRYPTO_0_CFG, 71 SM6115_SLAVE_DCC_CFG, 72 SM6115_SLAVE_DDR_PHY_CFG, 73 SM6115_SLAVE_DDR_SS_CFG, 74 SM6115_SLAVE_DISPLAY_CFG, 75 SM6115_SLAVE_DISPLAY_THROTTLE_CFG, 76 SM6115_SLAVE_EBI_CH0, 77 SM6115_SLAVE_GPU_CFG, 78 SM6115_SLAVE_GPU_THROTTLE_CFG, 79 SM6115_SLAVE_HWKM_CORE, 80 SM6115_SLAVE_IMEM_CFG, 81 SM6115_SLAVE_IPA_CFG, 82 SM6115_SLAVE_LPASS, 83 SM6115_SLAVE_MAPSS, 84 SM6115_SLAVE_MDSP_MPU_CFG, 85 SM6115_SLAVE_MESSAGE_RAM, 86 SM6115_SLAVE_OCIMEM, 87 SM6115_SLAVE_PDM, 88 SM6115_SLAVE_PIMEM_CFG, 89 SM6115_SLAVE_PIMEM, 90 SM6115_SLAVE_PKA_CORE, 91 SM6115_SLAVE_PMIC_ARB, 92 SM6115_SLAVE_QDSS_CFG, 93 SM6115_SLAVE_QDSS_STM, 94 SM6115_SLAVE_QM_CFG, 95 SM6115_SLAVE_QM_MPU_CFG, 96 SM6115_SLAVE_QPIC, 97 SM6115_SLAVE_QUP_0, 98 SM6115_SLAVE_QUP_CORE_0, 99 SM6115_SLAVE_RBCPR_CX_CFG, 100 SM6115_SLAVE_RBCPR_MX_CFG, 101 SM6115_SLAVE_RPM, 102 SM6115_SLAVE_SDCC_1, 103 SM6115_SLAVE_SDCC_2, 104 SM6115_SLAVE_SECURITY, 105 SM6115_SLAVE_SERVICE_CNOC, 106 SM6115_SLAVE_SERVICE_SNOC, 107 SM6115_SLAVE_SNOC_BIMC_NRT, 108 SM6115_SLAVE_SNOC_BIMC_RT, 109 SM6115_SLAVE_SNOC_BIMC, 110 SM6115_SLAVE_SNOC_CFG, 111 SM6115_SLAVE_SNOC_CNOC, 112 SM6115_SLAVE_TCSR, 113 SM6115_SLAVE_TCU, 114 SM6115_SLAVE_TLMM, 115 SM6115_SLAVE_USB3, 116 SM6115_SLAVE_VENUS_CFG, 117 SM6115_SLAVE_VENUS_THROTTLE_CFG, 118 SM6115_SLAVE_VSENSE_CTRL_CFG, 119 }; 120 121 static const u16 slv_ebi_slv_bimc_snoc_links[] = { 122 SM6115_SLAVE_EBI_CH0, 123 SM6115_SLAVE_BIMC_SNOC, 124 }; 125 126 static struct qcom_icc_node apps_proc = { 127 .name = "apps_proc", 128 .id = SM6115_MASTER_AMPSS_M0, 129 .channels = 1, 130 .buswidth = 16, 131 .qos.qos_port = 0, 132 .qos.qos_mode = NOC_QOS_MODE_FIXED, 133 .qos.prio_level = 0, 134 .qos.areq_prio = 0, 135 .mas_rpm_id = 0, 136 .slv_rpm_id = -1, 137 .num_links = ARRAY_SIZE(slv_ebi_slv_bimc_snoc_links), 138 .links = slv_ebi_slv_bimc_snoc_links, 139 }; 140 141 static const u16 link_slv_ebi[] = { 142 SM6115_SLAVE_EBI_CH0, 143 }; 144 145 static struct qcom_icc_node mas_snoc_bimc_rt = { 146 .name = "mas_snoc_bimc_rt", 147 .id = SM6115_MASTER_SNOC_BIMC_RT, 148 .channels = 1, 149 .buswidth = 16, 150 .qos.qos_port = 2, 151 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 152 .qos.areq_prio = 0, 153 .qos.prio_level = 0, 154 .mas_rpm_id = -1, 155 .slv_rpm_id = -1, 156 .num_links = ARRAY_SIZE(link_slv_ebi), 157 .links = link_slv_ebi, 158 }; 159 160 static struct qcom_icc_node mas_snoc_bimc_nrt = { 161 .name = "mas_snoc_bimc_nrt", 162 .id = SM6115_MASTER_SNOC_BIMC_NRT, 163 .channels = 1, 164 .buswidth = 16, 165 .qos.qos_port = 3, 166 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 167 .qos.areq_prio = 0, 168 .qos.prio_level = 0, 169 .mas_rpm_id = -1, 170 .slv_rpm_id = -1, 171 .num_links = ARRAY_SIZE(link_slv_ebi), 172 .links = link_slv_ebi, 173 }; 174 175 static struct qcom_icc_node mas_snoc_bimc = { 176 .name = "mas_snoc_bimc", 177 .id = SM6115_MASTER_SNOC_BIMC, 178 .channels = 1, 179 .buswidth = 16, 180 .qos.qos_port = 6, 181 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 182 .qos.areq_prio = 0, 183 .qos.prio_level = 0, 184 .mas_rpm_id = 3, 185 .slv_rpm_id = -1, 186 .num_links = ARRAY_SIZE(link_slv_ebi), 187 .links = link_slv_ebi, 188 }; 189 190 static struct qcom_icc_node qnm_gpu = { 191 .name = "qnm_gpu", 192 .id = SM6115_MASTER_GRAPHICS_3D, 193 .channels = 1, 194 .buswidth = 32, 195 .qos.qos_port = 1, 196 .qos.qos_mode = NOC_QOS_MODE_FIXED, 197 .qos.prio_level = 0, 198 .qos.areq_prio = 0, 199 .mas_rpm_id = -1, 200 .slv_rpm_id = -1, 201 .num_links = ARRAY_SIZE(slv_ebi_slv_bimc_snoc_links), 202 .links = slv_ebi_slv_bimc_snoc_links, 203 }; 204 205 static struct qcom_icc_node tcu_0 = { 206 .name = "tcu_0", 207 .id = SM6115_MASTER_TCU_0, 208 .channels = 1, 209 .buswidth = 8, 210 .qos.qos_port = 4, 211 .qos.qos_mode = NOC_QOS_MODE_FIXED, 212 .qos.prio_level = 6, 213 .qos.areq_prio = 6, 214 .mas_rpm_id = -1, 215 .slv_rpm_id = -1, 216 .num_links = ARRAY_SIZE(slv_ebi_slv_bimc_snoc_links), 217 .links = slv_ebi_slv_bimc_snoc_links, 218 }; 219 220 static const u16 qup_core_0_links[] = { 221 SM6115_SLAVE_QUP_CORE_0, 222 }; 223 224 static struct qcom_icc_node qup0_core_master = { 225 .name = "qup0_core_master", 226 .id = SM6115_MASTER_QUP_CORE_0, 227 .channels = 1, 228 .buswidth = 4, 229 .mas_rpm_id = 170, 230 .slv_rpm_id = -1, 231 .num_links = ARRAY_SIZE(qup_core_0_links), 232 .links = qup_core_0_links, 233 }; 234 235 static const u16 link_slv_anoc_snoc[] = { 236 SM6115_SLAVE_ANOC_SNOC, 237 }; 238 239 static struct qcom_icc_node crypto_c0 = { 240 .name = "crypto_c0", 241 .id = SM6115_MASTER_CRYPTO_CORE0, 242 .channels = 1, 243 .buswidth = 8, 244 .qos.qos_port = 22, 245 .qos.qos_mode = NOC_QOS_MODE_FIXED, 246 .qos.areq_prio = 2, 247 .mas_rpm_id = 23, 248 .slv_rpm_id = -1, 249 .num_links = ARRAY_SIZE(link_slv_anoc_snoc), 250 .links = link_slv_anoc_snoc, 251 }; 252 253 static const u16 mas_snoc_cnoc_links[] = { 254 SM6115_SLAVE_AHB2PHY_USB, 255 SM6115_SLAVE_APSS_THROTTLE_CFG, 256 SM6115_SLAVE_BIMC_CFG, 257 SM6115_SLAVE_BOOT_ROM, 258 SM6115_SLAVE_CAMERA_CFG, 259 SM6115_SLAVE_CAMERA_NRT_THROTTLE_CFG, 260 SM6115_SLAVE_CAMERA_RT_THROTTLE_CFG, 261 SM6115_SLAVE_CLK_CTL, 262 SM6115_SLAVE_CNOC_MSS, 263 SM6115_SLAVE_CRYPTO_0_CFG, 264 SM6115_SLAVE_DCC_CFG, 265 SM6115_SLAVE_DDR_PHY_CFG, 266 SM6115_SLAVE_DDR_SS_CFG, 267 SM6115_SLAVE_DISPLAY_CFG, 268 SM6115_SLAVE_DISPLAY_THROTTLE_CFG, 269 SM6115_SLAVE_GPU_CFG, 270 SM6115_SLAVE_GPU_THROTTLE_CFG, 271 SM6115_SLAVE_HWKM_CORE, 272 SM6115_SLAVE_IMEM_CFG, 273 SM6115_SLAVE_IPA_CFG, 274 SM6115_SLAVE_LPASS, 275 SM6115_SLAVE_MAPSS, 276 SM6115_SLAVE_MDSP_MPU_CFG, 277 SM6115_SLAVE_MESSAGE_RAM, 278 SM6115_SLAVE_PDM, 279 SM6115_SLAVE_PIMEM_CFG, 280 SM6115_SLAVE_PKA_CORE, 281 SM6115_SLAVE_PMIC_ARB, 282 SM6115_SLAVE_QDSS_CFG, 283 SM6115_SLAVE_QM_CFG, 284 SM6115_SLAVE_QM_MPU_CFG, 285 SM6115_SLAVE_QPIC, 286 SM6115_SLAVE_QUP_0, 287 SM6115_SLAVE_RBCPR_CX_CFG, 288 SM6115_SLAVE_RBCPR_MX_CFG, 289 SM6115_SLAVE_RPM, 290 SM6115_SLAVE_SDCC_1, 291 SM6115_SLAVE_SDCC_2, 292 SM6115_SLAVE_SECURITY, 293 SM6115_SLAVE_SERVICE_CNOC, 294 SM6115_SLAVE_SNOC_CFG, 295 SM6115_SLAVE_TCSR, 296 SM6115_SLAVE_TLMM, 297 SM6115_SLAVE_USB3, 298 SM6115_SLAVE_VENUS_CFG, 299 SM6115_SLAVE_VENUS_THROTTLE_CFG, 300 SM6115_SLAVE_VSENSE_CTRL_CFG, 301 }; 302 303 static struct qcom_icc_node mas_snoc_cnoc = { 304 .name = "mas_snoc_cnoc", 305 .id = SM6115_MASTER_SNOC_CNOC, 306 .channels = 1, 307 .buswidth = 8, 308 .mas_rpm_id = -1, 309 .slv_rpm_id = -1, 310 .num_links = ARRAY_SIZE(mas_snoc_cnoc_links), 311 .links = mas_snoc_cnoc_links, 312 }; 313 314 static struct qcom_icc_node xm_dap = { 315 .name = "xm_dap", 316 .id = SM6115_MASTER_QDSS_DAP, 317 .channels = 1, 318 .buswidth = 8, 319 .mas_rpm_id = -1, 320 .slv_rpm_id = -1, 321 .num_links = ARRAY_SIZE(mas_snoc_cnoc_links), 322 .links = mas_snoc_cnoc_links, 323 }; 324 325 static const u16 link_slv_snoc_bimc_nrt[] = { 326 SM6115_SLAVE_SNOC_BIMC_NRT, 327 }; 328 329 static struct qcom_icc_node qnm_camera_nrt = { 330 .name = "qnm_camera_nrt", 331 .id = SM6115_MASTER_CAMNOC_SF, 332 .channels = 1, 333 .buswidth = 32, 334 .qos.qos_port = 4, 335 .qos.qos_mode = NOC_QOS_MODE_FIXED, 336 .qos.areq_prio = 3, 337 .mas_rpm_id = -1, 338 .slv_rpm_id = -1, 339 .num_links = ARRAY_SIZE(link_slv_snoc_bimc_nrt), 340 .links = link_slv_snoc_bimc_nrt, 341 }; 342 343 static struct qcom_icc_node qxm_venus0 = { 344 .name = "qxm_venus0", 345 .id = SM6115_MASTER_VIDEO_P0, 346 .channels = 1, 347 .buswidth = 16, 348 .qos.qos_port = 9, 349 .qos.qos_mode = NOC_QOS_MODE_FIXED, 350 .qos.areq_prio = 3, 351 .qos.urg_fwd_en = true, 352 .mas_rpm_id = -1, 353 .slv_rpm_id = -1, 354 .num_links = ARRAY_SIZE(link_slv_snoc_bimc_nrt), 355 .links = link_slv_snoc_bimc_nrt, 356 }; 357 358 static struct qcom_icc_node qxm_venus_cpu = { 359 .name = "qxm_venus_cpu", 360 .id = SM6115_MASTER_VIDEO_PROC, 361 .channels = 1, 362 .buswidth = 8, 363 .qos.qos_port = 13, 364 .qos.qos_mode = NOC_QOS_MODE_FIXED, 365 .qos.areq_prio = 4, 366 .mas_rpm_id = -1, 367 .slv_rpm_id = -1, 368 .num_links = ARRAY_SIZE(link_slv_snoc_bimc_nrt), 369 .links = link_slv_snoc_bimc_nrt, 370 }; 371 372 static const u16 link_slv_snoc_bimc_rt[] = { 373 SM6115_SLAVE_SNOC_BIMC_RT, 374 }; 375 376 static struct qcom_icc_node qnm_camera_rt = { 377 .name = "qnm_camera_rt", 378 .id = SM6115_MASTER_CAMNOC_HF, 379 .channels = 1, 380 .buswidth = 32, 381 .qos.qos_port = 10, 382 .qos.qos_mode = NOC_QOS_MODE_FIXED, 383 .qos.areq_prio = 3, 384 .qos.urg_fwd_en = true, 385 .mas_rpm_id = -1, 386 .slv_rpm_id = -1, 387 .num_links = ARRAY_SIZE(link_slv_snoc_bimc_rt), 388 .links = link_slv_snoc_bimc_rt, 389 }; 390 391 static struct qcom_icc_node qxm_mdp0 = { 392 .name = "qxm_mdp0", 393 .id = SM6115_MASTER_MDP_PORT0, 394 .channels = 1, 395 .buswidth = 16, 396 .qos.qos_port = 5, 397 .qos.qos_mode = NOC_QOS_MODE_FIXED, 398 .qos.areq_prio = 3, 399 .qos.urg_fwd_en = true, 400 .mas_rpm_id = -1, 401 .slv_rpm_id = -1, 402 .num_links = ARRAY_SIZE(link_slv_snoc_bimc_rt), 403 .links = link_slv_snoc_bimc_rt, 404 }; 405 406 static const u16 slv_service_snoc_links[] = { 407 SM6115_SLAVE_SERVICE_SNOC, 408 }; 409 410 static struct qcom_icc_node qhm_snoc_cfg = { 411 .name = "qhm_snoc_cfg", 412 .id = SM6115_MASTER_SNOC_CFG, 413 .channels = 1, 414 .buswidth = 4, 415 .mas_rpm_id = -1, 416 .slv_rpm_id = -1, 417 .num_links = ARRAY_SIZE(slv_service_snoc_links), 418 .links = slv_service_snoc_links, 419 }; 420 421 static const u16 mas_tic_links[] = { 422 SM6115_SLAVE_APPSS, 423 SM6115_SLAVE_OCIMEM, 424 SM6115_SLAVE_PIMEM, 425 SM6115_SLAVE_QDSS_STM, 426 SM6115_SLAVE_TCU, 427 SM6115_SLAVE_SNOC_BIMC, 428 SM6115_SLAVE_SNOC_CNOC, 429 }; 430 431 static struct qcom_icc_node qhm_tic = { 432 .name = "qhm_tic", 433 .id = SM6115_MASTER_TIC, 434 .channels = 1, 435 .buswidth = 4, 436 .qos.qos_port = 8, 437 .qos.qos_mode = NOC_QOS_MODE_FIXED, 438 .qos.areq_prio = 2, 439 .mas_rpm_id = -1, 440 .slv_rpm_id = -1, 441 .num_links = ARRAY_SIZE(mas_tic_links), 442 .links = mas_tic_links, 443 }; 444 445 static struct qcom_icc_node mas_anoc_snoc = { 446 .name = "mas_anoc_snoc", 447 .id = SM6115_MASTER_ANOC_SNOC, 448 .channels = 1, 449 .buswidth = 16, 450 .mas_rpm_id = -1, 451 .slv_rpm_id = -1, 452 .num_links = ARRAY_SIZE(mas_tic_links), 453 .links = mas_tic_links, 454 }; 455 456 static const u16 mas_bimc_snoc_links[] = { 457 SM6115_SLAVE_APPSS, 458 SM6115_SLAVE_SNOC_CNOC, 459 SM6115_SLAVE_OCIMEM, 460 SM6115_SLAVE_PIMEM, 461 SM6115_SLAVE_QDSS_STM, 462 SM6115_SLAVE_TCU, 463 }; 464 465 static struct qcom_icc_node mas_bimc_snoc = { 466 .name = "mas_bimc_snoc", 467 .id = SM6115_MASTER_BIMC_SNOC, 468 .channels = 1, 469 .buswidth = 8, 470 .mas_rpm_id = 21, 471 .slv_rpm_id = -1, 472 .num_links = ARRAY_SIZE(mas_bimc_snoc_links), 473 .links = mas_bimc_snoc_links, 474 }; 475 476 static const u16 mas_pimem_links[] = { 477 SM6115_SLAVE_OCIMEM, 478 SM6115_SLAVE_SNOC_BIMC, 479 }; 480 481 static struct qcom_icc_node qxm_pimem = { 482 .name = "qxm_pimem", 483 .id = SM6115_MASTER_PIMEM, 484 .channels = 1, 485 .buswidth = 8, 486 .qos.qos_port = 20, 487 .qos.qos_mode = NOC_QOS_MODE_FIXED, 488 .qos.areq_prio = 2, 489 .mas_rpm_id = -1, 490 .slv_rpm_id = -1, 491 .num_links = ARRAY_SIZE(mas_pimem_links), 492 .links = mas_pimem_links, 493 }; 494 495 static struct qcom_icc_node qhm_qdss_bam = { 496 .name = "qhm_qdss_bam", 497 .id = SM6115_MASTER_QDSS_BAM, 498 .channels = 1, 499 .buswidth = 4, 500 .qos.qos_port = 2, 501 .qos.qos_mode = NOC_QOS_MODE_FIXED, 502 .qos.areq_prio = 2, 503 .mas_rpm_id = -1, 504 .slv_rpm_id = -1, 505 .num_links = ARRAY_SIZE(link_slv_anoc_snoc), 506 .links = link_slv_anoc_snoc, 507 }; 508 509 static struct qcom_icc_node qhm_qpic = { 510 .name = "qhm_qpic", 511 .id = SM6115_MASTER_QPIC, 512 .channels = 1, 513 .buswidth = 4, 514 .mas_rpm_id = -1, 515 .slv_rpm_id = -1, 516 .num_links = ARRAY_SIZE(link_slv_anoc_snoc), 517 .links = link_slv_anoc_snoc, 518 }; 519 520 static struct qcom_icc_node qhm_qup0 = { 521 .name = "qhm_qup0", 522 .id = SM6115_MASTER_QUP_0, 523 .channels = 1, 524 .buswidth = 4, 525 .qos.qos_port = 0, 526 .qos.qos_mode = NOC_QOS_MODE_FIXED, 527 .qos.areq_prio = 2, 528 .mas_rpm_id = 166, 529 .slv_rpm_id = -1, 530 .num_links = ARRAY_SIZE(link_slv_anoc_snoc), 531 .links = link_slv_anoc_snoc, 532 }; 533 534 static struct qcom_icc_node qxm_ipa = { 535 .name = "qxm_ipa", 536 .id = SM6115_MASTER_IPA, 537 .channels = 1, 538 .buswidth = 8, 539 .qos.qos_port = 3, 540 .qos.qos_mode = NOC_QOS_MODE_FIXED, 541 .qos.areq_prio = 2, 542 .mas_rpm_id = 59, 543 .slv_rpm_id = -1, 544 .num_links = ARRAY_SIZE(link_slv_anoc_snoc), 545 .links = link_slv_anoc_snoc, 546 }; 547 548 static struct qcom_icc_node xm_qdss_etr = { 549 .name = "xm_qdss_etr", 550 .id = SM6115_MASTER_QDSS_ETR, 551 .channels = 1, 552 .buswidth = 8, 553 .qos.qos_port = 12, 554 .qos.qos_mode = NOC_QOS_MODE_FIXED, 555 .qos.areq_prio = 2, 556 .mas_rpm_id = -1, 557 .slv_rpm_id = -1, 558 .num_links = ARRAY_SIZE(link_slv_anoc_snoc), 559 .links = link_slv_anoc_snoc, 560 }; 561 562 static struct qcom_icc_node xm_sdc1 = { 563 .name = "xm_sdc1", 564 .id = SM6115_MASTER_SDCC_1, 565 .channels = 1, 566 .buswidth = 8, 567 .qos.qos_port = 17, 568 .qos.qos_mode = NOC_QOS_MODE_FIXED, 569 .qos.areq_prio = 2, 570 .mas_rpm_id = 33, 571 .slv_rpm_id = -1, 572 .num_links = ARRAY_SIZE(link_slv_anoc_snoc), 573 .links = link_slv_anoc_snoc, 574 }; 575 576 static struct qcom_icc_node xm_sdc2 = { 577 .name = "xm_sdc2", 578 .id = SM6115_MASTER_SDCC_2, 579 .channels = 1, 580 .buswidth = 8, 581 .qos.qos_port = 23, 582 .qos.qos_mode = NOC_QOS_MODE_FIXED, 583 .qos.areq_prio = 2, 584 .mas_rpm_id = 35, 585 .slv_rpm_id = -1, 586 .num_links = ARRAY_SIZE(link_slv_anoc_snoc), 587 .links = link_slv_anoc_snoc, 588 }; 589 590 static struct qcom_icc_node xm_usb3_0 = { 591 .name = "xm_usb3_0", 592 .id = SM6115_MASTER_USB3, 593 .channels = 1, 594 .buswidth = 8, 595 .qos.qos_port = 24, 596 .qos.qos_mode = NOC_QOS_MODE_FIXED, 597 .qos.areq_prio = 2, 598 .mas_rpm_id = -1, 599 .slv_rpm_id = -1, 600 .num_links = ARRAY_SIZE(link_slv_anoc_snoc), 601 .links = link_slv_anoc_snoc, 602 }; 603 604 static struct qcom_icc_node ebi = { 605 .name = "ebi", 606 .id = SM6115_SLAVE_EBI_CH0, 607 .channels = 2, 608 .buswidth = 4, 609 .mas_rpm_id = -1, 610 .slv_rpm_id = 0, 611 }; 612 613 static const u16 slv_bimc_snoc_links[] = { 614 SM6115_MASTER_BIMC_SNOC, 615 }; 616 617 static struct qcom_icc_node slv_bimc_snoc = { 618 .name = "slv_bimc_snoc", 619 .id = SM6115_SLAVE_BIMC_SNOC, 620 .channels = 1, 621 .buswidth = 16, 622 .mas_rpm_id = -1, 623 .slv_rpm_id = 2, 624 .num_links = ARRAY_SIZE(slv_bimc_snoc_links), 625 .links = slv_bimc_snoc_links, 626 }; 627 628 static struct qcom_icc_node qup0_core_slave = { 629 .name = "qup0_core_slave", 630 .id = SM6115_SLAVE_QUP_CORE_0, 631 .channels = 1, 632 .buswidth = 4, 633 .mas_rpm_id = -1, 634 .slv_rpm_id = -1, 635 }; 636 637 static struct qcom_icc_node qhs_ahb2phy_usb = { 638 .name = "qhs_ahb2phy_usb", 639 .id = SM6115_SLAVE_AHB2PHY_USB, 640 .channels = 1, 641 .buswidth = 4, 642 .mas_rpm_id = -1, 643 .slv_rpm_id = -1, 644 }; 645 646 static struct qcom_icc_node qhs_apss_throttle_cfg = { 647 .name = "qhs_apss_throttle_cfg", 648 .id = SM6115_SLAVE_APSS_THROTTLE_CFG, 649 .channels = 1, 650 .buswidth = 4, 651 .mas_rpm_id = -1, 652 .slv_rpm_id = -1, 653 }; 654 655 static struct qcom_icc_node qhs_bimc_cfg = { 656 .name = "qhs_bimc_cfg", 657 .id = SM6115_SLAVE_BIMC_CFG, 658 .channels = 1, 659 .buswidth = 4, 660 .mas_rpm_id = -1, 661 .slv_rpm_id = -1, 662 }; 663 664 static struct qcom_icc_node qhs_boot_rom = { 665 .name = "qhs_boot_rom", 666 .id = SM6115_SLAVE_BOOT_ROM, 667 .channels = 1, 668 .buswidth = 4, 669 .mas_rpm_id = -1, 670 .slv_rpm_id = -1, 671 }; 672 673 static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = { 674 .name = "qhs_camera_nrt_throttle_cfg", 675 .id = SM6115_SLAVE_CAMERA_NRT_THROTTLE_CFG, 676 .channels = 1, 677 .buswidth = 4, 678 .mas_rpm_id = -1, 679 .slv_rpm_id = -1, 680 }; 681 682 static struct qcom_icc_node qhs_camera_rt_throttle_cfg = { 683 .name = "qhs_camera_rt_throttle_cfg", 684 .id = SM6115_SLAVE_CAMERA_RT_THROTTLE_CFG, 685 .channels = 1, 686 .buswidth = 4, 687 .mas_rpm_id = -1, 688 .slv_rpm_id = -1, 689 }; 690 691 static struct qcom_icc_node qhs_camera_ss_cfg = { 692 .name = "qhs_camera_ss_cfg", 693 .id = SM6115_SLAVE_CAMERA_CFG, 694 .channels = 1, 695 .buswidth = 4, 696 .mas_rpm_id = -1, 697 .slv_rpm_id = -1, 698 }; 699 700 static struct qcom_icc_node qhs_clk_ctl = { 701 .name = "qhs_clk_ctl", 702 .id = SM6115_SLAVE_CLK_CTL, 703 .channels = 1, 704 .buswidth = 4, 705 .mas_rpm_id = -1, 706 .slv_rpm_id = -1, 707 }; 708 709 static struct qcom_icc_node qhs_cpr_cx = { 710 .name = "qhs_cpr_cx", 711 .id = SM6115_SLAVE_RBCPR_CX_CFG, 712 .channels = 1, 713 .buswidth = 4, 714 .mas_rpm_id = -1, 715 .slv_rpm_id = -1, 716 }; 717 718 static struct qcom_icc_node qhs_cpr_mx = { 719 .name = "qhs_cpr_mx", 720 .id = SM6115_SLAVE_RBCPR_MX_CFG, 721 .channels = 1, 722 .buswidth = 4, 723 .mas_rpm_id = -1, 724 .slv_rpm_id = -1, 725 }; 726 727 static struct qcom_icc_node qhs_crypto0_cfg = { 728 .name = "qhs_crypto0_cfg", 729 .id = SM6115_SLAVE_CRYPTO_0_CFG, 730 .channels = 1, 731 .buswidth = 4, 732 .mas_rpm_id = -1, 733 .slv_rpm_id = -1, 734 }; 735 736 static struct qcom_icc_node qhs_dcc_cfg = { 737 .name = "qhs_dcc_cfg", 738 .id = SM6115_SLAVE_DCC_CFG, 739 .channels = 1, 740 .buswidth = 4, 741 .mas_rpm_id = -1, 742 .slv_rpm_id = -1, 743 }; 744 745 static struct qcom_icc_node qhs_ddr_phy_cfg = { 746 .name = "qhs_ddr_phy_cfg", 747 .id = SM6115_SLAVE_DDR_PHY_CFG, 748 .channels = 1, 749 .buswidth = 4, 750 .mas_rpm_id = -1, 751 .slv_rpm_id = -1, 752 }; 753 754 static struct qcom_icc_node qhs_ddr_ss_cfg = { 755 .name = "qhs_ddr_ss_cfg", 756 .id = SM6115_SLAVE_DDR_SS_CFG, 757 .channels = 1, 758 .buswidth = 4, 759 .mas_rpm_id = -1, 760 .slv_rpm_id = -1, 761 }; 762 763 static struct qcom_icc_node qhs_disp_ss_cfg = { 764 .name = "qhs_disp_ss_cfg", 765 .id = SM6115_SLAVE_DISPLAY_CFG, 766 .channels = 1, 767 .buswidth = 4, 768 .mas_rpm_id = -1, 769 .slv_rpm_id = -1, 770 }; 771 772 static struct qcom_icc_node qhs_display_throttle_cfg = { 773 .name = "qhs_display_throttle_cfg", 774 .id = SM6115_SLAVE_DISPLAY_THROTTLE_CFG, 775 .channels = 1, 776 .buswidth = 4, 777 .mas_rpm_id = -1, 778 .slv_rpm_id = -1, 779 }; 780 781 static struct qcom_icc_node qhs_gpu_cfg = { 782 .name = "qhs_gpu_cfg", 783 .id = SM6115_SLAVE_GPU_CFG, 784 .channels = 1, 785 .buswidth = 8, 786 .mas_rpm_id = -1, 787 .slv_rpm_id = -1, 788 }; 789 790 static struct qcom_icc_node qhs_gpu_throttle_cfg = { 791 .name = "qhs_gpu_throttle_cfg", 792 .id = SM6115_SLAVE_GPU_THROTTLE_CFG, 793 .channels = 1, 794 .buswidth = 4, 795 .mas_rpm_id = -1, 796 .slv_rpm_id = -1, 797 }; 798 799 static struct qcom_icc_node qhs_hwkm = { 800 .name = "qhs_hwkm", 801 .id = SM6115_SLAVE_HWKM_CORE, 802 .channels = 1, 803 .buswidth = 4, 804 .mas_rpm_id = -1, 805 .slv_rpm_id = -1, 806 }; 807 808 static struct qcom_icc_node qhs_imem_cfg = { 809 .name = "qhs_imem_cfg", 810 .id = SM6115_SLAVE_IMEM_CFG, 811 .channels = 1, 812 .buswidth = 4, 813 .mas_rpm_id = -1, 814 .slv_rpm_id = -1, 815 }; 816 817 static struct qcom_icc_node qhs_ipa_cfg = { 818 .name = "qhs_ipa_cfg", 819 .id = SM6115_SLAVE_IPA_CFG, 820 .channels = 1, 821 .buswidth = 4, 822 .mas_rpm_id = -1, 823 .slv_rpm_id = -1, 824 }; 825 826 static struct qcom_icc_node qhs_lpass = { 827 .name = "qhs_lpass", 828 .id = SM6115_SLAVE_LPASS, 829 .channels = 1, 830 .buswidth = 4, 831 .mas_rpm_id = -1, 832 .slv_rpm_id = -1, 833 }; 834 835 static struct qcom_icc_node qhs_mapss = { 836 .name = "qhs_mapss", 837 .id = SM6115_SLAVE_MAPSS, 838 .channels = 1, 839 .buswidth = 4, 840 .mas_rpm_id = -1, 841 .slv_rpm_id = -1, 842 }; 843 844 static struct qcom_icc_node qhs_mdsp_mpu_cfg = { 845 .name = "qhs_mdsp_mpu_cfg", 846 .id = SM6115_SLAVE_MDSP_MPU_CFG, 847 .channels = 1, 848 .buswidth = 4, 849 .mas_rpm_id = -1, 850 .slv_rpm_id = -1, 851 }; 852 853 static struct qcom_icc_node qhs_mesg_ram = { 854 .name = "qhs_mesg_ram", 855 .id = SM6115_SLAVE_MESSAGE_RAM, 856 .channels = 1, 857 .buswidth = 4, 858 .mas_rpm_id = -1, 859 .slv_rpm_id = -1, 860 }; 861 862 static struct qcom_icc_node qhs_mss = { 863 .name = "qhs_mss", 864 .id = SM6115_SLAVE_CNOC_MSS, 865 .channels = 1, 866 .buswidth = 4, 867 .mas_rpm_id = -1, 868 .slv_rpm_id = -1, 869 }; 870 871 static struct qcom_icc_node qhs_pdm = { 872 .name = "qhs_pdm", 873 .id = SM6115_SLAVE_PDM, 874 .channels = 1, 875 .buswidth = 4, 876 .mas_rpm_id = -1, 877 .slv_rpm_id = -1, 878 }; 879 880 static struct qcom_icc_node qhs_pimem_cfg = { 881 .name = "qhs_pimem_cfg", 882 .id = SM6115_SLAVE_PIMEM_CFG, 883 .channels = 1, 884 .buswidth = 4, 885 .mas_rpm_id = -1, 886 .slv_rpm_id = -1, 887 }; 888 889 static struct qcom_icc_node qhs_pka_wrapper = { 890 .name = "qhs_pka_wrapper", 891 .id = SM6115_SLAVE_PKA_CORE, 892 .channels = 1, 893 .buswidth = 4, 894 .mas_rpm_id = -1, 895 .slv_rpm_id = -1, 896 }; 897 898 static struct qcom_icc_node qhs_pmic_arb = { 899 .name = "qhs_pmic_arb", 900 .id = SM6115_SLAVE_PMIC_ARB, 901 .channels = 1, 902 .buswidth = 4, 903 .mas_rpm_id = -1, 904 .slv_rpm_id = -1, 905 }; 906 907 static struct qcom_icc_node qhs_qdss_cfg = { 908 .name = "qhs_qdss_cfg", 909 .id = SM6115_SLAVE_QDSS_CFG, 910 .channels = 1, 911 .buswidth = 4, 912 .mas_rpm_id = -1, 913 .slv_rpm_id = -1, 914 }; 915 916 static struct qcom_icc_node qhs_qm_cfg = { 917 .name = "qhs_qm_cfg", 918 .id = SM6115_SLAVE_QM_CFG, 919 .channels = 1, 920 .buswidth = 4, 921 .mas_rpm_id = -1, 922 .slv_rpm_id = -1, 923 }; 924 925 static struct qcom_icc_node qhs_qm_mpu_cfg = { 926 .name = "qhs_qm_mpu_cfg", 927 .id = SM6115_SLAVE_QM_MPU_CFG, 928 .channels = 1, 929 .buswidth = 4, 930 .mas_rpm_id = -1, 931 .slv_rpm_id = -1, 932 }; 933 934 static struct qcom_icc_node qhs_qpic = { 935 .name = "qhs_qpic", 936 .id = SM6115_SLAVE_QPIC, 937 .channels = 1, 938 .buswidth = 4, 939 .mas_rpm_id = -1, 940 .slv_rpm_id = -1, 941 }; 942 943 static struct qcom_icc_node qhs_qup0 = { 944 .name = "qhs_qup0", 945 .id = SM6115_SLAVE_QUP_0, 946 .channels = 1, 947 .buswidth = 4, 948 .mas_rpm_id = -1, 949 .slv_rpm_id = -1, 950 }; 951 952 static struct qcom_icc_node qhs_rpm = { 953 .name = "qhs_rpm", 954 .id = SM6115_SLAVE_RPM, 955 .channels = 1, 956 .buswidth = 4, 957 .mas_rpm_id = -1, 958 .slv_rpm_id = -1, 959 }; 960 961 static struct qcom_icc_node qhs_sdc1 = { 962 .name = "qhs_sdc1", 963 .id = SM6115_SLAVE_SDCC_1, 964 .channels = 1, 965 .buswidth = 4, 966 .mas_rpm_id = -1, 967 .slv_rpm_id = -1, 968 }; 969 970 static struct qcom_icc_node qhs_sdc2 = { 971 .name = "qhs_sdc2", 972 .id = SM6115_SLAVE_SDCC_2, 973 .channels = 1, 974 .buswidth = 4, 975 .mas_rpm_id = -1, 976 .slv_rpm_id = -1, 977 }; 978 979 static struct qcom_icc_node qhs_security = { 980 .name = "qhs_security", 981 .id = SM6115_SLAVE_SECURITY, 982 .channels = 1, 983 .buswidth = 4, 984 .mas_rpm_id = -1, 985 .slv_rpm_id = -1, 986 }; 987 988 static const u16 slv_snoc_cfg_links[] = { 989 SM6115_MASTER_SNOC_CFG, 990 }; 991 992 static struct qcom_icc_node qhs_snoc_cfg = { 993 .name = "qhs_snoc_cfg", 994 .id = SM6115_SLAVE_SNOC_CFG, 995 .channels = 1, 996 .buswidth = 4, 997 .mas_rpm_id = -1, 998 .slv_rpm_id = -1, 999 .num_links = ARRAY_SIZE(slv_snoc_cfg_links), 1000 .links = slv_snoc_cfg_links, 1001 }; 1002 1003 static struct qcom_icc_node qhs_tcsr = { 1004 .name = "qhs_tcsr", 1005 .id = SM6115_SLAVE_TCSR, 1006 .channels = 1, 1007 .buswidth = 4, 1008 .mas_rpm_id = -1, 1009 .slv_rpm_id = -1, 1010 }; 1011 1012 static struct qcom_icc_node qhs_tlmm = { 1013 .name = "qhs_tlmm", 1014 .id = SM6115_SLAVE_TLMM, 1015 .channels = 1, 1016 .buswidth = 4, 1017 .mas_rpm_id = -1, 1018 .slv_rpm_id = -1, 1019 }; 1020 1021 static struct qcom_icc_node qhs_usb3 = { 1022 .name = "qhs_usb3", 1023 .id = SM6115_SLAVE_USB3, 1024 .channels = 1, 1025 .buswidth = 4, 1026 .mas_rpm_id = -1, 1027 .slv_rpm_id = -1, 1028 }; 1029 1030 static struct qcom_icc_node qhs_venus_cfg = { 1031 .name = "qhs_venus_cfg", 1032 .id = SM6115_SLAVE_VENUS_CFG, 1033 .channels = 1, 1034 .buswidth = 4, 1035 .mas_rpm_id = -1, 1036 .slv_rpm_id = -1, 1037 }; 1038 1039 static struct qcom_icc_node qhs_venus_throttle_cfg = { 1040 .name = "qhs_venus_throttle_cfg", 1041 .id = SM6115_SLAVE_VENUS_THROTTLE_CFG, 1042 .channels = 1, 1043 .buswidth = 4, 1044 .mas_rpm_id = -1, 1045 .slv_rpm_id = -1, 1046 }; 1047 1048 static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 1049 .name = "qhs_vsense_ctrl_cfg", 1050 .id = SM6115_SLAVE_VSENSE_CTRL_CFG, 1051 .channels = 1, 1052 .buswidth = 4, 1053 .mas_rpm_id = -1, 1054 .slv_rpm_id = -1, 1055 }; 1056 1057 static struct qcom_icc_node srvc_cnoc = { 1058 .name = "srvc_cnoc", 1059 .id = SM6115_SLAVE_SERVICE_CNOC, 1060 .channels = 1, 1061 .buswidth = 4, 1062 .mas_rpm_id = -1, 1063 .slv_rpm_id = -1, 1064 }; 1065 1066 static const u16 slv_snoc_bimc_nrt_links[] = { 1067 SM6115_MASTER_SNOC_BIMC_NRT, 1068 }; 1069 1070 static struct qcom_icc_node slv_snoc_bimc_nrt = { 1071 .name = "slv_snoc_bimc_nrt", 1072 .id = SM6115_SLAVE_SNOC_BIMC_NRT, 1073 .channels = 1, 1074 .buswidth = 16, 1075 .mas_rpm_id = -1, 1076 .slv_rpm_id = -1, 1077 .num_links = ARRAY_SIZE(slv_snoc_bimc_nrt_links), 1078 .links = slv_snoc_bimc_nrt_links, 1079 }; 1080 1081 static const u16 slv_snoc_bimc_rt_links[] = { 1082 SM6115_MASTER_SNOC_BIMC_RT, 1083 }; 1084 1085 static struct qcom_icc_node slv_snoc_bimc_rt = { 1086 .name = "slv_snoc_bimc_rt", 1087 .id = SM6115_SLAVE_SNOC_BIMC_RT, 1088 .channels = 1, 1089 .buswidth = 16, 1090 .mas_rpm_id = -1, 1091 .slv_rpm_id = -1, 1092 .num_links = ARRAY_SIZE(slv_snoc_bimc_rt_links), 1093 .links = slv_snoc_bimc_rt_links, 1094 }; 1095 1096 static struct qcom_icc_node qhs_apss = { 1097 .name = "qhs_apss", 1098 .id = SM6115_SLAVE_APPSS, 1099 .channels = 1, 1100 .buswidth = 8, 1101 .mas_rpm_id = -1, 1102 .slv_rpm_id = -1, 1103 }; 1104 1105 static const u16 slv_snoc_cnoc_links[] = { 1106 SM6115_MASTER_SNOC_CNOC 1107 }; 1108 1109 static struct qcom_icc_node slv_snoc_cnoc = { 1110 .name = "slv_snoc_cnoc", 1111 .id = SM6115_SLAVE_SNOC_CNOC, 1112 .channels = 1, 1113 .buswidth = 8, 1114 .mas_rpm_id = -1, 1115 .slv_rpm_id = 25, 1116 .num_links = ARRAY_SIZE(slv_snoc_cnoc_links), 1117 .links = slv_snoc_cnoc_links, 1118 }; 1119 1120 static struct qcom_icc_node qxs_imem = { 1121 .name = "qxs_imem", 1122 .id = SM6115_SLAVE_OCIMEM, 1123 .channels = 1, 1124 .buswidth = 8, 1125 .mas_rpm_id = -1, 1126 .slv_rpm_id = 26, 1127 }; 1128 1129 static struct qcom_icc_node qxs_pimem = { 1130 .name = "qxs_pimem", 1131 .id = SM6115_SLAVE_PIMEM, 1132 .channels = 1, 1133 .buswidth = 8, 1134 .mas_rpm_id = -1, 1135 .slv_rpm_id = -1, 1136 }; 1137 1138 static const u16 slv_snoc_bimc_links[] = { 1139 SM6115_MASTER_SNOC_BIMC, 1140 }; 1141 1142 static struct qcom_icc_node slv_snoc_bimc = { 1143 .name = "slv_snoc_bimc", 1144 .id = SM6115_SLAVE_SNOC_BIMC, 1145 .channels = 1, 1146 .buswidth = 16, 1147 .mas_rpm_id = -1, 1148 .slv_rpm_id = 24, 1149 .num_links = ARRAY_SIZE(slv_snoc_bimc_links), 1150 .links = slv_snoc_bimc_links, 1151 }; 1152 1153 static struct qcom_icc_node srvc_snoc = { 1154 .name = "srvc_snoc", 1155 .id = SM6115_SLAVE_SERVICE_SNOC, 1156 .channels = 1, 1157 .buswidth = 4, 1158 .mas_rpm_id = -1, 1159 .slv_rpm_id = -1, 1160 }; 1161 1162 static struct qcom_icc_node xs_qdss_stm = { 1163 .name = "xs_qdss_stm", 1164 .id = SM6115_SLAVE_QDSS_STM, 1165 .channels = 1, 1166 .buswidth = 4, 1167 .mas_rpm_id = -1, 1168 .slv_rpm_id = 30, 1169 }; 1170 1171 static struct qcom_icc_node xs_sys_tcu_cfg = { 1172 .name = "xs_sys_tcu_cfg", 1173 .id = SM6115_SLAVE_TCU, 1174 .channels = 1, 1175 .buswidth = 8, 1176 .mas_rpm_id = -1, 1177 .slv_rpm_id = -1, 1178 }; 1179 1180 static const u16 slv_anoc_snoc_links[] = { 1181 SM6115_MASTER_ANOC_SNOC, 1182 }; 1183 1184 static struct qcom_icc_node slv_anoc_snoc = { 1185 .name = "slv_anoc_snoc", 1186 .id = SM6115_SLAVE_ANOC_SNOC, 1187 .channels = 1, 1188 .buswidth = 16, 1189 .mas_rpm_id = -1, 1190 .slv_rpm_id = -1, 1191 .num_links = ARRAY_SIZE(slv_anoc_snoc_links), 1192 .links = slv_anoc_snoc_links, 1193 }; 1194 1195 static struct qcom_icc_node * const bimc_nodes[] = { 1196 [MASTER_AMPSS_M0] = &apps_proc, 1197 [MASTER_SNOC_BIMC_RT] = &mas_snoc_bimc_rt, 1198 [MASTER_SNOC_BIMC_NRT] = &mas_snoc_bimc_nrt, 1199 [SNOC_BIMC_MAS] = &mas_snoc_bimc, 1200 [MASTER_GRAPHICS_3D] = &qnm_gpu, 1201 [MASTER_TCU_0] = &tcu_0, 1202 [SLAVE_EBI_CH0] = &ebi, 1203 [BIMC_SNOC_SLV] = &slv_bimc_snoc, 1204 }; 1205 1206 static const struct regmap_config bimc_regmap_config = { 1207 .reg_bits = 32, 1208 .reg_stride = 4, 1209 .val_bits = 32, 1210 .max_register = 0x80000, 1211 .fast_io = true, 1212 }; 1213 1214 static const struct qcom_icc_desc sm6115_bimc = { 1215 .type = QCOM_ICC_BIMC, 1216 .nodes = bimc_nodes, 1217 .num_nodes = ARRAY_SIZE(bimc_nodes), 1218 .regmap_cfg = &bimc_regmap_config, 1219 .bus_clk_desc = &bimc_clk, 1220 .keep_alive = true, 1221 .qos_offset = 0x8000, 1222 .ab_coeff = 153, 1223 }; 1224 1225 static struct qcom_icc_node * const config_noc_nodes[] = { 1226 [SNOC_CNOC_MAS] = &mas_snoc_cnoc, 1227 [MASTER_QDSS_DAP] = &xm_dap, 1228 [SLAVE_AHB2PHY_USB] = &qhs_ahb2phy_usb, 1229 [SLAVE_APSS_THROTTLE_CFG] = &qhs_apss_throttle_cfg, 1230 [SLAVE_BIMC_CFG] = &qhs_bimc_cfg, 1231 [SLAVE_BOOT_ROM] = &qhs_boot_rom, 1232 [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_throttle_cfg, 1233 [SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg, 1234 [SLAVE_CAMERA_CFG] = &qhs_camera_ss_cfg, 1235 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1236 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 1237 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, 1238 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1239 [SLAVE_DCC_CFG] = &qhs_dcc_cfg, 1240 [SLAVE_DDR_PHY_CFG] = &qhs_ddr_phy_cfg, 1241 [SLAVE_DDR_SS_CFG] = &qhs_ddr_ss_cfg, 1242 [SLAVE_DISPLAY_CFG] = &qhs_disp_ss_cfg, 1243 [SLAVE_DISPLAY_THROTTLE_CFG] = &qhs_display_throttle_cfg, 1244 [SLAVE_GPU_CFG] = &qhs_gpu_cfg, 1245 [SLAVE_GPU_THROTTLE_CFG] = &qhs_gpu_throttle_cfg, 1246 [SLAVE_HWKM_CORE] = &qhs_hwkm, 1247 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1248 [SLAVE_IPA_CFG] = &qhs_ipa_cfg, 1249 [SLAVE_LPASS] = &qhs_lpass, 1250 [SLAVE_MAPSS] = &qhs_mapss, 1251 [SLAVE_MDSP_MPU_CFG] = &qhs_mdsp_mpu_cfg, 1252 [SLAVE_MESSAGE_RAM] = &qhs_mesg_ram, 1253 [SLAVE_CNOC_MSS] = &qhs_mss, 1254 [SLAVE_PDM] = &qhs_pdm, 1255 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 1256 [SLAVE_PKA_CORE] = &qhs_pka_wrapper, 1257 [SLAVE_PMIC_ARB] = &qhs_pmic_arb, 1258 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1259 [SLAVE_QM_CFG] = &qhs_qm_cfg, 1260 [SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg, 1261 [SLAVE_QPIC] = &qhs_qpic, 1262 [SLAVE_QUP_0] = &qhs_qup0, 1263 [SLAVE_RPM] = &qhs_rpm, 1264 [SLAVE_SDCC_1] = &qhs_sdc1, 1265 [SLAVE_SDCC_2] = &qhs_sdc2, 1266 [SLAVE_SECURITY] = &qhs_security, 1267 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, 1268 [SLAVE_TCSR] = &qhs_tcsr, 1269 [SLAVE_TLMM] = &qhs_tlmm, 1270 [SLAVE_USB3] = &qhs_usb3, 1271 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1272 [SLAVE_VENUS_THROTTLE_CFG] = &qhs_venus_throttle_cfg, 1273 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 1274 [SLAVE_SERVICE_CNOC] = &srvc_cnoc, 1275 }; 1276 1277 static const struct regmap_config cnoc_regmap_config = { 1278 .reg_bits = 32, 1279 .reg_stride = 4, 1280 .val_bits = 32, 1281 .max_register = 0x6200, 1282 .fast_io = true, 1283 }; 1284 1285 static const struct qcom_icc_desc sm6115_config_noc = { 1286 .type = QCOM_ICC_QNOC, 1287 .nodes = config_noc_nodes, 1288 .num_nodes = ARRAY_SIZE(config_noc_nodes), 1289 .regmap_cfg = &cnoc_regmap_config, 1290 .intf_clocks = cnoc_intf_clocks, 1291 .num_intf_clocks = ARRAY_SIZE(cnoc_intf_clocks), 1292 .bus_clk_desc = &bus_1_clk, 1293 .keep_alive = true, 1294 }; 1295 1296 static struct qcom_icc_node * const sys_noc_nodes[] = { 1297 [MASTER_CRYPTO_CORE0] = &crypto_c0, 1298 [MASTER_SNOC_CFG] = &qhm_snoc_cfg, 1299 [MASTER_TIC] = &qhm_tic, 1300 [MASTER_ANOC_SNOC] = &mas_anoc_snoc, 1301 [BIMC_SNOC_MAS] = &mas_bimc_snoc, 1302 [MASTER_PIMEM] = &qxm_pimem, 1303 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 1304 [MASTER_QPIC] = &qhm_qpic, 1305 [MASTER_QUP_0] = &qhm_qup0, 1306 [MASTER_IPA] = &qxm_ipa, 1307 [MASTER_QDSS_ETR] = &xm_qdss_etr, 1308 [MASTER_SDCC_1] = &xm_sdc1, 1309 [MASTER_SDCC_2] = &xm_sdc2, 1310 [MASTER_USB3] = &xm_usb3_0, 1311 [SLAVE_APPSS] = &qhs_apss, 1312 [SNOC_CNOC_SLV] = &slv_snoc_cnoc, 1313 [SLAVE_OCIMEM] = &qxs_imem, 1314 [SLAVE_PIMEM] = &qxs_pimem, 1315 [SNOC_BIMC_SLV] = &slv_snoc_bimc, 1316 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 1317 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1318 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1319 [SLAVE_ANOC_SNOC] = &slv_anoc_snoc, 1320 }; 1321 1322 static const struct regmap_config sys_noc_regmap_config = { 1323 .reg_bits = 32, 1324 .reg_stride = 4, 1325 .val_bits = 32, 1326 .max_register = 0x5f080, 1327 .fast_io = true, 1328 }; 1329 1330 static const struct qcom_icc_desc sm6115_sys_noc = { 1331 .type = QCOM_ICC_QNOC, 1332 .nodes = sys_noc_nodes, 1333 .num_nodes = ARRAY_SIZE(sys_noc_nodes), 1334 .regmap_cfg = &sys_noc_regmap_config, 1335 .intf_clocks = snoc_intf_clocks, 1336 .num_intf_clocks = ARRAY_SIZE(snoc_intf_clocks), 1337 .bus_clk_desc = &bus_2_clk, 1338 .qos_offset = 0x15000, 1339 .keep_alive = true, 1340 }; 1341 1342 static struct qcom_icc_node * const clk_virt_nodes[] = { 1343 [MASTER_QUP_CORE_0] = &qup0_core_master, 1344 [SLAVE_QUP_CORE_0] = &qup0_core_slave, 1345 }; 1346 1347 static const struct qcom_icc_desc sm6115_clk_virt = { 1348 .type = QCOM_ICC_QNOC, 1349 .nodes = clk_virt_nodes, 1350 .num_nodes = ARRAY_SIZE(clk_virt_nodes), 1351 .regmap_cfg = &sys_noc_regmap_config, 1352 .bus_clk_desc = &qup_clk, 1353 .keep_alive = true, 1354 }; 1355 1356 static struct qcom_icc_node * const mmnrt_virt_nodes[] = { 1357 [MASTER_CAMNOC_SF] = &qnm_camera_nrt, 1358 [MASTER_VIDEO_P0] = &qxm_venus0, 1359 [MASTER_VIDEO_PROC] = &qxm_venus_cpu, 1360 [SLAVE_SNOC_BIMC_NRT] = &slv_snoc_bimc_nrt, 1361 }; 1362 1363 static const struct qcom_icc_desc sm6115_mmnrt_virt = { 1364 .type = QCOM_ICC_QNOC, 1365 .nodes = mmnrt_virt_nodes, 1366 .num_nodes = ARRAY_SIZE(mmnrt_virt_nodes), 1367 .regmap_cfg = &sys_noc_regmap_config, 1368 .bus_clk_desc = &mmaxi_0_clk, 1369 .keep_alive = true, 1370 .qos_offset = 0x15000, 1371 .ab_coeff = 142, 1372 }; 1373 1374 static struct qcom_icc_node * const mmrt_virt_nodes[] = { 1375 [MASTER_CAMNOC_HF] = &qnm_camera_rt, 1376 [MASTER_MDP_PORT0] = &qxm_mdp0, 1377 [SLAVE_SNOC_BIMC_RT] = &slv_snoc_bimc_rt, 1378 }; 1379 1380 static const struct qcom_icc_desc sm6115_mmrt_virt = { 1381 .type = QCOM_ICC_QNOC, 1382 .nodes = mmrt_virt_nodes, 1383 .num_nodes = ARRAY_SIZE(mmrt_virt_nodes), 1384 .regmap_cfg = &sys_noc_regmap_config, 1385 .bus_clk_desc = &mmaxi_1_clk, 1386 .keep_alive = true, 1387 .qos_offset = 0x15000, 1388 .ab_coeff = 139, 1389 }; 1390 1391 static const struct of_device_id qnoc_of_match[] = { 1392 { .compatible = "qcom,sm6115-bimc", .data = &sm6115_bimc }, 1393 { .compatible = "qcom,sm6115-clk-virt", .data = &sm6115_clk_virt }, 1394 { .compatible = "qcom,sm6115-cnoc", .data = &sm6115_config_noc }, 1395 { .compatible = "qcom,sm6115-mmrt-virt", .data = &sm6115_mmrt_virt }, 1396 { .compatible = "qcom,sm6115-mmnrt-virt", .data = &sm6115_mmnrt_virt }, 1397 { .compatible = "qcom,sm6115-snoc", .data = &sm6115_sys_noc }, 1398 { } 1399 }; 1400 MODULE_DEVICE_TABLE(of, qnoc_of_match); 1401 1402 static struct platform_driver qnoc_driver = { 1403 .probe = qnoc_probe, 1404 .remove = qnoc_remove, 1405 .driver = { 1406 .name = "qnoc-sm6115", 1407 .of_match_table = qnoc_of_match, 1408 .sync_state = icc_sync_state, 1409 }, 1410 }; 1411 1412 static int __init qnoc_driver_init(void) 1413 { 1414 return platform_driver_register(&qnoc_driver); 1415 } 1416 core_initcall(qnoc_driver_init); 1417 1418 static void __exit qnoc_driver_exit(void) 1419 { 1420 platform_driver_unregister(&qnoc_driver); 1421 } 1422 module_exit(qnoc_driver_exit); 1423 1424 MODULE_DESCRIPTION("SM6115 NoC driver"); 1425 MODULE_LICENSE("GPL"); 1426