1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 * 5 */ 6 7 #include <dt-bindings/interconnect/qcom,shikra.h> 8 #include <linux/device.h> 9 #include <linux/interconnect-provider.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 15 #include "icc-rpm.h" 16 17 static const char * const sys_noc_intf_clocks[] = { 18 "emac0_axi", 19 "emac1_axi", 20 "usb2_axi", 21 "usb3_axi", 22 }; 23 24 static const char * const memnoc_intf_clocks[] = { 25 "gpu_axi", 26 }; 27 28 enum { 29 SHIKRA_MASTER_QUP_CORE_0 = 1, 30 SHIKRA_SNOC_CNOC_MAS, 31 SHIKRA_MASTER_QDSS_DAP, 32 SHIKRA_MASTER_LLCC, 33 SHIKRA_MASTER_GRAPHICS_3D, 34 SHIKRA_MASTER_MNOC_HF_MEM_NOC, 35 SHIKRA_MASTER_ANOC_PCIE_MEM_NOC, 36 SHIKRA_MASTER_SNOC_SF_MEM_NOC, 37 SHIKRA_MASTER_AMPSS_M0, 38 SHIKRA_MASTER_SYS_TCU, 39 SHIKRA_MASTER_CAMNOC_SF, 40 SHIKRA_MASTER_VIDEO_P0, 41 SHIKRA_MASTER_VIDEO_PROC, 42 SHIKRA_MASTER_CAMNOC_HF, 43 SHIKRA_MASTER_MDP_PORT0, 44 SHIKRA_MASTER_MMRT_VIRT, 45 SHIKRA_MASTER_SNOC_CFG, 46 SHIKRA_MASTER_TIC, 47 SHIKRA_MASTER_ANOC_SNOC, 48 SHIKRA_MASTER_MEMNOC_PCIE, 49 SHIKRA_MASTER_MEMNOC_SNOC, 50 SHIKRA_MASTER_PIMEM, 51 SHIKRA_MASTER_PCIE2_0, 52 SHIKRA_MASTER_QDSS_BAM, 53 SHIKRA_MASTER_QPIC, 54 SHIKRA_MASTER_QUP_0, 55 SHIKRA_CNOC_SNOC_MAS, 56 SHIKRA_MASTER_AUDIO, 57 SHIKRA_MASTER_EMAC_0, 58 SHIKRA_MASTER_EMAC_1, 59 SHIKRA_MASTER_QDSS_ETR, 60 SHIKRA_MASTER_SDCC_1, 61 SHIKRA_MASTER_SDCC_2, 62 SHIKRA_MASTER_USB2_0, 63 SHIKRA_MASTER_USB3, 64 SHIKRA_MASTER_CRYPTO_CORE0, 65 66 SHIKRA_SLAVE_QUP_CORE_0, 67 SHIKRA_SLAVE_AHB2PHY_USB, 68 SHIKRA_SLAVE_APSS_THROTTLE_CFG, 69 SHIKRA_SLAVE_AUDIO, 70 SHIKRA_SLAVE_BOOT_ROM, 71 SHIKRA_SLAVE_CAMERA_NRT_THROTTLE_CFG, 72 SHIKRA_SLAVE_CAMERA_CFG, 73 SHIKRA_SLAVE_CDSP_THROTTLE_CFG, 74 SHIKRA_SLAVE_CLK_CTL, 75 SHIKRA_SLAVE_DSP_CFG, 76 SHIKRA_SLAVE_RBCPR_CX_CFG, 77 SHIKRA_SLAVE_RBCPR_MX_CFG, 78 SHIKRA_SLAVE_CRYPTO_0_CFG, 79 SHIKRA_SLAVE_DDR_SS_CFG, 80 SHIKRA_SLAVE_DISPLAY_CFG, 81 SHIKRA_SLAVE_EMAC0_CFG, 82 SHIKRA_SLAVE_EMAC1_CFG, 83 SHIKRA_SLAVE_GPU_CFG, 84 SHIKRA_SLAVE_GPU_THROTTLE_CFG, 85 SHIKRA_SLAVE_HWKM, 86 SHIKRA_SLAVE_IMEM_CFG, 87 SHIKRA_SLAVE_MAPSS, 88 SHIKRA_SLAVE_MDSP_MPU_CFG, 89 SHIKRA_SLAVE_MESSAGE_RAM, 90 SHIKRA_SLAVE_MSS, 91 SHIKRA_SLAVE_PCIE_CFG, 92 SHIKRA_SLAVE_PDM, 93 SHIKRA_SLAVE_PIMEM_CFG, 94 SHIKRA_SLAVE_PKA_WRAPPER_CFG, 95 SHIKRA_SLAVE_PMIC_ARB, 96 SHIKRA_SLAVE_QDSS_CFG, 97 SHIKRA_SLAVE_QM_CFG, 98 SHIKRA_SLAVE_QM_MPU_CFG, 99 SHIKRA_SLAVE_QPIC, 100 SHIKRA_SLAVE_QUP_0, 101 SHIKRA_SLAVE_RPM, 102 SHIKRA_SLAVE_SDCC_1, 103 SHIKRA_SLAVE_SDCC_2, 104 SHIKRA_SLAVE_SECURITY, 105 SHIKRA_SLAVE_SNOC_CFG, 106 SHIKRA_SNOC_SF_THROTTLE_CFG, 107 SHIKRA_SLAVE_TLMM, 108 SHIKRA_SLAVE_TSCSS, 109 SHIKRA_SLAVE_USB2, 110 SHIKRA_SLAVE_USB3, 111 SHIKRA_SLAVE_VENUS_CFG, 112 SHIKRA_SLAVE_VENUS_THROTTLE_CFG, 113 SHIKRA_SLAVE_VSENSE_CTRL_CFG, 114 SHIKRA_SLAVE_SERVICE_CNOC, 115 SHIKRA_SLAVE_EBI_CH0, 116 SHIKRA_SLAVE_LLCC, 117 SHIKRA_SLAVE_MEMNOC_SNOC, 118 SHIKRA_SLAVE_MEM_NOC_PCIE_SNOC, 119 SHIKRA_SLAVE_MMNRT_VIRT, 120 SHIKRA_SLAVE_MM_MEMNOC, 121 SHIKRA_SLAVE_APPSS, 122 SHIKRA_SLAVE_MCUSS, 123 SHIKRA_SLAVE_WCSS, 124 SHIKRA_SLAVE_MEMNOC_SF, 125 SHIKRA_SNOC_CNOC_SLV, 126 SHIKRA_SLAVE_BOOTIMEM, 127 SHIKRA_SLAVE_OCIMEM, 128 SHIKRA_SLAVE_PIMEM, 129 SHIKRA_SLAVE_SERVICE_SNOC, 130 SHIKRA_SLAVE_PCIE2_0, 131 SHIKRA_SLAVE_QDSS_STM, 132 SHIKRA_SLAVE_TCU, 133 SHIKRA_SLAVE_PCIE_MEMNOC, 134 SHIKRA_SLAVE_ANOC_SNOC, 135 }; 136 137 /* Master nodes */ 138 static const u16 qup0_core_master_links[] = { 139 SHIKRA_SLAVE_QUP_CORE_0, 140 }; 141 142 static struct qcom_icc_node qup0_core_master = { 143 .id = SHIKRA_MASTER_QUP_CORE_0, 144 .name = "qup0_core_master", 145 .buswidth = 4, 146 .mas_rpm_id = 170, 147 .slv_rpm_id = -1, 148 .num_links = ARRAY_SIZE(qup0_core_master_links), 149 .links = qup0_core_master_links, 150 }; 151 152 static const u16 qnm_snoc_cnoc_links[] = { 153 SHIKRA_SLAVE_AHB2PHY_USB, 154 SHIKRA_SLAVE_APSS_THROTTLE_CFG, 155 SHIKRA_SLAVE_AUDIO, 156 SHIKRA_SLAVE_BOOT_ROM, 157 SHIKRA_SLAVE_CAMERA_NRT_THROTTLE_CFG, 158 SHIKRA_SLAVE_CAMERA_CFG, 159 SHIKRA_SLAVE_CDSP_THROTTLE_CFG, 160 SHIKRA_SLAVE_CLK_CTL, 161 SHIKRA_SLAVE_DSP_CFG, 162 SHIKRA_SLAVE_RBCPR_CX_CFG, 163 SHIKRA_SLAVE_RBCPR_MX_CFG, 164 SHIKRA_SLAVE_CRYPTO_0_CFG, 165 SHIKRA_SLAVE_DDR_SS_CFG, 166 SHIKRA_SLAVE_DISPLAY_CFG, 167 SHIKRA_SLAVE_EMAC0_CFG, 168 SHIKRA_SLAVE_EMAC1_CFG, 169 SHIKRA_SLAVE_GPU_CFG, 170 SHIKRA_SLAVE_GPU_THROTTLE_CFG, 171 SHIKRA_SLAVE_HWKM, 172 SHIKRA_SLAVE_IMEM_CFG, 173 SHIKRA_SLAVE_MAPSS, 174 SHIKRA_SLAVE_MDSP_MPU_CFG, 175 SHIKRA_SLAVE_MESSAGE_RAM, 176 SHIKRA_SLAVE_MSS, 177 SHIKRA_SLAVE_PCIE_CFG, 178 SHIKRA_SLAVE_PDM, 179 SHIKRA_SLAVE_PIMEM_CFG, 180 SHIKRA_SLAVE_PKA_WRAPPER_CFG, 181 SHIKRA_SLAVE_PMIC_ARB, 182 SHIKRA_SLAVE_QDSS_CFG, 183 SHIKRA_SLAVE_QM_CFG, 184 SHIKRA_SLAVE_QM_MPU_CFG, 185 SHIKRA_SLAVE_QPIC, 186 SHIKRA_SLAVE_QUP_0, 187 SHIKRA_SLAVE_RPM, 188 SHIKRA_SLAVE_SDCC_1, 189 SHIKRA_SLAVE_SDCC_2, 190 SHIKRA_SLAVE_SECURITY, 191 SHIKRA_SLAVE_SNOC_CFG, 192 SHIKRA_SNOC_SF_THROTTLE_CFG, 193 SHIKRA_SLAVE_TLMM, 194 SHIKRA_SLAVE_TSCSS, 195 SHIKRA_SLAVE_USB2, 196 SHIKRA_SLAVE_USB3, 197 SHIKRA_SLAVE_VENUS_CFG, 198 SHIKRA_SLAVE_VENUS_THROTTLE_CFG, 199 SHIKRA_SLAVE_VSENSE_CTRL_CFG, 200 SHIKRA_SLAVE_SERVICE_CNOC, 201 }; 202 203 static struct qcom_icc_node qnm_snoc_cnoc = { 204 .id = SHIKRA_SNOC_CNOC_MAS, 205 .name = "qnm_snoc_cnoc", 206 .buswidth = 8, 207 .mas_rpm_id = -1, 208 .slv_rpm_id = -1, 209 .num_links = ARRAY_SIZE(qnm_snoc_cnoc_links), 210 .links = qnm_snoc_cnoc_links, 211 }; 212 213 static const u16 xm_dap_links[] = { 214 SHIKRA_SLAVE_AHB2PHY_USB, 215 SHIKRA_SLAVE_APSS_THROTTLE_CFG, 216 SHIKRA_SLAVE_AUDIO, 217 SHIKRA_SLAVE_BOOT_ROM, 218 SHIKRA_SLAVE_CAMERA_NRT_THROTTLE_CFG, 219 SHIKRA_SLAVE_CAMERA_CFG, 220 SHIKRA_SLAVE_CDSP_THROTTLE_CFG, 221 SHIKRA_SLAVE_CLK_CTL, 222 SHIKRA_SLAVE_DSP_CFG, 223 SHIKRA_SLAVE_RBCPR_CX_CFG, 224 SHIKRA_SLAVE_RBCPR_MX_CFG, 225 SHIKRA_SLAVE_CRYPTO_0_CFG, 226 SHIKRA_SLAVE_DDR_SS_CFG, 227 SHIKRA_SLAVE_DISPLAY_CFG, 228 SHIKRA_SLAVE_EMAC0_CFG, 229 SHIKRA_SLAVE_EMAC1_CFG, 230 SHIKRA_SLAVE_GPU_CFG, 231 SHIKRA_SLAVE_GPU_THROTTLE_CFG, 232 SHIKRA_SLAVE_HWKM, 233 SHIKRA_SLAVE_IMEM_CFG, 234 SHIKRA_SLAVE_MAPSS, 235 SHIKRA_SLAVE_MDSP_MPU_CFG, 236 SHIKRA_SLAVE_MESSAGE_RAM, 237 SHIKRA_SLAVE_MSS, 238 SHIKRA_SLAVE_PCIE_CFG, 239 SHIKRA_SLAVE_PDM, 240 SHIKRA_SLAVE_PIMEM_CFG, 241 SHIKRA_SLAVE_PKA_WRAPPER_CFG, 242 SHIKRA_SLAVE_PMIC_ARB, 243 SHIKRA_SLAVE_QDSS_CFG, 244 SHIKRA_SLAVE_QM_CFG, 245 SHIKRA_SLAVE_QM_MPU_CFG, 246 SHIKRA_SLAVE_QPIC, 247 SHIKRA_SLAVE_QUP_0, 248 SHIKRA_SLAVE_RPM, 249 SHIKRA_SLAVE_SDCC_1, 250 SHIKRA_SLAVE_SDCC_2, 251 SHIKRA_SLAVE_SECURITY, 252 SHIKRA_SLAVE_SNOC_CFG, 253 SHIKRA_SNOC_SF_THROTTLE_CFG, 254 SHIKRA_SLAVE_TLMM, 255 SHIKRA_SLAVE_TSCSS, 256 SHIKRA_SLAVE_USB2, 257 SHIKRA_SLAVE_USB3, 258 SHIKRA_SLAVE_VENUS_CFG, 259 SHIKRA_SLAVE_VENUS_THROTTLE_CFG, 260 SHIKRA_SLAVE_VSENSE_CTRL_CFG, 261 SHIKRA_SLAVE_SERVICE_CNOC, 262 }; 263 264 static struct qcom_icc_node xm_dap = { 265 .id = SHIKRA_MASTER_QDSS_DAP, 266 .name = "xm_dap", 267 .buswidth = 8, 268 .mas_rpm_id = -1, 269 .slv_rpm_id = -1, 270 .num_links = ARRAY_SIZE(xm_dap_links), 271 .links = xm_dap_links, 272 }; 273 274 static const u16 llcc_mc_links[] = { 275 SHIKRA_SLAVE_EBI_CH0, 276 }; 277 278 static struct qcom_icc_node llcc_mc = { 279 .id = SHIKRA_MASTER_LLCC, 280 .name = "llcc_mc", 281 .buswidth = 4, 282 .channels = 2, 283 .mas_rpm_id = 190, 284 .slv_rpm_id = -1, 285 .num_links = ARRAY_SIZE(llcc_mc_links), 286 .links = llcc_mc_links, 287 }; 288 289 static const u16 qnm_gpu_links[] = { 290 SHIKRA_SLAVE_LLCC, 291 SHIKRA_SLAVE_MEMNOC_SNOC, 292 SHIKRA_SLAVE_MEM_NOC_PCIE_SNOC, 293 }; 294 295 static struct qcom_icc_node qnm_gpu = { 296 .id = SHIKRA_MASTER_GRAPHICS_3D, 297 .name = "qnm_gpu", 298 .buswidth = 16, 299 .qos.ap_owned = true, 300 .qos.qos_port = 6, 301 .qos.urg_fwd_en = false, 302 .qos.qos_mode = NOC_QOS_MODE_FIXED, 303 .qos.areq_prio = 0, 304 .mas_rpm_id = -1, 305 .slv_rpm_id = -1, 306 .num_links = ARRAY_SIZE(qnm_gpu_links), 307 .links = qnm_gpu_links, 308 }; 309 310 static const u16 qnm_mnoc_hf_links[] = { 311 SHIKRA_SLAVE_LLCC, 312 SHIKRA_SLAVE_MEMNOC_SNOC, 313 SHIKRA_SLAVE_MEM_NOC_PCIE_SNOC, 314 }; 315 316 static struct qcom_icc_node qnm_mnoc_hf = { 317 .id = SHIKRA_MASTER_MNOC_HF_MEM_NOC, 318 .name = "qnm_mnoc_hf", 319 .buswidth = 16, 320 .qos.ap_owned = true, 321 .qos.qos_port = 7, 322 .qos.urg_fwd_en = true, 323 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 324 .qos.areq_prio = 0, 325 .mas_rpm_id = -1, 326 .slv_rpm_id = -1, 327 .num_links = ARRAY_SIZE(qnm_mnoc_hf_links), 328 .links = qnm_mnoc_hf_links, 329 }; 330 331 static const u16 qnm_pcie_links[] = { 332 SHIKRA_SLAVE_LLCC, 333 SHIKRA_SLAVE_MEMNOC_SNOC, 334 }; 335 336 static struct qcom_icc_node qnm_pcie = { 337 .id = SHIKRA_MASTER_ANOC_PCIE_MEM_NOC, 338 .name = "qnm_pcie", 339 .buswidth = 8, 340 .qos.ap_owned = true, 341 .qos.qos_port = 4, 342 .qos.urg_fwd_en = true, 343 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 344 .qos.areq_prio = 0, 345 .mas_rpm_id = 185, 346 .slv_rpm_id = -1, 347 .num_links = ARRAY_SIZE(qnm_pcie_links), 348 .links = qnm_pcie_links, 349 }; 350 351 static const u16 qnm_snoc_sf_links[] = { 352 SHIKRA_SLAVE_LLCC, 353 SHIKRA_SLAVE_MEMNOC_SNOC, 354 SHIKRA_SLAVE_MEM_NOC_PCIE_SNOC, 355 }; 356 357 static struct qcom_icc_node qnm_snoc_sf = { 358 .id = SHIKRA_MASTER_SNOC_SF_MEM_NOC, 359 .name = "qnm_snoc_sf", 360 .buswidth = 16, 361 .qos.ap_owned = true, 362 .qos.qos_port = 3, 363 .qos.urg_fwd_en = true, 364 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 365 .qos.areq_prio = 0, 366 .mas_rpm_id = 76, 367 .slv_rpm_id = -1, 368 .num_links = ARRAY_SIZE(qnm_snoc_sf_links), 369 .links = qnm_snoc_sf_links, 370 }; 371 372 static const u16 xm_apps_links[] = { 373 SHIKRA_SLAVE_LLCC, 374 SHIKRA_SLAVE_MEMNOC_SNOC, 375 SHIKRA_SLAVE_MEM_NOC_PCIE_SNOC, 376 }; 377 378 static struct qcom_icc_node xm_apps = { 379 .id = SHIKRA_MASTER_AMPSS_M0, 380 .name = "xm_apps", 381 .buswidth = 16, 382 .qos.ap_owned = true, 383 .qos.qos_port = 5, 384 .qos.urg_fwd_en = false, 385 .qos.qos_mode = NOC_QOS_MODE_FIXED, 386 .qos.areq_prio = 0, 387 .mas_rpm_id = 0, 388 .slv_rpm_id = -1, 389 .num_links = ARRAY_SIZE(xm_apps_links), 390 .links = xm_apps_links, 391 }; 392 393 static const u16 xm_tcu_links[] = { 394 SHIKRA_SLAVE_LLCC, 395 SHIKRA_SLAVE_MEMNOC_SNOC, 396 }; 397 398 static struct qcom_icc_node xm_tcu = { 399 .id = SHIKRA_MASTER_SYS_TCU, 400 .name = "xm_tcu", 401 .buswidth = 8, 402 .qos.ap_owned = true, 403 .qos.qos_port = 2, 404 .qos.urg_fwd_en = false, 405 .qos.qos_mode = NOC_QOS_MODE_FIXED, 406 .qos.areq_prio = 6, 407 .mas_rpm_id = -1, 408 .slv_rpm_id = -1, 409 .num_links = ARRAY_SIZE(xm_tcu_links), 410 .links = xm_tcu_links, 411 }; 412 413 static const u16 qnm_camera_nrt_links[] = { 414 SHIKRA_SLAVE_MMNRT_VIRT, 415 }; 416 417 static struct qcom_icc_node qnm_camera_nrt = { 418 .id = SHIKRA_MASTER_CAMNOC_SF, 419 .name = "qnm_camera_nrt", 420 .buswidth = 32, 421 .qos.ap_owned = true, 422 .qos.qos_port = 3, 423 .qos.urg_fwd_en = false, 424 .qos.qos_mode = NOC_QOS_MODE_FIXED, 425 .qos.areq_prio = 3, 426 .mas_rpm_id = -1, 427 .slv_rpm_id = -1, 428 .num_links = ARRAY_SIZE(qnm_camera_nrt_links), 429 .links = qnm_camera_nrt_links, 430 }; 431 432 static const u16 qxm_venus0_links[] = { 433 SHIKRA_SLAVE_MMNRT_VIRT, 434 }; 435 436 static struct qcom_icc_node qxm_venus0 = { 437 .id = SHIKRA_MASTER_VIDEO_P0, 438 .name = "qxm_venus0", 439 .buswidth = 16, 440 .qos.ap_owned = true, 441 .qos.qos_port = 8, 442 .qos.urg_fwd_en = true, 443 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 444 .qos.areq_prio = 0, 445 .mas_rpm_id = -1, 446 .slv_rpm_id = -1, 447 .num_links = ARRAY_SIZE(qxm_venus0_links), 448 .links = qxm_venus0_links, 449 }; 450 451 static const u16 qxm_venus_cpu_links[] = { 452 SHIKRA_SLAVE_MMNRT_VIRT, 453 }; 454 455 static struct qcom_icc_node qxm_venus_cpu = { 456 .id = SHIKRA_MASTER_VIDEO_PROC, 457 .name = "qxm_venus_cpu", 458 .buswidth = 8, 459 .qos.ap_owned = true, 460 .qos.qos_port = 12, 461 .qos.urg_fwd_en = false, 462 .qos.qos_mode = NOC_QOS_MODE_FIXED, 463 .qos.areq_prio = 4, 464 .mas_rpm_id = -1, 465 .slv_rpm_id = -1, 466 .num_links = ARRAY_SIZE(qxm_venus_cpu_links), 467 .links = qxm_venus_cpu_links, 468 }; 469 470 static const u16 qnm_camera_rt_links[] = { 471 SHIKRA_SLAVE_MM_MEMNOC, 472 }; 473 474 static struct qcom_icc_node qnm_camera_rt = { 475 .id = SHIKRA_MASTER_CAMNOC_HF, 476 .name = "qnm_camera_rt", 477 .buswidth = 32, 478 .qos.ap_owned = true, 479 .qos.qos_port = 9, 480 .qos.urg_fwd_en = true, 481 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 482 .qos.areq_prio = 0, 483 .mas_rpm_id = -1, 484 .slv_rpm_id = -1, 485 .num_links = ARRAY_SIZE(qnm_camera_rt_links), 486 .links = qnm_camera_rt_links, 487 }; 488 489 static const u16 qxm_mdp0_links[] = { 490 SHIKRA_SLAVE_MM_MEMNOC, 491 }; 492 493 static struct qcom_icc_node qxm_mdp0 = { 494 .id = SHIKRA_MASTER_MDP_PORT0, 495 .name = "qxm_mdp0", 496 .buswidth = 16, 497 .qos.ap_owned = true, 498 .qos.qos_port = 4, 499 .qos.urg_fwd_en = true, 500 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 501 .qos.areq_prio = 0, 502 .mas_rpm_id = -1, 503 .slv_rpm_id = -1, 504 .num_links = ARRAY_SIZE(qxm_mdp0_links), 505 .links = qxm_mdp0_links, 506 }; 507 508 static const u16 mmrt_virt_master_links[] = { 509 SHIKRA_SLAVE_MM_MEMNOC, 510 }; 511 512 static struct qcom_icc_node mmrt_virt_master = { 513 .id = SHIKRA_MASTER_MMRT_VIRT, 514 .name = "mmrt_virt_master", 515 .buswidth = 16, 516 .mas_rpm_id = -1, 517 .slv_rpm_id = -1, 518 .num_links = ARRAY_SIZE(mmrt_virt_master_links), 519 .links = mmrt_virt_master_links, 520 }; 521 522 static const u16 qhm_snoc_cfg_links[] = { 523 SHIKRA_SLAVE_SERVICE_SNOC, 524 }; 525 526 static struct qcom_icc_node qhm_snoc_cfg = { 527 .id = SHIKRA_MASTER_SNOC_CFG, 528 .name = "qhm_snoc_cfg", 529 .buswidth = 4, 530 .mas_rpm_id = -1, 531 .slv_rpm_id = -1, 532 .num_links = ARRAY_SIZE(qhm_snoc_cfg_links), 533 .links = qhm_snoc_cfg_links, 534 }; 535 536 static const u16 qhm_tic_links[] = { 537 SHIKRA_SLAVE_APPSS, 538 SHIKRA_SLAVE_MCUSS, 539 SHIKRA_SLAVE_WCSS, 540 SHIKRA_SLAVE_MEMNOC_SF, 541 SHIKRA_SNOC_CNOC_SLV, 542 SHIKRA_SLAVE_BOOTIMEM, 543 SHIKRA_SLAVE_OCIMEM, 544 SHIKRA_SLAVE_PIMEM, 545 SHIKRA_SLAVE_QDSS_STM, 546 SHIKRA_SLAVE_TCU, 547 }; 548 549 static struct qcom_icc_node qhm_tic = { 550 .id = SHIKRA_MASTER_TIC, 551 .name = "qhm_tic", 552 .buswidth = 4, 553 .mas_rpm_id = -1, 554 .slv_rpm_id = -1, 555 .num_links = ARRAY_SIZE(qhm_tic_links), 556 .links = qhm_tic_links, 557 }; 558 559 static const u16 qnm_anoc_snoc_links[] = { 560 SHIKRA_SLAVE_MEMNOC_SF, 561 }; 562 563 static struct qcom_icc_node qnm_anoc_snoc = { 564 .id = SHIKRA_MASTER_ANOC_SNOC, 565 .name = "qnm_anoc_snoc", 566 .buswidth = 16, 567 .mas_rpm_id = 110, 568 .slv_rpm_id = -1, 569 .num_links = ARRAY_SIZE(qnm_anoc_snoc_links), 570 .links = qnm_anoc_snoc_links, 571 }; 572 573 static const u16 qnm_memnoc_pcie_links[] = { 574 SHIKRA_SLAVE_PCIE2_0, 575 }; 576 577 static struct qcom_icc_node qnm_memnoc_pcie = { 578 .id = SHIKRA_MASTER_MEMNOC_PCIE, 579 .name = "qnm_memnoc_pcie", 580 .buswidth = 8, 581 .mas_rpm_id = -1, 582 .slv_rpm_id = -1, 583 .num_links = ARRAY_SIZE(qnm_memnoc_pcie_links), 584 .links = qnm_memnoc_pcie_links, 585 }; 586 587 static const u16 qnm_memnoc_snoc_links[] = { 588 SHIKRA_SLAVE_APPSS, 589 SHIKRA_SLAVE_MCUSS, 590 SHIKRA_SLAVE_WCSS, 591 SHIKRA_SNOC_CNOC_SLV, 592 SHIKRA_SLAVE_BOOTIMEM, 593 SHIKRA_SLAVE_OCIMEM, 594 SHIKRA_SLAVE_PIMEM, 595 SHIKRA_SLAVE_QDSS_STM, 596 SHIKRA_SLAVE_TCU, 597 }; 598 599 static struct qcom_icc_node qnm_memnoc_snoc = { 600 .id = SHIKRA_MASTER_MEMNOC_SNOC, 601 .name = "qnm_memnoc_snoc", 602 .buswidth = 8, 603 .mas_rpm_id = 184, 604 .slv_rpm_id = -1, 605 .num_links = ARRAY_SIZE(qnm_memnoc_snoc_links), 606 .links = qnm_memnoc_snoc_links, 607 }; 608 609 static const u16 qxm_pimem_links[] = { 610 SHIKRA_SLAVE_MEMNOC_SF, 611 SHIKRA_SLAVE_OCIMEM, 612 }; 613 614 static struct qcom_icc_node qxm_pimem = { 615 .id = SHIKRA_MASTER_PIMEM, 616 .name = "qxm_pimem", 617 .buswidth = 8, 618 .qos.ap_owned = true, 619 .qos.qos_port = 14, 620 .qos.urg_fwd_en = false, 621 .qos.qos_mode = NOC_QOS_MODE_FIXED, 622 .qos.areq_prio = 2, 623 .mas_rpm_id = -1, 624 .slv_rpm_id = -1, 625 .num_links = ARRAY_SIZE(qxm_pimem_links), 626 .links = qxm_pimem_links, 627 }; 628 629 static const u16 xm_pcie2_0_links[] = { 630 SHIKRA_SLAVE_PCIE_MEMNOC, 631 }; 632 633 static struct qcom_icc_node xm_pcie2_0 = { 634 .id = SHIKRA_MASTER_PCIE2_0, 635 .name = "xm_pcie2_0", 636 .buswidth = 8, 637 .qos.ap_owned = true, 638 .qos.qos_port = 21, 639 .qos.urg_fwd_en = false, 640 .qos.qos_mode = NOC_QOS_MODE_FIXED, 641 .qos.areq_prio = 2, 642 .mas_rpm_id = 186, 643 .slv_rpm_id = -1, 644 .num_links = ARRAY_SIZE(xm_pcie2_0_links), 645 .links = xm_pcie2_0_links, 646 }; 647 648 static const u16 qhm_qdss_bam_links[] = { 649 SHIKRA_SLAVE_ANOC_SNOC, 650 }; 651 652 static struct qcom_icc_node qhm_qdss_bam = { 653 .id = SHIKRA_MASTER_QDSS_BAM, 654 .name = "qhm_qdss_bam", 655 .buswidth = 4, 656 .qos.ap_owned = true, 657 .qos.qos_port = 2, 658 .qos.urg_fwd_en = false, 659 .qos.qos_mode = NOC_QOS_MODE_FIXED, 660 .qos.areq_prio = 2, 661 .mas_rpm_id = -1, 662 .slv_rpm_id = -1, 663 .num_links = ARRAY_SIZE(qhm_qdss_bam_links), 664 .links = qhm_qdss_bam_links, 665 }; 666 667 static const u16 qhm_qpic_links[] = { 668 SHIKRA_SLAVE_ANOC_SNOC, 669 }; 670 671 static struct qcom_icc_node qhm_qpic = { 672 .id = SHIKRA_MASTER_QPIC, 673 .name = "qhm_qpic", 674 .buswidth = 4, 675 .qos.ap_owned = true, 676 .qos.qos_port = 1, 677 .qos.urg_fwd_en = false, 678 .qos.qos_mode = NOC_QOS_MODE_FIXED, 679 .qos.areq_prio = 2, 680 .mas_rpm_id = -1, 681 .slv_rpm_id = -1, 682 .num_links = ARRAY_SIZE(qhm_qpic_links), 683 .links = qhm_qpic_links, 684 }; 685 686 static const u16 qhm_qup0_links[] = { 687 SHIKRA_SLAVE_ANOC_SNOC, 688 }; 689 690 static struct qcom_icc_node qhm_qup0 = { 691 .id = SHIKRA_MASTER_QUP_0, 692 .name = "qhm_qup0", 693 .buswidth = 4, 694 .qos.ap_owned = true, 695 .qos.qos_port = 0, 696 .qos.urg_fwd_en = false, 697 .qos.qos_mode = NOC_QOS_MODE_FIXED, 698 .qos.areq_prio = 2, 699 .mas_rpm_id = 166, 700 .slv_rpm_id = -1, 701 .num_links = ARRAY_SIZE(qhm_qup0_links), 702 .links = qhm_qup0_links, 703 }; 704 705 static const u16 qnm_cnoc_snoc_links[] = { 706 SHIKRA_SLAVE_ANOC_SNOC, 707 }; 708 709 static struct qcom_icc_node qnm_cnoc_snoc = { 710 .id = SHIKRA_CNOC_SNOC_MAS, 711 .name = "qnm_cnoc_snoc", 712 .buswidth = 4, 713 .qos.ap_owned = true, 714 .qos.qos_port = 7, 715 .qos.urg_fwd_en = false, 716 .qos.qos_mode = NOC_QOS_MODE_FIXED, 717 .qos.areq_prio = 2, 718 .mas_rpm_id = -1, 719 .slv_rpm_id = -1, 720 .num_links = ARRAY_SIZE(qnm_cnoc_snoc_links), 721 .links = qnm_cnoc_snoc_links, 722 }; 723 724 static const u16 qxm_audio_links[] = { 725 SHIKRA_SLAVE_ANOC_SNOC, 726 }; 727 728 static struct qcom_icc_node qxm_audio = { 729 .id = SHIKRA_MASTER_AUDIO, 730 .name = "qxm_audio", 731 .buswidth = 8, 732 .qos.ap_owned = true, 733 .qos.qos_port = 22, 734 .qos.urg_fwd_en = false, 735 .qos.qos_mode = NOC_QOS_MODE_FIXED, 736 .qos.areq_prio = 3, 737 .mas_rpm_id = 78, 738 .slv_rpm_id = -1, 739 .num_links = ARRAY_SIZE(qxm_audio_links), 740 .links = qxm_audio_links, 741 }; 742 743 static const u16 xm_emac_0_links[] = { 744 SHIKRA_SLAVE_ANOC_SNOC, 745 }; 746 747 static struct qcom_icc_node xm_emac_0 = { 748 .id = SHIKRA_MASTER_EMAC_0, 749 .name = "xm_emac_0", 750 .buswidth = 8, 751 .qos.ap_owned = true, 752 .qos.qos_port = 19, 753 .qos.urg_fwd_en = false, 754 .qos.qos_mode = NOC_QOS_MODE_FIXED, 755 .qos.areq_prio = 2, 756 .mas_rpm_id = -1, 757 .slv_rpm_id = -1, 758 .num_links = ARRAY_SIZE(xm_emac_0_links), 759 .links = xm_emac_0_links, 760 }; 761 762 static const u16 xm_emac_1_links[] = { 763 SHIKRA_SLAVE_ANOC_SNOC, 764 }; 765 766 static struct qcom_icc_node xm_emac_1 = { 767 .id = SHIKRA_MASTER_EMAC_1, 768 .name = "xm_emac_1", 769 .buswidth = 8, 770 .qos.ap_owned = true, 771 .qos.qos_port = 20, 772 .qos.urg_fwd_en = false, 773 .qos.qos_mode = NOC_QOS_MODE_FIXED, 774 .qos.areq_prio = 2, 775 .mas_rpm_id = -1, 776 .slv_rpm_id = -1, 777 .num_links = ARRAY_SIZE(xm_emac_1_links), 778 .links = xm_emac_1_links, 779 }; 780 781 static const u16 xm_qdss_etr_links[] = { 782 SHIKRA_SLAVE_ANOC_SNOC, 783 }; 784 785 static struct qcom_icc_node xm_qdss_etr = { 786 .id = SHIKRA_MASTER_QDSS_ETR, 787 .name = "xm_qdss_etr", 788 .buswidth = 8, 789 .qos.ap_owned = true, 790 .qos.qos_port = 11, 791 .qos.urg_fwd_en = false, 792 .qos.qos_mode = NOC_QOS_MODE_FIXED, 793 .qos.areq_prio = 2, 794 .mas_rpm_id = -1, 795 .slv_rpm_id = -1, 796 .num_links = ARRAY_SIZE(xm_qdss_etr_links), 797 .links = xm_qdss_etr_links, 798 }; 799 800 static const u16 xm_sdc1_links[] = { 801 SHIKRA_SLAVE_ANOC_SNOC, 802 }; 803 804 static struct qcom_icc_node xm_sdc1 = { 805 .id = SHIKRA_MASTER_SDCC_1, 806 .name = "xm_sdc1", 807 .buswidth = 8, 808 .qos.ap_owned = true, 809 .qos.qos_port = 13, 810 .qos.urg_fwd_en = false, 811 .qos.qos_mode = NOC_QOS_MODE_FIXED, 812 .qos.areq_prio = 2, 813 .mas_rpm_id = -1, 814 .slv_rpm_id = -1, 815 .num_links = ARRAY_SIZE(xm_sdc1_links), 816 .links = xm_sdc1_links, 817 }; 818 819 static const u16 xm_sdc2_links[] = { 820 SHIKRA_SLAVE_ANOC_SNOC, 821 }; 822 823 static struct qcom_icc_node xm_sdc2 = { 824 .id = SHIKRA_MASTER_SDCC_2, 825 .name = "xm_sdc2", 826 .buswidth = 8, 827 .qos.ap_owned = true, 828 .qos.qos_port = 17, 829 .qos.urg_fwd_en = false, 830 .qos.qos_mode = NOC_QOS_MODE_FIXED, 831 .qos.areq_prio = 2, 832 .mas_rpm_id = -1, 833 .slv_rpm_id = -1, 834 .num_links = ARRAY_SIZE(xm_sdc2_links), 835 .links = xm_sdc2_links, 836 }; 837 838 static const u16 xm_usb2_0_links[] = { 839 SHIKRA_SLAVE_ANOC_SNOC, 840 }; 841 842 static struct qcom_icc_node xm_usb2_0 = { 843 .id = SHIKRA_MASTER_USB2_0, 844 .name = "xm_usb2_0", 845 .buswidth = 8, 846 .qos.ap_owned = true, 847 .qos.qos_port = 24, 848 .qos.urg_fwd_en = false, 849 .qos.qos_mode = NOC_QOS_MODE_FIXED, 850 .qos.areq_prio = 2, 851 .mas_rpm_id = -1, 852 .slv_rpm_id = -1, 853 .num_links = ARRAY_SIZE(xm_usb2_0_links), 854 .links = xm_usb2_0_links, 855 }; 856 857 static const u16 xm_usb3_0_links[] = { 858 SHIKRA_SLAVE_ANOC_SNOC, 859 }; 860 861 static struct qcom_icc_node xm_usb3_0 = { 862 .id = SHIKRA_MASTER_USB3, 863 .name = "xm_usb3_0", 864 .buswidth = 8, 865 .qos.ap_owned = true, 866 .qos.qos_port = 18, 867 .qos.urg_fwd_en = false, 868 .qos.qos_mode = NOC_QOS_MODE_FIXED, 869 .qos.areq_prio = 2, 870 .mas_rpm_id = -1, 871 .slv_rpm_id = -1, 872 .num_links = ARRAY_SIZE(xm_usb3_0_links), 873 .links = xm_usb3_0_links, 874 }; 875 876 static const u16 crypto_c0_links[] = { 877 SHIKRA_SLAVE_ANOC_SNOC, 878 }; 879 880 static struct qcom_icc_node crypto_c0 = { 881 .id = SHIKRA_MASTER_CRYPTO_CORE0, 882 .name = "crypto_c0", 883 .buswidth = 8, 884 .qos.ap_owned = true, 885 .qos.qos_port = 16, 886 .qos.urg_fwd_en = false, 887 .qos.qos_mode = NOC_QOS_MODE_FIXED, 888 .qos.areq_prio = 2, 889 .mas_rpm_id = 23, 890 .slv_rpm_id = -1, 891 .num_links = ARRAY_SIZE(crypto_c0_links), 892 .links = crypto_c0_links, 893 }; 894 895 /* Slave nodes */ 896 static struct qcom_icc_node qup0_core_slave = { 897 .id = SHIKRA_SLAVE_QUP_CORE_0, 898 .name = "qup0_core_slave", 899 .channels = 1, 900 .buswidth = 4, 901 .mas_rpm_id = -1, 902 .slv_rpm_id = 264, 903 }; 904 905 static struct qcom_icc_node qhs_ahb2phy_usb = { 906 .id = SHIKRA_SLAVE_AHB2PHY_USB, 907 .name = "qhs_ahb2phy_usb", 908 .channels = 1, 909 .buswidth = 4, 910 .mas_rpm_id = -1, 911 .slv_rpm_id = -1, 912 }; 913 914 static struct qcom_icc_node qhs_apss_throttle_cfg = { 915 .id = SHIKRA_SLAVE_APSS_THROTTLE_CFG, 916 .name = "qhs_apss_throttle_cfg", 917 .channels = 1, 918 .buswidth = 4, 919 .mas_rpm_id = -1, 920 .slv_rpm_id = -1, 921 }; 922 923 static struct qcom_icc_node qhs_audio = { 924 .id = SHIKRA_SLAVE_AUDIO, 925 .name = "qhs_audio", 926 .channels = 1, 927 .buswidth = 4, 928 .mas_rpm_id = -1, 929 .slv_rpm_id = -1, 930 }; 931 932 static struct qcom_icc_node qhs_boot_rom = { 933 .id = SHIKRA_SLAVE_BOOT_ROM, 934 .name = "qhs_boot_rom", 935 .channels = 1, 936 .buswidth = 4, 937 .mas_rpm_id = -1, 938 .slv_rpm_id = -1, 939 }; 940 941 static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = { 942 .id = SHIKRA_SLAVE_CAMERA_NRT_THROTTLE_CFG, 943 .name = "qhs_camera_nrt_throttle_cfg", 944 .channels = 1, 945 .buswidth = 4, 946 .mas_rpm_id = -1, 947 .slv_rpm_id = -1, 948 }; 949 950 static struct qcom_icc_node qhs_camera_ss_cfg = { 951 .id = SHIKRA_SLAVE_CAMERA_CFG, 952 .name = "qhs_camera_ss_cfg", 953 .channels = 1, 954 .buswidth = 4, 955 .mas_rpm_id = -1, 956 .slv_rpm_id = -1, 957 }; 958 959 static struct qcom_icc_node qhs_cdsp_throttle_cfg = { 960 .id = SHIKRA_SLAVE_CDSP_THROTTLE_CFG, 961 .name = "qhs_cdsp_throttle_cfg", 962 .channels = 1, 963 .buswidth = 4, 964 .mas_rpm_id = -1, 965 .slv_rpm_id = -1, 966 }; 967 968 static struct qcom_icc_node qhs_clk_ctl = { 969 .id = SHIKRA_SLAVE_CLK_CTL, 970 .name = "qhs_clk_ctl", 971 .channels = 1, 972 .buswidth = 4, 973 .mas_rpm_id = -1, 974 .slv_rpm_id = -1, 975 }; 976 977 static struct qcom_icc_node qhs_compute_dsp_cfg = { 978 .id = SHIKRA_SLAVE_DSP_CFG, 979 .name = "qhs_compute_dsp_cfg", 980 .channels = 1, 981 .buswidth = 4, 982 .mas_rpm_id = -1, 983 .slv_rpm_id = -1, 984 }; 985 986 static struct qcom_icc_node qhs_cpr_cx = { 987 .id = SHIKRA_SLAVE_RBCPR_CX_CFG, 988 .name = "qhs_cpr_cx", 989 .channels = 1, 990 .buswidth = 4, 991 .mas_rpm_id = -1, 992 .slv_rpm_id = -1, 993 }; 994 995 static struct qcom_icc_node qhs_cpr_mx = { 996 .id = SHIKRA_SLAVE_RBCPR_MX_CFG, 997 .name = "qhs_cpr_mx", 998 .channels = 1, 999 .buswidth = 4, 1000 .mas_rpm_id = -1, 1001 .slv_rpm_id = -1, 1002 }; 1003 1004 static struct qcom_icc_node qhs_crypto0_cfg = { 1005 .id = SHIKRA_SLAVE_CRYPTO_0_CFG, 1006 .name = "qhs_crypto0_cfg", 1007 .channels = 1, 1008 .buswidth = 4, 1009 .mas_rpm_id = -1, 1010 .slv_rpm_id = -1, 1011 }; 1012 1013 static struct qcom_icc_node qhs_ddr_ss_cfg = { 1014 .id = SHIKRA_SLAVE_DDR_SS_CFG, 1015 .name = "qhs_ddr_ss_cfg", 1016 .channels = 1, 1017 .buswidth = 4, 1018 .mas_rpm_id = -1, 1019 .slv_rpm_id = -1, 1020 }; 1021 1022 static struct qcom_icc_node qhs_disp_ss_cfg = { 1023 .id = SHIKRA_SLAVE_DISPLAY_CFG, 1024 .name = "qhs_disp_ss_cfg", 1025 .channels = 1, 1026 .buswidth = 4, 1027 .mas_rpm_id = -1, 1028 .slv_rpm_id = -1, 1029 }; 1030 1031 static struct qcom_icc_node qhs_emac0_cfg = { 1032 .id = SHIKRA_SLAVE_EMAC0_CFG, 1033 .name = "qhs_emac0_cfg", 1034 .channels = 1, 1035 .buswidth = 4, 1036 .mas_rpm_id = -1, 1037 .slv_rpm_id = -1, 1038 }; 1039 1040 static struct qcom_icc_node qhs_emac1_cfg = { 1041 .id = SHIKRA_SLAVE_EMAC1_CFG, 1042 .name = "qhs_emac1_cfg", 1043 .channels = 1, 1044 .buswidth = 4, 1045 .mas_rpm_id = -1, 1046 .slv_rpm_id = -1, 1047 }; 1048 1049 static struct qcom_icc_node qhs_gpu_cfg = { 1050 .id = SHIKRA_SLAVE_GPU_CFG, 1051 .name = "qhs_gpu_cfg", 1052 .channels = 1, 1053 .buswidth = 8, 1054 .mas_rpm_id = -1, 1055 .slv_rpm_id = -1, 1056 }; 1057 1058 static struct qcom_icc_node qhs_gpu_throttle_cfg = { 1059 .id = SHIKRA_SLAVE_GPU_THROTTLE_CFG, 1060 .name = "qhs_gpu_throttle_cfg", 1061 .channels = 1, 1062 .buswidth = 4, 1063 .mas_rpm_id = -1, 1064 .slv_rpm_id = -1, 1065 }; 1066 1067 static struct qcom_icc_node qhs_hwkm = { 1068 .id = SHIKRA_SLAVE_HWKM, 1069 .name = "qhs_hwkm", 1070 .channels = 1, 1071 .buswidth = 4, 1072 .mas_rpm_id = -1, 1073 .slv_rpm_id = -1, 1074 }; 1075 1076 static struct qcom_icc_node qhs_imem_cfg = { 1077 .id = SHIKRA_SLAVE_IMEM_CFG, 1078 .name = "qhs_imem_cfg", 1079 .channels = 1, 1080 .buswidth = 4, 1081 .mas_rpm_id = -1, 1082 .slv_rpm_id = -1, 1083 }; 1084 1085 static struct qcom_icc_node qhs_mapss = { 1086 .id = SHIKRA_SLAVE_MAPSS, 1087 .name = "qhs_mapss", 1088 .channels = 1, 1089 .buswidth = 4, 1090 .mas_rpm_id = -1, 1091 .slv_rpm_id = -1, 1092 }; 1093 1094 static struct qcom_icc_node qhs_mdsp_mpu_cfg = { 1095 .id = SHIKRA_SLAVE_MDSP_MPU_CFG, 1096 .name = "qhs_mdsp_mpu_cfg", 1097 .channels = 1, 1098 .buswidth = 4, 1099 .mas_rpm_id = -1, 1100 .slv_rpm_id = -1, 1101 }; 1102 1103 static struct qcom_icc_node qhs_mesg_ram = { 1104 .id = SHIKRA_SLAVE_MESSAGE_RAM, 1105 .name = "qhs_mesg_ram", 1106 .channels = 1, 1107 .buswidth = 4, 1108 .mas_rpm_id = -1, 1109 .slv_rpm_id = -1, 1110 }; 1111 1112 static struct qcom_icc_node qhs_mss = { 1113 .id = SHIKRA_SLAVE_MSS, 1114 .name = "qhs_mss", 1115 .channels = 1, 1116 .buswidth = 4, 1117 .mas_rpm_id = -1, 1118 .slv_rpm_id = -1, 1119 }; 1120 1121 static struct qcom_icc_node qhs_pcie_cfg = { 1122 .id = SHIKRA_SLAVE_PCIE_CFG, 1123 .name = "qhs_pcie_cfg", 1124 .channels = 1, 1125 .buswidth = 4, 1126 .mas_rpm_id = -1, 1127 .slv_rpm_id = -1, 1128 }; 1129 1130 static struct qcom_icc_node qhs_pdm = { 1131 .id = SHIKRA_SLAVE_PDM, 1132 .name = "qhs_pdm", 1133 .channels = 1, 1134 .buswidth = 4, 1135 .mas_rpm_id = -1, 1136 .slv_rpm_id = -1, 1137 }; 1138 1139 static struct qcom_icc_node qhs_pimem_cfg = { 1140 .id = SHIKRA_SLAVE_PIMEM_CFG, 1141 .name = "qhs_pimem_cfg", 1142 .channels = 1, 1143 .buswidth = 4, 1144 .mas_rpm_id = -1, 1145 .slv_rpm_id = -1, 1146 }; 1147 1148 static struct qcom_icc_node qhs_pka_wrapper = { 1149 .id = SHIKRA_SLAVE_PKA_WRAPPER_CFG, 1150 .name = "qhs_pka_wrapper", 1151 .channels = 1, 1152 .buswidth = 4, 1153 .mas_rpm_id = -1, 1154 .slv_rpm_id = -1, 1155 }; 1156 1157 static struct qcom_icc_node qhs_pmic_arb = { 1158 .id = SHIKRA_SLAVE_PMIC_ARB, 1159 .name = "qhs_pmic_arb", 1160 .channels = 1, 1161 .buswidth = 4, 1162 .mas_rpm_id = -1, 1163 .slv_rpm_id = -1, 1164 }; 1165 1166 static struct qcom_icc_node qhs_qdss_cfg = { 1167 .id = SHIKRA_SLAVE_QDSS_CFG, 1168 .name = "qhs_qdss_cfg", 1169 .channels = 1, 1170 .buswidth = 4, 1171 .mas_rpm_id = -1, 1172 .slv_rpm_id = -1, 1173 }; 1174 1175 static struct qcom_icc_node qhs_qm_cfg = { 1176 .id = SHIKRA_SLAVE_QM_CFG, 1177 .name = "qhs_qm_cfg", 1178 .channels = 1, 1179 .buswidth = 4, 1180 .mas_rpm_id = -1, 1181 .slv_rpm_id = -1, 1182 }; 1183 1184 static struct qcom_icc_node qhs_qm_mpu_cfg = { 1185 .id = SHIKRA_SLAVE_QM_MPU_CFG, 1186 .name = "qhs_qm_mpu_cfg", 1187 .channels = 1, 1188 .buswidth = 4, 1189 .mas_rpm_id = -1, 1190 .slv_rpm_id = -1, 1191 }; 1192 1193 static struct qcom_icc_node qhs_qpic = { 1194 .id = SHIKRA_SLAVE_QPIC, 1195 .name = "qhs_qpic", 1196 .channels = 1, 1197 .buswidth = 4, 1198 .mas_rpm_id = -1, 1199 .slv_rpm_id = -1, 1200 }; 1201 1202 static struct qcom_icc_node qhs_qup0 = { 1203 .id = SHIKRA_SLAVE_QUP_0, 1204 .name = "qhs_qup0", 1205 .channels = 1, 1206 .buswidth = 4, 1207 .mas_rpm_id = -1, 1208 .slv_rpm_id = -1, 1209 }; 1210 1211 static struct qcom_icc_node qhs_rpm = { 1212 .id = SHIKRA_SLAVE_RPM, 1213 .name = "qhs_rpm", 1214 .channels = 1, 1215 .buswidth = 4, 1216 .mas_rpm_id = -1, 1217 .slv_rpm_id = -1, 1218 }; 1219 1220 static struct qcom_icc_node qhs_sdc1 = { 1221 .id = SHIKRA_SLAVE_SDCC_1, 1222 .name = "qhs_sdc1", 1223 .channels = 1, 1224 .buswidth = 4, 1225 .mas_rpm_id = -1, 1226 .slv_rpm_id = -1, 1227 }; 1228 1229 static struct qcom_icc_node qhs_sdc2 = { 1230 .id = SHIKRA_SLAVE_SDCC_2, 1231 .name = "qhs_sdc2", 1232 .channels = 1, 1233 .buswidth = 4, 1234 .mas_rpm_id = -1, 1235 .slv_rpm_id = -1, 1236 }; 1237 1238 static struct qcom_icc_node qhs_security = { 1239 .id = SHIKRA_SLAVE_SECURITY, 1240 .name = "qhs_security", 1241 .channels = 1, 1242 .buswidth = 4, 1243 .mas_rpm_id = -1, 1244 .slv_rpm_id = -1, 1245 }; 1246 1247 static const u16 qhs_snoc_cfg_links[] = { 1248 SHIKRA_MASTER_SNOC_CFG, 1249 }; 1250 1251 static struct qcom_icc_node qhs_snoc_cfg = { 1252 .id = SHIKRA_SLAVE_SNOC_CFG, 1253 .name = "qhs_snoc_cfg", 1254 .channels = 1, 1255 .buswidth = 4, 1256 .mas_rpm_id = -1, 1257 .slv_rpm_id = -1, 1258 .num_links = 1, 1259 .links = qhs_snoc_cfg_links, 1260 }; 1261 1262 static struct qcom_icc_node qhs_snoc_sf_throttle_cfg = { 1263 .id = SHIKRA_SNOC_SF_THROTTLE_CFG, 1264 .name = "qhs_snoc_sf_throttle_cfg", 1265 .channels = 1, 1266 .buswidth = 4, 1267 .mas_rpm_id = -1, 1268 .slv_rpm_id = -1, 1269 }; 1270 1271 static struct qcom_icc_node qhs_tlmm = { 1272 .id = SHIKRA_SLAVE_TLMM, 1273 .name = "qhs_tlmm", 1274 .channels = 1, 1275 .buswidth = 4, 1276 .mas_rpm_id = -1, 1277 .slv_rpm_id = -1, 1278 }; 1279 1280 static struct qcom_icc_node qhs_tscss = { 1281 .id = SHIKRA_SLAVE_TSCSS, 1282 .name = "qhs_tscss", 1283 .channels = 1, 1284 .buswidth = 4, 1285 .mas_rpm_id = -1, 1286 .slv_rpm_id = -1, 1287 }; 1288 1289 static struct qcom_icc_node qhs_usb2 = { 1290 .id = SHIKRA_SLAVE_USB2, 1291 .name = "qhs_usb2", 1292 .channels = 1, 1293 .buswidth = 4, 1294 .mas_rpm_id = -1, 1295 .slv_rpm_id = -1, 1296 }; 1297 1298 static struct qcom_icc_node qhs_usb3 = { 1299 .id = SHIKRA_SLAVE_USB3, 1300 .name = "qhs_usb3", 1301 .channels = 1, 1302 .buswidth = 4, 1303 .mas_rpm_id = -1, 1304 .slv_rpm_id = -1, 1305 }; 1306 1307 static struct qcom_icc_node qhs_venus_cfg = { 1308 .id = SHIKRA_SLAVE_VENUS_CFG, 1309 .name = "qhs_venus_cfg", 1310 .channels = 1, 1311 .buswidth = 4, 1312 .mas_rpm_id = -1, 1313 .slv_rpm_id = -1, 1314 }; 1315 1316 static struct qcom_icc_node qhs_venus_throttle_cfg = { 1317 .id = SHIKRA_SLAVE_VENUS_THROTTLE_CFG, 1318 .name = "qhs_venus_throttle_cfg", 1319 .channels = 1, 1320 .buswidth = 4, 1321 .mas_rpm_id = -1, 1322 .slv_rpm_id = -1, 1323 }; 1324 1325 static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 1326 .id = SHIKRA_SLAVE_VSENSE_CTRL_CFG, 1327 .name = "qhs_vsense_ctrl_cfg", 1328 .channels = 1, 1329 .buswidth = 4, 1330 .mas_rpm_id = -1, 1331 .slv_rpm_id = -1, 1332 }; 1333 1334 static struct qcom_icc_node srvc_cnoc = { 1335 .id = SHIKRA_SLAVE_SERVICE_CNOC, 1336 .name = "srvc_cnoc", 1337 .channels = 1, 1338 .buswidth = 4, 1339 .mas_rpm_id = -1, 1340 .slv_rpm_id = -1, 1341 }; 1342 1343 static struct qcom_icc_node ebi = { 1344 .id = SHIKRA_SLAVE_EBI_CH0, 1345 .name = "ebi", 1346 .channels = 2, 1347 .buswidth = 4, 1348 .mas_rpm_id = -1, 1349 .slv_rpm_id = 0, 1350 }; 1351 1352 static const u16 qns_llcc_links[] = { 1353 SHIKRA_MASTER_LLCC, 1354 }; 1355 1356 static struct qcom_icc_node qns_llcc = { 1357 .id = SHIKRA_SLAVE_LLCC, 1358 .name = "qns_llcc", 1359 .channels = 2, 1360 .buswidth = 16, 1361 .mas_rpm_id = -1, 1362 .slv_rpm_id = 312, 1363 .num_links = 1, 1364 .links = qns_llcc_links, 1365 }; 1366 1367 static const u16 qns_memnoc_snoc_links[] = { 1368 SHIKRA_MASTER_MEMNOC_SNOC, 1369 }; 1370 1371 static struct qcom_icc_node qns_memnoc_snoc = { 1372 .id = SHIKRA_SLAVE_MEMNOC_SNOC, 1373 .name = "qns_memnoc_snoc", 1374 .channels = 1, 1375 .buswidth = 8, 1376 .mas_rpm_id = -1, 1377 .slv_rpm_id = 314, 1378 .num_links = 1, 1379 .links = qns_memnoc_snoc_links, 1380 }; 1381 1382 static const u16 qns_pcie_links[] = { 1383 SHIKRA_MASTER_MEMNOC_PCIE, 1384 }; 1385 1386 static struct qcom_icc_node qns_pcie = { 1387 .id = SHIKRA_SLAVE_MEM_NOC_PCIE_SNOC, 1388 .name = "qns_pcie", 1389 .channels = 1, 1390 .buswidth = 8, 1391 .mas_rpm_id = -1, 1392 .slv_rpm_id = -1, 1393 .num_links = 1, 1394 .links = qns_pcie_links, 1395 }; 1396 1397 static const u16 mmnrt_virt_slave_links[] = { 1398 SHIKRA_MASTER_MMRT_VIRT, 1399 }; 1400 1401 static struct qcom_icc_node mmnrt_virt_slave = { 1402 .id = SHIKRA_SLAVE_MMNRT_VIRT, 1403 .name = "mmnrt_virt_slave", 1404 .channels = 1, 1405 .buswidth = 16, 1406 .mas_rpm_id = -1, 1407 .slv_rpm_id = -1, 1408 .num_links = 1, 1409 .links = mmnrt_virt_slave_links, 1410 }; 1411 1412 static const u16 qns_mm_memnoc_links[] = { 1413 SHIKRA_MASTER_MNOC_HF_MEM_NOC, 1414 }; 1415 1416 static struct qcom_icc_node qns_mm_memnoc = { 1417 .id = SHIKRA_SLAVE_MM_MEMNOC, 1418 .name = "qns_mm_memnoc", 1419 .channels = 1, 1420 .buswidth = 16, 1421 .mas_rpm_id = -1, 1422 .slv_rpm_id = -1, 1423 .num_links = 1, 1424 .links = qns_mm_memnoc_links, 1425 }; 1426 1427 static struct qcom_icc_node qhs_apss = { 1428 .id = SHIKRA_SLAVE_APPSS, 1429 .name = "qhs_apss", 1430 .channels = 1, 1431 .buswidth = 8, 1432 .mas_rpm_id = -1, 1433 .slv_rpm_id = -1, 1434 }; 1435 1436 static struct qcom_icc_node qhs_mcuss = { 1437 .id = SHIKRA_SLAVE_MCUSS, 1438 .name = "qhs_mcuss", 1439 .channels = 1, 1440 .buswidth = 4, 1441 .mas_rpm_id = -1, 1442 .slv_rpm_id = 319, 1443 }; 1444 1445 static struct qcom_icc_node qhs_wcss = { 1446 .id = SHIKRA_SLAVE_WCSS, 1447 .name = "qhs_wcss", 1448 .channels = 1, 1449 .buswidth = 4, 1450 .mas_rpm_id = -1, 1451 .slv_rpm_id = 23, 1452 }; 1453 1454 static const u16 qns_memnoc_sf_links[] = { 1455 SHIKRA_MASTER_SNOC_SF_MEM_NOC, 1456 }; 1457 1458 static struct qcom_icc_node qns_memnoc_sf = { 1459 .id = SHIKRA_SLAVE_MEMNOC_SF, 1460 .name = "qns_memnoc_sf", 1461 .channels = 1, 1462 .buswidth = 16, 1463 .mas_rpm_id = -1, 1464 .slv_rpm_id = 313, 1465 .num_links = 1, 1466 .links = qns_memnoc_sf_links, 1467 }; 1468 1469 static const u16 qns_snoc_cnoc_links[] = { 1470 SHIKRA_SNOC_CNOC_MAS, 1471 }; 1472 1473 static struct qcom_icc_node qns_snoc_cnoc = { 1474 .id = SHIKRA_SNOC_CNOC_SLV, 1475 .name = "qns_snoc_cnoc", 1476 .channels = 1, 1477 .buswidth = 8, 1478 .mas_rpm_id = -1, 1479 .slv_rpm_id = 25, 1480 .num_links = 1, 1481 .links = qns_snoc_cnoc_links, 1482 }; 1483 1484 static struct qcom_icc_node qxs_bootimem = { 1485 .id = SHIKRA_SLAVE_BOOTIMEM, 1486 .name = "qxs_bootimem", 1487 .channels = 1, 1488 .buswidth = 8, 1489 .mas_rpm_id = -1, 1490 .slv_rpm_id = -1, 1491 }; 1492 1493 static struct qcom_icc_node qxs_imem = { 1494 .id = SHIKRA_SLAVE_OCIMEM, 1495 .name = "qxs_imem", 1496 .channels = 1, 1497 .buswidth = 8, 1498 .mas_rpm_id = -1, 1499 .slv_rpm_id = 26, 1500 }; 1501 1502 static struct qcom_icc_node qxs_pimem = { 1503 .id = SHIKRA_SLAVE_PIMEM, 1504 .name = "qxs_pimem", 1505 .channels = 1, 1506 .buswidth = 8, 1507 .mas_rpm_id = -1, 1508 .slv_rpm_id = -1, 1509 }; 1510 1511 static struct qcom_icc_node srvc_snoc = { 1512 .id = SHIKRA_SLAVE_SERVICE_SNOC, 1513 .name = "srvc_snoc", 1514 .channels = 1, 1515 .buswidth = 4, 1516 .mas_rpm_id = -1, 1517 .slv_rpm_id = -1, 1518 }; 1519 1520 static struct qcom_icc_node xs_pcie2_0 = { 1521 .id = SHIKRA_SLAVE_PCIE2_0, 1522 .name = "xs_pcie2_0", 1523 .channels = 1, 1524 .buswidth = 8, 1525 .mas_rpm_id = -1, 1526 .slv_rpm_id = -1, 1527 }; 1528 1529 static struct qcom_icc_node xs_qdss_stm = { 1530 .id = SHIKRA_SLAVE_QDSS_STM, 1531 .name = "xs_qdss_stm", 1532 .channels = 1, 1533 .buswidth = 4, 1534 .mas_rpm_id = -1, 1535 .slv_rpm_id = 30, 1536 }; 1537 1538 static struct qcom_icc_node xs_sys_tcu_cfg = { 1539 .id = SHIKRA_SLAVE_TCU, 1540 .name = "xs_sys_tcu_cfg", 1541 .channels = 1, 1542 .buswidth = 8, 1543 .mas_rpm_id = -1, 1544 .slv_rpm_id = -1, 1545 }; 1546 1547 static const u16 qns_pcie_memnoc_links[] = { 1548 SHIKRA_MASTER_ANOC_PCIE_MEM_NOC, 1549 }; 1550 1551 static struct qcom_icc_node qns_pcie_memnoc = { 1552 .id = SHIKRA_SLAVE_PCIE_MEMNOC, 1553 .name = "qns_pcie_memnoc", 1554 .channels = 1, 1555 .buswidth = 8, 1556 .mas_rpm_id = -1, 1557 .slv_rpm_id = 317, 1558 .num_links = 1, 1559 .links = qns_pcie_memnoc_links, 1560 }; 1561 1562 static const u16 qns_anoc_snoc_links[] = { 1563 SHIKRA_MASTER_ANOC_SNOC, 1564 }; 1565 1566 static struct qcom_icc_node qns_anoc_snoc = { 1567 .id = SHIKRA_SLAVE_ANOC_SNOC, 1568 .name = "qns_anoc_snoc", 1569 .channels = 1, 1570 .buswidth = 16, 1571 .mas_rpm_id = -1, 1572 .slv_rpm_id = 141, 1573 .num_links = 1, 1574 .links = qns_anoc_snoc_links, 1575 }; 1576 1577 /* NoC descriptors */ 1578 static struct qcom_icc_node * const shikra_clk_virt_nodes[] = { 1579 [MASTER_QUP_CORE_0] = &qup0_core_master, 1580 [SLAVE_QUP_CORE_0] = &qup0_core_slave, 1581 }; 1582 1583 static const struct qcom_icc_desc shikra_clk_virt = { 1584 .type = QCOM_ICC_QNOC, 1585 .nodes = shikra_clk_virt_nodes, 1586 .num_nodes = ARRAY_SIZE(shikra_clk_virt_nodes), 1587 .bus_clk_desc = &qup_clk, 1588 .keep_alive = true, 1589 }; 1590 1591 static struct qcom_icc_node * const shikra_config_noc_nodes[] = { 1592 [SNOC_CNOC_MAS] = &qnm_snoc_cnoc, 1593 [MASTER_QDSS_DAP] = &xm_dap, 1594 [SLAVE_AHB2PHY_USB] = &qhs_ahb2phy_usb, 1595 [SLAVE_APSS_THROTTLE_CFG] = &qhs_apss_throttle_cfg, 1596 [SLAVE_AUDIO] = &qhs_audio, 1597 [SLAVE_BOOT_ROM] = &qhs_boot_rom, 1598 [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_throttle_cfg, 1599 [SLAVE_CAMERA_CFG] = &qhs_camera_ss_cfg, 1600 [SLAVE_CDSP_THROTTLE_CFG] = &qhs_cdsp_throttle_cfg, 1601 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1602 [SLAVE_DSP_CFG] = &qhs_compute_dsp_cfg, 1603 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 1604 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, 1605 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1606 [SLAVE_DDR_SS_CFG] = &qhs_ddr_ss_cfg, 1607 [SLAVE_DISPLAY_CFG] = &qhs_disp_ss_cfg, 1608 [SLAVE_EMAC0_CFG] = &qhs_emac0_cfg, 1609 [SLAVE_EMAC1_CFG] = &qhs_emac1_cfg, 1610 [SLAVE_GPU_CFG] = &qhs_gpu_cfg, 1611 [SLAVE_GPU_THROTTLE_CFG] = &qhs_gpu_throttle_cfg, 1612 [SLAVE_HWKM] = &qhs_hwkm, 1613 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1614 [SLAVE_MAPSS] = &qhs_mapss, 1615 [SLAVE_MDSP_MPU_CFG] = &qhs_mdsp_mpu_cfg, 1616 [SLAVE_MESSAGE_RAM] = &qhs_mesg_ram, 1617 [SLAVE_MSS] = &qhs_mss, 1618 [SLAVE_PCIE_CFG] = &qhs_pcie_cfg, 1619 [SLAVE_PDM] = &qhs_pdm, 1620 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 1621 [SLAVE_PKA_WRAPPER_CFG] = &qhs_pka_wrapper, 1622 [SLAVE_PMIC_ARB] = &qhs_pmic_arb, 1623 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1624 [SLAVE_QM_CFG] = &qhs_qm_cfg, 1625 [SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg, 1626 [SLAVE_QPIC] = &qhs_qpic, 1627 [SLAVE_QUP_0] = &qhs_qup0, 1628 [SLAVE_RPM] = &qhs_rpm, 1629 [SLAVE_SDCC_1] = &qhs_sdc1, 1630 [SLAVE_SDCC_2] = &qhs_sdc2, 1631 [SLAVE_SECURITY] = &qhs_security, 1632 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, 1633 [SNOC_SF_THROTTLE_CFG] = &qhs_snoc_sf_throttle_cfg, 1634 [SLAVE_TLMM] = &qhs_tlmm, 1635 [SLAVE_TSCSS] = &qhs_tscss, 1636 [SLAVE_USB2] = &qhs_usb2, 1637 [SLAVE_USB3] = &qhs_usb3, 1638 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1639 [SLAVE_VENUS_THROTTLE_CFG] = &qhs_venus_throttle_cfg, 1640 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 1641 [SLAVE_SERVICE_CNOC] = &srvc_cnoc, 1642 }; 1643 1644 static const struct regmap_config shikra_config_noc_regmap_config = { 1645 .reg_bits = 32, 1646 .reg_stride = 4, 1647 .val_bits = 32, 1648 .max_register = 0x8080, 1649 .fast_io = true, 1650 }; 1651 1652 static const struct qcom_icc_desc shikra_config_noc = { 1653 .type = QCOM_ICC_QNOC, 1654 .nodes = shikra_config_noc_nodes, 1655 .num_nodes = ARRAY_SIZE(shikra_config_noc_nodes), 1656 .bus_clk_desc = &bus_1_clk, 1657 .regmap_cfg = &shikra_config_noc_regmap_config, 1658 .keep_alive = true, 1659 }; 1660 1661 static struct qcom_icc_node * const shikra_mc_virt_nodes[] = { 1662 [MASTER_LLCC] = &llcc_mc, 1663 [SLAVE_EBI_CH0] = &ebi, 1664 }; 1665 1666 static const struct qcom_icc_desc shikra_mc_virt = { 1667 .type = QCOM_ICC_QNOC, 1668 .nodes = shikra_mc_virt_nodes, 1669 .num_nodes = ARRAY_SIZE(shikra_mc_virt_nodes), 1670 .bus_clk_desc = &bimc_clk, 1671 .keep_alive = true, 1672 .ab_coeff = 152, 1673 }; 1674 1675 static struct qcom_icc_node * const shikra_mem_noc_core_nodes[] = { 1676 [MASTER_GRAPHICS_3D] = &qnm_gpu, 1677 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 1678 [MASTER_ANOC_PCIE_MEM_NOC] = &qnm_pcie, 1679 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 1680 [MASTER_AMPSS_M0] = &xm_apps, 1681 [MASTER_SYS_TCU] = &xm_tcu, 1682 [SLAVE_LLCC] = &qns_llcc, 1683 [SLAVE_MEMNOC_SNOC] = &qns_memnoc_snoc, 1684 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, 1685 }; 1686 1687 static const struct regmap_config shikra_mem_noc_core_regmap_config = { 1688 .reg_bits = 32, 1689 .reg_stride = 4, 1690 .val_bits = 32, 1691 .max_register = 0x43080, 1692 .fast_io = true, 1693 }; 1694 1695 static const struct qcom_icc_desc shikra_mem_noc_core = { 1696 .type = QCOM_ICC_QNOC, 1697 .nodes = shikra_mem_noc_core_nodes, 1698 .num_nodes = ARRAY_SIZE(shikra_mem_noc_core_nodes), 1699 .bus_clk_desc = &mem_1_clk, 1700 .regmap_cfg = &shikra_mem_noc_core_regmap_config, 1701 .intf_clocks = memnoc_intf_clocks, 1702 .num_intf_clocks = ARRAY_SIZE(memnoc_intf_clocks), 1703 .qos_offset = 0x28000, 1704 .keep_alive = true, 1705 .ab_coeff = 142, 1706 }; 1707 1708 static struct qcom_icc_node * const shikra_mmnrt_virt_nodes[] = { 1709 [MASTER_CAMNOC_SF] = &qnm_camera_nrt, 1710 [MASTER_VIDEO_P0] = &qxm_venus0, 1711 [MASTER_VIDEO_PROC] = &qxm_venus_cpu, 1712 [SLAVE_MMNRT_VIRT] = &mmnrt_virt_slave, 1713 }; 1714 1715 static const struct regmap_config shikra_sys_noc_regmap_config = { 1716 .reg_bits = 32, 1717 .reg_stride = 4, 1718 .val_bits = 32, 1719 .max_register = 0x6a080, 1720 .fast_io = true, 1721 }; 1722 1723 static const struct qcom_icc_desc shikra_mmnrt_virt = { 1724 .type = QCOM_ICC_QNOC, 1725 .nodes = shikra_mmnrt_virt_nodes, 1726 .num_nodes = ARRAY_SIZE(shikra_mmnrt_virt_nodes), 1727 .bus_clk_desc = &mmaxi_0_clk, 1728 .regmap_cfg = &shikra_sys_noc_regmap_config, 1729 .qos_offset = 0x51000, 1730 .keep_alive = true, 1731 .ab_coeff = 142, 1732 }; 1733 1734 static struct qcom_icc_node * const shikra_mmrt_virt_nodes[] = { 1735 [MASTER_CAMNOC_HF] = &qnm_camera_rt, 1736 [MASTER_MDP_PORT0] = &qxm_mdp0, 1737 [MASTER_MMRT_VIRT] = &mmrt_virt_master, 1738 [SLAVE_MM_MEMNOC] = &qns_mm_memnoc, 1739 }; 1740 1741 static const struct qcom_icc_desc shikra_mmrt_virt = { 1742 .type = QCOM_ICC_QNOC, 1743 .nodes = shikra_mmrt_virt_nodes, 1744 .num_nodes = ARRAY_SIZE(shikra_mmrt_virt_nodes), 1745 .bus_clk_desc = &mmaxi_1_clk, 1746 .regmap_cfg = &shikra_sys_noc_regmap_config, 1747 .qos_offset = 0x51000, 1748 .keep_alive = true, 1749 .ab_coeff = 142, 1750 }; 1751 1752 static struct qcom_icc_node * const shikra_sys_noc_nodes[] = { 1753 [MASTER_SNOC_CFG] = &qhm_snoc_cfg, 1754 [MASTER_TIC] = &qhm_tic, 1755 [MASTER_ANOC_SNOC] = &qnm_anoc_snoc, 1756 [MASTER_MEMNOC_PCIE] = &qnm_memnoc_pcie, 1757 [MASTER_MEMNOC_SNOC] = &qnm_memnoc_snoc, 1758 [MASTER_PIMEM] = &qxm_pimem, 1759 [MASTER_PCIE2_0] = &xm_pcie2_0, 1760 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 1761 [MASTER_QPIC] = &qhm_qpic, 1762 [MASTER_QUP_0] = &qhm_qup0, 1763 [CNOC_SNOC_MAS] = &qnm_cnoc_snoc, 1764 [MASTER_AUDIO] = &qxm_audio, 1765 [MASTER_EMAC_0] = &xm_emac_0, 1766 [MASTER_EMAC_1] = &xm_emac_1, 1767 [MASTER_QDSS_ETR] = &xm_qdss_etr, 1768 [MASTER_SDCC_1] = &xm_sdc1, 1769 [MASTER_SDCC_2] = &xm_sdc2, 1770 [MASTER_USB2_0] = &xm_usb2_0, 1771 [MASTER_USB3] = &xm_usb3_0, 1772 [MASTER_CRYPTO_CORE0] = &crypto_c0, 1773 [SLAVE_APPSS] = &qhs_apss, 1774 [SLAVE_MCUSS] = &qhs_mcuss, 1775 [SLAVE_WCSS] = &qhs_wcss, 1776 [SLAVE_MEMNOC_SF] = &qns_memnoc_sf, 1777 [SNOC_CNOC_SLV] = &qns_snoc_cnoc, 1778 [SLAVE_BOOTIMEM] = &qxs_bootimem, 1779 [SLAVE_OCIMEM] = &qxs_imem, 1780 [SLAVE_PIMEM] = &qxs_pimem, 1781 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 1782 [SLAVE_PCIE2_0] = &xs_pcie2_0, 1783 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1784 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1785 [SLAVE_PCIE_MEMNOC] = &qns_pcie_memnoc, 1786 [SLAVE_ANOC_SNOC] = &qns_anoc_snoc, 1787 }; 1788 1789 static const struct qcom_icc_desc shikra_sys_noc = { 1790 .type = QCOM_ICC_QNOC, 1791 .nodes = shikra_sys_noc_nodes, 1792 .num_nodes = ARRAY_SIZE(shikra_sys_noc_nodes), 1793 .bus_clk_desc = &bus_2_clk, 1794 .regmap_cfg = &shikra_sys_noc_regmap_config, 1795 .intf_clocks = sys_noc_intf_clocks, 1796 .num_intf_clocks = ARRAY_SIZE(sys_noc_intf_clocks), 1797 .qos_offset = 0x51000, 1798 .keep_alive = true, 1799 }; 1800 1801 static const struct of_device_id shikra_qnoc_of_match[] = { 1802 { .compatible = "qcom,shikra-clk-virt", .data = &shikra_clk_virt }, 1803 { .compatible = "qcom,shikra-config-noc", .data = &shikra_config_noc }, 1804 { .compatible = "qcom,shikra-mc-virt", .data = &shikra_mc_virt }, 1805 { .compatible = "qcom,shikra-mem-noc-core", .data = &shikra_mem_noc_core }, 1806 { .compatible = "qcom,shikra-mmnrt-virt", .data = &shikra_mmnrt_virt }, 1807 { .compatible = "qcom,shikra-mmrt-virt", .data = &shikra_mmrt_virt }, 1808 { .compatible = "qcom,shikra-sys-noc", .data = &shikra_sys_noc }, 1809 { }, 1810 }; 1811 MODULE_DEVICE_TABLE(of, shikra_qnoc_of_match); 1812 1813 static struct platform_driver shikra_qnoc_driver = { 1814 .probe = qnoc_probe, 1815 .remove = qnoc_remove, 1816 .driver = { 1817 .name = "qnoc-shikra", 1818 .of_match_table = shikra_qnoc_of_match, 1819 .sync_state = icc_sync_state, 1820 }, 1821 }; 1822 1823 static int __init qnoc_driver_init(void) 1824 { 1825 return platform_driver_register(&shikra_qnoc_driver); 1826 } 1827 core_initcall(qnoc_driver_init); 1828 1829 static void __exit qnoc_driver_exit(void) 1830 { 1831 platform_driver_unregister(&shikra_qnoc_driver); 1832 } 1833 module_exit(qnoc_driver_exit); 1834 1835 MODULE_DESCRIPTION("Qualcomm Shikra NoC driver"); 1836 MODULE_LICENSE("GPL"); 1837