1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 * 5 */ 6 7 #include <dt-bindings/interconnect/qcom,shikra.h> 8 #include <linux/device.h> 9 #include <linux/interconnect-provider.h> 10 #include <linux/io.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/module.h> 13 #include <linux/platform_device.h> 14 #include <linux/regmap.h> 15 16 #include "icc-rpm.h" 17 18 static const char * const sys_noc_intf_clocks[] = { 19 "emac0_axi", 20 "emac1_axi", 21 "usb2_axi", 22 "usb3_axi", 23 }; 24 25 static const char * const memnoc_intf_clocks[] = { 26 "gpu_axi", 27 }; 28 29 enum { 30 SHIKRA_MASTER_QUP_CORE_0 = 1, 31 SHIKRA_SNOC_CNOC_MAS, 32 SHIKRA_MASTER_QDSS_DAP, 33 SHIKRA_MASTER_LLCC, 34 SHIKRA_MASTER_GRAPHICS_3D, 35 SHIKRA_MASTER_MNOC_HF_MEM_NOC, 36 SHIKRA_MASTER_ANOC_PCIE_MEM_NOC, 37 SHIKRA_MASTER_SNOC_SF_MEM_NOC, 38 SHIKRA_MASTER_AMPSS_M0, 39 SHIKRA_MASTER_SYS_TCU, 40 SHIKRA_MASTER_CAMNOC_SF, 41 SHIKRA_MASTER_VIDEO_P0, 42 SHIKRA_MASTER_VIDEO_PROC, 43 SHIKRA_MASTER_CAMNOC_HF, 44 SHIKRA_MASTER_MDP_PORT0, 45 SHIKRA_MASTER_MMRT_VIRT, 46 SHIKRA_MASTER_SNOC_CFG, 47 SHIKRA_MASTER_TIC, 48 SHIKRA_MASTER_ANOC_SNOC, 49 SHIKRA_MASTER_MEMNOC_PCIE, 50 SHIKRA_MASTER_MEMNOC_SNOC, 51 SHIKRA_MASTER_PIMEM, 52 SHIKRA_MASTER_PCIE2_0, 53 SHIKRA_MASTER_QDSS_BAM, 54 SHIKRA_MASTER_QPIC, 55 SHIKRA_MASTER_QUP_0, 56 SHIKRA_CNOC_SNOC_MAS, 57 SHIKRA_MASTER_AUDIO, 58 SHIKRA_MASTER_EMAC_0, 59 SHIKRA_MASTER_EMAC_1, 60 SHIKRA_MASTER_QDSS_ETR, 61 SHIKRA_MASTER_SDCC_1, 62 SHIKRA_MASTER_SDCC_2, 63 SHIKRA_MASTER_USB2_0, 64 SHIKRA_MASTER_USB3, 65 SHIKRA_MASTER_CRYPTO_CORE0, 66 67 SHIKRA_SLAVE_QUP_CORE_0, 68 SHIKRA_SLAVE_AHB2PHY_USB, 69 SHIKRA_SLAVE_APSS_THROTTLE_CFG, 70 SHIKRA_SLAVE_AUDIO, 71 SHIKRA_SLAVE_BOOT_ROM, 72 SHIKRA_SLAVE_CAMERA_NRT_THROTTLE_CFG, 73 SHIKRA_SLAVE_CAMERA_CFG, 74 SHIKRA_SLAVE_CDSP_THROTTLE_CFG, 75 SHIKRA_SLAVE_CLK_CTL, 76 SHIKRA_SLAVE_DSP_CFG, 77 SHIKRA_SLAVE_RBCPR_CX_CFG, 78 SHIKRA_SLAVE_RBCPR_MX_CFG, 79 SHIKRA_SLAVE_CRYPTO_0_CFG, 80 SHIKRA_SLAVE_DDR_SS_CFG, 81 SHIKRA_SLAVE_DISPLAY_CFG, 82 SHIKRA_SLAVE_EMAC0_CFG, 83 SHIKRA_SLAVE_EMAC1_CFG, 84 SHIKRA_SLAVE_GPU_CFG, 85 SHIKRA_SLAVE_GPU_THROTTLE_CFG, 86 SHIKRA_SLAVE_HWKM, 87 SHIKRA_SLAVE_IMEM_CFG, 88 SHIKRA_SLAVE_MAPSS, 89 SHIKRA_SLAVE_MDSP_MPU_CFG, 90 SHIKRA_SLAVE_MESSAGE_RAM, 91 SHIKRA_SLAVE_MSS, 92 SHIKRA_SLAVE_PCIE_CFG, 93 SHIKRA_SLAVE_PDM, 94 SHIKRA_SLAVE_PIMEM_CFG, 95 SHIKRA_SLAVE_PKA_WRAPPER_CFG, 96 SHIKRA_SLAVE_PMIC_ARB, 97 SHIKRA_SLAVE_QDSS_CFG, 98 SHIKRA_SLAVE_QM_CFG, 99 SHIKRA_SLAVE_QM_MPU_CFG, 100 SHIKRA_SLAVE_QPIC, 101 SHIKRA_SLAVE_QUP_0, 102 SHIKRA_SLAVE_RPM, 103 SHIKRA_SLAVE_SDCC_1, 104 SHIKRA_SLAVE_SDCC_2, 105 SHIKRA_SLAVE_SECURITY, 106 SHIKRA_SLAVE_SNOC_CFG, 107 SHIKRA_SNOC_SF_THROTTLE_CFG, 108 SHIKRA_SLAVE_TLMM, 109 SHIKRA_SLAVE_TSCSS, 110 SHIKRA_SLAVE_USB2, 111 SHIKRA_SLAVE_USB3, 112 SHIKRA_SLAVE_VENUS_CFG, 113 SHIKRA_SLAVE_VENUS_THROTTLE_CFG, 114 SHIKRA_SLAVE_VSENSE_CTRL_CFG, 115 SHIKRA_SLAVE_SERVICE_CNOC, 116 SHIKRA_SLAVE_EBI_CH0, 117 SHIKRA_SLAVE_LLCC, 118 SHIKRA_SLAVE_MEMNOC_SNOC, 119 SHIKRA_SLAVE_MEM_NOC_PCIE_SNOC, 120 SHIKRA_SLAVE_MMNRT_VIRT, 121 SHIKRA_SLAVE_MM_MEMNOC, 122 SHIKRA_SLAVE_APPSS, 123 SHIKRA_SLAVE_MCUSS, 124 SHIKRA_SLAVE_WCSS, 125 SHIKRA_SLAVE_MEMNOC_SF, 126 SHIKRA_SNOC_CNOC_SLV, 127 SHIKRA_SLAVE_BOOTIMEM, 128 SHIKRA_SLAVE_OCIMEM, 129 SHIKRA_SLAVE_PIMEM, 130 SHIKRA_SLAVE_SERVICE_SNOC, 131 SHIKRA_SLAVE_PCIE2_0, 132 SHIKRA_SLAVE_QDSS_STM, 133 SHIKRA_SLAVE_TCU, 134 SHIKRA_SLAVE_PCIE_MEMNOC, 135 SHIKRA_SLAVE_ANOC_SNOC, 136 }; 137 138 /* Master nodes */ 139 static const u16 qup0_core_master_links[] = { 140 SHIKRA_SLAVE_QUP_CORE_0, 141 }; 142 143 static struct qcom_icc_node qup0_core_master = { 144 .id = SHIKRA_MASTER_QUP_CORE_0, 145 .name = "qup0_core_master", 146 .buswidth = 4, 147 .mas_rpm_id = 170, 148 .slv_rpm_id = -1, 149 .num_links = ARRAY_SIZE(qup0_core_master_links), 150 .links = qup0_core_master_links, 151 }; 152 153 static const u16 qnm_snoc_cnoc_links[] = { 154 SHIKRA_SLAVE_AHB2PHY_USB, 155 SHIKRA_SLAVE_APSS_THROTTLE_CFG, 156 SHIKRA_SLAVE_AUDIO, 157 SHIKRA_SLAVE_BOOT_ROM, 158 SHIKRA_SLAVE_CAMERA_NRT_THROTTLE_CFG, 159 SHIKRA_SLAVE_CAMERA_CFG, 160 SHIKRA_SLAVE_CDSP_THROTTLE_CFG, 161 SHIKRA_SLAVE_CLK_CTL, 162 SHIKRA_SLAVE_DSP_CFG, 163 SHIKRA_SLAVE_RBCPR_CX_CFG, 164 SHIKRA_SLAVE_RBCPR_MX_CFG, 165 SHIKRA_SLAVE_CRYPTO_0_CFG, 166 SHIKRA_SLAVE_DDR_SS_CFG, 167 SHIKRA_SLAVE_DISPLAY_CFG, 168 SHIKRA_SLAVE_EMAC0_CFG, 169 SHIKRA_SLAVE_EMAC1_CFG, 170 SHIKRA_SLAVE_GPU_CFG, 171 SHIKRA_SLAVE_GPU_THROTTLE_CFG, 172 SHIKRA_SLAVE_HWKM, 173 SHIKRA_SLAVE_IMEM_CFG, 174 SHIKRA_SLAVE_MAPSS, 175 SHIKRA_SLAVE_MDSP_MPU_CFG, 176 SHIKRA_SLAVE_MESSAGE_RAM, 177 SHIKRA_SLAVE_MSS, 178 SHIKRA_SLAVE_PCIE_CFG, 179 SHIKRA_SLAVE_PDM, 180 SHIKRA_SLAVE_PIMEM_CFG, 181 SHIKRA_SLAVE_PKA_WRAPPER_CFG, 182 SHIKRA_SLAVE_PMIC_ARB, 183 SHIKRA_SLAVE_QDSS_CFG, 184 SHIKRA_SLAVE_QM_CFG, 185 SHIKRA_SLAVE_QM_MPU_CFG, 186 SHIKRA_SLAVE_QPIC, 187 SHIKRA_SLAVE_QUP_0, 188 SHIKRA_SLAVE_RPM, 189 SHIKRA_SLAVE_SDCC_1, 190 SHIKRA_SLAVE_SDCC_2, 191 SHIKRA_SLAVE_SECURITY, 192 SHIKRA_SLAVE_SNOC_CFG, 193 SHIKRA_SNOC_SF_THROTTLE_CFG, 194 SHIKRA_SLAVE_TLMM, 195 SHIKRA_SLAVE_TSCSS, 196 SHIKRA_SLAVE_USB2, 197 SHIKRA_SLAVE_USB3, 198 SHIKRA_SLAVE_VENUS_CFG, 199 SHIKRA_SLAVE_VENUS_THROTTLE_CFG, 200 SHIKRA_SLAVE_VSENSE_CTRL_CFG, 201 SHIKRA_SLAVE_SERVICE_CNOC, 202 }; 203 204 static struct qcom_icc_node qnm_snoc_cnoc = { 205 .id = SHIKRA_SNOC_CNOC_MAS, 206 .name = "qnm_snoc_cnoc", 207 .buswidth = 8, 208 .mas_rpm_id = -1, 209 .slv_rpm_id = -1, 210 .num_links = ARRAY_SIZE(qnm_snoc_cnoc_links), 211 .links = qnm_snoc_cnoc_links, 212 }; 213 214 static const u16 xm_dap_links[] = { 215 SHIKRA_SLAVE_AHB2PHY_USB, 216 SHIKRA_SLAVE_APSS_THROTTLE_CFG, 217 SHIKRA_SLAVE_AUDIO, 218 SHIKRA_SLAVE_BOOT_ROM, 219 SHIKRA_SLAVE_CAMERA_NRT_THROTTLE_CFG, 220 SHIKRA_SLAVE_CAMERA_CFG, 221 SHIKRA_SLAVE_CDSP_THROTTLE_CFG, 222 SHIKRA_SLAVE_CLK_CTL, 223 SHIKRA_SLAVE_DSP_CFG, 224 SHIKRA_SLAVE_RBCPR_CX_CFG, 225 SHIKRA_SLAVE_RBCPR_MX_CFG, 226 SHIKRA_SLAVE_CRYPTO_0_CFG, 227 SHIKRA_SLAVE_DDR_SS_CFG, 228 SHIKRA_SLAVE_DISPLAY_CFG, 229 SHIKRA_SLAVE_EMAC0_CFG, 230 SHIKRA_SLAVE_EMAC1_CFG, 231 SHIKRA_SLAVE_GPU_CFG, 232 SHIKRA_SLAVE_GPU_THROTTLE_CFG, 233 SHIKRA_SLAVE_HWKM, 234 SHIKRA_SLAVE_IMEM_CFG, 235 SHIKRA_SLAVE_MAPSS, 236 SHIKRA_SLAVE_MDSP_MPU_CFG, 237 SHIKRA_SLAVE_MESSAGE_RAM, 238 SHIKRA_SLAVE_MSS, 239 SHIKRA_SLAVE_PCIE_CFG, 240 SHIKRA_SLAVE_PDM, 241 SHIKRA_SLAVE_PIMEM_CFG, 242 SHIKRA_SLAVE_PKA_WRAPPER_CFG, 243 SHIKRA_SLAVE_PMIC_ARB, 244 SHIKRA_SLAVE_QDSS_CFG, 245 SHIKRA_SLAVE_QM_CFG, 246 SHIKRA_SLAVE_QM_MPU_CFG, 247 SHIKRA_SLAVE_QPIC, 248 SHIKRA_SLAVE_QUP_0, 249 SHIKRA_SLAVE_RPM, 250 SHIKRA_SLAVE_SDCC_1, 251 SHIKRA_SLAVE_SDCC_2, 252 SHIKRA_SLAVE_SECURITY, 253 SHIKRA_SLAVE_SNOC_CFG, 254 SHIKRA_SNOC_SF_THROTTLE_CFG, 255 SHIKRA_SLAVE_TLMM, 256 SHIKRA_SLAVE_TSCSS, 257 SHIKRA_SLAVE_USB2, 258 SHIKRA_SLAVE_USB3, 259 SHIKRA_SLAVE_VENUS_CFG, 260 SHIKRA_SLAVE_VENUS_THROTTLE_CFG, 261 SHIKRA_SLAVE_VSENSE_CTRL_CFG, 262 SHIKRA_SLAVE_SERVICE_CNOC, 263 }; 264 265 static struct qcom_icc_node xm_dap = { 266 .id = SHIKRA_MASTER_QDSS_DAP, 267 .name = "xm_dap", 268 .buswidth = 8, 269 .mas_rpm_id = -1, 270 .slv_rpm_id = -1, 271 .num_links = ARRAY_SIZE(xm_dap_links), 272 .links = xm_dap_links, 273 }; 274 275 static const u16 llcc_mc_links[] = { 276 SHIKRA_SLAVE_EBI_CH0, 277 }; 278 279 static struct qcom_icc_node llcc_mc = { 280 .id = SHIKRA_MASTER_LLCC, 281 .name = "llcc_mc", 282 .buswidth = 4, 283 .channels = 2, 284 .mas_rpm_id = 190, 285 .slv_rpm_id = -1, 286 .num_links = ARRAY_SIZE(llcc_mc_links), 287 .links = llcc_mc_links, 288 }; 289 290 static const u16 qnm_gpu_links[] = { 291 SHIKRA_SLAVE_LLCC, 292 SHIKRA_SLAVE_MEMNOC_SNOC, 293 SHIKRA_SLAVE_MEM_NOC_PCIE_SNOC, 294 }; 295 296 static struct qcom_icc_node qnm_gpu = { 297 .id = SHIKRA_MASTER_GRAPHICS_3D, 298 .name = "qnm_gpu", 299 .buswidth = 16, 300 .qos.ap_owned = true, 301 .qos.qos_port = 6, 302 .qos.urg_fwd_en = false, 303 .qos.qos_mode = NOC_QOS_MODE_FIXED, 304 .qos.areq_prio = 0, 305 .mas_rpm_id = -1, 306 .slv_rpm_id = -1, 307 .num_links = ARRAY_SIZE(qnm_gpu_links), 308 .links = qnm_gpu_links, 309 }; 310 311 static const u16 qnm_mnoc_hf_links[] = { 312 SHIKRA_SLAVE_LLCC, 313 SHIKRA_SLAVE_MEMNOC_SNOC, 314 SHIKRA_SLAVE_MEM_NOC_PCIE_SNOC, 315 }; 316 317 static struct qcom_icc_node qnm_mnoc_hf = { 318 .id = SHIKRA_MASTER_MNOC_HF_MEM_NOC, 319 .name = "qnm_mnoc_hf", 320 .buswidth = 16, 321 .qos.ap_owned = true, 322 .qos.qos_port = 7, 323 .qos.urg_fwd_en = true, 324 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 325 .qos.areq_prio = 0, 326 .mas_rpm_id = -1, 327 .slv_rpm_id = -1, 328 .num_links = ARRAY_SIZE(qnm_mnoc_hf_links), 329 .links = qnm_mnoc_hf_links, 330 }; 331 332 static const u16 qnm_pcie_links[] = { 333 SHIKRA_SLAVE_LLCC, 334 SHIKRA_SLAVE_MEMNOC_SNOC, 335 }; 336 337 static struct qcom_icc_node qnm_pcie = { 338 .id = SHIKRA_MASTER_ANOC_PCIE_MEM_NOC, 339 .name = "qnm_pcie", 340 .buswidth = 8, 341 .qos.ap_owned = true, 342 .qos.qos_port = 4, 343 .qos.urg_fwd_en = true, 344 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 345 .qos.areq_prio = 0, 346 .mas_rpm_id = 185, 347 .slv_rpm_id = -1, 348 .num_links = ARRAY_SIZE(qnm_pcie_links), 349 .links = qnm_pcie_links, 350 }; 351 352 static const u16 qnm_snoc_sf_links[] = { 353 SHIKRA_SLAVE_LLCC, 354 SHIKRA_SLAVE_MEMNOC_SNOC, 355 SHIKRA_SLAVE_MEM_NOC_PCIE_SNOC, 356 }; 357 358 static struct qcom_icc_node qnm_snoc_sf = { 359 .id = SHIKRA_MASTER_SNOC_SF_MEM_NOC, 360 .name = "qnm_snoc_sf", 361 .buswidth = 16, 362 .qos.ap_owned = true, 363 .qos.qos_port = 3, 364 .qos.urg_fwd_en = true, 365 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 366 .qos.areq_prio = 0, 367 .mas_rpm_id = 76, 368 .slv_rpm_id = -1, 369 .num_links = ARRAY_SIZE(qnm_snoc_sf_links), 370 .links = qnm_snoc_sf_links, 371 }; 372 373 static const u16 xm_apps_links[] = { 374 SHIKRA_SLAVE_LLCC, 375 SHIKRA_SLAVE_MEMNOC_SNOC, 376 SHIKRA_SLAVE_MEM_NOC_PCIE_SNOC, 377 }; 378 379 static struct qcom_icc_node xm_apps = { 380 .id = SHIKRA_MASTER_AMPSS_M0, 381 .name = "xm_apps", 382 .buswidth = 16, 383 .qos.ap_owned = true, 384 .qos.qos_port = 5, 385 .qos.urg_fwd_en = false, 386 .qos.qos_mode = NOC_QOS_MODE_FIXED, 387 .qos.areq_prio = 0, 388 .mas_rpm_id = 0, 389 .slv_rpm_id = -1, 390 .num_links = ARRAY_SIZE(xm_apps_links), 391 .links = xm_apps_links, 392 }; 393 394 static const u16 xm_tcu_links[] = { 395 SHIKRA_SLAVE_LLCC, 396 SHIKRA_SLAVE_MEMNOC_SNOC, 397 }; 398 399 static struct qcom_icc_node xm_tcu = { 400 .id = SHIKRA_MASTER_SYS_TCU, 401 .name = "xm_tcu", 402 .buswidth = 8, 403 .qos.ap_owned = true, 404 .qos.qos_port = 2, 405 .qos.urg_fwd_en = false, 406 .qos.qos_mode = NOC_QOS_MODE_FIXED, 407 .qos.areq_prio = 6, 408 .mas_rpm_id = -1, 409 .slv_rpm_id = -1, 410 .num_links = ARRAY_SIZE(xm_tcu_links), 411 .links = xm_tcu_links, 412 }; 413 414 static const u16 qnm_camera_nrt_links[] = { 415 SHIKRA_SLAVE_MMNRT_VIRT, 416 }; 417 418 static struct qcom_icc_node qnm_camera_nrt = { 419 .id = SHIKRA_MASTER_CAMNOC_SF, 420 .name = "qnm_camera_nrt", 421 .buswidth = 32, 422 .qos.ap_owned = true, 423 .qos.qos_port = 3, 424 .qos.urg_fwd_en = false, 425 .qos.qos_mode = NOC_QOS_MODE_FIXED, 426 .qos.areq_prio = 3, 427 .mas_rpm_id = -1, 428 .slv_rpm_id = -1, 429 .num_links = ARRAY_SIZE(qnm_camera_nrt_links), 430 .links = qnm_camera_nrt_links, 431 }; 432 433 static const u16 qxm_venus0_links[] = { 434 SHIKRA_SLAVE_MMNRT_VIRT, 435 }; 436 437 static struct qcom_icc_node qxm_venus0 = { 438 .id = SHIKRA_MASTER_VIDEO_P0, 439 .name = "qxm_venus0", 440 .buswidth = 16, 441 .qos.ap_owned = true, 442 .qos.qos_port = 8, 443 .qos.urg_fwd_en = true, 444 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 445 .qos.areq_prio = 0, 446 .mas_rpm_id = -1, 447 .slv_rpm_id = -1, 448 .num_links = ARRAY_SIZE(qxm_venus0_links), 449 .links = qxm_venus0_links, 450 }; 451 452 static const u16 qxm_venus_cpu_links[] = { 453 SHIKRA_SLAVE_MMNRT_VIRT, 454 }; 455 456 static struct qcom_icc_node qxm_venus_cpu = { 457 .id = SHIKRA_MASTER_VIDEO_PROC, 458 .name = "qxm_venus_cpu", 459 .buswidth = 8, 460 .qos.ap_owned = true, 461 .qos.qos_port = 12, 462 .qos.urg_fwd_en = false, 463 .qos.qos_mode = NOC_QOS_MODE_FIXED, 464 .qos.areq_prio = 4, 465 .mas_rpm_id = -1, 466 .slv_rpm_id = -1, 467 .num_links = ARRAY_SIZE(qxm_venus_cpu_links), 468 .links = qxm_venus_cpu_links, 469 }; 470 471 static const u16 qnm_camera_rt_links[] = { 472 SHIKRA_SLAVE_MM_MEMNOC, 473 }; 474 475 static struct qcom_icc_node qnm_camera_rt = { 476 .id = SHIKRA_MASTER_CAMNOC_HF, 477 .name = "qnm_camera_rt", 478 .buswidth = 32, 479 .qos.ap_owned = true, 480 .qos.qos_port = 9, 481 .qos.urg_fwd_en = true, 482 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 483 .qos.areq_prio = 0, 484 .mas_rpm_id = -1, 485 .slv_rpm_id = -1, 486 .num_links = ARRAY_SIZE(qnm_camera_rt_links), 487 .links = qnm_camera_rt_links, 488 }; 489 490 static const u16 qxm_mdp0_links[] = { 491 SHIKRA_SLAVE_MM_MEMNOC, 492 }; 493 494 static struct qcom_icc_node qxm_mdp0 = { 495 .id = SHIKRA_MASTER_MDP_PORT0, 496 .name = "qxm_mdp0", 497 .buswidth = 16, 498 .qos.ap_owned = true, 499 .qos.qos_port = 4, 500 .qos.urg_fwd_en = true, 501 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 502 .qos.areq_prio = 0, 503 .mas_rpm_id = -1, 504 .slv_rpm_id = -1, 505 .num_links = ARRAY_SIZE(qxm_mdp0_links), 506 .links = qxm_mdp0_links, 507 }; 508 509 static const u16 mmrt_virt_master_links[] = { 510 SHIKRA_SLAVE_MM_MEMNOC, 511 }; 512 513 static struct qcom_icc_node mmrt_virt_master = { 514 .id = SHIKRA_MASTER_MMRT_VIRT, 515 .name = "mmrt_virt_master", 516 .buswidth = 16, 517 .mas_rpm_id = -1, 518 .slv_rpm_id = -1, 519 .num_links = ARRAY_SIZE(mmrt_virt_master_links), 520 .links = mmrt_virt_master_links, 521 }; 522 523 static const u16 qhm_snoc_cfg_links[] = { 524 SHIKRA_SLAVE_SERVICE_SNOC, 525 }; 526 527 static struct qcom_icc_node qhm_snoc_cfg = { 528 .id = SHIKRA_MASTER_SNOC_CFG, 529 .name = "qhm_snoc_cfg", 530 .buswidth = 4, 531 .mas_rpm_id = -1, 532 .slv_rpm_id = -1, 533 .num_links = ARRAY_SIZE(qhm_snoc_cfg_links), 534 .links = qhm_snoc_cfg_links, 535 }; 536 537 static const u16 qhm_tic_links[] = { 538 SHIKRA_SLAVE_APPSS, 539 SHIKRA_SLAVE_MCUSS, 540 SHIKRA_SLAVE_WCSS, 541 SHIKRA_SLAVE_MEMNOC_SF, 542 SHIKRA_SNOC_CNOC_SLV, 543 SHIKRA_SLAVE_BOOTIMEM, 544 SHIKRA_SLAVE_OCIMEM, 545 SHIKRA_SLAVE_PIMEM, 546 SHIKRA_SLAVE_QDSS_STM, 547 SHIKRA_SLAVE_TCU, 548 }; 549 550 static struct qcom_icc_node qhm_tic = { 551 .id = SHIKRA_MASTER_TIC, 552 .name = "qhm_tic", 553 .buswidth = 4, 554 .mas_rpm_id = -1, 555 .slv_rpm_id = -1, 556 .num_links = ARRAY_SIZE(qhm_tic_links), 557 .links = qhm_tic_links, 558 }; 559 560 static const u16 qnm_anoc_snoc_links[] = { 561 SHIKRA_SLAVE_MEMNOC_SF, 562 }; 563 564 static struct qcom_icc_node qnm_anoc_snoc = { 565 .id = SHIKRA_MASTER_ANOC_SNOC, 566 .name = "qnm_anoc_snoc", 567 .buswidth = 16, 568 .mas_rpm_id = 110, 569 .slv_rpm_id = -1, 570 .num_links = ARRAY_SIZE(qnm_anoc_snoc_links), 571 .links = qnm_anoc_snoc_links, 572 }; 573 574 static const u16 qnm_memnoc_pcie_links[] = { 575 SHIKRA_SLAVE_PCIE2_0, 576 }; 577 578 static struct qcom_icc_node qnm_memnoc_pcie = { 579 .id = SHIKRA_MASTER_MEMNOC_PCIE, 580 .name = "qnm_memnoc_pcie", 581 .buswidth = 8, 582 .mas_rpm_id = -1, 583 .slv_rpm_id = -1, 584 .num_links = ARRAY_SIZE(qnm_memnoc_pcie_links), 585 .links = qnm_memnoc_pcie_links, 586 }; 587 588 static const u16 qnm_memnoc_snoc_links[] = { 589 SHIKRA_SLAVE_APPSS, 590 SHIKRA_SLAVE_MCUSS, 591 SHIKRA_SLAVE_WCSS, 592 SHIKRA_SNOC_CNOC_SLV, 593 SHIKRA_SLAVE_BOOTIMEM, 594 SHIKRA_SLAVE_OCIMEM, 595 SHIKRA_SLAVE_PIMEM, 596 SHIKRA_SLAVE_QDSS_STM, 597 SHIKRA_SLAVE_TCU, 598 }; 599 600 static struct qcom_icc_node qnm_memnoc_snoc = { 601 .id = SHIKRA_MASTER_MEMNOC_SNOC, 602 .name = "qnm_memnoc_snoc", 603 .buswidth = 8, 604 .mas_rpm_id = 184, 605 .slv_rpm_id = -1, 606 .num_links = ARRAY_SIZE(qnm_memnoc_snoc_links), 607 .links = qnm_memnoc_snoc_links, 608 }; 609 610 static const u16 qxm_pimem_links[] = { 611 SHIKRA_SLAVE_MEMNOC_SF, 612 SHIKRA_SLAVE_OCIMEM, 613 }; 614 615 static struct qcom_icc_node qxm_pimem = { 616 .id = SHIKRA_MASTER_PIMEM, 617 .name = "qxm_pimem", 618 .buswidth = 8, 619 .qos.ap_owned = true, 620 .qos.qos_port = 14, 621 .qos.urg_fwd_en = false, 622 .qos.qos_mode = NOC_QOS_MODE_FIXED, 623 .qos.areq_prio = 2, 624 .mas_rpm_id = -1, 625 .slv_rpm_id = -1, 626 .num_links = ARRAY_SIZE(qxm_pimem_links), 627 .links = qxm_pimem_links, 628 }; 629 630 static const u16 xm_pcie2_0_links[] = { 631 SHIKRA_SLAVE_PCIE_MEMNOC, 632 }; 633 634 static struct qcom_icc_node xm_pcie2_0 = { 635 .id = SHIKRA_MASTER_PCIE2_0, 636 .name = "xm_pcie2_0", 637 .buswidth = 8, 638 .qos.ap_owned = true, 639 .qos.qos_port = 21, 640 .qos.urg_fwd_en = false, 641 .qos.qos_mode = NOC_QOS_MODE_FIXED, 642 .qos.areq_prio = 2, 643 .mas_rpm_id = 186, 644 .slv_rpm_id = -1, 645 .num_links = ARRAY_SIZE(xm_pcie2_0_links), 646 .links = xm_pcie2_0_links, 647 }; 648 649 static const u16 qhm_qdss_bam_links[] = { 650 SHIKRA_SLAVE_ANOC_SNOC, 651 }; 652 653 static struct qcom_icc_node qhm_qdss_bam = { 654 .id = SHIKRA_MASTER_QDSS_BAM, 655 .name = "qhm_qdss_bam", 656 .buswidth = 4, 657 .qos.ap_owned = true, 658 .qos.qos_port = 2, 659 .qos.urg_fwd_en = false, 660 .qos.qos_mode = NOC_QOS_MODE_FIXED, 661 .qos.areq_prio = 2, 662 .mas_rpm_id = -1, 663 .slv_rpm_id = -1, 664 .num_links = ARRAY_SIZE(qhm_qdss_bam_links), 665 .links = qhm_qdss_bam_links, 666 }; 667 668 static const u16 qhm_qpic_links[] = { 669 SHIKRA_SLAVE_ANOC_SNOC, 670 }; 671 672 static struct qcom_icc_node qhm_qpic = { 673 .id = SHIKRA_MASTER_QPIC, 674 .name = "qhm_qpic", 675 .buswidth = 4, 676 .qos.ap_owned = true, 677 .qos.qos_port = 1, 678 .qos.urg_fwd_en = false, 679 .qos.qos_mode = NOC_QOS_MODE_FIXED, 680 .qos.areq_prio = 2, 681 .mas_rpm_id = -1, 682 .slv_rpm_id = -1, 683 .num_links = ARRAY_SIZE(qhm_qpic_links), 684 .links = qhm_qpic_links, 685 }; 686 687 static const u16 qhm_qup0_links[] = { 688 SHIKRA_SLAVE_ANOC_SNOC, 689 }; 690 691 static struct qcom_icc_node qhm_qup0 = { 692 .id = SHIKRA_MASTER_QUP_0, 693 .name = "qhm_qup0", 694 .buswidth = 4, 695 .qos.ap_owned = true, 696 .qos.qos_port = 0, 697 .qos.urg_fwd_en = false, 698 .qos.qos_mode = NOC_QOS_MODE_FIXED, 699 .qos.areq_prio = 2, 700 .mas_rpm_id = 166, 701 .slv_rpm_id = -1, 702 .num_links = ARRAY_SIZE(qhm_qup0_links), 703 .links = qhm_qup0_links, 704 }; 705 706 static const u16 qnm_cnoc_snoc_links[] = { 707 SHIKRA_SLAVE_ANOC_SNOC, 708 }; 709 710 static struct qcom_icc_node qnm_cnoc_snoc = { 711 .id = SHIKRA_CNOC_SNOC_MAS, 712 .name = "qnm_cnoc_snoc", 713 .buswidth = 4, 714 .qos.ap_owned = true, 715 .qos.qos_port = 7, 716 .qos.urg_fwd_en = false, 717 .qos.qos_mode = NOC_QOS_MODE_FIXED, 718 .qos.areq_prio = 2, 719 .mas_rpm_id = -1, 720 .slv_rpm_id = -1, 721 .num_links = ARRAY_SIZE(qnm_cnoc_snoc_links), 722 .links = qnm_cnoc_snoc_links, 723 }; 724 725 static const u16 qxm_audio_links[] = { 726 SHIKRA_SLAVE_ANOC_SNOC, 727 }; 728 729 static struct qcom_icc_node qxm_audio = { 730 .id = SHIKRA_MASTER_AUDIO, 731 .name = "qxm_audio", 732 .buswidth = 8, 733 .qos.ap_owned = true, 734 .qos.qos_port = 22, 735 .qos.urg_fwd_en = false, 736 .qos.qos_mode = NOC_QOS_MODE_FIXED, 737 .qos.areq_prio = 3, 738 .mas_rpm_id = 78, 739 .slv_rpm_id = -1, 740 .num_links = ARRAY_SIZE(qxm_audio_links), 741 .links = qxm_audio_links, 742 }; 743 744 static const u16 xm_emac_0_links[] = { 745 SHIKRA_SLAVE_ANOC_SNOC, 746 }; 747 748 static struct qcom_icc_node xm_emac_0 = { 749 .id = SHIKRA_MASTER_EMAC_0, 750 .name = "xm_emac_0", 751 .buswidth = 8, 752 .qos.ap_owned = true, 753 .qos.qos_port = 19, 754 .qos.urg_fwd_en = false, 755 .qos.qos_mode = NOC_QOS_MODE_FIXED, 756 .qos.areq_prio = 2, 757 .mas_rpm_id = -1, 758 .slv_rpm_id = -1, 759 .num_links = ARRAY_SIZE(xm_emac_0_links), 760 .links = xm_emac_0_links, 761 }; 762 763 static const u16 xm_emac_1_links[] = { 764 SHIKRA_SLAVE_ANOC_SNOC, 765 }; 766 767 static struct qcom_icc_node xm_emac_1 = { 768 .id = SHIKRA_MASTER_EMAC_1, 769 .name = "xm_emac_1", 770 .buswidth = 8, 771 .qos.ap_owned = true, 772 .qos.qos_port = 20, 773 .qos.urg_fwd_en = false, 774 .qos.qos_mode = NOC_QOS_MODE_FIXED, 775 .qos.areq_prio = 2, 776 .mas_rpm_id = -1, 777 .slv_rpm_id = -1, 778 .num_links = ARRAY_SIZE(xm_emac_1_links), 779 .links = xm_emac_1_links, 780 }; 781 782 static const u16 xm_qdss_etr_links[] = { 783 SHIKRA_SLAVE_ANOC_SNOC, 784 }; 785 786 static struct qcom_icc_node xm_qdss_etr = { 787 .id = SHIKRA_MASTER_QDSS_ETR, 788 .name = "xm_qdss_etr", 789 .buswidth = 8, 790 .qos.ap_owned = true, 791 .qos.qos_port = 11, 792 .qos.urg_fwd_en = false, 793 .qos.qos_mode = NOC_QOS_MODE_FIXED, 794 .qos.areq_prio = 2, 795 .mas_rpm_id = -1, 796 .slv_rpm_id = -1, 797 .num_links = ARRAY_SIZE(xm_qdss_etr_links), 798 .links = xm_qdss_etr_links, 799 }; 800 801 static const u16 xm_sdc1_links[] = { 802 SHIKRA_SLAVE_ANOC_SNOC, 803 }; 804 805 static struct qcom_icc_node xm_sdc1 = { 806 .id = SHIKRA_MASTER_SDCC_1, 807 .name = "xm_sdc1", 808 .buswidth = 8, 809 .qos.ap_owned = true, 810 .qos.qos_port = 13, 811 .qos.urg_fwd_en = false, 812 .qos.qos_mode = NOC_QOS_MODE_FIXED, 813 .qos.areq_prio = 2, 814 .mas_rpm_id = -1, 815 .slv_rpm_id = -1, 816 .num_links = ARRAY_SIZE(xm_sdc1_links), 817 .links = xm_sdc1_links, 818 }; 819 820 static const u16 xm_sdc2_links[] = { 821 SHIKRA_SLAVE_ANOC_SNOC, 822 }; 823 824 static struct qcom_icc_node xm_sdc2 = { 825 .id = SHIKRA_MASTER_SDCC_2, 826 .name = "xm_sdc2", 827 .buswidth = 8, 828 .qos.ap_owned = true, 829 .qos.qos_port = 17, 830 .qos.urg_fwd_en = false, 831 .qos.qos_mode = NOC_QOS_MODE_FIXED, 832 .qos.areq_prio = 2, 833 .mas_rpm_id = -1, 834 .slv_rpm_id = -1, 835 .num_links = ARRAY_SIZE(xm_sdc2_links), 836 .links = xm_sdc2_links, 837 }; 838 839 static const u16 xm_usb2_0_links[] = { 840 SHIKRA_SLAVE_ANOC_SNOC, 841 }; 842 843 static struct qcom_icc_node xm_usb2_0 = { 844 .id = SHIKRA_MASTER_USB2_0, 845 .name = "xm_usb2_0", 846 .buswidth = 8, 847 .qos.ap_owned = true, 848 .qos.qos_port = 24, 849 .qos.urg_fwd_en = false, 850 .qos.qos_mode = NOC_QOS_MODE_FIXED, 851 .qos.areq_prio = 2, 852 .mas_rpm_id = -1, 853 .slv_rpm_id = -1, 854 .num_links = ARRAY_SIZE(xm_usb2_0_links), 855 .links = xm_usb2_0_links, 856 }; 857 858 static const u16 xm_usb3_0_links[] = { 859 SHIKRA_SLAVE_ANOC_SNOC, 860 }; 861 862 static struct qcom_icc_node xm_usb3_0 = { 863 .id = SHIKRA_MASTER_USB3, 864 .name = "xm_usb3_0", 865 .buswidth = 8, 866 .qos.ap_owned = true, 867 .qos.qos_port = 18, 868 .qos.urg_fwd_en = false, 869 .qos.qos_mode = NOC_QOS_MODE_FIXED, 870 .qos.areq_prio = 2, 871 .mas_rpm_id = -1, 872 .slv_rpm_id = -1, 873 .num_links = ARRAY_SIZE(xm_usb3_0_links), 874 .links = xm_usb3_0_links, 875 }; 876 877 static const u16 crypto_c0_links[] = { 878 SHIKRA_SLAVE_ANOC_SNOC, 879 }; 880 881 static struct qcom_icc_node crypto_c0 = { 882 .id = SHIKRA_MASTER_CRYPTO_CORE0, 883 .name = "crypto_c0", 884 .buswidth = 8, 885 .qos.ap_owned = true, 886 .qos.qos_port = 16, 887 .qos.urg_fwd_en = false, 888 .qos.qos_mode = NOC_QOS_MODE_FIXED, 889 .qos.areq_prio = 2, 890 .mas_rpm_id = 23, 891 .slv_rpm_id = -1, 892 .num_links = ARRAY_SIZE(crypto_c0_links), 893 .links = crypto_c0_links, 894 }; 895 896 /* Slave nodes */ 897 static struct qcom_icc_node qup0_core_slave = { 898 .id = SHIKRA_SLAVE_QUP_CORE_0, 899 .name = "qup0_core_slave", 900 .channels = 1, 901 .buswidth = 4, 902 .mas_rpm_id = -1, 903 .slv_rpm_id = 264, 904 }; 905 906 static struct qcom_icc_node qhs_ahb2phy_usb = { 907 .id = SHIKRA_SLAVE_AHB2PHY_USB, 908 .name = "qhs_ahb2phy_usb", 909 .channels = 1, 910 .buswidth = 4, 911 .mas_rpm_id = -1, 912 .slv_rpm_id = -1, 913 }; 914 915 static struct qcom_icc_node qhs_apss_throttle_cfg = { 916 .id = SHIKRA_SLAVE_APSS_THROTTLE_CFG, 917 .name = "qhs_apss_throttle_cfg", 918 .channels = 1, 919 .buswidth = 4, 920 .mas_rpm_id = -1, 921 .slv_rpm_id = -1, 922 }; 923 924 static struct qcom_icc_node qhs_audio = { 925 .id = SHIKRA_SLAVE_AUDIO, 926 .name = "qhs_audio", 927 .channels = 1, 928 .buswidth = 4, 929 .mas_rpm_id = -1, 930 .slv_rpm_id = -1, 931 }; 932 933 static struct qcom_icc_node qhs_boot_rom = { 934 .id = SHIKRA_SLAVE_BOOT_ROM, 935 .name = "qhs_boot_rom", 936 .channels = 1, 937 .buswidth = 4, 938 .mas_rpm_id = -1, 939 .slv_rpm_id = -1, 940 }; 941 942 static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = { 943 .id = SHIKRA_SLAVE_CAMERA_NRT_THROTTLE_CFG, 944 .name = "qhs_camera_nrt_throttle_cfg", 945 .channels = 1, 946 .buswidth = 4, 947 .mas_rpm_id = -1, 948 .slv_rpm_id = -1, 949 }; 950 951 static struct qcom_icc_node qhs_camera_ss_cfg = { 952 .id = SHIKRA_SLAVE_CAMERA_CFG, 953 .name = "qhs_camera_ss_cfg", 954 .channels = 1, 955 .buswidth = 4, 956 .mas_rpm_id = -1, 957 .slv_rpm_id = -1, 958 }; 959 960 static struct qcom_icc_node qhs_cdsp_throttle_cfg = { 961 .id = SHIKRA_SLAVE_CDSP_THROTTLE_CFG, 962 .name = "qhs_cdsp_throttle_cfg", 963 .channels = 1, 964 .buswidth = 4, 965 .mas_rpm_id = -1, 966 .slv_rpm_id = -1, 967 }; 968 969 static struct qcom_icc_node qhs_clk_ctl = { 970 .id = SHIKRA_SLAVE_CLK_CTL, 971 .name = "qhs_clk_ctl", 972 .channels = 1, 973 .buswidth = 4, 974 .mas_rpm_id = -1, 975 .slv_rpm_id = -1, 976 }; 977 978 static struct qcom_icc_node qhs_compute_dsp_cfg = { 979 .id = SHIKRA_SLAVE_DSP_CFG, 980 .name = "qhs_compute_dsp_cfg", 981 .channels = 1, 982 .buswidth = 4, 983 .mas_rpm_id = -1, 984 .slv_rpm_id = -1, 985 }; 986 987 static struct qcom_icc_node qhs_cpr_cx = { 988 .id = SHIKRA_SLAVE_RBCPR_CX_CFG, 989 .name = "qhs_cpr_cx", 990 .channels = 1, 991 .buswidth = 4, 992 .mas_rpm_id = -1, 993 .slv_rpm_id = -1, 994 }; 995 996 static struct qcom_icc_node qhs_cpr_mx = { 997 .id = SHIKRA_SLAVE_RBCPR_MX_CFG, 998 .name = "qhs_cpr_mx", 999 .channels = 1, 1000 .buswidth = 4, 1001 .mas_rpm_id = -1, 1002 .slv_rpm_id = -1, 1003 }; 1004 1005 static struct qcom_icc_node qhs_crypto0_cfg = { 1006 .id = SHIKRA_SLAVE_CRYPTO_0_CFG, 1007 .name = "qhs_crypto0_cfg", 1008 .channels = 1, 1009 .buswidth = 4, 1010 .mas_rpm_id = -1, 1011 .slv_rpm_id = -1, 1012 }; 1013 1014 static struct qcom_icc_node qhs_ddr_ss_cfg = { 1015 .id = SHIKRA_SLAVE_DDR_SS_CFG, 1016 .name = "qhs_ddr_ss_cfg", 1017 .channels = 1, 1018 .buswidth = 4, 1019 .mas_rpm_id = -1, 1020 .slv_rpm_id = -1, 1021 }; 1022 1023 static struct qcom_icc_node qhs_disp_ss_cfg = { 1024 .id = SHIKRA_SLAVE_DISPLAY_CFG, 1025 .name = "qhs_disp_ss_cfg", 1026 .channels = 1, 1027 .buswidth = 4, 1028 .mas_rpm_id = -1, 1029 .slv_rpm_id = -1, 1030 }; 1031 1032 static struct qcom_icc_node qhs_emac0_cfg = { 1033 .id = SHIKRA_SLAVE_EMAC0_CFG, 1034 .name = "qhs_emac0_cfg", 1035 .channels = 1, 1036 .buswidth = 4, 1037 .mas_rpm_id = -1, 1038 .slv_rpm_id = -1, 1039 }; 1040 1041 static struct qcom_icc_node qhs_emac1_cfg = { 1042 .id = SHIKRA_SLAVE_EMAC1_CFG, 1043 .name = "qhs_emac1_cfg", 1044 .channels = 1, 1045 .buswidth = 4, 1046 .mas_rpm_id = -1, 1047 .slv_rpm_id = -1, 1048 }; 1049 1050 static struct qcom_icc_node qhs_gpu_cfg = { 1051 .id = SHIKRA_SLAVE_GPU_CFG, 1052 .name = "qhs_gpu_cfg", 1053 .channels = 1, 1054 .buswidth = 8, 1055 .mas_rpm_id = -1, 1056 .slv_rpm_id = -1, 1057 }; 1058 1059 static struct qcom_icc_node qhs_gpu_throttle_cfg = { 1060 .id = SHIKRA_SLAVE_GPU_THROTTLE_CFG, 1061 .name = "qhs_gpu_throttle_cfg", 1062 .channels = 1, 1063 .buswidth = 4, 1064 .mas_rpm_id = -1, 1065 .slv_rpm_id = -1, 1066 }; 1067 1068 static struct qcom_icc_node qhs_hwkm = { 1069 .id = SHIKRA_SLAVE_HWKM, 1070 .name = "qhs_hwkm", 1071 .channels = 1, 1072 .buswidth = 4, 1073 .mas_rpm_id = -1, 1074 .slv_rpm_id = -1, 1075 }; 1076 1077 static struct qcom_icc_node qhs_imem_cfg = { 1078 .id = SHIKRA_SLAVE_IMEM_CFG, 1079 .name = "qhs_imem_cfg", 1080 .channels = 1, 1081 .buswidth = 4, 1082 .mas_rpm_id = -1, 1083 .slv_rpm_id = -1, 1084 }; 1085 1086 static struct qcom_icc_node qhs_mapss = { 1087 .id = SHIKRA_SLAVE_MAPSS, 1088 .name = "qhs_mapss", 1089 .channels = 1, 1090 .buswidth = 4, 1091 .mas_rpm_id = -1, 1092 .slv_rpm_id = -1, 1093 }; 1094 1095 static struct qcom_icc_node qhs_mdsp_mpu_cfg = { 1096 .id = SHIKRA_SLAVE_MDSP_MPU_CFG, 1097 .name = "qhs_mdsp_mpu_cfg", 1098 .channels = 1, 1099 .buswidth = 4, 1100 .mas_rpm_id = -1, 1101 .slv_rpm_id = -1, 1102 }; 1103 1104 static struct qcom_icc_node qhs_mesg_ram = { 1105 .id = SHIKRA_SLAVE_MESSAGE_RAM, 1106 .name = "qhs_mesg_ram", 1107 .channels = 1, 1108 .buswidth = 4, 1109 .mas_rpm_id = -1, 1110 .slv_rpm_id = -1, 1111 }; 1112 1113 static struct qcom_icc_node qhs_mss = { 1114 .id = SHIKRA_SLAVE_MSS, 1115 .name = "qhs_mss", 1116 .channels = 1, 1117 .buswidth = 4, 1118 .mas_rpm_id = -1, 1119 .slv_rpm_id = -1, 1120 }; 1121 1122 static struct qcom_icc_node qhs_pcie_cfg = { 1123 .id = SHIKRA_SLAVE_PCIE_CFG, 1124 .name = "qhs_pcie_cfg", 1125 .channels = 1, 1126 .buswidth = 4, 1127 .mas_rpm_id = -1, 1128 .slv_rpm_id = -1, 1129 }; 1130 1131 static struct qcom_icc_node qhs_pdm = { 1132 .id = SHIKRA_SLAVE_PDM, 1133 .name = "qhs_pdm", 1134 .channels = 1, 1135 .buswidth = 4, 1136 .mas_rpm_id = -1, 1137 .slv_rpm_id = -1, 1138 }; 1139 1140 static struct qcom_icc_node qhs_pimem_cfg = { 1141 .id = SHIKRA_SLAVE_PIMEM_CFG, 1142 .name = "qhs_pimem_cfg", 1143 .channels = 1, 1144 .buswidth = 4, 1145 .mas_rpm_id = -1, 1146 .slv_rpm_id = -1, 1147 }; 1148 1149 static struct qcom_icc_node qhs_pka_wrapper = { 1150 .id = SHIKRA_SLAVE_PKA_WRAPPER_CFG, 1151 .name = "qhs_pka_wrapper", 1152 .channels = 1, 1153 .buswidth = 4, 1154 .mas_rpm_id = -1, 1155 .slv_rpm_id = -1, 1156 }; 1157 1158 static struct qcom_icc_node qhs_pmic_arb = { 1159 .id = SHIKRA_SLAVE_PMIC_ARB, 1160 .name = "qhs_pmic_arb", 1161 .channels = 1, 1162 .buswidth = 4, 1163 .mas_rpm_id = -1, 1164 .slv_rpm_id = -1, 1165 }; 1166 1167 static struct qcom_icc_node qhs_qdss_cfg = { 1168 .id = SHIKRA_SLAVE_QDSS_CFG, 1169 .name = "qhs_qdss_cfg", 1170 .channels = 1, 1171 .buswidth = 4, 1172 .mas_rpm_id = -1, 1173 .slv_rpm_id = -1, 1174 }; 1175 1176 static struct qcom_icc_node qhs_qm_cfg = { 1177 .id = SHIKRA_SLAVE_QM_CFG, 1178 .name = "qhs_qm_cfg", 1179 .channels = 1, 1180 .buswidth = 4, 1181 .mas_rpm_id = -1, 1182 .slv_rpm_id = -1, 1183 }; 1184 1185 static struct qcom_icc_node qhs_qm_mpu_cfg = { 1186 .id = SHIKRA_SLAVE_QM_MPU_CFG, 1187 .name = "qhs_qm_mpu_cfg", 1188 .channels = 1, 1189 .buswidth = 4, 1190 .mas_rpm_id = -1, 1191 .slv_rpm_id = -1, 1192 }; 1193 1194 static struct qcom_icc_node qhs_qpic = { 1195 .id = SHIKRA_SLAVE_QPIC, 1196 .name = "qhs_qpic", 1197 .channels = 1, 1198 .buswidth = 4, 1199 .mas_rpm_id = -1, 1200 .slv_rpm_id = -1, 1201 }; 1202 1203 static struct qcom_icc_node qhs_qup0 = { 1204 .id = SHIKRA_SLAVE_QUP_0, 1205 .name = "qhs_qup0", 1206 .channels = 1, 1207 .buswidth = 4, 1208 .mas_rpm_id = -1, 1209 .slv_rpm_id = -1, 1210 }; 1211 1212 static struct qcom_icc_node qhs_rpm = { 1213 .id = SHIKRA_SLAVE_RPM, 1214 .name = "qhs_rpm", 1215 .channels = 1, 1216 .buswidth = 4, 1217 .mas_rpm_id = -1, 1218 .slv_rpm_id = -1, 1219 }; 1220 1221 static struct qcom_icc_node qhs_sdc1 = { 1222 .id = SHIKRA_SLAVE_SDCC_1, 1223 .name = "qhs_sdc1", 1224 .channels = 1, 1225 .buswidth = 4, 1226 .mas_rpm_id = -1, 1227 .slv_rpm_id = -1, 1228 }; 1229 1230 static struct qcom_icc_node qhs_sdc2 = { 1231 .id = SHIKRA_SLAVE_SDCC_2, 1232 .name = "qhs_sdc2", 1233 .channels = 1, 1234 .buswidth = 4, 1235 .mas_rpm_id = -1, 1236 .slv_rpm_id = -1, 1237 }; 1238 1239 static struct qcom_icc_node qhs_security = { 1240 .id = SHIKRA_SLAVE_SECURITY, 1241 .name = "qhs_security", 1242 .channels = 1, 1243 .buswidth = 4, 1244 .mas_rpm_id = -1, 1245 .slv_rpm_id = -1, 1246 }; 1247 1248 static const u16 qhs_snoc_cfg_links[] = { 1249 SHIKRA_MASTER_SNOC_CFG, 1250 }; 1251 1252 static struct qcom_icc_node qhs_snoc_cfg = { 1253 .id = SHIKRA_SLAVE_SNOC_CFG, 1254 .name = "qhs_snoc_cfg", 1255 .channels = 1, 1256 .buswidth = 4, 1257 .mas_rpm_id = -1, 1258 .slv_rpm_id = -1, 1259 .num_links = 1, 1260 .links = qhs_snoc_cfg_links, 1261 }; 1262 1263 static struct qcom_icc_node qhs_snoc_sf_throttle_cfg = { 1264 .id = SHIKRA_SNOC_SF_THROTTLE_CFG, 1265 .name = "qhs_snoc_sf_throttle_cfg", 1266 .channels = 1, 1267 .buswidth = 4, 1268 .mas_rpm_id = -1, 1269 .slv_rpm_id = -1, 1270 }; 1271 1272 static struct qcom_icc_node qhs_tlmm = { 1273 .id = SHIKRA_SLAVE_TLMM, 1274 .name = "qhs_tlmm", 1275 .channels = 1, 1276 .buswidth = 4, 1277 .mas_rpm_id = -1, 1278 .slv_rpm_id = -1, 1279 }; 1280 1281 static struct qcom_icc_node qhs_tscss = { 1282 .id = SHIKRA_SLAVE_TSCSS, 1283 .name = "qhs_tscss", 1284 .channels = 1, 1285 .buswidth = 4, 1286 .mas_rpm_id = -1, 1287 .slv_rpm_id = -1, 1288 }; 1289 1290 static struct qcom_icc_node qhs_usb2 = { 1291 .id = SHIKRA_SLAVE_USB2, 1292 .name = "qhs_usb2", 1293 .channels = 1, 1294 .buswidth = 4, 1295 .mas_rpm_id = -1, 1296 .slv_rpm_id = -1, 1297 }; 1298 1299 static struct qcom_icc_node qhs_usb3 = { 1300 .id = SHIKRA_SLAVE_USB3, 1301 .name = "qhs_usb3", 1302 .channels = 1, 1303 .buswidth = 4, 1304 .mas_rpm_id = -1, 1305 .slv_rpm_id = -1, 1306 }; 1307 1308 static struct qcom_icc_node qhs_venus_cfg = { 1309 .id = SHIKRA_SLAVE_VENUS_CFG, 1310 .name = "qhs_venus_cfg", 1311 .channels = 1, 1312 .buswidth = 4, 1313 .mas_rpm_id = -1, 1314 .slv_rpm_id = -1, 1315 }; 1316 1317 static struct qcom_icc_node qhs_venus_throttle_cfg = { 1318 .id = SHIKRA_SLAVE_VENUS_THROTTLE_CFG, 1319 .name = "qhs_venus_throttle_cfg", 1320 .channels = 1, 1321 .buswidth = 4, 1322 .mas_rpm_id = -1, 1323 .slv_rpm_id = -1, 1324 }; 1325 1326 static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 1327 .id = SHIKRA_SLAVE_VSENSE_CTRL_CFG, 1328 .name = "qhs_vsense_ctrl_cfg", 1329 .channels = 1, 1330 .buswidth = 4, 1331 .mas_rpm_id = -1, 1332 .slv_rpm_id = -1, 1333 }; 1334 1335 static struct qcom_icc_node srvc_cnoc = { 1336 .id = SHIKRA_SLAVE_SERVICE_CNOC, 1337 .name = "srvc_cnoc", 1338 .channels = 1, 1339 .buswidth = 4, 1340 .mas_rpm_id = -1, 1341 .slv_rpm_id = -1, 1342 }; 1343 1344 static struct qcom_icc_node ebi = { 1345 .id = SHIKRA_SLAVE_EBI_CH0, 1346 .name = "ebi", 1347 .channels = 2, 1348 .buswidth = 4, 1349 .mas_rpm_id = -1, 1350 .slv_rpm_id = 0, 1351 }; 1352 1353 static const u16 qns_llcc_links[] = { 1354 SHIKRA_MASTER_LLCC, 1355 }; 1356 1357 static struct qcom_icc_node qns_llcc = { 1358 .id = SHIKRA_SLAVE_LLCC, 1359 .name = "qns_llcc", 1360 .channels = 2, 1361 .buswidth = 16, 1362 .mas_rpm_id = -1, 1363 .slv_rpm_id = 312, 1364 .num_links = 1, 1365 .links = qns_llcc_links, 1366 }; 1367 1368 static const u16 qns_memnoc_snoc_links[] = { 1369 SHIKRA_MASTER_MEMNOC_SNOC, 1370 }; 1371 1372 static struct qcom_icc_node qns_memnoc_snoc = { 1373 .id = SHIKRA_SLAVE_MEMNOC_SNOC, 1374 .name = "qns_memnoc_snoc", 1375 .channels = 1, 1376 .buswidth = 8, 1377 .mas_rpm_id = -1, 1378 .slv_rpm_id = 314, 1379 .num_links = 1, 1380 .links = qns_memnoc_snoc_links, 1381 }; 1382 1383 static const u16 qns_pcie_links[] = { 1384 SHIKRA_MASTER_MEMNOC_PCIE, 1385 }; 1386 1387 static struct qcom_icc_node qns_pcie = { 1388 .id = SHIKRA_SLAVE_MEM_NOC_PCIE_SNOC, 1389 .name = "qns_pcie", 1390 .channels = 1, 1391 .buswidth = 8, 1392 .mas_rpm_id = -1, 1393 .slv_rpm_id = -1, 1394 .num_links = 1, 1395 .links = qns_pcie_links, 1396 }; 1397 1398 static const u16 mmnrt_virt_slave_links[] = { 1399 SHIKRA_MASTER_MMRT_VIRT, 1400 }; 1401 1402 static struct qcom_icc_node mmnrt_virt_slave = { 1403 .id = SHIKRA_SLAVE_MMNRT_VIRT, 1404 .name = "mmnrt_virt_slave", 1405 .channels = 1, 1406 .buswidth = 16, 1407 .mas_rpm_id = -1, 1408 .slv_rpm_id = -1, 1409 .num_links = 1, 1410 .links = mmnrt_virt_slave_links, 1411 }; 1412 1413 static const u16 qns_mm_memnoc_links[] = { 1414 SHIKRA_MASTER_MNOC_HF_MEM_NOC, 1415 }; 1416 1417 static struct qcom_icc_node qns_mm_memnoc = { 1418 .id = SHIKRA_SLAVE_MM_MEMNOC, 1419 .name = "qns_mm_memnoc", 1420 .channels = 1, 1421 .buswidth = 16, 1422 .mas_rpm_id = -1, 1423 .slv_rpm_id = -1, 1424 .num_links = 1, 1425 .links = qns_mm_memnoc_links, 1426 }; 1427 1428 static struct qcom_icc_node qhs_apss = { 1429 .id = SHIKRA_SLAVE_APPSS, 1430 .name = "qhs_apss", 1431 .channels = 1, 1432 .buswidth = 8, 1433 .mas_rpm_id = -1, 1434 .slv_rpm_id = -1, 1435 }; 1436 1437 static struct qcom_icc_node qhs_mcuss = { 1438 .id = SHIKRA_SLAVE_MCUSS, 1439 .name = "qhs_mcuss", 1440 .channels = 1, 1441 .buswidth = 4, 1442 .mas_rpm_id = -1, 1443 .slv_rpm_id = 319, 1444 }; 1445 1446 static struct qcom_icc_node qhs_wcss = { 1447 .id = SHIKRA_SLAVE_WCSS, 1448 .name = "qhs_wcss", 1449 .channels = 1, 1450 .buswidth = 4, 1451 .mas_rpm_id = -1, 1452 .slv_rpm_id = 23, 1453 }; 1454 1455 static const u16 qns_memnoc_sf_links[] = { 1456 SHIKRA_MASTER_SNOC_SF_MEM_NOC, 1457 }; 1458 1459 static struct qcom_icc_node qns_memnoc_sf = { 1460 .id = SHIKRA_SLAVE_MEMNOC_SF, 1461 .name = "qns_memnoc_sf", 1462 .channels = 1, 1463 .buswidth = 16, 1464 .mas_rpm_id = -1, 1465 .slv_rpm_id = 313, 1466 .num_links = 1, 1467 .links = qns_memnoc_sf_links, 1468 }; 1469 1470 static const u16 qns_snoc_cnoc_links[] = { 1471 SHIKRA_SNOC_CNOC_MAS, 1472 }; 1473 1474 static struct qcom_icc_node qns_snoc_cnoc = { 1475 .id = SHIKRA_SNOC_CNOC_SLV, 1476 .name = "qns_snoc_cnoc", 1477 .channels = 1, 1478 .buswidth = 8, 1479 .mas_rpm_id = -1, 1480 .slv_rpm_id = 25, 1481 .num_links = 1, 1482 .links = qns_snoc_cnoc_links, 1483 }; 1484 1485 static struct qcom_icc_node qxs_bootimem = { 1486 .id = SHIKRA_SLAVE_BOOTIMEM, 1487 .name = "qxs_bootimem", 1488 .channels = 1, 1489 .buswidth = 8, 1490 .mas_rpm_id = -1, 1491 .slv_rpm_id = -1, 1492 }; 1493 1494 static struct qcom_icc_node qxs_imem = { 1495 .id = SHIKRA_SLAVE_OCIMEM, 1496 .name = "qxs_imem", 1497 .channels = 1, 1498 .buswidth = 8, 1499 .mas_rpm_id = -1, 1500 .slv_rpm_id = 26, 1501 }; 1502 1503 static struct qcom_icc_node qxs_pimem = { 1504 .id = SHIKRA_SLAVE_PIMEM, 1505 .name = "qxs_pimem", 1506 .channels = 1, 1507 .buswidth = 8, 1508 .mas_rpm_id = -1, 1509 .slv_rpm_id = -1, 1510 }; 1511 1512 static struct qcom_icc_node srvc_snoc = { 1513 .id = SHIKRA_SLAVE_SERVICE_SNOC, 1514 .name = "srvc_snoc", 1515 .channels = 1, 1516 .buswidth = 4, 1517 .mas_rpm_id = -1, 1518 .slv_rpm_id = -1, 1519 }; 1520 1521 static struct qcom_icc_node xs_pcie2_0 = { 1522 .id = SHIKRA_SLAVE_PCIE2_0, 1523 .name = "xs_pcie2_0", 1524 .channels = 1, 1525 .buswidth = 8, 1526 .mas_rpm_id = -1, 1527 .slv_rpm_id = -1, 1528 }; 1529 1530 static struct qcom_icc_node xs_qdss_stm = { 1531 .id = SHIKRA_SLAVE_QDSS_STM, 1532 .name = "xs_qdss_stm", 1533 .channels = 1, 1534 .buswidth = 4, 1535 .mas_rpm_id = -1, 1536 .slv_rpm_id = 30, 1537 }; 1538 1539 static struct qcom_icc_node xs_sys_tcu_cfg = { 1540 .id = SHIKRA_SLAVE_TCU, 1541 .name = "xs_sys_tcu_cfg", 1542 .channels = 1, 1543 .buswidth = 8, 1544 .mas_rpm_id = -1, 1545 .slv_rpm_id = -1, 1546 }; 1547 1548 static const u16 qns_pcie_memnoc_links[] = { 1549 SHIKRA_MASTER_ANOC_PCIE_MEM_NOC, 1550 }; 1551 1552 static struct qcom_icc_node qns_pcie_memnoc = { 1553 .id = SHIKRA_SLAVE_PCIE_MEMNOC, 1554 .name = "qns_pcie_memnoc", 1555 .channels = 1, 1556 .buswidth = 8, 1557 .mas_rpm_id = -1, 1558 .slv_rpm_id = 317, 1559 .num_links = 1, 1560 .links = qns_pcie_memnoc_links, 1561 }; 1562 1563 static const u16 qns_anoc_snoc_links[] = { 1564 SHIKRA_MASTER_ANOC_SNOC, 1565 }; 1566 1567 static struct qcom_icc_node qns_anoc_snoc = { 1568 .id = SHIKRA_SLAVE_ANOC_SNOC, 1569 .name = "qns_anoc_snoc", 1570 .channels = 1, 1571 .buswidth = 16, 1572 .mas_rpm_id = -1, 1573 .slv_rpm_id = 141, 1574 .num_links = 1, 1575 .links = qns_anoc_snoc_links, 1576 }; 1577 1578 /* NoC descriptors */ 1579 static struct qcom_icc_node * const shikra_clk_virt_nodes[] = { 1580 [MASTER_QUP_CORE_0] = &qup0_core_master, 1581 [SLAVE_QUP_CORE_0] = &qup0_core_slave, 1582 }; 1583 1584 static const struct qcom_icc_desc shikra_clk_virt = { 1585 .type = QCOM_ICC_QNOC, 1586 .nodes = shikra_clk_virt_nodes, 1587 .num_nodes = ARRAY_SIZE(shikra_clk_virt_nodes), 1588 .bus_clk_desc = &qup_clk, 1589 .keep_alive = true, 1590 }; 1591 1592 static struct qcom_icc_node * const shikra_config_noc_nodes[] = { 1593 [SNOC_CNOC_MAS] = &qnm_snoc_cnoc, 1594 [MASTER_QDSS_DAP] = &xm_dap, 1595 [SLAVE_AHB2PHY_USB] = &qhs_ahb2phy_usb, 1596 [SLAVE_APSS_THROTTLE_CFG] = &qhs_apss_throttle_cfg, 1597 [SLAVE_AUDIO] = &qhs_audio, 1598 [SLAVE_BOOT_ROM] = &qhs_boot_rom, 1599 [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_throttle_cfg, 1600 [SLAVE_CAMERA_CFG] = &qhs_camera_ss_cfg, 1601 [SLAVE_CDSP_THROTTLE_CFG] = &qhs_cdsp_throttle_cfg, 1602 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1603 [SLAVE_DSP_CFG] = &qhs_compute_dsp_cfg, 1604 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 1605 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, 1606 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1607 [SLAVE_DDR_SS_CFG] = &qhs_ddr_ss_cfg, 1608 [SLAVE_DISPLAY_CFG] = &qhs_disp_ss_cfg, 1609 [SLAVE_EMAC0_CFG] = &qhs_emac0_cfg, 1610 [SLAVE_EMAC1_CFG] = &qhs_emac1_cfg, 1611 [SLAVE_GPU_CFG] = &qhs_gpu_cfg, 1612 [SLAVE_GPU_THROTTLE_CFG] = &qhs_gpu_throttle_cfg, 1613 [SLAVE_HWKM] = &qhs_hwkm, 1614 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1615 [SLAVE_MAPSS] = &qhs_mapss, 1616 [SLAVE_MDSP_MPU_CFG] = &qhs_mdsp_mpu_cfg, 1617 [SLAVE_MESSAGE_RAM] = &qhs_mesg_ram, 1618 [SLAVE_MSS] = &qhs_mss, 1619 [SLAVE_PCIE_CFG] = &qhs_pcie_cfg, 1620 [SLAVE_PDM] = &qhs_pdm, 1621 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 1622 [SLAVE_PKA_WRAPPER_CFG] = &qhs_pka_wrapper, 1623 [SLAVE_PMIC_ARB] = &qhs_pmic_arb, 1624 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1625 [SLAVE_QM_CFG] = &qhs_qm_cfg, 1626 [SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg, 1627 [SLAVE_QPIC] = &qhs_qpic, 1628 [SLAVE_QUP_0] = &qhs_qup0, 1629 [SLAVE_RPM] = &qhs_rpm, 1630 [SLAVE_SDCC_1] = &qhs_sdc1, 1631 [SLAVE_SDCC_2] = &qhs_sdc2, 1632 [SLAVE_SECURITY] = &qhs_security, 1633 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, 1634 [SNOC_SF_THROTTLE_CFG] = &qhs_snoc_sf_throttle_cfg, 1635 [SLAVE_TLMM] = &qhs_tlmm, 1636 [SLAVE_TSCSS] = &qhs_tscss, 1637 [SLAVE_USB2] = &qhs_usb2, 1638 [SLAVE_USB3] = &qhs_usb3, 1639 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1640 [SLAVE_VENUS_THROTTLE_CFG] = &qhs_venus_throttle_cfg, 1641 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 1642 [SLAVE_SERVICE_CNOC] = &srvc_cnoc, 1643 }; 1644 1645 static const struct regmap_config shikra_config_noc_regmap_config = { 1646 .reg_bits = 32, 1647 .reg_stride = 4, 1648 .val_bits = 32, 1649 .max_register = 0x8080, 1650 .fast_io = true, 1651 }; 1652 1653 static const struct qcom_icc_desc shikra_config_noc = { 1654 .type = QCOM_ICC_QNOC, 1655 .nodes = shikra_config_noc_nodes, 1656 .num_nodes = ARRAY_SIZE(shikra_config_noc_nodes), 1657 .bus_clk_desc = &bus_1_clk, 1658 .regmap_cfg = &shikra_config_noc_regmap_config, 1659 .keep_alive = true, 1660 }; 1661 1662 static struct qcom_icc_node * const shikra_mc_virt_nodes[] = { 1663 [MASTER_LLCC] = &llcc_mc, 1664 [SLAVE_EBI_CH0] = &ebi, 1665 }; 1666 1667 static const struct qcom_icc_desc shikra_mc_virt = { 1668 .type = QCOM_ICC_QNOC, 1669 .nodes = shikra_mc_virt_nodes, 1670 .num_nodes = ARRAY_SIZE(shikra_mc_virt_nodes), 1671 .bus_clk_desc = &bimc_clk, 1672 .keep_alive = true, 1673 .ab_coeff = 152, 1674 }; 1675 1676 static struct qcom_icc_node * const shikra_mem_noc_core_nodes[] = { 1677 [MASTER_GRAPHICS_3D] = &qnm_gpu, 1678 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 1679 [MASTER_ANOC_PCIE_MEM_NOC] = &qnm_pcie, 1680 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 1681 [MASTER_AMPSS_M0] = &xm_apps, 1682 [MASTER_SYS_TCU] = &xm_tcu, 1683 [SLAVE_LLCC] = &qns_llcc, 1684 [SLAVE_MEMNOC_SNOC] = &qns_memnoc_snoc, 1685 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, 1686 }; 1687 1688 static const struct regmap_config shikra_mem_noc_core_regmap_config = { 1689 .reg_bits = 32, 1690 .reg_stride = 4, 1691 .val_bits = 32, 1692 .max_register = 0x43080, 1693 .fast_io = true, 1694 }; 1695 1696 static const struct qcom_icc_desc shikra_mem_noc_core = { 1697 .type = QCOM_ICC_QNOC, 1698 .nodes = shikra_mem_noc_core_nodes, 1699 .num_nodes = ARRAY_SIZE(shikra_mem_noc_core_nodes), 1700 .bus_clk_desc = &mem_1_clk, 1701 .regmap_cfg = &shikra_mem_noc_core_regmap_config, 1702 .intf_clocks = memnoc_intf_clocks, 1703 .num_intf_clocks = ARRAY_SIZE(memnoc_intf_clocks), 1704 .qos_offset = 0x28000, 1705 .keep_alive = true, 1706 .ab_coeff = 142, 1707 }; 1708 1709 static struct qcom_icc_node * const shikra_mmnrt_virt_nodes[] = { 1710 [MASTER_CAMNOC_SF] = &qnm_camera_nrt, 1711 [MASTER_VIDEO_P0] = &qxm_venus0, 1712 [MASTER_VIDEO_PROC] = &qxm_venus_cpu, 1713 [SLAVE_MMNRT_VIRT] = &mmnrt_virt_slave, 1714 }; 1715 1716 static const struct regmap_config shikra_sys_noc_regmap_config = { 1717 .reg_bits = 32, 1718 .reg_stride = 4, 1719 .val_bits = 32, 1720 .max_register = 0x6a080, 1721 .fast_io = true, 1722 }; 1723 1724 static const struct qcom_icc_desc shikra_mmnrt_virt = { 1725 .type = QCOM_ICC_QNOC, 1726 .nodes = shikra_mmnrt_virt_nodes, 1727 .num_nodes = ARRAY_SIZE(shikra_mmnrt_virt_nodes), 1728 .bus_clk_desc = &mmaxi_0_clk, 1729 .regmap_cfg = &shikra_sys_noc_regmap_config, 1730 .qos_offset = 0x51000, 1731 .keep_alive = true, 1732 .ab_coeff = 142, 1733 }; 1734 1735 static struct qcom_icc_node * const shikra_mmrt_virt_nodes[] = { 1736 [MASTER_CAMNOC_HF] = &qnm_camera_rt, 1737 [MASTER_MDP_PORT0] = &qxm_mdp0, 1738 [MASTER_MMRT_VIRT] = &mmrt_virt_master, 1739 [SLAVE_MM_MEMNOC] = &qns_mm_memnoc, 1740 }; 1741 1742 static const struct qcom_icc_desc shikra_mmrt_virt = { 1743 .type = QCOM_ICC_QNOC, 1744 .nodes = shikra_mmrt_virt_nodes, 1745 .num_nodes = ARRAY_SIZE(shikra_mmrt_virt_nodes), 1746 .bus_clk_desc = &mmaxi_1_clk, 1747 .regmap_cfg = &shikra_sys_noc_regmap_config, 1748 .qos_offset = 0x51000, 1749 .keep_alive = true, 1750 .ab_coeff = 142, 1751 }; 1752 1753 static struct qcom_icc_node * const shikra_sys_noc_nodes[] = { 1754 [MASTER_SNOC_CFG] = &qhm_snoc_cfg, 1755 [MASTER_TIC] = &qhm_tic, 1756 [MASTER_ANOC_SNOC] = &qnm_anoc_snoc, 1757 [MASTER_MEMNOC_PCIE] = &qnm_memnoc_pcie, 1758 [MASTER_MEMNOC_SNOC] = &qnm_memnoc_snoc, 1759 [MASTER_PIMEM] = &qxm_pimem, 1760 [MASTER_PCIE2_0] = &xm_pcie2_0, 1761 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 1762 [MASTER_QPIC] = &qhm_qpic, 1763 [MASTER_QUP_0] = &qhm_qup0, 1764 [CNOC_SNOC_MAS] = &qnm_cnoc_snoc, 1765 [MASTER_AUDIO] = &qxm_audio, 1766 [MASTER_EMAC_0] = &xm_emac_0, 1767 [MASTER_EMAC_1] = &xm_emac_1, 1768 [MASTER_QDSS_ETR] = &xm_qdss_etr, 1769 [MASTER_SDCC_1] = &xm_sdc1, 1770 [MASTER_SDCC_2] = &xm_sdc2, 1771 [MASTER_USB2_0] = &xm_usb2_0, 1772 [MASTER_USB3] = &xm_usb3_0, 1773 [MASTER_CRYPTO_CORE0] = &crypto_c0, 1774 [SLAVE_APPSS] = &qhs_apss, 1775 [SLAVE_MCUSS] = &qhs_mcuss, 1776 [SLAVE_WCSS] = &qhs_wcss, 1777 [SLAVE_MEMNOC_SF] = &qns_memnoc_sf, 1778 [SNOC_CNOC_SLV] = &qns_snoc_cnoc, 1779 [SLAVE_BOOTIMEM] = &qxs_bootimem, 1780 [SLAVE_OCIMEM] = &qxs_imem, 1781 [SLAVE_PIMEM] = &qxs_pimem, 1782 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 1783 [SLAVE_PCIE2_0] = &xs_pcie2_0, 1784 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1785 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1786 [SLAVE_PCIE_MEMNOC] = &qns_pcie_memnoc, 1787 [SLAVE_ANOC_SNOC] = &qns_anoc_snoc, 1788 }; 1789 1790 static const struct qcom_icc_desc shikra_sys_noc = { 1791 .type = QCOM_ICC_QNOC, 1792 .nodes = shikra_sys_noc_nodes, 1793 .num_nodes = ARRAY_SIZE(shikra_sys_noc_nodes), 1794 .bus_clk_desc = &bus_2_clk, 1795 .regmap_cfg = &shikra_sys_noc_regmap_config, 1796 .intf_clocks = sys_noc_intf_clocks, 1797 .num_intf_clocks = ARRAY_SIZE(sys_noc_intf_clocks), 1798 .qos_offset = 0x51000, 1799 .keep_alive = true, 1800 }; 1801 1802 static const struct of_device_id shikra_qnoc_of_match[] = { 1803 { .compatible = "qcom,shikra-clk-virt", .data = &shikra_clk_virt }, 1804 { .compatible = "qcom,shikra-config-noc", .data = &shikra_config_noc }, 1805 { .compatible = "qcom,shikra-mc-virt", .data = &shikra_mc_virt }, 1806 { .compatible = "qcom,shikra-mem-noc-core", .data = &shikra_mem_noc_core }, 1807 { .compatible = "qcom,shikra-mmnrt-virt", .data = &shikra_mmnrt_virt }, 1808 { .compatible = "qcom,shikra-mmrt-virt", .data = &shikra_mmrt_virt }, 1809 { .compatible = "qcom,shikra-sys-noc", .data = &shikra_sys_noc }, 1810 { }, 1811 }; 1812 MODULE_DEVICE_TABLE(of, shikra_qnoc_of_match); 1813 1814 static struct platform_driver shikra_qnoc_driver = { 1815 .probe = qnoc_probe, 1816 .remove = qnoc_remove, 1817 .driver = { 1818 .name = "qnoc-shikra", 1819 .of_match_table = shikra_qnoc_of_match, 1820 .sync_state = icc_sync_state, 1821 }, 1822 }; 1823 1824 static int __init qnoc_driver_init(void) 1825 { 1826 return platform_driver_register(&shikra_qnoc_driver); 1827 } 1828 core_initcall(qnoc_driver_init); 1829 1830 static void __exit qnoc_driver_exit(void) 1831 { 1832 platform_driver_unregister(&shikra_qnoc_driver); 1833 } 1834 module_exit(qnoc_driver_exit); 1835 1836 MODULE_DESCRIPTION("Qualcomm Shikra NoC driver"); 1837 MODULE_LICENSE("GPL"); 1838