1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include <linux/device.h> 7 #include <linux/interconnect.h> 8 #include <linux/interconnect-provider.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 #include <dt-bindings/interconnect/qcom,sdx65.h> 12 13 #include "bcm-voter.h" 14 #include "icc-rpmh.h" 15 16 static struct qcom_icc_node llcc_mc; 17 static struct qcom_icc_node acm_tcu; 18 static struct qcom_icc_node qnm_snoc_gc; 19 static struct qcom_icc_node xm_apps_rdwr; 20 static struct qcom_icc_node qhm_audio; 21 static struct qcom_icc_node qhm_blsp1; 22 static struct qcom_icc_node qhm_qdss_bam; 23 static struct qcom_icc_node qhm_qpic; 24 static struct qcom_icc_node qhm_snoc_cfg; 25 static struct qcom_icc_node qhm_spmi_fetcher1; 26 static struct qcom_icc_node qnm_aggre_noc; 27 static struct qcom_icc_node qnm_ipa; 28 static struct qcom_icc_node qnm_memnoc; 29 static struct qcom_icc_node qnm_memnoc_pcie; 30 static struct qcom_icc_node qxm_crypto; 31 static struct qcom_icc_node xm_ipa2pcie_slv; 32 static struct qcom_icc_node xm_pcie; 33 static struct qcom_icc_node xm_qdss_etr; 34 static struct qcom_icc_node xm_sdc1; 35 static struct qcom_icc_node xm_usb3; 36 static struct qcom_icc_node ebi; 37 static struct qcom_icc_node qns_llcc; 38 static struct qcom_icc_node qns_memnoc_snoc; 39 static struct qcom_icc_node qns_sys_pcie; 40 static struct qcom_icc_node qhs_aoss; 41 static struct qcom_icc_node qhs_apss; 42 static struct qcom_icc_node qhs_audio; 43 static struct qcom_icc_node qhs_blsp1; 44 static struct qcom_icc_node qhs_clk_ctl; 45 static struct qcom_icc_node qhs_crypto0_cfg; 46 static struct qcom_icc_node qhs_ddrss_cfg; 47 static struct qcom_icc_node qhs_ecc_cfg; 48 static struct qcom_icc_node qhs_imem_cfg; 49 static struct qcom_icc_node qhs_ipa; 50 static struct qcom_icc_node qhs_mss_cfg; 51 static struct qcom_icc_node qhs_pcie_parf; 52 static struct qcom_icc_node qhs_pdm; 53 static struct qcom_icc_node qhs_prng; 54 static struct qcom_icc_node qhs_qdss_cfg; 55 static struct qcom_icc_node qhs_qpic; 56 static struct qcom_icc_node qhs_sdc1; 57 static struct qcom_icc_node qhs_snoc_cfg; 58 static struct qcom_icc_node qhs_spmi_fetcher; 59 static struct qcom_icc_node qhs_spmi_vgi_coex; 60 static struct qcom_icc_node qhs_tcsr; 61 static struct qcom_icc_node qhs_tlmm; 62 static struct qcom_icc_node qhs_usb3; 63 static struct qcom_icc_node qhs_usb3_phy; 64 static struct qcom_icc_node qns_aggre_noc; 65 static struct qcom_icc_node qns_snoc_memnoc; 66 static struct qcom_icc_node qxs_imem; 67 static struct qcom_icc_node srvc_snoc; 68 static struct qcom_icc_node xs_pcie; 69 static struct qcom_icc_node xs_qdss_stm; 70 static struct qcom_icc_node xs_sys_tcu_cfg; 71 72 static struct qcom_icc_node llcc_mc = { 73 .name = "llcc_mc", 74 .channels = 1, 75 .buswidth = 4, 76 .num_links = 1, 77 .link_nodes = { &ebi }, 78 }; 79 80 static struct qcom_icc_node acm_tcu = { 81 .name = "acm_tcu", 82 .channels = 1, 83 .buswidth = 8, 84 .num_links = 3, 85 .link_nodes = { &qns_llcc, 86 &qns_memnoc_snoc, 87 &qns_sys_pcie }, 88 }; 89 90 static struct qcom_icc_node qnm_snoc_gc = { 91 .name = "qnm_snoc_gc", 92 .channels = 1, 93 .buswidth = 16, 94 .num_links = 1, 95 .link_nodes = { &qns_llcc }, 96 }; 97 98 static struct qcom_icc_node xm_apps_rdwr = { 99 .name = "xm_apps_rdwr", 100 .channels = 1, 101 .buswidth = 16, 102 .num_links = 3, 103 .link_nodes = { &qns_llcc, 104 &qns_memnoc_snoc, 105 &qns_sys_pcie }, 106 }; 107 108 static struct qcom_icc_node qhm_audio = { 109 .name = "qhm_audio", 110 .channels = 1, 111 .buswidth = 4, 112 .num_links = 1, 113 .link_nodes = { &qns_aggre_noc }, 114 }; 115 116 static struct qcom_icc_node qhm_blsp1 = { 117 .name = "qhm_blsp1", 118 .channels = 1, 119 .buswidth = 4, 120 .num_links = 1, 121 .link_nodes = { &qns_aggre_noc }, 122 }; 123 124 static struct qcom_icc_node qhm_qdss_bam = { 125 .name = "qhm_qdss_bam", 126 .channels = 1, 127 .buswidth = 4, 128 .num_links = 26, 129 .link_nodes = { &qhs_aoss, 130 &qhs_audio, 131 &qhs_blsp1, 132 &qhs_clk_ctl, 133 &qhs_crypto0_cfg, 134 &qhs_ddrss_cfg, 135 &qhs_ecc_cfg, 136 &qhs_imem_cfg, 137 &qhs_ipa, 138 &qhs_mss_cfg, 139 &qhs_pcie_parf, 140 &qhs_pdm, 141 &qhs_prng, 142 &qhs_qdss_cfg, 143 &qhs_qpic, 144 &qhs_sdc1, 145 &qhs_snoc_cfg, 146 &qhs_spmi_fetcher, 147 &qhs_spmi_vgi_coex, 148 &qhs_tcsr, 149 &qhs_tlmm, 150 &qhs_usb3, 151 &qhs_usb3_phy, 152 &qns_snoc_memnoc, 153 &qxs_imem, 154 &xs_sys_tcu_cfg }, 155 }; 156 157 static struct qcom_icc_node qhm_qpic = { 158 .name = "qhm_qpic", 159 .channels = 1, 160 .buswidth = 4, 161 .num_links = 4, 162 .link_nodes = { &qhs_aoss, 163 &qhs_audio, 164 &qhs_ipa, 165 &qns_aggre_noc }, 166 }; 167 168 static struct qcom_icc_node qhm_snoc_cfg = { 169 .name = "qhm_snoc_cfg", 170 .channels = 1, 171 .buswidth = 4, 172 .num_links = 1, 173 .link_nodes = { &srvc_snoc }, 174 }; 175 176 static struct qcom_icc_node qhm_spmi_fetcher1 = { 177 .name = "qhm_spmi_fetcher1", 178 .channels = 1, 179 .buswidth = 4, 180 .num_links = 2, 181 .link_nodes = { &qhs_aoss, 182 &qns_aggre_noc }, 183 }; 184 185 static struct qcom_icc_node qnm_aggre_noc = { 186 .name = "qnm_aggre_noc", 187 .channels = 1, 188 .buswidth = 8, 189 .num_links = 29, 190 .link_nodes = { &qhs_aoss, 191 &qhs_apss, 192 &qhs_audio, 193 &qhs_blsp1, 194 &qhs_clk_ctl, 195 &qhs_crypto0_cfg, 196 &qhs_ddrss_cfg, 197 &qhs_ecc_cfg, 198 &qhs_imem_cfg, 199 &qhs_ipa, 200 &qhs_mss_cfg, 201 &qhs_pcie_parf, 202 &qhs_pdm, 203 &qhs_prng, 204 &qhs_qdss_cfg, 205 &qhs_qpic, 206 &qhs_sdc1, 207 &qhs_snoc_cfg, 208 &qhs_spmi_fetcher, 209 &qhs_spmi_vgi_coex, 210 &qhs_tcsr, 211 &qhs_tlmm, 212 &qhs_usb3, 213 &qhs_usb3_phy, 214 &qns_snoc_memnoc, 215 &qxs_imem, 216 &xs_pcie, 217 &xs_qdss_stm, 218 &xs_sys_tcu_cfg }, 219 }; 220 221 static struct qcom_icc_node qnm_ipa = { 222 .name = "qnm_ipa", 223 .channels = 1, 224 .buswidth = 8, 225 .num_links = 26, 226 .link_nodes = { &qhs_aoss, 227 &qhs_audio, 228 &qhs_blsp1, 229 &qhs_clk_ctl, 230 &qhs_crypto0_cfg, 231 &qhs_ddrss_cfg, 232 &qhs_ecc_cfg, 233 &qhs_imem_cfg, 234 &qhs_ipa, 235 &qhs_mss_cfg, 236 &qhs_pcie_parf, 237 &qhs_pdm, 238 &qhs_prng, 239 &qhs_qdss_cfg, 240 &qhs_qpic, 241 &qhs_sdc1, 242 &qhs_snoc_cfg, 243 &qhs_spmi_fetcher, 244 &qhs_tcsr, 245 &qhs_tlmm, 246 &qhs_usb3, 247 &qhs_usb3_phy, 248 &qns_snoc_memnoc, 249 &qxs_imem, 250 &xs_pcie, 251 &xs_qdss_stm }, 252 }; 253 254 static struct qcom_icc_node qnm_memnoc = { 255 .name = "qnm_memnoc", 256 .channels = 1, 257 .buswidth = 8, 258 .num_links = 27, 259 .link_nodes = { &qhs_aoss, 260 &qhs_apss, 261 &qhs_audio, 262 &qhs_blsp1, 263 &qhs_clk_ctl, 264 &qhs_crypto0_cfg, 265 &qhs_ddrss_cfg, 266 &qhs_ecc_cfg, 267 &qhs_imem_cfg, 268 &qhs_ipa, 269 &qhs_mss_cfg, 270 &qhs_pcie_parf, 271 &qhs_pdm, 272 &qhs_prng, 273 &qhs_qdss_cfg, 274 &qhs_qpic, 275 &qhs_sdc1, 276 &qhs_snoc_cfg, 277 &qhs_spmi_fetcher, 278 &qhs_spmi_vgi_coex, 279 &qhs_tcsr, 280 &qhs_tlmm, 281 &qhs_usb3, 282 &qhs_usb3_phy, 283 &qxs_imem, 284 &xs_qdss_stm, 285 &xs_sys_tcu_cfg }, 286 }; 287 288 static struct qcom_icc_node qnm_memnoc_pcie = { 289 .name = "qnm_memnoc_pcie", 290 .channels = 1, 291 .buswidth = 8, 292 .num_links = 1, 293 .link_nodes = { &xs_pcie }, 294 }; 295 296 static struct qcom_icc_node qxm_crypto = { 297 .name = "qxm_crypto", 298 .channels = 1, 299 .buswidth = 8, 300 .num_links = 2, 301 .link_nodes = { &qhs_aoss, 302 &qns_aggre_noc }, 303 }; 304 305 static struct qcom_icc_node xm_ipa2pcie_slv = { 306 .name = "xm_ipa2pcie_slv", 307 .channels = 1, 308 .buswidth = 8, 309 .num_links = 1, 310 .link_nodes = { &xs_pcie }, 311 }; 312 313 static struct qcom_icc_node xm_pcie = { 314 .name = "xm_pcie", 315 .channels = 1, 316 .buswidth = 8, 317 .num_links = 1, 318 .link_nodes = { &qns_aggre_noc }, 319 }; 320 321 static struct qcom_icc_node xm_qdss_etr = { 322 .name = "xm_qdss_etr", 323 .channels = 1, 324 .buswidth = 8, 325 .num_links = 26, 326 .link_nodes = { &qhs_aoss, 327 &qhs_audio, 328 &qhs_blsp1, 329 &qhs_clk_ctl, 330 &qhs_crypto0_cfg, 331 &qhs_ddrss_cfg, 332 &qhs_ecc_cfg, 333 &qhs_imem_cfg, 334 &qhs_ipa, 335 &qhs_mss_cfg, 336 &qhs_pcie_parf, 337 &qhs_pdm, 338 &qhs_prng, 339 &qhs_qdss_cfg, 340 &qhs_qpic, 341 &qhs_sdc1, 342 &qhs_snoc_cfg, 343 &qhs_spmi_fetcher, 344 &qhs_spmi_vgi_coex, 345 &qhs_tcsr, 346 &qhs_tlmm, 347 &qhs_usb3, 348 &qhs_usb3_phy, 349 &qns_snoc_memnoc, 350 &qxs_imem, 351 &xs_sys_tcu_cfg }, 352 }; 353 354 static struct qcom_icc_node xm_sdc1 = { 355 .name = "xm_sdc1", 356 .channels = 1, 357 .buswidth = 8, 358 .num_links = 4, 359 .link_nodes = { &qhs_aoss, 360 &qhs_audio, 361 &qhs_ipa, 362 &qns_aggre_noc }, 363 }; 364 365 static struct qcom_icc_node xm_usb3 = { 366 .name = "xm_usb3", 367 .channels = 1, 368 .buswidth = 8, 369 .num_links = 1, 370 .link_nodes = { &qns_aggre_noc }, 371 }; 372 373 static struct qcom_icc_node ebi = { 374 .name = "ebi", 375 .channels = 1, 376 .buswidth = 4, 377 }; 378 379 static struct qcom_icc_node qns_llcc = { 380 .name = "qns_llcc", 381 .channels = 1, 382 .buswidth = 16, 383 .num_links = 1, 384 .link_nodes = { &llcc_mc }, 385 }; 386 387 static struct qcom_icc_node qns_memnoc_snoc = { 388 .name = "qns_memnoc_snoc", 389 .channels = 1, 390 .buswidth = 8, 391 .num_links = 1, 392 .link_nodes = { &qnm_memnoc }, 393 }; 394 395 static struct qcom_icc_node qns_sys_pcie = { 396 .name = "qns_sys_pcie", 397 .channels = 1, 398 .buswidth = 8, 399 .num_links = 1, 400 .link_nodes = { &qnm_memnoc_pcie }, 401 }; 402 403 static struct qcom_icc_node qhs_aoss = { 404 .name = "qhs_aoss", 405 .channels = 1, 406 .buswidth = 4, 407 }; 408 409 static struct qcom_icc_node qhs_apss = { 410 .name = "qhs_apss", 411 .channels = 1, 412 .buswidth = 4, 413 }; 414 415 static struct qcom_icc_node qhs_audio = { 416 .name = "qhs_audio", 417 .channels = 1, 418 .buswidth = 4, 419 }; 420 421 static struct qcom_icc_node qhs_blsp1 = { 422 .name = "qhs_blsp1", 423 .channels = 1, 424 .buswidth = 4, 425 }; 426 427 static struct qcom_icc_node qhs_clk_ctl = { 428 .name = "qhs_clk_ctl", 429 .channels = 1, 430 .buswidth = 4, 431 }; 432 433 static struct qcom_icc_node qhs_crypto0_cfg = { 434 .name = "qhs_crypto0_cfg", 435 .channels = 1, 436 .buswidth = 4, 437 }; 438 439 static struct qcom_icc_node qhs_ddrss_cfg = { 440 .name = "qhs_ddrss_cfg", 441 .channels = 1, 442 .buswidth = 4, 443 }; 444 445 static struct qcom_icc_node qhs_ecc_cfg = { 446 .name = "qhs_ecc_cfg", 447 .channels = 1, 448 .buswidth = 4, 449 }; 450 451 static struct qcom_icc_node qhs_imem_cfg = { 452 .name = "qhs_imem_cfg", 453 .channels = 1, 454 .buswidth = 4, 455 }; 456 457 static struct qcom_icc_node qhs_ipa = { 458 .name = "qhs_ipa", 459 .channels = 1, 460 .buswidth = 4, 461 }; 462 463 static struct qcom_icc_node qhs_mss_cfg = { 464 .name = "qhs_mss_cfg", 465 .channels = 1, 466 .buswidth = 4, 467 }; 468 469 static struct qcom_icc_node qhs_pcie_parf = { 470 .name = "qhs_pcie_parf", 471 .channels = 1, 472 .buswidth = 4, 473 }; 474 475 static struct qcom_icc_node qhs_pdm = { 476 .name = "qhs_pdm", 477 .channels = 1, 478 .buswidth = 4, 479 }; 480 481 static struct qcom_icc_node qhs_prng = { 482 .name = "qhs_prng", 483 .channels = 1, 484 .buswidth = 4, 485 }; 486 487 static struct qcom_icc_node qhs_qdss_cfg = { 488 .name = "qhs_qdss_cfg", 489 .channels = 1, 490 .buswidth = 4, 491 }; 492 493 static struct qcom_icc_node qhs_qpic = { 494 .name = "qhs_qpic", 495 .channels = 1, 496 .buswidth = 4, 497 }; 498 499 static struct qcom_icc_node qhs_sdc1 = { 500 .name = "qhs_sdc1", 501 .channels = 1, 502 .buswidth = 4, 503 }; 504 505 static struct qcom_icc_node qhs_snoc_cfg = { 506 .name = "qhs_snoc_cfg", 507 .channels = 1, 508 .buswidth = 4, 509 .num_links = 1, 510 .link_nodes = { &qhm_snoc_cfg }, 511 }; 512 513 static struct qcom_icc_node qhs_spmi_fetcher = { 514 .name = "qhs_spmi_fetcher", 515 .channels = 1, 516 .buswidth = 4, 517 }; 518 519 static struct qcom_icc_node qhs_spmi_vgi_coex = { 520 .name = "qhs_spmi_vgi_coex", 521 .channels = 1, 522 .buswidth = 4, 523 }; 524 525 static struct qcom_icc_node qhs_tcsr = { 526 .name = "qhs_tcsr", 527 .channels = 1, 528 .buswidth = 4, 529 }; 530 531 static struct qcom_icc_node qhs_tlmm = { 532 .name = "qhs_tlmm", 533 .channels = 1, 534 .buswidth = 4, 535 }; 536 537 static struct qcom_icc_node qhs_usb3 = { 538 .name = "qhs_usb3", 539 .channels = 1, 540 .buswidth = 4, 541 }; 542 543 static struct qcom_icc_node qhs_usb3_phy = { 544 .name = "qhs_usb3_phy", 545 .channels = 1, 546 .buswidth = 4, 547 }; 548 549 static struct qcom_icc_node qns_aggre_noc = { 550 .name = "qns_aggre_noc", 551 .channels = 1, 552 .buswidth = 8, 553 .num_links = 1, 554 .link_nodes = { &qnm_aggre_noc }, 555 }; 556 557 static struct qcom_icc_node qns_snoc_memnoc = { 558 .name = "qns_snoc_memnoc", 559 .channels = 1, 560 .buswidth = 16, 561 .num_links = 1, 562 .link_nodes = { &qnm_snoc_gc }, 563 }; 564 565 static struct qcom_icc_node qxs_imem = { 566 .name = "qxs_imem", 567 .channels = 1, 568 .buswidth = 8, 569 }; 570 571 static struct qcom_icc_node srvc_snoc = { 572 .name = "srvc_snoc", 573 .channels = 1, 574 .buswidth = 4, 575 }; 576 577 static struct qcom_icc_node xs_pcie = { 578 .name = "xs_pcie", 579 .channels = 1, 580 .buswidth = 8, 581 }; 582 583 static struct qcom_icc_node xs_qdss_stm = { 584 .name = "xs_qdss_stm", 585 .channels = 1, 586 .buswidth = 4, 587 }; 588 589 static struct qcom_icc_node xs_sys_tcu_cfg = { 590 .name = "xs_sys_tcu_cfg", 591 .channels = 1, 592 .buswidth = 8, 593 }; 594 595 static struct qcom_icc_bcm bcm_ce0 = { 596 .name = "CE0", 597 .keepalive = false, 598 .num_nodes = 1, 599 .nodes = { &qxm_crypto }, 600 }; 601 602 static struct qcom_icc_bcm bcm_mc0 = { 603 .name = "MC0", 604 .keepalive = true, 605 .num_nodes = 1, 606 .nodes = { &ebi }, 607 }; 608 609 static struct qcom_icc_bcm bcm_pn0 = { 610 .name = "PN0", 611 .keepalive = true, 612 .num_nodes = 26, 613 .nodes = { &qhm_snoc_cfg, 614 &qhs_aoss, 615 &qhs_apss, 616 &qhs_audio, 617 &qhs_blsp1, 618 &qhs_clk_ctl, 619 &qhs_crypto0_cfg, 620 &qhs_ddrss_cfg, 621 &qhs_ecc_cfg, 622 &qhs_imem_cfg, 623 &qhs_ipa, 624 &qhs_mss_cfg, 625 &qhs_pcie_parf, 626 &qhs_pdm, 627 &qhs_prng, 628 &qhs_qdss_cfg, 629 &qhs_qpic, 630 &qhs_sdc1, 631 &qhs_snoc_cfg, 632 &qhs_spmi_fetcher, 633 &qhs_spmi_vgi_coex, 634 &qhs_tcsr, 635 &qhs_tlmm, 636 &qhs_usb3, 637 &qhs_usb3_phy, 638 &srvc_snoc 639 }, 640 }; 641 642 static struct qcom_icc_bcm bcm_pn1 = { 643 .name = "PN1", 644 .keepalive = false, 645 .num_nodes = 1, 646 .nodes = { &xm_sdc1 }, 647 }; 648 649 static struct qcom_icc_bcm bcm_pn2 = { 650 .name = "PN2", 651 .keepalive = false, 652 .num_nodes = 2, 653 .nodes = { &qhm_audio, &qhm_spmi_fetcher1 }, 654 }; 655 656 static struct qcom_icc_bcm bcm_pn3 = { 657 .name = "PN3", 658 .keepalive = false, 659 .num_nodes = 2, 660 .nodes = { &qhm_blsp1, &qhm_qpic }, 661 }; 662 663 static struct qcom_icc_bcm bcm_pn4 = { 664 .name = "PN4", 665 .keepalive = false, 666 .num_nodes = 1, 667 .nodes = { &qxm_crypto }, 668 }; 669 670 static struct qcom_icc_bcm bcm_sh0 = { 671 .name = "SH0", 672 .keepalive = true, 673 .num_nodes = 1, 674 .nodes = { &qns_llcc }, 675 }; 676 677 static struct qcom_icc_bcm bcm_sh1 = { 678 .name = "SH1", 679 .keepalive = false, 680 .num_nodes = 1, 681 .nodes = { &qns_memnoc_snoc }, 682 }; 683 684 static struct qcom_icc_bcm bcm_sh3 = { 685 .name = "SH3", 686 .keepalive = false, 687 .num_nodes = 1, 688 .nodes = { &xm_apps_rdwr }, 689 }; 690 691 static struct qcom_icc_bcm bcm_sn0 = { 692 .name = "SN0", 693 .keepalive = true, 694 .num_nodes = 1, 695 .nodes = { &qns_snoc_memnoc }, 696 }; 697 698 static struct qcom_icc_bcm bcm_sn1 = { 699 .name = "SN1", 700 .keepalive = false, 701 .num_nodes = 1, 702 .nodes = { &qxs_imem }, 703 }; 704 705 static struct qcom_icc_bcm bcm_sn2 = { 706 .name = "SN2", 707 .keepalive = false, 708 .num_nodes = 1, 709 .nodes = { &xs_qdss_stm }, 710 }; 711 712 static struct qcom_icc_bcm bcm_sn3 = { 713 .name = "SN3", 714 .keepalive = false, 715 .num_nodes = 1, 716 .nodes = { &xs_sys_tcu_cfg }, 717 }; 718 719 static struct qcom_icc_bcm bcm_sn5 = { 720 .name = "SN5", 721 .keepalive = false, 722 .num_nodes = 1, 723 .nodes = { &xs_pcie }, 724 }; 725 726 static struct qcom_icc_bcm bcm_sn6 = { 727 .name = "SN6", 728 .keepalive = false, 729 .num_nodes = 2, 730 .nodes = { &qhm_qdss_bam, &xm_qdss_etr }, 731 }; 732 733 static struct qcom_icc_bcm bcm_sn7 = { 734 .name = "SN7", 735 .keepalive = false, 736 .num_nodes = 4, 737 .nodes = { &qnm_aggre_noc, &xm_pcie, &xm_usb3, &qns_aggre_noc }, 738 }; 739 740 static struct qcom_icc_bcm bcm_sn8 = { 741 .name = "SN8", 742 .keepalive = false, 743 .num_nodes = 1, 744 .nodes = { &qnm_memnoc }, 745 }; 746 747 static struct qcom_icc_bcm bcm_sn9 = { 748 .name = "SN9", 749 .keepalive = false, 750 .num_nodes = 1, 751 .nodes = { &qnm_memnoc_pcie }, 752 }; 753 754 static struct qcom_icc_bcm bcm_sn10 = { 755 .name = "SN10", 756 .keepalive = false, 757 .num_nodes = 2, 758 .nodes = { &qnm_ipa, &xm_ipa2pcie_slv }, 759 }; 760 761 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 762 &bcm_mc0, 763 }; 764 765 static struct qcom_icc_node * const mc_virt_nodes[] = { 766 [MASTER_LLCC] = &llcc_mc, 767 [SLAVE_EBI1] = &ebi, 768 }; 769 770 static const struct qcom_icc_desc sdx65_mc_virt = { 771 .nodes = mc_virt_nodes, 772 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 773 .bcms = mc_virt_bcms, 774 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 775 }; 776 777 static struct qcom_icc_bcm * const mem_noc_bcms[] = { 778 &bcm_sh0, 779 &bcm_sh1, 780 &bcm_sh3, 781 }; 782 783 static struct qcom_icc_node * const mem_noc_nodes[] = { 784 [MASTER_TCU_0] = &acm_tcu, 785 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 786 [MASTER_APPSS_PROC] = &xm_apps_rdwr, 787 [SLAVE_LLCC] = &qns_llcc, 788 [SLAVE_MEM_NOC_SNOC] = &qns_memnoc_snoc, 789 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_sys_pcie, 790 }; 791 792 static const struct qcom_icc_desc sdx65_mem_noc = { 793 .nodes = mem_noc_nodes, 794 .num_nodes = ARRAY_SIZE(mem_noc_nodes), 795 .bcms = mem_noc_bcms, 796 .num_bcms = ARRAY_SIZE(mem_noc_bcms), 797 }; 798 799 static struct qcom_icc_bcm * const system_noc_bcms[] = { 800 &bcm_ce0, 801 &bcm_pn0, 802 &bcm_pn1, 803 &bcm_pn2, 804 &bcm_pn3, 805 &bcm_pn4, 806 &bcm_sn0, 807 &bcm_sn1, 808 &bcm_sn2, 809 &bcm_sn3, 810 &bcm_sn5, 811 &bcm_sn6, 812 &bcm_sn7, 813 &bcm_sn8, 814 &bcm_sn9, 815 &bcm_sn10, 816 }; 817 818 static struct qcom_icc_node * const system_noc_nodes[] = { 819 [MASTER_AUDIO] = &qhm_audio, 820 [MASTER_BLSP_1] = &qhm_blsp1, 821 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 822 [MASTER_QPIC] = &qhm_qpic, 823 [MASTER_SNOC_CFG] = &qhm_snoc_cfg, 824 [MASTER_SPMI_FETCHER] = &qhm_spmi_fetcher1, 825 [MASTER_ANOC_SNOC] = &qnm_aggre_noc, 826 [MASTER_IPA] = &qnm_ipa, 827 [MASTER_MEM_NOC_SNOC] = &qnm_memnoc, 828 [MASTER_MEM_NOC_PCIE_SNOC] = &qnm_memnoc_pcie, 829 [MASTER_CRYPTO] = &qxm_crypto, 830 [MASTER_IPA_PCIE] = &xm_ipa2pcie_slv, 831 [MASTER_PCIE_0] = &xm_pcie, 832 [MASTER_QDSS_ETR] = &xm_qdss_etr, 833 [MASTER_SDCC_1] = &xm_sdc1, 834 [MASTER_USB3] = &xm_usb3, 835 [SLAVE_AOSS] = &qhs_aoss, 836 [SLAVE_APPSS] = &qhs_apss, 837 [SLAVE_AUDIO] = &qhs_audio, 838 [SLAVE_BLSP_1] = &qhs_blsp1, 839 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 840 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 841 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg, 842 [SLAVE_ECC_CFG] = &qhs_ecc_cfg, 843 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 844 [SLAVE_IPA_CFG] = &qhs_ipa, 845 [SLAVE_CNOC_MSS] = &qhs_mss_cfg, 846 [SLAVE_PCIE_PARF] = &qhs_pcie_parf, 847 [SLAVE_PDM] = &qhs_pdm, 848 [SLAVE_PRNG] = &qhs_prng, 849 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 850 [SLAVE_QPIC] = &qhs_qpic, 851 [SLAVE_SDCC_1] = &qhs_sdc1, 852 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, 853 [SLAVE_SPMI_FETCHER] = &qhs_spmi_fetcher, 854 [SLAVE_SPMI_VGI_COEX] = &qhs_spmi_vgi_coex, 855 [SLAVE_TCSR] = &qhs_tcsr, 856 [SLAVE_TLMM] = &qhs_tlmm, 857 [SLAVE_USB3] = &qhs_usb3, 858 [SLAVE_USB3_PHY_CFG] = &qhs_usb3_phy, 859 [SLAVE_ANOC_SNOC] = &qns_aggre_noc, 860 [SLAVE_SNOC_MEM_NOC_GC] = &qns_snoc_memnoc, 861 [SLAVE_IMEM] = &qxs_imem, 862 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 863 [SLAVE_PCIE_0] = &xs_pcie, 864 [SLAVE_QDSS_STM] = &xs_qdss_stm, 865 [SLAVE_TCU] = &xs_sys_tcu_cfg, 866 }; 867 868 static const struct qcom_icc_desc sdx65_system_noc = { 869 .nodes = system_noc_nodes, 870 .num_nodes = ARRAY_SIZE(system_noc_nodes), 871 .bcms = system_noc_bcms, 872 .num_bcms = ARRAY_SIZE(system_noc_bcms), 873 }; 874 875 static const struct of_device_id qnoc_of_match[] = { 876 { .compatible = "qcom,sdx65-mc-virt", 877 .data = &sdx65_mc_virt}, 878 { .compatible = "qcom,sdx65-mem-noc", 879 .data = &sdx65_mem_noc}, 880 { .compatible = "qcom,sdx65-system-noc", 881 .data = &sdx65_system_noc}, 882 { } 883 }; 884 MODULE_DEVICE_TABLE(of, qnoc_of_match); 885 886 static struct platform_driver qnoc_driver = { 887 .probe = qcom_icc_rpmh_probe, 888 .remove = qcom_icc_rpmh_remove, 889 .driver = { 890 .name = "qnoc-sdx65", 891 .of_match_table = qnoc_of_match, 892 .sync_state = icc_sync_state, 893 }, 894 }; 895 module_platform_driver(qnoc_driver); 896 897 MODULE_DESCRIPTION("Qualcomm SDX65 NoC driver"); 898 MODULE_LICENSE("GPL v2"); 899