1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Qualcomm SDX55 interconnect driver 4 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 5 * 6 * Copyright (c) 2021, Linaro Ltd. 7 * 8 */ 9 10 #include <linux/device.h> 11 #include <linux/interconnect.h> 12 #include <linux/interconnect-provider.h> 13 #include <linux/module.h> 14 #include <linux/platform_device.h> 15 #include <dt-bindings/interconnect/qcom,sdx55.h> 16 17 #include "bcm-voter.h" 18 #include "icc-rpmh.h" 19 20 static struct qcom_icc_node llcc_mc; 21 static struct qcom_icc_node acm_tcu; 22 static struct qcom_icc_node qnm_snoc_gc; 23 static struct qcom_icc_node xm_apps_rdwr; 24 static struct qcom_icc_node qhm_audio; 25 static struct qcom_icc_node qhm_blsp1; 26 static struct qcom_icc_node qhm_qdss_bam; 27 static struct qcom_icc_node qhm_qpic; 28 static struct qcom_icc_node qhm_snoc_cfg; 29 static struct qcom_icc_node qhm_spmi_fetcher1; 30 static struct qcom_icc_node qnm_aggre_noc; 31 static struct qcom_icc_node qnm_ipa; 32 static struct qcom_icc_node qnm_memnoc; 33 static struct qcom_icc_node qnm_memnoc_pcie; 34 static struct qcom_icc_node qxm_crypto; 35 static struct qcom_icc_node xm_emac; 36 static struct qcom_icc_node xm_ipa2pcie_slv; 37 static struct qcom_icc_node xm_pcie; 38 static struct qcom_icc_node xm_qdss_etr; 39 static struct qcom_icc_node xm_sdc1; 40 static struct qcom_icc_node xm_usb3; 41 static struct qcom_icc_node ebi; 42 static struct qcom_icc_node qns_llcc; 43 static struct qcom_icc_node qns_memnoc_snoc; 44 static struct qcom_icc_node qns_sys_pcie; 45 static struct qcom_icc_node qhs_aop; 46 static struct qcom_icc_node qhs_aoss; 47 static struct qcom_icc_node qhs_apss; 48 static struct qcom_icc_node qhs_audio; 49 static struct qcom_icc_node qhs_blsp1; 50 static struct qcom_icc_node qhs_clk_ctl; 51 static struct qcom_icc_node qhs_crypto0_cfg; 52 static struct qcom_icc_node qhs_ddrss_cfg; 53 static struct qcom_icc_node qhs_ecc_cfg; 54 static struct qcom_icc_node qhs_emac_cfg; 55 static struct qcom_icc_node qhs_imem_cfg; 56 static struct qcom_icc_node qhs_ipa; 57 static struct qcom_icc_node qhs_mss_cfg; 58 static struct qcom_icc_node qhs_pcie_parf; 59 static struct qcom_icc_node qhs_pdm; 60 static struct qcom_icc_node qhs_prng; 61 static struct qcom_icc_node qhs_qdss_cfg; 62 static struct qcom_icc_node qhs_qpic; 63 static struct qcom_icc_node qhs_sdc1; 64 static struct qcom_icc_node qhs_snoc_cfg; 65 static struct qcom_icc_node qhs_spmi_fetcher; 66 static struct qcom_icc_node qhs_spmi_vgi_coex; 67 static struct qcom_icc_node qhs_tcsr; 68 static struct qcom_icc_node qhs_tlmm; 69 static struct qcom_icc_node qhs_usb3; 70 static struct qcom_icc_node qhs_usb3_phy; 71 static struct qcom_icc_node qns_aggre_noc; 72 static struct qcom_icc_node qns_snoc_memnoc; 73 static struct qcom_icc_node qxs_imem; 74 static struct qcom_icc_node srvc_snoc; 75 static struct qcom_icc_node xs_pcie; 76 static struct qcom_icc_node xs_qdss_stm; 77 static struct qcom_icc_node xs_sys_tcu_cfg; 78 79 static struct qcom_icc_node llcc_mc = { 80 .name = "llcc_mc", 81 .channels = 4, 82 .buswidth = 4, 83 .num_links = 1, 84 .link_nodes = { &ebi }, 85 }; 86 87 static struct qcom_icc_node acm_tcu = { 88 .name = "acm_tcu", 89 .channels = 1, 90 .buswidth = 8, 91 .num_links = 3, 92 .link_nodes = { &qns_llcc, 93 &qns_memnoc_snoc, 94 &qns_sys_pcie }, 95 }; 96 97 static struct qcom_icc_node qnm_snoc_gc = { 98 .name = "qnm_snoc_gc", 99 .channels = 1, 100 .buswidth = 8, 101 .num_links = 1, 102 .link_nodes = { &qns_llcc }, 103 }; 104 105 static struct qcom_icc_node xm_apps_rdwr = { 106 .name = "xm_apps_rdwr", 107 .channels = 1, 108 .buswidth = 16, 109 .num_links = 3, 110 .link_nodes = { &qns_llcc, 111 &qns_memnoc_snoc, 112 &qns_sys_pcie }, 113 }; 114 115 static struct qcom_icc_node qhm_audio = { 116 .name = "qhm_audio", 117 .channels = 1, 118 .buswidth = 4, 119 .num_links = 1, 120 .link_nodes = { &qns_aggre_noc }, 121 }; 122 123 static struct qcom_icc_node qhm_blsp1 = { 124 .name = "qhm_blsp1", 125 .channels = 1, 126 .buswidth = 4, 127 .num_links = 1, 128 .link_nodes = { &qns_aggre_noc }, 129 }; 130 131 static struct qcom_icc_node qhm_qdss_bam = { 132 .name = "qhm_qdss_bam", 133 .channels = 1, 134 .buswidth = 4, 135 .num_links = 28, 136 .link_nodes = { &qhs_snoc_cfg, 137 &qhs_emac_cfg, 138 &qhs_usb3, 139 &qhs_tlmm, 140 &qhs_spmi_fetcher, 141 &qhs_qdss_cfg, 142 &qhs_pdm, 143 &qns_snoc_memnoc, 144 &qhs_tcsr, 145 &qhs_ddrss_cfg, 146 &qhs_spmi_vgi_coex, 147 &qhs_qpic, 148 &qxs_imem, 149 &qhs_ipa, 150 &qhs_usb3_phy, 151 &qhs_aop, 152 &qhs_blsp1, 153 &qhs_sdc1, 154 &qhs_mss_cfg, 155 &qhs_pcie_parf, 156 &qhs_ecc_cfg, 157 &qhs_audio, 158 &qhs_aoss, 159 &qhs_prng, 160 &qhs_crypto0_cfg, 161 &xs_sys_tcu_cfg, 162 &qhs_clk_ctl, 163 &qhs_imem_cfg }, 164 }; 165 166 static struct qcom_icc_node qhm_qpic = { 167 .name = "qhm_qpic", 168 .channels = 1, 169 .buswidth = 4, 170 .num_links = 5, 171 .link_nodes = { &qhs_aoss, 172 &qhs_ipa, 173 &qns_aggre_noc, 174 &qhs_aop, 175 &qhs_audio }, 176 }; 177 178 static struct qcom_icc_node qhm_snoc_cfg = { 179 .name = "qhm_snoc_cfg", 180 .channels = 1, 181 .buswidth = 4, 182 .num_links = 1, 183 .link_nodes = { &srvc_snoc }, 184 }; 185 186 static struct qcom_icc_node qhm_spmi_fetcher1 = { 187 .name = "qhm_spmi_fetcher1", 188 .channels = 1, 189 .buswidth = 4, 190 .num_links = 3, 191 .link_nodes = { &qhs_aoss, 192 &qns_aggre_noc, 193 &qhs_aop }, 194 }; 195 196 static struct qcom_icc_node qnm_aggre_noc = { 197 .name = "qnm_aggre_noc", 198 .channels = 1, 199 .buswidth = 8, 200 .num_links = 30, 201 .link_nodes = { &xs_pcie, 202 &qhs_snoc_cfg, 203 &qhs_sdc1, 204 &qhs_tlmm, 205 &qhs_spmi_fetcher, 206 &qhs_qdss_cfg, 207 &qhs_pdm, 208 &qns_snoc_memnoc, 209 &qhs_tcsr, 210 &qhs_ddrss_cfg, 211 &qhs_spmi_vgi_coex, 212 &xs_qdss_stm, 213 &qhs_qpic, 214 &qxs_imem, 215 &qhs_ipa, 216 &qhs_usb3_phy, 217 &qhs_aop, 218 &qhs_blsp1, 219 &qhs_usb3, 220 &qhs_mss_cfg, 221 &qhs_pcie_parf, 222 &qhs_ecc_cfg, 223 &qhs_apss, 224 &qhs_audio, 225 &qhs_aoss, 226 &qhs_prng, 227 &qhs_crypto0_cfg, 228 &xs_sys_tcu_cfg, 229 &qhs_clk_ctl, 230 &qhs_imem_cfg }, 231 }; 232 233 static struct qcom_icc_node qnm_ipa = { 234 .name = "qnm_ipa", 235 .channels = 1, 236 .buswidth = 8, 237 .num_links = 27, 238 .link_nodes = { &qhs_snoc_cfg, 239 &qhs_emac_cfg, 240 &qhs_usb3, 241 &qhs_aoss, 242 &qhs_spmi_fetcher, 243 &qhs_qdss_cfg, 244 &qhs_pdm, 245 &qns_snoc_memnoc, 246 &qhs_tcsr, 247 &qhs_ddrss_cfg, 248 &xs_qdss_stm, 249 &qhs_qpic, 250 &qxs_imem, 251 &qhs_ipa, 252 &qhs_usb3_phy, 253 &qhs_aop, 254 &qhs_blsp1, 255 &qhs_sdc1, 256 &qhs_mss_cfg, 257 &qhs_pcie_parf, 258 &qhs_ecc_cfg, 259 &qhs_audio, 260 &qhs_tlmm, 261 &qhs_prng, 262 &qhs_crypto0_cfg, 263 &qhs_clk_ctl, 264 &qhs_imem_cfg }, 265 }; 266 267 static struct qcom_icc_node qnm_memnoc = { 268 .name = "qnm_memnoc", 269 .channels = 1, 270 .buswidth = 8, 271 .num_links = 29, 272 .link_nodes = { &qhs_snoc_cfg, 273 &qhs_emac_cfg, 274 &qhs_usb3, 275 &qhs_tlmm, 276 &qhs_spmi_fetcher, 277 &qhs_qdss_cfg, 278 &qhs_pdm, 279 &qhs_tcsr, 280 &qhs_ddrss_cfg, 281 &qhs_spmi_vgi_coex, 282 &xs_qdss_stm, 283 &qhs_qpic, 284 &qxs_imem, 285 &qhs_ipa, 286 &qhs_usb3_phy, 287 &qhs_aop, 288 &qhs_blsp1, 289 &qhs_sdc1, 290 &qhs_mss_cfg, 291 &qhs_pcie_parf, 292 &qhs_ecc_cfg, 293 &qhs_apss, 294 &qhs_audio, 295 &qhs_aoss, 296 &qhs_prng, 297 &qhs_crypto0_cfg, 298 &xs_sys_tcu_cfg, 299 &qhs_clk_ctl, 300 &qhs_imem_cfg }, 301 }; 302 303 static struct qcom_icc_node qnm_memnoc_pcie = { 304 .name = "qnm_memnoc_pcie", 305 .channels = 1, 306 .buswidth = 8, 307 .num_links = 1, 308 .link_nodes = { &xs_pcie }, 309 }; 310 311 static struct qcom_icc_node qxm_crypto = { 312 .name = "qxm_crypto", 313 .channels = 1, 314 .buswidth = 8, 315 .num_links = 3, 316 .link_nodes = { &qhs_aoss, 317 &qns_aggre_noc, 318 &qhs_aop }, 319 }; 320 321 static struct qcom_icc_node xm_emac = { 322 .name = "xm_emac", 323 .channels = 1, 324 .buswidth = 8, 325 .num_links = 1, 326 .link_nodes = { &qns_aggre_noc }, 327 }; 328 329 static struct qcom_icc_node xm_ipa2pcie_slv = { 330 .name = "xm_ipa2pcie_slv", 331 .channels = 1, 332 .buswidth = 8, 333 .num_links = 1, 334 .link_nodes = { &xs_pcie }, 335 }; 336 337 static struct qcom_icc_node xm_pcie = { 338 .name = "xm_pcie", 339 .channels = 1, 340 .buswidth = 8, 341 .num_links = 1, 342 .link_nodes = { &qns_aggre_noc }, 343 }; 344 345 static struct qcom_icc_node xm_qdss_etr = { 346 .name = "xm_qdss_etr", 347 .channels = 1, 348 .buswidth = 8, 349 .num_links = 28, 350 .link_nodes = { &qhs_snoc_cfg, 351 &qhs_emac_cfg, 352 &qhs_usb3, 353 &qhs_aoss, 354 &qhs_spmi_fetcher, 355 &qhs_qdss_cfg, 356 &qhs_pdm, 357 &qns_snoc_memnoc, 358 &qhs_tcsr, 359 &qhs_ddrss_cfg, 360 &qhs_spmi_vgi_coex, 361 &qhs_qpic, 362 &qxs_imem, 363 &qhs_ipa, 364 &qhs_usb3_phy, 365 &qhs_aop, 366 &qhs_blsp1, 367 &qhs_sdc1, 368 &qhs_mss_cfg, 369 &qhs_pcie_parf, 370 &qhs_ecc_cfg, 371 &qhs_audio, 372 &qhs_aoss, 373 &qhs_prng, 374 &qhs_crypto0_cfg, 375 &xs_sys_tcu_cfg, 376 &qhs_clk_ctl, 377 &qhs_imem_cfg }, 378 }; 379 380 static struct qcom_icc_node xm_sdc1 = { 381 .name = "xm_sdc1", 382 .channels = 1, 383 .buswidth = 8, 384 .num_links = 5, 385 .link_nodes = { &qhs_aoss, 386 &qhs_ipa, 387 &qns_aggre_noc, 388 &qhs_aop, 389 &qhs_audio }, 390 }; 391 392 static struct qcom_icc_node xm_usb3 = { 393 .name = "xm_usb3", 394 .channels = 1, 395 .buswidth = 8, 396 .num_links = 1, 397 .link_nodes = { &qns_aggre_noc }, 398 }; 399 400 static struct qcom_icc_node ebi = { 401 .name = "ebi", 402 .channels = 1, 403 .buswidth = 4, 404 }; 405 406 static struct qcom_icc_node qns_llcc = { 407 .name = "qns_llcc", 408 .channels = 1, 409 .buswidth = 16, 410 .num_links = 1, 411 .link_nodes = { &ebi }, 412 }; 413 414 static struct qcom_icc_node qns_memnoc_snoc = { 415 .name = "qns_memnoc_snoc", 416 .channels = 1, 417 .buswidth = 8, 418 .num_links = 1, 419 .link_nodes = { &qnm_memnoc }, 420 }; 421 422 static struct qcom_icc_node qns_sys_pcie = { 423 .name = "qns_sys_pcie", 424 .channels = 1, 425 .buswidth = 8, 426 .num_links = 1, 427 .link_nodes = { &qnm_memnoc_pcie }, 428 }; 429 430 static struct qcom_icc_node qhs_aop = { 431 .name = "qhs_aop", 432 .channels = 1, 433 .buswidth = 4, 434 }; 435 436 static struct qcom_icc_node qhs_aoss = { 437 .name = "qhs_aoss", 438 .channels = 1, 439 .buswidth = 4, 440 }; 441 442 static struct qcom_icc_node qhs_apss = { 443 .name = "qhs_apss", 444 .channels = 1, 445 .buswidth = 4, 446 }; 447 448 static struct qcom_icc_node qhs_audio = { 449 .name = "qhs_audio", 450 .channels = 1, 451 .buswidth = 4, 452 }; 453 454 static struct qcom_icc_node qhs_blsp1 = { 455 .name = "qhs_blsp1", 456 .channels = 1, 457 .buswidth = 4, 458 }; 459 460 static struct qcom_icc_node qhs_clk_ctl = { 461 .name = "qhs_clk_ctl", 462 .channels = 1, 463 .buswidth = 4, 464 }; 465 466 static struct qcom_icc_node qhs_crypto0_cfg = { 467 .name = "qhs_crypto0_cfg", 468 .channels = 1, 469 .buswidth = 4, 470 }; 471 472 static struct qcom_icc_node qhs_ddrss_cfg = { 473 .name = "qhs_ddrss_cfg", 474 .channels = 1, 475 .buswidth = 4, 476 }; 477 478 static struct qcom_icc_node qhs_ecc_cfg = { 479 .name = "qhs_ecc_cfg", 480 .channels = 1, 481 .buswidth = 4, 482 }; 483 484 static struct qcom_icc_node qhs_emac_cfg = { 485 .name = "qhs_emac_cfg", 486 .channels = 1, 487 .buswidth = 4, 488 }; 489 490 static struct qcom_icc_node qhs_imem_cfg = { 491 .name = "qhs_imem_cfg", 492 .channels = 1, 493 .buswidth = 4, 494 }; 495 496 static struct qcom_icc_node qhs_ipa = { 497 .name = "qhs_ipa", 498 .channels = 1, 499 .buswidth = 4, 500 }; 501 502 static struct qcom_icc_node qhs_mss_cfg = { 503 .name = "qhs_mss_cfg", 504 .channels = 1, 505 .buswidth = 4, 506 }; 507 508 static struct qcom_icc_node qhs_pcie_parf = { 509 .name = "qhs_pcie_parf", 510 .channels = 1, 511 .buswidth = 4, 512 }; 513 514 static struct qcom_icc_node qhs_pdm = { 515 .name = "qhs_pdm", 516 .channels = 1, 517 .buswidth = 4, 518 }; 519 520 static struct qcom_icc_node qhs_prng = { 521 .name = "qhs_prng", 522 .channels = 1, 523 .buswidth = 4, 524 }; 525 526 static struct qcom_icc_node qhs_qdss_cfg = { 527 .name = "qhs_qdss_cfg", 528 .channels = 1, 529 .buswidth = 4, 530 }; 531 532 static struct qcom_icc_node qhs_qpic = { 533 .name = "qhs_qpic", 534 .channels = 1, 535 .buswidth = 4, 536 }; 537 538 static struct qcom_icc_node qhs_sdc1 = { 539 .name = "qhs_sdc1", 540 .channels = 1, 541 .buswidth = 4, 542 }; 543 544 static struct qcom_icc_node qhs_snoc_cfg = { 545 .name = "qhs_snoc_cfg", 546 .channels = 1, 547 .buswidth = 4, 548 .num_links = 1, 549 .link_nodes = { &qhm_snoc_cfg }, 550 }; 551 552 static struct qcom_icc_node qhs_spmi_fetcher = { 553 .name = "qhs_spmi_fetcher", 554 .channels = 1, 555 .buswidth = 4, 556 }; 557 558 static struct qcom_icc_node qhs_spmi_vgi_coex = { 559 .name = "qhs_spmi_vgi_coex", 560 .channels = 1, 561 .buswidth = 4, 562 }; 563 564 static struct qcom_icc_node qhs_tcsr = { 565 .name = "qhs_tcsr", 566 .channels = 1, 567 .buswidth = 4, 568 }; 569 570 static struct qcom_icc_node qhs_tlmm = { 571 .name = "qhs_tlmm", 572 .channels = 1, 573 .buswidth = 4, 574 }; 575 576 static struct qcom_icc_node qhs_usb3 = { 577 .name = "qhs_usb3", 578 .channels = 1, 579 .buswidth = 4, 580 }; 581 582 static struct qcom_icc_node qhs_usb3_phy = { 583 .name = "qhs_usb3_phy", 584 .channels = 1, 585 .buswidth = 4, 586 }; 587 588 static struct qcom_icc_node qns_aggre_noc = { 589 .name = "qns_aggre_noc", 590 .channels = 1, 591 .buswidth = 8, 592 .num_links = 1, 593 .link_nodes = { &qnm_aggre_noc }, 594 }; 595 596 static struct qcom_icc_node qns_snoc_memnoc = { 597 .name = "qns_snoc_memnoc", 598 .channels = 1, 599 .buswidth = 8, 600 .num_links = 1, 601 .link_nodes = { &qnm_snoc_gc }, 602 }; 603 604 static struct qcom_icc_node qxs_imem = { 605 .name = "qxs_imem", 606 .channels = 1, 607 .buswidth = 8, 608 }; 609 610 static struct qcom_icc_node srvc_snoc = { 611 .name = "srvc_snoc", 612 .channels = 1, 613 .buswidth = 4, 614 }; 615 616 static struct qcom_icc_node xs_pcie = { 617 .name = "xs_pcie", 618 .channels = 1, 619 .buswidth = 8, 620 }; 621 622 static struct qcom_icc_node xs_qdss_stm = { 623 .name = "xs_qdss_stm", 624 .channels = 1, 625 .buswidth = 4, 626 }; 627 628 static struct qcom_icc_node xs_sys_tcu_cfg = { 629 .name = "xs_sys_tcu_cfg", 630 .channels = 1, 631 .buswidth = 8, 632 }; 633 634 static struct qcom_icc_bcm bcm_mc0 = { 635 .name = "MC0", 636 .keepalive = true, 637 .num_nodes = 1, 638 .nodes = { &ebi }, 639 }; 640 641 static struct qcom_icc_bcm bcm_sh0 = { 642 .name = "SH0", 643 .keepalive = true, 644 .num_nodes = 1, 645 .nodes = { &qns_llcc }, 646 }; 647 648 static struct qcom_icc_bcm bcm_ce0 = { 649 .name = "CE0", 650 .keepalive = false, 651 .num_nodes = 1, 652 .nodes = { &qxm_crypto }, 653 }; 654 655 static struct qcom_icc_bcm bcm_pn0 = { 656 .name = "PN0", 657 .keepalive = false, 658 .num_nodes = 1, 659 .nodes = { &qhm_snoc_cfg }, 660 }; 661 662 static struct qcom_icc_bcm bcm_sh3 = { 663 .name = "SH3", 664 .keepalive = false, 665 .num_nodes = 1, 666 .nodes = { &xm_apps_rdwr }, 667 }; 668 669 static struct qcom_icc_bcm bcm_sh4 = { 670 .name = "SH4", 671 .keepalive = false, 672 .num_nodes = 2, 673 .nodes = { &qns_memnoc_snoc, &qns_sys_pcie }, 674 }; 675 676 static struct qcom_icc_bcm bcm_sn0 = { 677 .name = "SN0", 678 .keepalive = true, 679 .num_nodes = 1, 680 .nodes = { &qns_snoc_memnoc }, 681 }; 682 683 static struct qcom_icc_bcm bcm_sn1 = { 684 .name = "SN1", 685 .keepalive = false, 686 .num_nodes = 1, 687 .nodes = { &qxs_imem }, 688 }; 689 690 static struct qcom_icc_bcm bcm_pn1 = { 691 .name = "PN1", 692 .keepalive = false, 693 .num_nodes = 1, 694 .nodes = { &xm_sdc1 }, 695 }; 696 697 static struct qcom_icc_bcm bcm_pn2 = { 698 .name = "PN2", 699 .keepalive = false, 700 .num_nodes = 2, 701 .nodes = { &qhm_audio, &qhm_spmi_fetcher1 }, 702 }; 703 704 static struct qcom_icc_bcm bcm_sn3 = { 705 .name = "SN3", 706 .keepalive = false, 707 .num_nodes = 1, 708 .nodes = { &xs_qdss_stm }, 709 }; 710 711 static struct qcom_icc_bcm bcm_pn3 = { 712 .name = "PN3", 713 .keepalive = false, 714 .num_nodes = 2, 715 .nodes = { &qhm_blsp1, &qhm_qpic }, 716 }; 717 718 static struct qcom_icc_bcm bcm_sn4 = { 719 .name = "SN4", 720 .keepalive = false, 721 .num_nodes = 1, 722 .nodes = { &xs_sys_tcu_cfg }, 723 }; 724 725 static struct qcom_icc_bcm bcm_pn5 = { 726 .name = "PN5", 727 .keepalive = false, 728 .num_nodes = 1, 729 .nodes = { &qxm_crypto }, 730 }; 731 732 static struct qcom_icc_bcm bcm_sn6 = { 733 .name = "SN6", 734 .keepalive = false, 735 .num_nodes = 1, 736 .nodes = { &xs_pcie }, 737 }; 738 739 static struct qcom_icc_bcm bcm_sn7 = { 740 .name = "SN7", 741 .keepalive = false, 742 .num_nodes = 5, 743 .nodes = { &qnm_aggre_noc, &xm_emac, &xm_emac, &xm_usb3, &qns_aggre_noc }, 744 }; 745 746 static struct qcom_icc_bcm bcm_sn8 = { 747 .name = "SN8", 748 .keepalive = false, 749 .num_nodes = 2, 750 .nodes = { &qhm_qdss_bam, &xm_qdss_etr }, 751 }; 752 753 static struct qcom_icc_bcm bcm_sn9 = { 754 .name = "SN9", 755 .keepalive = false, 756 .num_nodes = 1, 757 .nodes = { &qnm_memnoc }, 758 }; 759 760 static struct qcom_icc_bcm bcm_sn10 = { 761 .name = "SN10", 762 .keepalive = false, 763 .num_nodes = 1, 764 .nodes = { &qnm_memnoc_pcie }, 765 }; 766 767 static struct qcom_icc_bcm bcm_sn11 = { 768 .name = "SN11", 769 .keepalive = false, 770 .num_nodes = 2, 771 .nodes = { &qnm_ipa, &xm_ipa2pcie_slv }, 772 }; 773 774 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 775 &bcm_mc0, 776 }; 777 778 static struct qcom_icc_node * const mc_virt_nodes[] = { 779 [MASTER_LLCC] = &llcc_mc, 780 [SLAVE_EBI_CH0] = &ebi, 781 }; 782 783 static const struct qcom_icc_desc sdx55_mc_virt = { 784 .nodes = mc_virt_nodes, 785 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 786 .bcms = mc_virt_bcms, 787 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 788 }; 789 790 static struct qcom_icc_bcm * const mem_noc_bcms[] = { 791 &bcm_sh0, 792 &bcm_sh3, 793 &bcm_sh4, 794 }; 795 796 static struct qcom_icc_node * const mem_noc_nodes[] = { 797 [MASTER_TCU_0] = &acm_tcu, 798 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 799 [MASTER_AMPSS_M0] = &xm_apps_rdwr, 800 [SLAVE_LLCC] = &qns_llcc, 801 [SLAVE_MEM_NOC_SNOC] = &qns_memnoc_snoc, 802 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_sys_pcie, 803 }; 804 805 static const struct qcom_icc_desc sdx55_mem_noc = { 806 .nodes = mem_noc_nodes, 807 .num_nodes = ARRAY_SIZE(mem_noc_nodes), 808 .bcms = mem_noc_bcms, 809 .num_bcms = ARRAY_SIZE(mem_noc_bcms), 810 }; 811 812 static struct qcom_icc_bcm * const system_noc_bcms[] = { 813 &bcm_ce0, 814 &bcm_pn0, 815 &bcm_pn1, 816 &bcm_pn2, 817 &bcm_pn3, 818 &bcm_pn5, 819 &bcm_sn0, 820 &bcm_sn1, 821 &bcm_sn3, 822 &bcm_sn4, 823 &bcm_sn6, 824 &bcm_sn7, 825 &bcm_sn8, 826 &bcm_sn9, 827 &bcm_sn10, 828 &bcm_sn11, 829 }; 830 831 static struct qcom_icc_node * const system_noc_nodes[] = { 832 [MASTER_AUDIO] = &qhm_audio, 833 [MASTER_BLSP_1] = &qhm_blsp1, 834 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 835 [MASTER_QPIC] = &qhm_qpic, 836 [MASTER_SNOC_CFG] = &qhm_snoc_cfg, 837 [MASTER_SPMI_FETCHER] = &qhm_spmi_fetcher1, 838 [MASTER_ANOC_SNOC] = &qnm_aggre_noc, 839 [MASTER_IPA] = &qnm_ipa, 840 [MASTER_MEM_NOC_SNOC] = &qnm_memnoc, 841 [MASTER_MEM_NOC_PCIE_SNOC] = &qnm_memnoc_pcie, 842 [MASTER_CRYPTO_CORE_0] = &qxm_crypto, 843 [MASTER_EMAC] = &xm_emac, 844 [MASTER_IPA_PCIE] = &xm_ipa2pcie_slv, 845 [MASTER_PCIE] = &xm_pcie, 846 [MASTER_QDSS_ETR] = &xm_qdss_etr, 847 [MASTER_SDCC_1] = &xm_sdc1, 848 [MASTER_USB3] = &xm_usb3, 849 [SLAVE_AOP] = &qhs_aop, 850 [SLAVE_AOSS] = &qhs_aoss, 851 [SLAVE_APPSS] = &qhs_apss, 852 [SLAVE_AUDIO] = &qhs_audio, 853 [SLAVE_BLSP_1] = &qhs_blsp1, 854 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 855 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 856 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg, 857 [SLAVE_ECC_CFG] = &qhs_ecc_cfg, 858 [SLAVE_EMAC_CFG] = &qhs_emac_cfg, 859 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 860 [SLAVE_IPA_CFG] = &qhs_ipa, 861 [SLAVE_CNOC_MSS] = &qhs_mss_cfg, 862 [SLAVE_PCIE_PARF] = &qhs_pcie_parf, 863 [SLAVE_PDM] = &qhs_pdm, 864 [SLAVE_PRNG] = &qhs_prng, 865 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 866 [SLAVE_QPIC] = &qhs_qpic, 867 [SLAVE_SDCC_1] = &qhs_sdc1, 868 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, 869 [SLAVE_SPMI_FETCHER] = &qhs_spmi_fetcher, 870 [SLAVE_SPMI_VGI_COEX] = &qhs_spmi_vgi_coex, 871 [SLAVE_TCSR] = &qhs_tcsr, 872 [SLAVE_TLMM] = &qhs_tlmm, 873 [SLAVE_USB3] = &qhs_usb3, 874 [SLAVE_USB3_PHY_CFG] = &qhs_usb3_phy, 875 [SLAVE_ANOC_SNOC] = &qns_aggre_noc, 876 [SLAVE_SNOC_MEM_NOC_GC] = &qns_snoc_memnoc, 877 [SLAVE_OCIMEM] = &qxs_imem, 878 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 879 [SLAVE_PCIE_0] = &xs_pcie, 880 [SLAVE_QDSS_STM] = &xs_qdss_stm, 881 [SLAVE_TCU] = &xs_sys_tcu_cfg, 882 }; 883 884 static const struct qcom_icc_desc sdx55_system_noc = { 885 .nodes = system_noc_nodes, 886 .num_nodes = ARRAY_SIZE(system_noc_nodes), 887 .bcms = system_noc_bcms, 888 .num_bcms = ARRAY_SIZE(system_noc_bcms), 889 }; 890 891 static const struct of_device_id qnoc_of_match[] = { 892 { .compatible = "qcom,sdx55-mc-virt", 893 .data = &sdx55_mc_virt}, 894 { .compatible = "qcom,sdx55-mem-noc", 895 .data = &sdx55_mem_noc}, 896 { .compatible = "qcom,sdx55-system-noc", 897 .data = &sdx55_system_noc}, 898 { } 899 }; 900 MODULE_DEVICE_TABLE(of, qnoc_of_match); 901 902 static struct platform_driver qnoc_driver = { 903 .probe = qcom_icc_rpmh_probe, 904 .remove = qcom_icc_rpmh_remove, 905 .driver = { 906 .name = "qnoc-sdx55", 907 .of_match_table = qnoc_of_match, 908 .sync_state = icc_sync_state, 909 }, 910 }; 911 module_platform_driver(qnoc_driver); 912 913 MODULE_DESCRIPTION("Qualcomm SDX55 NoC driver"); 914 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>"); 915 MODULE_LICENSE("GPL v2"); 916