1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/device.h> 7 #include <linux/interconnect.h> 8 #include <linux/interconnect-provider.h> 9 #include <linux/mod_devicetable.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include <dt-bindings/interconnect/qcom,sdm670-rpmh.h> 13 14 #include "bcm-voter.h" 15 #include "icc-rpmh.h" 16 #include "sdm670.h" 17 18 DEFINE_QNODE(qhm_a1noc_cfg, SDM670_MASTER_A1NOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_A1NOC); 19 DEFINE_QNODE(qhm_qup1, SDM670_MASTER_BLSP_1, 1, 4, SDM670_SLAVE_A1NOC_SNOC); 20 DEFINE_QNODE(qhm_tsif, SDM670_MASTER_TSIF, 1, 4, SDM670_SLAVE_A1NOC_SNOC); 21 DEFINE_QNODE(xm_emmc, SDM670_MASTER_EMMC, 1, 8, SDM670_SLAVE_A1NOC_SNOC); 22 DEFINE_QNODE(xm_sdc2, SDM670_MASTER_SDCC_2, 1, 8, SDM670_SLAVE_A1NOC_SNOC); 23 DEFINE_QNODE(xm_sdc4, SDM670_MASTER_SDCC_4, 1, 8, SDM670_SLAVE_A1NOC_SNOC); 24 DEFINE_QNODE(xm_ufs_mem, SDM670_MASTER_UFS_MEM, 1, 8, SDM670_SLAVE_A1NOC_SNOC); 25 DEFINE_QNODE(qhm_a2noc_cfg, SDM670_MASTER_A2NOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_A2NOC); 26 DEFINE_QNODE(qhm_qdss_bam, SDM670_MASTER_QDSS_BAM, 1, 4, SDM670_SLAVE_A2NOC_SNOC); 27 DEFINE_QNODE(qhm_qup2, SDM670_MASTER_BLSP_2, 1, 4, SDM670_SLAVE_A2NOC_SNOC); 28 DEFINE_QNODE(qnm_cnoc, SDM670_MASTER_CNOC_A2NOC, 1, 8, SDM670_SLAVE_A2NOC_SNOC); 29 DEFINE_QNODE(qxm_crypto, SDM670_MASTER_CRYPTO_CORE_0, 1, 8, SDM670_SLAVE_A2NOC_SNOC); 30 DEFINE_QNODE(qxm_ipa, SDM670_MASTER_IPA, 1, 8, SDM670_SLAVE_A2NOC_SNOC); 31 DEFINE_QNODE(xm_qdss_etr, SDM670_MASTER_QDSS_ETR, 1, 8, SDM670_SLAVE_A2NOC_SNOC); 32 DEFINE_QNODE(xm_usb3_0, SDM670_MASTER_USB3, 1, 8, SDM670_SLAVE_A2NOC_SNOC); 33 DEFINE_QNODE(qxm_camnoc_hf0_uncomp, SDM670_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SDM670_SLAVE_CAMNOC_UNCOMP); 34 DEFINE_QNODE(qxm_camnoc_hf1_uncomp, SDM670_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SDM670_SLAVE_CAMNOC_UNCOMP); 35 DEFINE_QNODE(qxm_camnoc_sf_uncomp, SDM670_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SDM670_SLAVE_CAMNOC_UNCOMP); 36 DEFINE_QNODE(qhm_spdm, SDM670_MASTER_SPDM, 1, 4, SDM670_SLAVE_CNOC_A2NOC); 37 DEFINE_QNODE(qnm_snoc, SDM670_MASTER_SNOC_CNOC, 1, 8, SDM670_SLAVE_TLMM_SOUTH, SDM670_SLAVE_CAMERA_CFG, SDM670_SLAVE_SDCC_4, SDM670_SLAVE_SDCC_2, SDM670_SLAVE_CNOC_MNOC_CFG, SDM670_SLAVE_UFS_MEM_CFG, SDM670_SLAVE_GLM, SDM670_SLAVE_PDM, SDM670_SLAVE_A2NOC_CFG, SDM670_SLAVE_QDSS_CFG, SDM670_SLAVE_DISPLAY_CFG, SDM670_SLAVE_TCSR, SDM670_SLAVE_DCC_CFG, SDM670_SLAVE_CNOC_DDRSS, SDM670_SLAVE_SNOC_CFG, SDM670_SLAVE_SOUTH_PHY_CFG, SDM670_SLAVE_GRAPHICS_3D_CFG, SDM670_SLAVE_VENUS_CFG, SDM670_SLAVE_TSIF, SDM670_SLAVE_CDSP_CFG, SDM670_SLAVE_AOP, SDM670_SLAVE_BLSP_2, SDM670_SLAVE_SERVICE_CNOC, SDM670_SLAVE_USB3, SDM670_SLAVE_IPA_CFG, SDM670_SLAVE_RBCPR_CX_CFG, SDM670_SLAVE_A1NOC_CFG, SDM670_SLAVE_AOSS, SDM670_SLAVE_PRNG, SDM670_SLAVE_VSENSE_CTRL_CFG, SDM670_SLAVE_EMMC_CFG, SDM670_SLAVE_BLSP_1, SDM670_SLAVE_SPDM_WRAPPER, SDM670_SLAVE_CRYPTO_0_CFG, SDM670_SLAVE_PIMEM_CFG, SDM670_SLAVE_TLMM_NORTH, SDM670_SLAVE_CLK_CTL, SDM670_SLAVE_IMEM_CFG); 38 DEFINE_QNODE(qhm_cnoc, SDM670_MASTER_CNOC_DC_NOC, 1, 4, SDM670_SLAVE_MEM_NOC_CFG, SDM670_SLAVE_LLCC_CFG); 39 DEFINE_QNODE(acm_l3, SDM670_MASTER_AMPSS_M0, 1, 16, SDM670_SLAVE_SERVICE_GNOC, SDM670_SLAVE_GNOC_SNOC, SDM670_SLAVE_GNOC_MEM_NOC); 40 DEFINE_QNODE(pm_gnoc_cfg, SDM670_MASTER_GNOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_GNOC); 41 DEFINE_QNODE(llcc_mc, SDM670_MASTER_LLCC, 2, 4, SDM670_SLAVE_EBI_CH0); 42 DEFINE_QNODE(acm_tcu, SDM670_MASTER_TCU_0, 1, 8, SDM670_SLAVE_MEM_NOC_GNOC, SDM670_SLAVE_LLCC, SDM670_SLAVE_MEM_NOC_SNOC); 43 DEFINE_QNODE(qhm_memnoc_cfg, SDM670_MASTER_MEM_NOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_MEM_NOC, SDM670_SLAVE_MSS_PROC_MS_MPU_CFG); 44 DEFINE_QNODE(qnm_apps, SDM670_MASTER_GNOC_MEM_NOC, 2, 32, SDM670_SLAVE_LLCC); 45 DEFINE_QNODE(qnm_mnoc_hf, SDM670_MASTER_MNOC_HF_MEM_NOC, 2, 32, SDM670_SLAVE_LLCC); 46 DEFINE_QNODE(qnm_mnoc_sf, SDM670_MASTER_MNOC_SF_MEM_NOC, 1, 32, SDM670_SLAVE_MEM_NOC_GNOC, SDM670_SLAVE_LLCC, SDM670_SLAVE_MEM_NOC_SNOC); 47 DEFINE_QNODE(qnm_snoc_gc, SDM670_MASTER_SNOC_GC_MEM_NOC, 1, 8, SDM670_SLAVE_LLCC); 48 DEFINE_QNODE(qnm_snoc_sf, SDM670_MASTER_SNOC_SF_MEM_NOC, 1, 16, SDM670_SLAVE_MEM_NOC_GNOC, SDM670_SLAVE_LLCC); 49 DEFINE_QNODE(qxm_gpu, SDM670_MASTER_GRAPHICS_3D, 2, 32, SDM670_SLAVE_MEM_NOC_GNOC, SDM670_SLAVE_LLCC, SDM670_SLAVE_MEM_NOC_SNOC); 50 DEFINE_QNODE(qhm_mnoc_cfg, SDM670_MASTER_CNOC_MNOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_MNOC); 51 DEFINE_QNODE(qxm_camnoc_hf0, SDM670_MASTER_CAMNOC_HF0, 1, 32, SDM670_SLAVE_MNOC_HF_MEM_NOC); 52 DEFINE_QNODE(qxm_camnoc_hf1, SDM670_MASTER_CAMNOC_HF1, 1, 32, SDM670_SLAVE_MNOC_HF_MEM_NOC); 53 DEFINE_QNODE(qxm_camnoc_sf, SDM670_MASTER_CAMNOC_SF, 1, 32, SDM670_SLAVE_MNOC_SF_MEM_NOC); 54 DEFINE_QNODE(qxm_mdp0, SDM670_MASTER_MDP_PORT0, 1, 32, SDM670_SLAVE_MNOC_HF_MEM_NOC); 55 DEFINE_QNODE(qxm_mdp1, SDM670_MASTER_MDP_PORT1, 1, 32, SDM670_SLAVE_MNOC_HF_MEM_NOC); 56 DEFINE_QNODE(qxm_rot, SDM670_MASTER_ROTATOR, 1, 32, SDM670_SLAVE_MNOC_SF_MEM_NOC); 57 DEFINE_QNODE(qxm_venus0, SDM670_MASTER_VIDEO_P0, 1, 32, SDM670_SLAVE_MNOC_SF_MEM_NOC); 58 DEFINE_QNODE(qxm_venus1, SDM670_MASTER_VIDEO_P1, 1, 32, SDM670_SLAVE_MNOC_SF_MEM_NOC); 59 DEFINE_QNODE(qxm_venus_arm9, SDM670_MASTER_VIDEO_PROC, 1, 8, SDM670_SLAVE_MNOC_SF_MEM_NOC); 60 DEFINE_QNODE(qhm_snoc_cfg, SDM670_MASTER_SNOC_CFG, 1, 4, SDM670_SLAVE_SERVICE_SNOC); 61 DEFINE_QNODE(qnm_aggre1_noc, SDM670_MASTER_A1NOC_SNOC, 1, 16, SDM670_SLAVE_PIMEM, SDM670_SLAVE_SNOC_MEM_NOC_SF, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_APPSS, SDM670_SLAVE_SNOC_CNOC, SDM670_SLAVE_QDSS_STM); 62 DEFINE_QNODE(qnm_aggre2_noc, SDM670_MASTER_A2NOC_SNOC, 1, 16, SDM670_SLAVE_PIMEM, SDM670_SLAVE_SNOC_MEM_NOC_SF, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_APPSS, SDM670_SLAVE_SNOC_CNOC, SDM670_SLAVE_TCU, SDM670_SLAVE_QDSS_STM); 63 DEFINE_QNODE(qnm_gladiator_sodv, SDM670_MASTER_GNOC_SNOC, 1, 8, SDM670_SLAVE_PIMEM, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_APPSS, SDM670_SLAVE_SNOC_CNOC, SDM670_SLAVE_TCU, SDM670_SLAVE_QDSS_STM); 64 DEFINE_QNODE(qnm_memnoc, SDM670_MASTER_MEM_NOC_SNOC, 1, 8, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_APPSS, SDM670_SLAVE_PIMEM, SDM670_SLAVE_SNOC_CNOC, SDM670_SLAVE_QDSS_STM); 65 DEFINE_QNODE(qxm_pimem, SDM670_MASTER_PIMEM, 1, 8, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_SNOC_MEM_NOC_GC); 66 DEFINE_QNODE(xm_gic, SDM670_MASTER_GIC, 1, 8, SDM670_SLAVE_OCIMEM, SDM670_SLAVE_SNOC_MEM_NOC_GC); 67 DEFINE_QNODE(qns_a1noc_snoc, SDM670_SLAVE_A1NOC_SNOC, 1, 16, SDM670_MASTER_A1NOC_SNOC); 68 DEFINE_QNODE(srvc_aggre1_noc, SDM670_SLAVE_SERVICE_A1NOC, 1, 4); 69 DEFINE_QNODE(qns_a2noc_snoc, SDM670_SLAVE_A2NOC_SNOC, 1, 16, SDM670_MASTER_A2NOC_SNOC); 70 DEFINE_QNODE(srvc_aggre2_noc, SDM670_SLAVE_SERVICE_A2NOC, 1, 4); 71 DEFINE_QNODE(qns_camnoc_uncomp, SDM670_SLAVE_CAMNOC_UNCOMP, 1, 32); 72 DEFINE_QNODE(qhs_a1_noc_cfg, SDM670_SLAVE_A1NOC_CFG, 1, 4, SDM670_MASTER_A1NOC_CFG); 73 DEFINE_QNODE(qhs_a2_noc_cfg, SDM670_SLAVE_A2NOC_CFG, 1, 4, SDM670_MASTER_A2NOC_CFG); 74 DEFINE_QNODE(qhs_aop, SDM670_SLAVE_AOP, 1, 4); 75 DEFINE_QNODE(qhs_aoss, SDM670_SLAVE_AOSS, 1, 4); 76 DEFINE_QNODE(qhs_camera_cfg, SDM670_SLAVE_CAMERA_CFG, 1, 4); 77 DEFINE_QNODE(qhs_clk_ctl, SDM670_SLAVE_CLK_CTL, 1, 4); 78 DEFINE_QNODE(qhs_compute_dsp_cfg, SDM670_SLAVE_CDSP_CFG, 1, 4); 79 DEFINE_QNODE(qhs_cpr_cx, SDM670_SLAVE_RBCPR_CX_CFG, 1, 4); 80 DEFINE_QNODE(qhs_crypto0_cfg, SDM670_SLAVE_CRYPTO_0_CFG, 1, 4); 81 DEFINE_QNODE(qhs_dcc_cfg, SDM670_SLAVE_DCC_CFG, 1, 4, SDM670_MASTER_CNOC_DC_NOC); 82 DEFINE_QNODE(qhs_ddrss_cfg, SDM670_SLAVE_CNOC_DDRSS, 1, 4); 83 DEFINE_QNODE(qhs_display_cfg, SDM670_SLAVE_DISPLAY_CFG, 1, 4); 84 DEFINE_QNODE(qhs_emmc_cfg, SDM670_SLAVE_EMMC_CFG, 1, 4); 85 DEFINE_QNODE(qhs_glm, SDM670_SLAVE_GLM, 1, 4); 86 DEFINE_QNODE(qhs_gpuss_cfg, SDM670_SLAVE_GRAPHICS_3D_CFG, 1, 8); 87 DEFINE_QNODE(qhs_imem_cfg, SDM670_SLAVE_IMEM_CFG, 1, 4); 88 DEFINE_QNODE(qhs_ipa, SDM670_SLAVE_IPA_CFG, 1, 4); 89 DEFINE_QNODE(qhs_mnoc_cfg, SDM670_SLAVE_CNOC_MNOC_CFG, 1, 4, SDM670_MASTER_CNOC_MNOC_CFG); 90 DEFINE_QNODE(qhs_pdm, SDM670_SLAVE_PDM, 1, 4); 91 DEFINE_QNODE(qhs_phy_refgen_south, SDM670_SLAVE_SOUTH_PHY_CFG, 1, 4); 92 DEFINE_QNODE(qhs_pimem_cfg, SDM670_SLAVE_PIMEM_CFG, 1, 4); 93 DEFINE_QNODE(qhs_prng, SDM670_SLAVE_PRNG, 1, 4); 94 DEFINE_QNODE(qhs_qdss_cfg, SDM670_SLAVE_QDSS_CFG, 1, 4); 95 DEFINE_QNODE(qhs_qupv3_north, SDM670_SLAVE_BLSP_2, 1, 4); 96 DEFINE_QNODE(qhs_qupv3_south, SDM670_SLAVE_BLSP_1, 1, 4); 97 DEFINE_QNODE(qhs_sdc2, SDM670_SLAVE_SDCC_2, 1, 4); 98 DEFINE_QNODE(qhs_sdc4, SDM670_SLAVE_SDCC_4, 1, 4); 99 DEFINE_QNODE(qhs_snoc_cfg, SDM670_SLAVE_SNOC_CFG, 1, 4, SDM670_MASTER_SNOC_CFG); 100 DEFINE_QNODE(qhs_spdm, SDM670_SLAVE_SPDM_WRAPPER, 1, 4); 101 DEFINE_QNODE(qhs_tcsr, SDM670_SLAVE_TCSR, 1, 4); 102 DEFINE_QNODE(qhs_tlmm_north, SDM670_SLAVE_TLMM_NORTH, 1, 4); 103 DEFINE_QNODE(qhs_tlmm_south, SDM670_SLAVE_TLMM_SOUTH, 1, 4); 104 DEFINE_QNODE(qhs_tsif, SDM670_SLAVE_TSIF, 1, 4); 105 DEFINE_QNODE(qhs_ufs_mem_cfg, SDM670_SLAVE_UFS_MEM_CFG, 1, 4); 106 DEFINE_QNODE(qhs_usb3_0, SDM670_SLAVE_USB3, 1, 4); 107 DEFINE_QNODE(qhs_venus_cfg, SDM670_SLAVE_VENUS_CFG, 1, 4); 108 DEFINE_QNODE(qhs_vsense_ctrl_cfg, SDM670_SLAVE_VSENSE_CTRL_CFG, 1, 4); 109 DEFINE_QNODE(qns_cnoc_a2noc, SDM670_SLAVE_CNOC_A2NOC, 1, 8, SDM670_MASTER_CNOC_A2NOC); 110 DEFINE_QNODE(srvc_cnoc, SDM670_SLAVE_SERVICE_CNOC, 1, 4); 111 DEFINE_QNODE(qhs_llcc, SDM670_SLAVE_LLCC_CFG, 1, 4); 112 DEFINE_QNODE(qhs_memnoc, SDM670_SLAVE_MEM_NOC_CFG, 1, 4, SDM670_MASTER_MEM_NOC_CFG); 113 DEFINE_QNODE(qns_gladiator_sodv, SDM670_SLAVE_GNOC_SNOC, 1, 8, SDM670_MASTER_GNOC_SNOC); 114 DEFINE_QNODE(qns_gnoc_memnoc, SDM670_SLAVE_GNOC_MEM_NOC, 2, 32, SDM670_MASTER_GNOC_MEM_NOC); 115 DEFINE_QNODE(srvc_gnoc, SDM670_SLAVE_SERVICE_GNOC, 1, 4); 116 DEFINE_QNODE(ebi, SDM670_SLAVE_EBI_CH0, 2, 4); 117 DEFINE_QNODE(qhs_mdsp_ms_mpu_cfg, SDM670_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4); 118 DEFINE_QNODE(qns_apps_io, SDM670_SLAVE_MEM_NOC_GNOC, 1, 32); 119 DEFINE_QNODE(qns_llcc, SDM670_SLAVE_LLCC, 2, 16, SDM670_MASTER_LLCC); 120 DEFINE_QNODE(qns_memnoc_snoc, SDM670_SLAVE_MEM_NOC_SNOC, 1, 8, SDM670_MASTER_MEM_NOC_SNOC); 121 DEFINE_QNODE(srvc_memnoc, SDM670_SLAVE_SERVICE_MEM_NOC, 1, 4); 122 DEFINE_QNODE(qns2_mem_noc, SDM670_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SDM670_MASTER_MNOC_SF_MEM_NOC); 123 DEFINE_QNODE(qns_mem_noc_hf, SDM670_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SDM670_MASTER_MNOC_HF_MEM_NOC); 124 DEFINE_QNODE(srvc_mnoc, SDM670_SLAVE_SERVICE_MNOC, 1, 4); 125 DEFINE_QNODE(qhs_apss, SDM670_SLAVE_APPSS, 1, 8); 126 DEFINE_QNODE(qns_cnoc, SDM670_SLAVE_SNOC_CNOC, 1, 8, SDM670_MASTER_SNOC_CNOC); 127 DEFINE_QNODE(qns_memnoc_gc, SDM670_SLAVE_SNOC_MEM_NOC_GC, 1, 8, SDM670_MASTER_SNOC_GC_MEM_NOC); 128 DEFINE_QNODE(qns_memnoc_sf, SDM670_SLAVE_SNOC_MEM_NOC_SF, 1, 16, SDM670_MASTER_SNOC_SF_MEM_NOC); 129 DEFINE_QNODE(qxs_imem, SDM670_SLAVE_OCIMEM, 1, 8); 130 DEFINE_QNODE(qxs_pimem, SDM670_SLAVE_PIMEM, 1, 8); 131 DEFINE_QNODE(srvc_snoc, SDM670_SLAVE_SERVICE_SNOC, 1, 4); 132 DEFINE_QNODE(xs_qdss_stm, SDM670_SLAVE_QDSS_STM, 1, 4); 133 DEFINE_QNODE(xs_sys_tcu_cfg, SDM670_SLAVE_TCU, 1, 8); 134 135 DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); 136 DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); 137 DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); 138 DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf); 139 DEFINE_QBCM(bcm_sh1, "SH1", false, &qns_apps_io); 140 DEFINE_QBCM(bcm_mm1, "MM1", true, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0, &qxm_camnoc_hf1, &qxm_mdp0, &qxm_mdp1); 141 DEFINE_QBCM(bcm_sh2, "SH2", false, &qns_memnoc_snoc); 142 DEFINE_QBCM(bcm_mm2, "MM2", false, &qns2_mem_noc); 143 DEFINE_QBCM(bcm_sh3, "SH3", false, &acm_tcu); 144 DEFINE_QBCM(bcm_mm3, "MM3", false, &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9); 145 DEFINE_QBCM(bcm_sh5, "SH5", false, &qnm_apps); 146 DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_memnoc_sf); 147 DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); 148 DEFINE_QBCM(bcm_cn0, "CN0", true, &qhm_spdm, &qnm_snoc, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_aop, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp_cfg, &qhs_cpr_cx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_emmc_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_pdm, &qhs_phy_refgen_south, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qupv3_north, &qhs_qupv3_south, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_spdm, &qhs_tcsr, &qhs_tlmm_north, &qhs_tlmm_south, &qhs_tsif, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc); 149 DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup1, &qhm_qup2); 150 DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem); 151 DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_memnoc_gc); 152 DEFINE_QBCM(bcm_sn3, "SN3", false, &qns_cnoc); 153 DEFINE_QBCM(bcm_sn4, "SN4", false, &qxm_pimem, &qxs_pimem); 154 DEFINE_QBCM(bcm_sn5, "SN5", false, &xs_qdss_stm); 155 DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_aggre1_noc, &srvc_aggre1_noc); 156 DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_aggre2_noc, &srvc_aggre2_noc); 157 DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_gladiator_sodv, &xm_gic); 158 DEFINE_QBCM(bcm_sn13, "SN13", false, &qnm_memnoc); 159 160 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 161 &bcm_qup0, 162 &bcm_sn8, 163 }; 164 165 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 166 [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg, 167 [MASTER_BLSP_1] = &qhm_qup1, 168 [MASTER_TSIF] = &qhm_tsif, 169 [MASTER_EMMC] = &xm_emmc, 170 [MASTER_SDCC_2] = &xm_sdc2, 171 [MASTER_SDCC_4] = &xm_sdc4, 172 [MASTER_UFS_MEM] = &xm_ufs_mem, 173 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, 174 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, 175 }; 176 177 static const struct qcom_icc_desc sdm670_aggre1_noc = { 178 .nodes = aggre1_noc_nodes, 179 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 180 .bcms = aggre1_noc_bcms, 181 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 182 }; 183 184 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 185 &bcm_ce0, 186 &bcm_qup0, 187 &bcm_sn10, 188 }; 189 190 static struct qcom_icc_node * const aggre2_noc_nodes[] = { 191 [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg, 192 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 193 [MASTER_BLSP_2] = &qhm_qup2, 194 [MASTER_CNOC_A2NOC] = &qnm_cnoc, 195 [MASTER_CRYPTO_CORE_0] = &qxm_crypto, 196 [MASTER_IPA] = &qxm_ipa, 197 [MASTER_QDSS_ETR] = &xm_qdss_etr, 198 [MASTER_USB3] = &xm_usb3_0, 199 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, 200 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, 201 }; 202 203 static const struct qcom_icc_desc sdm670_aggre2_noc = { 204 .nodes = aggre2_noc_nodes, 205 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 206 .bcms = aggre2_noc_bcms, 207 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 208 }; 209 210 static struct qcom_icc_bcm * const config_noc_bcms[] = { 211 &bcm_cn0, 212 }; 213 214 static struct qcom_icc_node * const config_noc_nodes[] = { 215 [MASTER_SPDM] = &qhm_spdm, 216 [MASTER_SNOC_CNOC] = &qnm_snoc, 217 [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg, 218 [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg, 219 [SLAVE_AOP] = &qhs_aop, 220 [SLAVE_AOSS] = &qhs_aoss, 221 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 222 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 223 [SLAVE_CDSP_CFG] = &qhs_compute_dsp_cfg, 224 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 225 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 226 [SLAVE_DCC_CFG] = &qhs_dcc_cfg, 227 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg, 228 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 229 [SLAVE_EMMC_CFG] = &qhs_emmc_cfg, 230 [SLAVE_GLM] = &qhs_glm, 231 [SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg, 232 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 233 [SLAVE_IPA_CFG] = &qhs_ipa, 234 [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg, 235 [SLAVE_PDM] = &qhs_pdm, 236 [SLAVE_SOUTH_PHY_CFG] = &qhs_phy_refgen_south, 237 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 238 [SLAVE_PRNG] = &qhs_prng, 239 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 240 [SLAVE_BLSP_2] = &qhs_qupv3_north, 241 [SLAVE_BLSP_1] = &qhs_qupv3_south, 242 [SLAVE_SDCC_2] = &qhs_sdc2, 243 [SLAVE_SDCC_4] = &qhs_sdc4, 244 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, 245 [SLAVE_SPDM_WRAPPER] = &qhs_spdm, 246 [SLAVE_TCSR] = &qhs_tcsr, 247 [SLAVE_TLMM_NORTH] = &qhs_tlmm_north, 248 [SLAVE_TLMM_SOUTH] = &qhs_tlmm_south, 249 [SLAVE_TSIF] = &qhs_tsif, 250 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 251 [SLAVE_USB3] = &qhs_usb3_0, 252 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 253 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 254 [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc, 255 [SLAVE_SERVICE_CNOC] = &srvc_cnoc, 256 }; 257 258 static const struct qcom_icc_desc sdm670_config_noc = { 259 .nodes = config_noc_nodes, 260 .num_nodes = ARRAY_SIZE(config_noc_nodes), 261 .bcms = config_noc_bcms, 262 .num_bcms = ARRAY_SIZE(config_noc_bcms), 263 }; 264 265 static struct qcom_icc_bcm * const dc_noc_bcms[] = { 266 }; 267 268 static struct qcom_icc_node * const dc_noc_nodes[] = { 269 [MASTER_CNOC_DC_NOC] = &qhm_cnoc, 270 [SLAVE_LLCC_CFG] = &qhs_llcc, 271 [SLAVE_MEM_NOC_CFG] = &qhs_memnoc, 272 }; 273 274 static const struct qcom_icc_desc sdm670_dc_noc = { 275 .nodes = dc_noc_nodes, 276 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 277 .bcms = dc_noc_bcms, 278 .num_bcms = ARRAY_SIZE(dc_noc_bcms), 279 }; 280 281 static struct qcom_icc_bcm * const gladiator_noc_bcms[] = { 282 }; 283 284 static struct qcom_icc_node * const gladiator_noc_nodes[] = { 285 [MASTER_AMPSS_M0] = &acm_l3, 286 [MASTER_GNOC_CFG] = &pm_gnoc_cfg, 287 [SLAVE_GNOC_SNOC] = &qns_gladiator_sodv, 288 [SLAVE_GNOC_MEM_NOC] = &qns_gnoc_memnoc, 289 [SLAVE_SERVICE_GNOC] = &srvc_gnoc, 290 }; 291 292 static const struct qcom_icc_desc sdm670_gladiator_noc = { 293 .nodes = gladiator_noc_nodes, 294 .num_nodes = ARRAY_SIZE(gladiator_noc_nodes), 295 .bcms = gladiator_noc_bcms, 296 .num_bcms = ARRAY_SIZE(gladiator_noc_bcms), 297 }; 298 299 static struct qcom_icc_bcm * const mem_noc_bcms[] = { 300 &bcm_acv, 301 &bcm_mc0, 302 &bcm_sh0, 303 &bcm_sh1, 304 &bcm_sh2, 305 &bcm_sh3, 306 &bcm_sh5, 307 }; 308 309 static struct qcom_icc_node * const mem_noc_nodes[] = { 310 [MASTER_TCU_0] = &acm_tcu, 311 [MASTER_MEM_NOC_CFG] = &qhm_memnoc_cfg, 312 [MASTER_GNOC_MEM_NOC] = &qnm_apps, 313 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 314 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 315 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 316 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 317 [MASTER_GRAPHICS_3D] = &qxm_gpu, 318 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg, 319 [SLAVE_MEM_NOC_GNOC] = &qns_apps_io, 320 [SLAVE_LLCC] = &qns_llcc, 321 [SLAVE_MEM_NOC_SNOC] = &qns_memnoc_snoc, 322 [SLAVE_SERVICE_MEM_NOC] = &srvc_memnoc, 323 [MASTER_LLCC] = &llcc_mc, 324 [SLAVE_EBI_CH0] = &ebi, 325 }; 326 327 static const struct qcom_icc_desc sdm670_mem_noc = { 328 .nodes = mem_noc_nodes, 329 .num_nodes = ARRAY_SIZE(mem_noc_nodes), 330 .bcms = mem_noc_bcms, 331 .num_bcms = ARRAY_SIZE(mem_noc_bcms), 332 }; 333 334 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 335 &bcm_mm0, 336 &bcm_mm1, 337 &bcm_mm2, 338 &bcm_mm3, 339 }; 340 341 static struct qcom_icc_node * const mmss_noc_nodes[] = { 342 [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg, 343 [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0, 344 [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1, 345 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf, 346 [MASTER_MDP_PORT0] = &qxm_mdp0, 347 [MASTER_MDP_PORT1] = &qxm_mdp1, 348 [MASTER_ROTATOR] = &qxm_rot, 349 [MASTER_VIDEO_P0] = &qxm_venus0, 350 [MASTER_VIDEO_P1] = &qxm_venus1, 351 [MASTER_VIDEO_PROC] = &qxm_venus_arm9, 352 [SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc, 353 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 354 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 355 }; 356 357 static const struct qcom_icc_desc sdm670_mmss_noc = { 358 .nodes = mmss_noc_nodes, 359 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 360 .bcms = mmss_noc_bcms, 361 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 362 }; 363 364 static struct qcom_icc_bcm * const system_noc_bcms[] = { 365 &bcm_mm1, 366 &bcm_sn0, 367 &bcm_sn1, 368 &bcm_sn10, 369 &bcm_sn11, 370 &bcm_sn13, 371 &bcm_sn2, 372 &bcm_sn3, 373 &bcm_sn4, 374 &bcm_sn5, 375 &bcm_sn8, 376 }; 377 378 static struct qcom_icc_node * const system_noc_nodes[] = { 379 [MASTER_SNOC_CFG] = &qhm_snoc_cfg, 380 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, 381 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, 382 [MASTER_GNOC_SNOC] = &qnm_gladiator_sodv, 383 [MASTER_MEM_NOC_SNOC] = &qnm_memnoc, 384 [MASTER_PIMEM] = &qxm_pimem, 385 [MASTER_GIC] = &xm_gic, 386 [SLAVE_APPSS] = &qhs_apss, 387 [SLAVE_SNOC_CNOC] = &qns_cnoc, 388 [SLAVE_SNOC_MEM_NOC_GC] = &qns_memnoc_gc, 389 [SLAVE_SNOC_MEM_NOC_SF] = &qns_memnoc_sf, 390 [SLAVE_OCIMEM] = &qxs_imem, 391 [SLAVE_PIMEM] = &qxs_pimem, 392 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 393 [SLAVE_QDSS_STM] = &xs_qdss_stm, 394 [SLAVE_TCU] = &xs_sys_tcu_cfg, 395 [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp, 396 [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp, 397 [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp, 398 [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp, 399 }; 400 401 static const struct qcom_icc_desc sdm670_system_noc = { 402 .nodes = system_noc_nodes, 403 .num_nodes = ARRAY_SIZE(system_noc_nodes), 404 .bcms = system_noc_bcms, 405 .num_bcms = ARRAY_SIZE(system_noc_bcms), 406 }; 407 408 static const struct of_device_id qnoc_of_match[] = { 409 { .compatible = "qcom,sdm670-aggre1-noc", 410 .data = &sdm670_aggre1_noc}, 411 { .compatible = "qcom,sdm670-aggre2-noc", 412 .data = &sdm670_aggre2_noc}, 413 { .compatible = "qcom,sdm670-config-noc", 414 .data = &sdm670_config_noc}, 415 { .compatible = "qcom,sdm670-dc-noc", 416 .data = &sdm670_dc_noc}, 417 { .compatible = "qcom,sdm670-gladiator-noc", 418 .data = &sdm670_gladiator_noc}, 419 { .compatible = "qcom,sdm670-mem-noc", 420 .data = &sdm670_mem_noc}, 421 { .compatible = "qcom,sdm670-mmss-noc", 422 .data = &sdm670_mmss_noc}, 423 { .compatible = "qcom,sdm670-system-noc", 424 .data = &sdm670_system_noc}, 425 { } 426 }; 427 MODULE_DEVICE_TABLE(of, qnoc_of_match); 428 429 static struct platform_driver qnoc_driver = { 430 .probe = qcom_icc_rpmh_probe, 431 .remove = qcom_icc_rpmh_remove, 432 .driver = { 433 .name = "qnoc-sdm670", 434 .of_match_table = qnoc_of_match, 435 .sync_state = icc_sync_state, 436 }, 437 }; 438 module_platform_driver(qnoc_driver); 439 440 MODULE_DESCRIPTION("Qualcomm SDM670 NoC driver"); 441 MODULE_LICENSE("GPL"); 442