1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/device.h> 7 #include <linux/interconnect.h> 8 #include <linux/interconnect-provider.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 #include <dt-bindings/interconnect/qcom,sdm670-rpmh.h> 12 13 #include "bcm-voter.h" 14 #include "icc-rpmh.h" 15 16 static struct qcom_icc_node qhm_a1noc_cfg; 17 static struct qcom_icc_node qhm_qup1; 18 static struct qcom_icc_node qhm_tsif; 19 static struct qcom_icc_node xm_emmc; 20 static struct qcom_icc_node xm_sdc2; 21 static struct qcom_icc_node xm_sdc4; 22 static struct qcom_icc_node xm_ufs_mem; 23 static struct qcom_icc_node qhm_a2noc_cfg; 24 static struct qcom_icc_node qhm_qdss_bam; 25 static struct qcom_icc_node qhm_qup2; 26 static struct qcom_icc_node qnm_cnoc; 27 static struct qcom_icc_node qxm_crypto; 28 static struct qcom_icc_node qxm_ipa; 29 static struct qcom_icc_node xm_qdss_etr; 30 static struct qcom_icc_node xm_usb3_0; 31 static struct qcom_icc_node qxm_camnoc_hf0_uncomp; 32 static struct qcom_icc_node qxm_camnoc_hf1_uncomp; 33 static struct qcom_icc_node qxm_camnoc_sf_uncomp; 34 static struct qcom_icc_node qhm_spdm; 35 static struct qcom_icc_node qnm_snoc; 36 static struct qcom_icc_node qhm_cnoc; 37 static struct qcom_icc_node acm_l3; 38 static struct qcom_icc_node pm_gnoc_cfg; 39 static struct qcom_icc_node llcc_mc; 40 static struct qcom_icc_node acm_tcu; 41 static struct qcom_icc_node qhm_memnoc_cfg; 42 static struct qcom_icc_node qnm_apps; 43 static struct qcom_icc_node qnm_mnoc_hf; 44 static struct qcom_icc_node qnm_mnoc_sf; 45 static struct qcom_icc_node qnm_snoc_gc; 46 static struct qcom_icc_node qnm_snoc_sf; 47 static struct qcom_icc_node qxm_gpu; 48 static struct qcom_icc_node qhm_mnoc_cfg; 49 static struct qcom_icc_node qxm_camnoc_hf0; 50 static struct qcom_icc_node qxm_camnoc_hf1; 51 static struct qcom_icc_node qxm_camnoc_sf; 52 static struct qcom_icc_node qxm_mdp0; 53 static struct qcom_icc_node qxm_mdp1; 54 static struct qcom_icc_node qxm_rot; 55 static struct qcom_icc_node qxm_venus0; 56 static struct qcom_icc_node qxm_venus1; 57 static struct qcom_icc_node qxm_venus_arm9; 58 static struct qcom_icc_node qhm_snoc_cfg; 59 static struct qcom_icc_node qnm_aggre1_noc; 60 static struct qcom_icc_node qnm_aggre2_noc; 61 static struct qcom_icc_node qnm_gladiator_sodv; 62 static struct qcom_icc_node qnm_memnoc; 63 static struct qcom_icc_node qxm_pimem; 64 static struct qcom_icc_node xm_gic; 65 static struct qcom_icc_node qns_a1noc_snoc; 66 static struct qcom_icc_node srvc_aggre1_noc; 67 static struct qcom_icc_node qns_a2noc_snoc; 68 static struct qcom_icc_node srvc_aggre2_noc; 69 static struct qcom_icc_node qns_camnoc_uncomp; 70 static struct qcom_icc_node qhs_a1_noc_cfg; 71 static struct qcom_icc_node qhs_a2_noc_cfg; 72 static struct qcom_icc_node qhs_aop; 73 static struct qcom_icc_node qhs_aoss; 74 static struct qcom_icc_node qhs_camera_cfg; 75 static struct qcom_icc_node qhs_clk_ctl; 76 static struct qcom_icc_node qhs_compute_dsp_cfg; 77 static struct qcom_icc_node qhs_cpr_cx; 78 static struct qcom_icc_node qhs_crypto0_cfg; 79 static struct qcom_icc_node qhs_dcc_cfg; 80 static struct qcom_icc_node qhs_ddrss_cfg; 81 static struct qcom_icc_node qhs_display_cfg; 82 static struct qcom_icc_node qhs_emmc_cfg; 83 static struct qcom_icc_node qhs_glm; 84 static struct qcom_icc_node qhs_gpuss_cfg; 85 static struct qcom_icc_node qhs_imem_cfg; 86 static struct qcom_icc_node qhs_ipa; 87 static struct qcom_icc_node qhs_mnoc_cfg; 88 static struct qcom_icc_node qhs_pdm; 89 static struct qcom_icc_node qhs_phy_refgen_south; 90 static struct qcom_icc_node qhs_pimem_cfg; 91 static struct qcom_icc_node qhs_prng; 92 static struct qcom_icc_node qhs_qdss_cfg; 93 static struct qcom_icc_node qhs_qupv3_north; 94 static struct qcom_icc_node qhs_qupv3_south; 95 static struct qcom_icc_node qhs_sdc2; 96 static struct qcom_icc_node qhs_sdc4; 97 static struct qcom_icc_node qhs_snoc_cfg; 98 static struct qcom_icc_node qhs_spdm; 99 static struct qcom_icc_node qhs_tcsr; 100 static struct qcom_icc_node qhs_tlmm_north; 101 static struct qcom_icc_node qhs_tlmm_south; 102 static struct qcom_icc_node qhs_tsif; 103 static struct qcom_icc_node qhs_ufs_mem_cfg; 104 static struct qcom_icc_node qhs_usb3_0; 105 static struct qcom_icc_node qhs_venus_cfg; 106 static struct qcom_icc_node qhs_vsense_ctrl_cfg; 107 static struct qcom_icc_node qns_cnoc_a2noc; 108 static struct qcom_icc_node srvc_cnoc; 109 static struct qcom_icc_node qhs_llcc; 110 static struct qcom_icc_node qhs_memnoc; 111 static struct qcom_icc_node qns_gladiator_sodv; 112 static struct qcom_icc_node qns_gnoc_memnoc; 113 static struct qcom_icc_node srvc_gnoc; 114 static struct qcom_icc_node ebi; 115 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; 116 static struct qcom_icc_node qns_apps_io; 117 static struct qcom_icc_node qns_llcc; 118 static struct qcom_icc_node qns_memnoc_snoc; 119 static struct qcom_icc_node srvc_memnoc; 120 static struct qcom_icc_node qns2_mem_noc; 121 static struct qcom_icc_node qns_mem_noc_hf; 122 static struct qcom_icc_node srvc_mnoc; 123 static struct qcom_icc_node qhs_apss; 124 static struct qcom_icc_node qns_cnoc; 125 static struct qcom_icc_node qns_memnoc_gc; 126 static struct qcom_icc_node qns_memnoc_sf; 127 static struct qcom_icc_node qxs_imem; 128 static struct qcom_icc_node qxs_pimem; 129 static struct qcom_icc_node srvc_snoc; 130 static struct qcom_icc_node xs_qdss_stm; 131 static struct qcom_icc_node xs_sys_tcu_cfg; 132 133 static struct qcom_icc_node qhm_a1noc_cfg = { 134 .name = "qhm_a1noc_cfg", 135 .channels = 1, 136 .buswidth = 4, 137 .num_links = 1, 138 .link_nodes = { &srvc_aggre1_noc }, 139 }; 140 141 static struct qcom_icc_node qhm_qup1 = { 142 .name = "qhm_qup1", 143 .channels = 1, 144 .buswidth = 4, 145 .num_links = 1, 146 .link_nodes = { &qns_a1noc_snoc }, 147 }; 148 149 static struct qcom_icc_node qhm_tsif = { 150 .name = "qhm_tsif", 151 .channels = 1, 152 .buswidth = 4, 153 .num_links = 1, 154 .link_nodes = { &qns_a1noc_snoc }, 155 }; 156 157 static struct qcom_icc_node xm_emmc = { 158 .name = "xm_emmc", 159 .channels = 1, 160 .buswidth = 8, 161 .num_links = 1, 162 .link_nodes = { &qns_a1noc_snoc }, 163 }; 164 165 static struct qcom_icc_node xm_sdc2 = { 166 .name = "xm_sdc2", 167 .channels = 1, 168 .buswidth = 8, 169 .num_links = 1, 170 .link_nodes = { &qns_a1noc_snoc }, 171 }; 172 173 static struct qcom_icc_node xm_sdc4 = { 174 .name = "xm_sdc4", 175 .channels = 1, 176 .buswidth = 8, 177 .num_links = 1, 178 .link_nodes = { &qns_a1noc_snoc }, 179 }; 180 181 static struct qcom_icc_node xm_ufs_mem = { 182 .name = "xm_ufs_mem", 183 .channels = 1, 184 .buswidth = 8, 185 .num_links = 1, 186 .link_nodes = { &qns_a1noc_snoc }, 187 }; 188 189 static struct qcom_icc_node qhm_a2noc_cfg = { 190 .name = "qhm_a2noc_cfg", 191 .channels = 1, 192 .buswidth = 4, 193 .num_links = 1, 194 .link_nodes = { &srvc_aggre2_noc }, 195 }; 196 197 static struct qcom_icc_node qhm_qdss_bam = { 198 .name = "qhm_qdss_bam", 199 .channels = 1, 200 .buswidth = 4, 201 .num_links = 1, 202 .link_nodes = { &qns_a2noc_snoc }, 203 }; 204 205 static struct qcom_icc_node qhm_qup2 = { 206 .name = "qhm_qup2", 207 .channels = 1, 208 .buswidth = 4, 209 .num_links = 1, 210 .link_nodes = { &qns_a2noc_snoc }, 211 }; 212 213 static struct qcom_icc_node qnm_cnoc = { 214 .name = "qnm_cnoc", 215 .channels = 1, 216 .buswidth = 8, 217 .num_links = 1, 218 .link_nodes = { &qns_a2noc_snoc }, 219 }; 220 221 static struct qcom_icc_node qxm_crypto = { 222 .name = "qxm_crypto", 223 .channels = 1, 224 .buswidth = 8, 225 .num_links = 1, 226 .link_nodes = { &qns_a2noc_snoc }, 227 }; 228 229 static struct qcom_icc_node qxm_ipa = { 230 .name = "qxm_ipa", 231 .channels = 1, 232 .buswidth = 8, 233 .num_links = 1, 234 .link_nodes = { &qns_a2noc_snoc }, 235 }; 236 237 static struct qcom_icc_node xm_qdss_etr = { 238 .name = "xm_qdss_etr", 239 .channels = 1, 240 .buswidth = 8, 241 .num_links = 1, 242 .link_nodes = { &qns_a2noc_snoc }, 243 }; 244 245 static struct qcom_icc_node xm_usb3_0 = { 246 .name = "xm_usb3_0", 247 .channels = 1, 248 .buswidth = 8, 249 .num_links = 1, 250 .link_nodes = { &qns_a2noc_snoc }, 251 }; 252 253 static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { 254 .name = "qxm_camnoc_hf0_uncomp", 255 .channels = 1, 256 .buswidth = 32, 257 .num_links = 1, 258 .link_nodes = { &qns_camnoc_uncomp }, 259 }; 260 261 static struct qcom_icc_node qxm_camnoc_hf1_uncomp = { 262 .name = "qxm_camnoc_hf1_uncomp", 263 .channels = 1, 264 .buswidth = 32, 265 .num_links = 1, 266 .link_nodes = { &qns_camnoc_uncomp }, 267 }; 268 269 static struct qcom_icc_node qxm_camnoc_sf_uncomp = { 270 .name = "qxm_camnoc_sf_uncomp", 271 .channels = 1, 272 .buswidth = 32, 273 .num_links = 1, 274 .link_nodes = { &qns_camnoc_uncomp }, 275 }; 276 277 static struct qcom_icc_node qhm_spdm = { 278 .name = "qhm_spdm", 279 .channels = 1, 280 .buswidth = 4, 281 .num_links = 1, 282 .link_nodes = { &qns_cnoc_a2noc }, 283 }; 284 285 static struct qcom_icc_node qnm_snoc = { 286 .name = "qnm_snoc", 287 .channels = 1, 288 .buswidth = 8, 289 .num_links = 38, 290 .link_nodes = { &qhs_tlmm_south, 291 &qhs_camera_cfg, 292 &qhs_sdc4, 293 &qhs_sdc2, 294 &qhs_mnoc_cfg, 295 &qhs_ufs_mem_cfg, 296 &qhs_glm, 297 &qhs_pdm, 298 &qhs_a2_noc_cfg, 299 &qhs_qdss_cfg, 300 &qhs_display_cfg, 301 &qhs_tcsr, 302 &qhs_dcc_cfg, 303 &qhs_ddrss_cfg, 304 &qhs_snoc_cfg, 305 &qhs_phy_refgen_south, 306 &qhs_gpuss_cfg, 307 &qhs_venus_cfg, 308 &qhs_tsif, 309 &qhs_compute_dsp_cfg, 310 &qhs_aop, 311 &qhs_qupv3_north, 312 &srvc_cnoc, 313 &qhs_usb3_0, 314 &qhs_ipa, 315 &qhs_cpr_cx, 316 &qhs_a1_noc_cfg, 317 &qhs_aoss, 318 &qhs_prng, 319 &qhs_vsense_ctrl_cfg, 320 &qhs_emmc_cfg, 321 &qhs_qupv3_south, 322 &qhs_spdm, 323 &qhs_crypto0_cfg, 324 &qhs_pimem_cfg, 325 &qhs_tlmm_north, 326 &qhs_clk_ctl, 327 &qhs_imem_cfg }, 328 }; 329 330 static struct qcom_icc_node qhm_cnoc = { 331 .name = "qhm_cnoc", 332 .channels = 1, 333 .buswidth = 4, 334 .num_links = 2, 335 .link_nodes = { &qhs_memnoc, 336 &qhs_llcc }, 337 }; 338 339 static struct qcom_icc_node acm_l3 = { 340 .name = "acm_l3", 341 .channels = 1, 342 .buswidth = 16, 343 .num_links = 3, 344 .link_nodes = { &srvc_gnoc, 345 &qns_gladiator_sodv, 346 &qns_gnoc_memnoc }, 347 }; 348 349 static struct qcom_icc_node pm_gnoc_cfg = { 350 .name = "pm_gnoc_cfg", 351 .channels = 1, 352 .buswidth = 4, 353 .num_links = 1, 354 .link_nodes = { &srvc_gnoc }, 355 }; 356 357 static struct qcom_icc_node llcc_mc = { 358 .name = "llcc_mc", 359 .channels = 2, 360 .buswidth = 4, 361 .num_links = 1, 362 .link_nodes = { &ebi }, 363 }; 364 365 static struct qcom_icc_node acm_tcu = { 366 .name = "acm_tcu", 367 .channels = 1, 368 .buswidth = 8, 369 .num_links = 3, 370 .link_nodes = { &qns_apps_io, 371 &qns_llcc, 372 &qns_memnoc_snoc }, 373 }; 374 375 static struct qcom_icc_node qhm_memnoc_cfg = { 376 .name = "qhm_memnoc_cfg", 377 .channels = 1, 378 .buswidth = 4, 379 .num_links = 2, 380 .link_nodes = { &srvc_memnoc, 381 &qhs_mdsp_ms_mpu_cfg }, 382 }; 383 384 static struct qcom_icc_node qnm_apps = { 385 .name = "qnm_apps", 386 .channels = 2, 387 .buswidth = 32, 388 .num_links = 1, 389 .link_nodes = { &qns_llcc }, 390 }; 391 392 static struct qcom_icc_node qnm_mnoc_hf = { 393 .name = "qnm_mnoc_hf", 394 .channels = 2, 395 .buswidth = 32, 396 .num_links = 1, 397 .link_nodes = { &qns_llcc }, 398 }; 399 400 static struct qcom_icc_node qnm_mnoc_sf = { 401 .name = "qnm_mnoc_sf", 402 .channels = 1, 403 .buswidth = 32, 404 .num_links = 3, 405 .link_nodes = { &qns_apps_io, 406 &qns_llcc, 407 &qns_memnoc_snoc }, 408 }; 409 410 static struct qcom_icc_node qnm_snoc_gc = { 411 .name = "qnm_snoc_gc", 412 .channels = 1, 413 .buswidth = 8, 414 .num_links = 1, 415 .link_nodes = { &qns_llcc }, 416 }; 417 418 static struct qcom_icc_node qnm_snoc_sf = { 419 .name = "qnm_snoc_sf", 420 .channels = 1, 421 .buswidth = 16, 422 .num_links = 2, 423 .link_nodes = { &qns_apps_io, 424 &qns_llcc }, 425 }; 426 427 static struct qcom_icc_node qxm_gpu = { 428 .name = "qxm_gpu", 429 .channels = 2, 430 .buswidth = 32, 431 .num_links = 3, 432 .link_nodes = { &qns_apps_io, 433 &qns_llcc, 434 &qns_memnoc_snoc }, 435 }; 436 437 static struct qcom_icc_node qhm_mnoc_cfg = { 438 .name = "qhm_mnoc_cfg", 439 .channels = 1, 440 .buswidth = 4, 441 .num_links = 1, 442 .link_nodes = { &srvc_mnoc }, 443 }; 444 445 static struct qcom_icc_node qxm_camnoc_hf0 = { 446 .name = "qxm_camnoc_hf0", 447 .channels = 1, 448 .buswidth = 32, 449 .num_links = 1, 450 .link_nodes = { &qns_mem_noc_hf }, 451 }; 452 453 static struct qcom_icc_node qxm_camnoc_hf1 = { 454 .name = "qxm_camnoc_hf1", 455 .channels = 1, 456 .buswidth = 32, 457 .num_links = 1, 458 .link_nodes = { &qns_mem_noc_hf }, 459 }; 460 461 static struct qcom_icc_node qxm_camnoc_sf = { 462 .name = "qxm_camnoc_sf", 463 .channels = 1, 464 .buswidth = 32, 465 .num_links = 1, 466 .link_nodes = { &qns2_mem_noc }, 467 }; 468 469 static struct qcom_icc_node qxm_mdp0 = { 470 .name = "qxm_mdp0", 471 .channels = 1, 472 .buswidth = 32, 473 .num_links = 1, 474 .link_nodes = { &qns_mem_noc_hf }, 475 }; 476 477 static struct qcom_icc_node qxm_mdp1 = { 478 .name = "qxm_mdp1", 479 .channels = 1, 480 .buswidth = 32, 481 .num_links = 1, 482 .link_nodes = { &qns_mem_noc_hf }, 483 }; 484 485 static struct qcom_icc_node qxm_rot = { 486 .name = "qxm_rot", 487 .channels = 1, 488 .buswidth = 32, 489 .num_links = 1, 490 .link_nodes = { &qns2_mem_noc }, 491 }; 492 493 static struct qcom_icc_node qxm_venus0 = { 494 .name = "qxm_venus0", 495 .channels = 1, 496 .buswidth = 32, 497 .num_links = 1, 498 .link_nodes = { &qns2_mem_noc }, 499 }; 500 501 static struct qcom_icc_node qxm_venus1 = { 502 .name = "qxm_venus1", 503 .channels = 1, 504 .buswidth = 32, 505 .num_links = 1, 506 .link_nodes = { &qns2_mem_noc }, 507 }; 508 509 static struct qcom_icc_node qxm_venus_arm9 = { 510 .name = "qxm_venus_arm9", 511 .channels = 1, 512 .buswidth = 8, 513 .num_links = 1, 514 .link_nodes = { &qns2_mem_noc }, 515 }; 516 517 static struct qcom_icc_node qhm_snoc_cfg = { 518 .name = "qhm_snoc_cfg", 519 .channels = 1, 520 .buswidth = 4, 521 .num_links = 1, 522 .link_nodes = { &srvc_snoc }, 523 }; 524 525 static struct qcom_icc_node qnm_aggre1_noc = { 526 .name = "qnm_aggre1_noc", 527 .channels = 1, 528 .buswidth = 16, 529 .num_links = 6, 530 .link_nodes = { &qxs_pimem, 531 &qns_memnoc_sf, 532 &qxs_imem, 533 &qhs_apss, 534 &qns_cnoc, 535 &xs_qdss_stm }, 536 }; 537 538 static struct qcom_icc_node qnm_aggre2_noc = { 539 .name = "qnm_aggre2_noc", 540 .channels = 1, 541 .buswidth = 16, 542 .num_links = 7, 543 .link_nodes = { &qxs_pimem, 544 &qns_memnoc_sf, 545 &qxs_imem, 546 &qhs_apss, 547 &qns_cnoc, 548 &xs_sys_tcu_cfg, 549 &xs_qdss_stm }, 550 }; 551 552 static struct qcom_icc_node qnm_gladiator_sodv = { 553 .name = "qnm_gladiator_sodv", 554 .channels = 1, 555 .buswidth = 8, 556 .num_links = 6, 557 .link_nodes = { &qxs_pimem, 558 &qxs_imem, 559 &qhs_apss, 560 &qns_cnoc, 561 &xs_sys_tcu_cfg, 562 &xs_qdss_stm }, 563 }; 564 565 static struct qcom_icc_node qnm_memnoc = { 566 .name = "qnm_memnoc", 567 .channels = 1, 568 .buswidth = 8, 569 .num_links = 5, 570 .link_nodes = { &qxs_imem, 571 &qhs_apss, 572 &qxs_pimem, 573 &qns_cnoc, 574 &xs_qdss_stm }, 575 }; 576 577 static struct qcom_icc_node qxm_pimem = { 578 .name = "qxm_pimem", 579 .channels = 1, 580 .buswidth = 8, 581 .num_links = 2, 582 .link_nodes = { &qxs_imem, 583 &qns_memnoc_gc }, 584 }; 585 586 static struct qcom_icc_node xm_gic = { 587 .name = "xm_gic", 588 .channels = 1, 589 .buswidth = 8, 590 .num_links = 2, 591 .link_nodes = { &qxs_imem, 592 &qns_memnoc_gc }, 593 }; 594 595 static struct qcom_icc_node qns_a1noc_snoc = { 596 .name = "qns_a1noc_snoc", 597 .channels = 1, 598 .buswidth = 16, 599 .num_links = 1, 600 .link_nodes = { &qnm_aggre1_noc }, 601 }; 602 603 static struct qcom_icc_node srvc_aggre1_noc = { 604 .name = "srvc_aggre1_noc", 605 .channels = 1, 606 .buswidth = 4, 607 }; 608 609 static struct qcom_icc_node qns_a2noc_snoc = { 610 .name = "qns_a2noc_snoc", 611 .channels = 1, 612 .buswidth = 16, 613 .num_links = 1, 614 .link_nodes = { &qnm_aggre2_noc }, 615 }; 616 617 static struct qcom_icc_node srvc_aggre2_noc = { 618 .name = "srvc_aggre2_noc", 619 .channels = 1, 620 .buswidth = 4, 621 }; 622 623 static struct qcom_icc_node qns_camnoc_uncomp = { 624 .name = "qns_camnoc_uncomp", 625 .channels = 1, 626 .buswidth = 32, 627 }; 628 629 static struct qcom_icc_node qhs_a1_noc_cfg = { 630 .name = "qhs_a1_noc_cfg", 631 .channels = 1, 632 .buswidth = 4, 633 .num_links = 1, 634 .link_nodes = { &qhm_a1noc_cfg }, 635 }; 636 637 static struct qcom_icc_node qhs_a2_noc_cfg = { 638 .name = "qhs_a2_noc_cfg", 639 .channels = 1, 640 .buswidth = 4, 641 .num_links = 1, 642 .link_nodes = { &qhm_a2noc_cfg }, 643 }; 644 645 static struct qcom_icc_node qhs_aop = { 646 .name = "qhs_aop", 647 .channels = 1, 648 .buswidth = 4, 649 }; 650 651 static struct qcom_icc_node qhs_aoss = { 652 .name = "qhs_aoss", 653 .channels = 1, 654 .buswidth = 4, 655 }; 656 657 static struct qcom_icc_node qhs_camera_cfg = { 658 .name = "qhs_camera_cfg", 659 .channels = 1, 660 .buswidth = 4, 661 }; 662 663 static struct qcom_icc_node qhs_clk_ctl = { 664 .name = "qhs_clk_ctl", 665 .channels = 1, 666 .buswidth = 4, 667 }; 668 669 static struct qcom_icc_node qhs_compute_dsp_cfg = { 670 .name = "qhs_compute_dsp_cfg", 671 .channels = 1, 672 .buswidth = 4, 673 }; 674 675 static struct qcom_icc_node qhs_cpr_cx = { 676 .name = "qhs_cpr_cx", 677 .channels = 1, 678 .buswidth = 4, 679 }; 680 681 static struct qcom_icc_node qhs_crypto0_cfg = { 682 .name = "qhs_crypto0_cfg", 683 .channels = 1, 684 .buswidth = 4, 685 }; 686 687 static struct qcom_icc_node qhs_dcc_cfg = { 688 .name = "qhs_dcc_cfg", 689 .channels = 1, 690 .buswidth = 4, 691 .num_links = 1, 692 .link_nodes = { &qhm_cnoc }, 693 }; 694 695 static struct qcom_icc_node qhs_ddrss_cfg = { 696 .name = "qhs_ddrss_cfg", 697 .channels = 1, 698 .buswidth = 4, 699 }; 700 701 static struct qcom_icc_node qhs_display_cfg = { 702 .name = "qhs_display_cfg", 703 .channels = 1, 704 .buswidth = 4, 705 }; 706 707 static struct qcom_icc_node qhs_emmc_cfg = { 708 .name = "qhs_emmc_cfg", 709 .channels = 1, 710 .buswidth = 4, 711 }; 712 713 static struct qcom_icc_node qhs_glm = { 714 .name = "qhs_glm", 715 .channels = 1, 716 .buswidth = 4, 717 }; 718 719 static struct qcom_icc_node qhs_gpuss_cfg = { 720 .name = "qhs_gpuss_cfg", 721 .channels = 1, 722 .buswidth = 8, 723 }; 724 725 static struct qcom_icc_node qhs_imem_cfg = { 726 .name = "qhs_imem_cfg", 727 .channels = 1, 728 .buswidth = 4, 729 }; 730 731 static struct qcom_icc_node qhs_ipa = { 732 .name = "qhs_ipa", 733 .channels = 1, 734 .buswidth = 4, 735 }; 736 737 static struct qcom_icc_node qhs_mnoc_cfg = { 738 .name = "qhs_mnoc_cfg", 739 .channels = 1, 740 .buswidth = 4, 741 .num_links = 1, 742 .link_nodes = { &qhm_mnoc_cfg }, 743 }; 744 745 static struct qcom_icc_node qhs_pdm = { 746 .name = "qhs_pdm", 747 .channels = 1, 748 .buswidth = 4, 749 }; 750 751 static struct qcom_icc_node qhs_phy_refgen_south = { 752 .name = "qhs_phy_refgen_south", 753 .channels = 1, 754 .buswidth = 4, 755 }; 756 757 static struct qcom_icc_node qhs_pimem_cfg = { 758 .name = "qhs_pimem_cfg", 759 .channels = 1, 760 .buswidth = 4, 761 }; 762 763 static struct qcom_icc_node qhs_prng = { 764 .name = "qhs_prng", 765 .channels = 1, 766 .buswidth = 4, 767 }; 768 769 static struct qcom_icc_node qhs_qdss_cfg = { 770 .name = "qhs_qdss_cfg", 771 .channels = 1, 772 .buswidth = 4, 773 }; 774 775 static struct qcom_icc_node qhs_qupv3_north = { 776 .name = "qhs_qupv3_north", 777 .channels = 1, 778 .buswidth = 4, 779 }; 780 781 static struct qcom_icc_node qhs_qupv3_south = { 782 .name = "qhs_qupv3_south", 783 .channels = 1, 784 .buswidth = 4, 785 }; 786 787 static struct qcom_icc_node qhs_sdc2 = { 788 .name = "qhs_sdc2", 789 .channels = 1, 790 .buswidth = 4, 791 }; 792 793 static struct qcom_icc_node qhs_sdc4 = { 794 .name = "qhs_sdc4", 795 .channels = 1, 796 .buswidth = 4, 797 }; 798 799 static struct qcom_icc_node qhs_snoc_cfg = { 800 .name = "qhs_snoc_cfg", 801 .channels = 1, 802 .buswidth = 4, 803 .num_links = 1, 804 .link_nodes = { &qhm_snoc_cfg }, 805 }; 806 807 static struct qcom_icc_node qhs_spdm = { 808 .name = "qhs_spdm", 809 .channels = 1, 810 .buswidth = 4, 811 }; 812 813 static struct qcom_icc_node qhs_tcsr = { 814 .name = "qhs_tcsr", 815 .channels = 1, 816 .buswidth = 4, 817 }; 818 819 static struct qcom_icc_node qhs_tlmm_north = { 820 .name = "qhs_tlmm_north", 821 .channels = 1, 822 .buswidth = 4, 823 }; 824 825 static struct qcom_icc_node qhs_tlmm_south = { 826 .name = "qhs_tlmm_south", 827 .channels = 1, 828 .buswidth = 4, 829 }; 830 831 static struct qcom_icc_node qhs_tsif = { 832 .name = "qhs_tsif", 833 .channels = 1, 834 .buswidth = 4, 835 }; 836 837 static struct qcom_icc_node qhs_ufs_mem_cfg = { 838 .name = "qhs_ufs_mem_cfg", 839 .channels = 1, 840 .buswidth = 4, 841 }; 842 843 static struct qcom_icc_node qhs_usb3_0 = { 844 .name = "qhs_usb3_0", 845 .channels = 1, 846 .buswidth = 4, 847 }; 848 849 static struct qcom_icc_node qhs_venus_cfg = { 850 .name = "qhs_venus_cfg", 851 .channels = 1, 852 .buswidth = 4, 853 }; 854 855 static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 856 .name = "qhs_vsense_ctrl_cfg", 857 .channels = 1, 858 .buswidth = 4, 859 }; 860 861 static struct qcom_icc_node qns_cnoc_a2noc = { 862 .name = "qns_cnoc_a2noc", 863 .channels = 1, 864 .buswidth = 8, 865 .num_links = 1, 866 .link_nodes = { &qnm_cnoc }, 867 }; 868 869 static struct qcom_icc_node srvc_cnoc = { 870 .name = "srvc_cnoc", 871 .channels = 1, 872 .buswidth = 4, 873 }; 874 875 static struct qcom_icc_node qhs_llcc = { 876 .name = "qhs_llcc", 877 .channels = 1, 878 .buswidth = 4, 879 }; 880 881 static struct qcom_icc_node qhs_memnoc = { 882 .name = "qhs_memnoc", 883 .channels = 1, 884 .buswidth = 4, 885 .num_links = 1, 886 .link_nodes = { &qhm_memnoc_cfg }, 887 }; 888 889 static struct qcom_icc_node qns_gladiator_sodv = { 890 .name = "qns_gladiator_sodv", 891 .channels = 1, 892 .buswidth = 8, 893 .num_links = 1, 894 .link_nodes = { &qnm_gladiator_sodv }, 895 }; 896 897 static struct qcom_icc_node qns_gnoc_memnoc = { 898 .name = "qns_gnoc_memnoc", 899 .channels = 2, 900 .buswidth = 32, 901 .num_links = 1, 902 .link_nodes = { &qnm_apps }, 903 }; 904 905 static struct qcom_icc_node srvc_gnoc = { 906 .name = "srvc_gnoc", 907 .channels = 1, 908 .buswidth = 4, 909 }; 910 911 static struct qcom_icc_node ebi = { 912 .name = "ebi", 913 .channels = 2, 914 .buswidth = 4, 915 }; 916 917 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { 918 .name = "qhs_mdsp_ms_mpu_cfg", 919 .channels = 1, 920 .buswidth = 4, 921 }; 922 923 static struct qcom_icc_node qns_apps_io = { 924 .name = "qns_apps_io", 925 .channels = 1, 926 .buswidth = 32, 927 }; 928 929 static struct qcom_icc_node qns_llcc = { 930 .name = "qns_llcc", 931 .channels = 2, 932 .buswidth = 16, 933 .num_links = 1, 934 .link_nodes = { &llcc_mc }, 935 }; 936 937 static struct qcom_icc_node qns_memnoc_snoc = { 938 .name = "qns_memnoc_snoc", 939 .channels = 1, 940 .buswidth = 8, 941 .num_links = 1, 942 .link_nodes = { &qnm_memnoc }, 943 }; 944 945 static struct qcom_icc_node srvc_memnoc = { 946 .name = "srvc_memnoc", 947 .channels = 1, 948 .buswidth = 4, 949 }; 950 951 static struct qcom_icc_node qns2_mem_noc = { 952 .name = "qns2_mem_noc", 953 .channels = 1, 954 .buswidth = 32, 955 .num_links = 1, 956 .link_nodes = { &qnm_mnoc_sf }, 957 }; 958 959 static struct qcom_icc_node qns_mem_noc_hf = { 960 .name = "qns_mem_noc_hf", 961 .channels = 2, 962 .buswidth = 32, 963 .num_links = 1, 964 .link_nodes = { &qnm_mnoc_hf }, 965 }; 966 967 static struct qcom_icc_node srvc_mnoc = { 968 .name = "srvc_mnoc", 969 .channels = 1, 970 .buswidth = 4, 971 }; 972 973 static struct qcom_icc_node qhs_apss = { 974 .name = "qhs_apss", 975 .channels = 1, 976 .buswidth = 8, 977 }; 978 979 static struct qcom_icc_node qns_cnoc = { 980 .name = "qns_cnoc", 981 .channels = 1, 982 .buswidth = 8, 983 .num_links = 1, 984 .link_nodes = { &qnm_snoc }, 985 }; 986 987 static struct qcom_icc_node qns_memnoc_gc = { 988 .name = "qns_memnoc_gc", 989 .channels = 1, 990 .buswidth = 8, 991 .num_links = 1, 992 .link_nodes = { &qnm_snoc_gc }, 993 }; 994 995 static struct qcom_icc_node qns_memnoc_sf = { 996 .name = "qns_memnoc_sf", 997 .channels = 1, 998 .buswidth = 16, 999 .num_links = 1, 1000 .link_nodes = { &qnm_snoc_sf }, 1001 }; 1002 1003 static struct qcom_icc_node qxs_imem = { 1004 .name = "qxs_imem", 1005 .channels = 1, 1006 .buswidth = 8, 1007 }; 1008 1009 static struct qcom_icc_node qxs_pimem = { 1010 .name = "qxs_pimem", 1011 .channels = 1, 1012 .buswidth = 8, 1013 }; 1014 1015 static struct qcom_icc_node srvc_snoc = { 1016 .name = "srvc_snoc", 1017 .channels = 1, 1018 .buswidth = 4, 1019 }; 1020 1021 static struct qcom_icc_node xs_qdss_stm = { 1022 .name = "xs_qdss_stm", 1023 .channels = 1, 1024 .buswidth = 4, 1025 }; 1026 1027 static struct qcom_icc_node xs_sys_tcu_cfg = { 1028 .name = "xs_sys_tcu_cfg", 1029 .channels = 1, 1030 .buswidth = 8, 1031 }; 1032 1033 static struct qcom_icc_bcm bcm_acv = { 1034 .name = "ACV", 1035 .enable_mask = BIT(3), 1036 .keepalive = false, 1037 .num_nodes = 1, 1038 .nodes = { &ebi }, 1039 }; 1040 1041 static struct qcom_icc_bcm bcm_mc0 = { 1042 .name = "MC0", 1043 .keepalive = true, 1044 .num_nodes = 1, 1045 .nodes = { &ebi }, 1046 }; 1047 1048 static struct qcom_icc_bcm bcm_sh0 = { 1049 .name = "SH0", 1050 .keepalive = true, 1051 .num_nodes = 1, 1052 .nodes = { &qns_llcc }, 1053 }; 1054 1055 static struct qcom_icc_bcm bcm_mm0 = { 1056 .name = "MM0", 1057 .keepalive = true, 1058 .num_nodes = 1, 1059 .nodes = { &qns_mem_noc_hf }, 1060 }; 1061 1062 static struct qcom_icc_bcm bcm_sh1 = { 1063 .name = "SH1", 1064 .keepalive = false, 1065 .num_nodes = 1, 1066 .nodes = { &qns_apps_io }, 1067 }; 1068 1069 static struct qcom_icc_bcm bcm_mm1 = { 1070 .name = "MM1", 1071 .keepalive = true, 1072 .num_nodes = 7, 1073 .nodes = { &qxm_camnoc_hf0_uncomp, 1074 &qxm_camnoc_hf1_uncomp, 1075 &qxm_camnoc_sf_uncomp, 1076 &qxm_camnoc_hf0, 1077 &qxm_camnoc_hf1, 1078 &qxm_mdp0, 1079 &qxm_mdp1 1080 }, 1081 }; 1082 1083 static struct qcom_icc_bcm bcm_sh2 = { 1084 .name = "SH2", 1085 .keepalive = false, 1086 .num_nodes = 1, 1087 .nodes = { &qns_memnoc_snoc }, 1088 }; 1089 1090 static struct qcom_icc_bcm bcm_mm2 = { 1091 .name = "MM2", 1092 .keepalive = false, 1093 .num_nodes = 1, 1094 .nodes = { &qns2_mem_noc }, 1095 }; 1096 1097 static struct qcom_icc_bcm bcm_sh3 = { 1098 .name = "SH3", 1099 .keepalive = false, 1100 .num_nodes = 1, 1101 .nodes = { &acm_tcu }, 1102 }; 1103 1104 static struct qcom_icc_bcm bcm_mm3 = { 1105 .name = "MM3", 1106 .keepalive = false, 1107 .num_nodes = 5, 1108 .nodes = { &qxm_camnoc_sf, &qxm_rot, &qxm_venus0, &qxm_venus1, &qxm_venus_arm9 }, 1109 }; 1110 1111 static struct qcom_icc_bcm bcm_sh5 = { 1112 .name = "SH5", 1113 .keepalive = false, 1114 .num_nodes = 1, 1115 .nodes = { &qnm_apps }, 1116 }; 1117 1118 static struct qcom_icc_bcm bcm_sn0 = { 1119 .name = "SN0", 1120 .keepalive = true, 1121 .num_nodes = 1, 1122 .nodes = { &qns_memnoc_sf }, 1123 }; 1124 1125 static struct qcom_icc_bcm bcm_ce0 = { 1126 .name = "CE0", 1127 .keepalive = false, 1128 .num_nodes = 1, 1129 .nodes = { &qxm_crypto }, 1130 }; 1131 1132 static struct qcom_icc_bcm bcm_cn0 = { 1133 .name = "CN0", 1134 .keepalive = true, 1135 .num_nodes = 41, 1136 .nodes = { &qhm_spdm, 1137 &qnm_snoc, 1138 &qhs_a1_noc_cfg, 1139 &qhs_a2_noc_cfg, 1140 &qhs_aop, 1141 &qhs_aoss, 1142 &qhs_camera_cfg, 1143 &qhs_clk_ctl, 1144 &qhs_compute_dsp_cfg, 1145 &qhs_cpr_cx, 1146 &qhs_crypto0_cfg, 1147 &qhs_dcc_cfg, 1148 &qhs_ddrss_cfg, 1149 &qhs_display_cfg, 1150 &qhs_emmc_cfg, 1151 &qhs_glm, 1152 &qhs_gpuss_cfg, 1153 &qhs_imem_cfg, 1154 &qhs_ipa, 1155 &qhs_mnoc_cfg, 1156 &qhs_pdm, 1157 &qhs_phy_refgen_south, 1158 &qhs_pimem_cfg, 1159 &qhs_prng, 1160 &qhs_qdss_cfg, 1161 &qhs_qupv3_north, 1162 &qhs_qupv3_south, 1163 &qhs_sdc2, 1164 &qhs_sdc4, 1165 &qhs_snoc_cfg, 1166 &qhs_spdm, 1167 &qhs_tcsr, 1168 &qhs_tlmm_north, 1169 &qhs_tlmm_south, 1170 &qhs_tsif, 1171 &qhs_ufs_mem_cfg, 1172 &qhs_usb3_0, 1173 &qhs_venus_cfg, 1174 &qhs_vsense_ctrl_cfg, 1175 &qns_cnoc_a2noc, 1176 &srvc_cnoc 1177 }, 1178 }; 1179 1180 static struct qcom_icc_bcm bcm_qup0 = { 1181 .name = "QUP0", 1182 .keepalive = false, 1183 .num_nodes = 2, 1184 .nodes = { &qhm_qup1, &qhm_qup2 }, 1185 }; 1186 1187 static struct qcom_icc_bcm bcm_sn1 = { 1188 .name = "SN1", 1189 .keepalive = false, 1190 .num_nodes = 1, 1191 .nodes = { &qxs_imem }, 1192 }; 1193 1194 static struct qcom_icc_bcm bcm_sn2 = { 1195 .name = "SN2", 1196 .keepalive = false, 1197 .num_nodes = 1, 1198 .nodes = { &qns_memnoc_gc }, 1199 }; 1200 1201 static struct qcom_icc_bcm bcm_sn3 = { 1202 .name = "SN3", 1203 .keepalive = false, 1204 .num_nodes = 1, 1205 .nodes = { &qns_cnoc }, 1206 }; 1207 1208 static struct qcom_icc_bcm bcm_sn4 = { 1209 .name = "SN4", 1210 .keepalive = false, 1211 .num_nodes = 2, 1212 .nodes = { &qxm_pimem, &qxs_pimem }, 1213 }; 1214 1215 static struct qcom_icc_bcm bcm_sn5 = { 1216 .name = "SN5", 1217 .keepalive = false, 1218 .num_nodes = 1, 1219 .nodes = { &xs_qdss_stm }, 1220 }; 1221 1222 static struct qcom_icc_bcm bcm_sn8 = { 1223 .name = "SN8", 1224 .keepalive = false, 1225 .num_nodes = 2, 1226 .nodes = { &qnm_aggre1_noc, &srvc_aggre1_noc }, 1227 }; 1228 1229 static struct qcom_icc_bcm bcm_sn10 = { 1230 .name = "SN10", 1231 .keepalive = false, 1232 .num_nodes = 2, 1233 .nodes = { &qnm_aggre2_noc, &srvc_aggre2_noc }, 1234 }; 1235 1236 static struct qcom_icc_bcm bcm_sn11 = { 1237 .name = "SN11", 1238 .keepalive = false, 1239 .num_nodes = 2, 1240 .nodes = { &qnm_gladiator_sodv, &xm_gic }, 1241 }; 1242 1243 static struct qcom_icc_bcm bcm_sn13 = { 1244 .name = "SN13", 1245 .keepalive = false, 1246 .num_nodes = 1, 1247 .nodes = { &qnm_memnoc }, 1248 }; 1249 1250 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 1251 &bcm_qup0, 1252 &bcm_sn8, 1253 }; 1254 1255 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1256 [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg, 1257 [MASTER_BLSP_1] = &qhm_qup1, 1258 [MASTER_TSIF] = &qhm_tsif, 1259 [MASTER_EMMC] = &xm_emmc, 1260 [MASTER_SDCC_2] = &xm_sdc2, 1261 [MASTER_SDCC_4] = &xm_sdc4, 1262 [MASTER_UFS_MEM] = &xm_ufs_mem, 1263 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, 1264 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, 1265 }; 1266 1267 static const struct qcom_icc_desc sdm670_aggre1_noc = { 1268 .nodes = aggre1_noc_nodes, 1269 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 1270 .bcms = aggre1_noc_bcms, 1271 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 1272 }; 1273 1274 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 1275 &bcm_ce0, 1276 &bcm_qup0, 1277 &bcm_sn10, 1278 }; 1279 1280 static struct qcom_icc_node * const aggre2_noc_nodes[] = { 1281 [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg, 1282 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 1283 [MASTER_BLSP_2] = &qhm_qup2, 1284 [MASTER_CNOC_A2NOC] = &qnm_cnoc, 1285 [MASTER_CRYPTO_CORE_0] = &qxm_crypto, 1286 [MASTER_IPA] = &qxm_ipa, 1287 [MASTER_QDSS_ETR] = &xm_qdss_etr, 1288 [MASTER_USB3] = &xm_usb3_0, 1289 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, 1290 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, 1291 }; 1292 1293 static const struct qcom_icc_desc sdm670_aggre2_noc = { 1294 .nodes = aggre2_noc_nodes, 1295 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 1296 .bcms = aggre2_noc_bcms, 1297 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 1298 }; 1299 1300 static struct qcom_icc_bcm * const config_noc_bcms[] = { 1301 &bcm_cn0, 1302 }; 1303 1304 static struct qcom_icc_node * const config_noc_nodes[] = { 1305 [MASTER_SPDM] = &qhm_spdm, 1306 [MASTER_SNOC_CNOC] = &qnm_snoc, 1307 [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg, 1308 [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg, 1309 [SLAVE_AOP] = &qhs_aop, 1310 [SLAVE_AOSS] = &qhs_aoss, 1311 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 1312 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1313 [SLAVE_CDSP_CFG] = &qhs_compute_dsp_cfg, 1314 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 1315 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1316 [SLAVE_DCC_CFG] = &qhs_dcc_cfg, 1317 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg, 1318 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 1319 [SLAVE_EMMC_CFG] = &qhs_emmc_cfg, 1320 [SLAVE_GLM] = &qhs_glm, 1321 [SLAVE_GRAPHICS_3D_CFG] = &qhs_gpuss_cfg, 1322 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1323 [SLAVE_IPA_CFG] = &qhs_ipa, 1324 [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg, 1325 [SLAVE_PDM] = &qhs_pdm, 1326 [SLAVE_SOUTH_PHY_CFG] = &qhs_phy_refgen_south, 1327 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 1328 [SLAVE_PRNG] = &qhs_prng, 1329 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1330 [SLAVE_BLSP_2] = &qhs_qupv3_north, 1331 [SLAVE_BLSP_1] = &qhs_qupv3_south, 1332 [SLAVE_SDCC_2] = &qhs_sdc2, 1333 [SLAVE_SDCC_4] = &qhs_sdc4, 1334 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, 1335 [SLAVE_SPDM_WRAPPER] = &qhs_spdm, 1336 [SLAVE_TCSR] = &qhs_tcsr, 1337 [SLAVE_TLMM_NORTH] = &qhs_tlmm_north, 1338 [SLAVE_TLMM_SOUTH] = &qhs_tlmm_south, 1339 [SLAVE_TSIF] = &qhs_tsif, 1340 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 1341 [SLAVE_USB3] = &qhs_usb3_0, 1342 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1343 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 1344 [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc, 1345 [SLAVE_SERVICE_CNOC] = &srvc_cnoc, 1346 }; 1347 1348 static const struct qcom_icc_desc sdm670_config_noc = { 1349 .nodes = config_noc_nodes, 1350 .num_nodes = ARRAY_SIZE(config_noc_nodes), 1351 .bcms = config_noc_bcms, 1352 .num_bcms = ARRAY_SIZE(config_noc_bcms), 1353 }; 1354 1355 static struct qcom_icc_bcm * const dc_noc_bcms[] = { 1356 }; 1357 1358 static struct qcom_icc_node * const dc_noc_nodes[] = { 1359 [MASTER_CNOC_DC_NOC] = &qhm_cnoc, 1360 [SLAVE_LLCC_CFG] = &qhs_llcc, 1361 [SLAVE_MEM_NOC_CFG] = &qhs_memnoc, 1362 }; 1363 1364 static const struct qcom_icc_desc sdm670_dc_noc = { 1365 .nodes = dc_noc_nodes, 1366 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 1367 .bcms = dc_noc_bcms, 1368 .num_bcms = ARRAY_SIZE(dc_noc_bcms), 1369 }; 1370 1371 static struct qcom_icc_bcm * const gladiator_noc_bcms[] = { 1372 }; 1373 1374 static struct qcom_icc_node * const gladiator_noc_nodes[] = { 1375 [MASTER_AMPSS_M0] = &acm_l3, 1376 [MASTER_GNOC_CFG] = &pm_gnoc_cfg, 1377 [SLAVE_GNOC_SNOC] = &qns_gladiator_sodv, 1378 [SLAVE_GNOC_MEM_NOC] = &qns_gnoc_memnoc, 1379 [SLAVE_SERVICE_GNOC] = &srvc_gnoc, 1380 }; 1381 1382 static const struct qcom_icc_desc sdm670_gladiator_noc = { 1383 .nodes = gladiator_noc_nodes, 1384 .num_nodes = ARRAY_SIZE(gladiator_noc_nodes), 1385 .bcms = gladiator_noc_bcms, 1386 .num_bcms = ARRAY_SIZE(gladiator_noc_bcms), 1387 }; 1388 1389 static struct qcom_icc_bcm * const mem_noc_bcms[] = { 1390 &bcm_acv, 1391 &bcm_mc0, 1392 &bcm_sh0, 1393 &bcm_sh1, 1394 &bcm_sh2, 1395 &bcm_sh3, 1396 &bcm_sh5, 1397 }; 1398 1399 static struct qcom_icc_node * const mem_noc_nodes[] = { 1400 [MASTER_TCU_0] = &acm_tcu, 1401 [MASTER_MEM_NOC_CFG] = &qhm_memnoc_cfg, 1402 [MASTER_GNOC_MEM_NOC] = &qnm_apps, 1403 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 1404 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 1405 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 1406 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 1407 [MASTER_GRAPHICS_3D] = &qxm_gpu, 1408 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg, 1409 [SLAVE_MEM_NOC_GNOC] = &qns_apps_io, 1410 [SLAVE_LLCC] = &qns_llcc, 1411 [SLAVE_MEM_NOC_SNOC] = &qns_memnoc_snoc, 1412 [SLAVE_SERVICE_MEM_NOC] = &srvc_memnoc, 1413 [MASTER_LLCC] = &llcc_mc, 1414 [SLAVE_EBI_CH0] = &ebi, 1415 }; 1416 1417 static const struct qcom_icc_desc sdm670_mem_noc = { 1418 .nodes = mem_noc_nodes, 1419 .num_nodes = ARRAY_SIZE(mem_noc_nodes), 1420 .bcms = mem_noc_bcms, 1421 .num_bcms = ARRAY_SIZE(mem_noc_bcms), 1422 }; 1423 1424 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 1425 &bcm_mm0, 1426 &bcm_mm1, 1427 &bcm_mm2, 1428 &bcm_mm3, 1429 }; 1430 1431 static struct qcom_icc_node * const mmss_noc_nodes[] = { 1432 [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg, 1433 [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0, 1434 [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1, 1435 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf, 1436 [MASTER_MDP_PORT0] = &qxm_mdp0, 1437 [MASTER_MDP_PORT1] = &qxm_mdp1, 1438 [MASTER_ROTATOR] = &qxm_rot, 1439 [MASTER_VIDEO_P0] = &qxm_venus0, 1440 [MASTER_VIDEO_P1] = &qxm_venus1, 1441 [MASTER_VIDEO_PROC] = &qxm_venus_arm9, 1442 [SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc, 1443 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 1444 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 1445 }; 1446 1447 static const struct qcom_icc_desc sdm670_mmss_noc = { 1448 .nodes = mmss_noc_nodes, 1449 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 1450 .bcms = mmss_noc_bcms, 1451 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 1452 }; 1453 1454 static struct qcom_icc_bcm * const system_noc_bcms[] = { 1455 &bcm_mm1, 1456 &bcm_sn0, 1457 &bcm_sn1, 1458 &bcm_sn10, 1459 &bcm_sn11, 1460 &bcm_sn13, 1461 &bcm_sn2, 1462 &bcm_sn3, 1463 &bcm_sn4, 1464 &bcm_sn5, 1465 &bcm_sn8, 1466 }; 1467 1468 static struct qcom_icc_node * const system_noc_nodes[] = { 1469 [MASTER_SNOC_CFG] = &qhm_snoc_cfg, 1470 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, 1471 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, 1472 [MASTER_GNOC_SNOC] = &qnm_gladiator_sodv, 1473 [MASTER_MEM_NOC_SNOC] = &qnm_memnoc, 1474 [MASTER_PIMEM] = &qxm_pimem, 1475 [MASTER_GIC] = &xm_gic, 1476 [SLAVE_APPSS] = &qhs_apss, 1477 [SLAVE_SNOC_CNOC] = &qns_cnoc, 1478 [SLAVE_SNOC_MEM_NOC_GC] = &qns_memnoc_gc, 1479 [SLAVE_SNOC_MEM_NOC_SF] = &qns_memnoc_sf, 1480 [SLAVE_OCIMEM] = &qxs_imem, 1481 [SLAVE_PIMEM] = &qxs_pimem, 1482 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 1483 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1484 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1485 [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp, 1486 [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp, 1487 [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp, 1488 [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp, 1489 }; 1490 1491 static const struct qcom_icc_desc sdm670_system_noc = { 1492 .nodes = system_noc_nodes, 1493 .num_nodes = ARRAY_SIZE(system_noc_nodes), 1494 .bcms = system_noc_bcms, 1495 .num_bcms = ARRAY_SIZE(system_noc_bcms), 1496 }; 1497 1498 static const struct of_device_id qnoc_of_match[] = { 1499 { .compatible = "qcom,sdm670-aggre1-noc", 1500 .data = &sdm670_aggre1_noc}, 1501 { .compatible = "qcom,sdm670-aggre2-noc", 1502 .data = &sdm670_aggre2_noc}, 1503 { .compatible = "qcom,sdm670-config-noc", 1504 .data = &sdm670_config_noc}, 1505 { .compatible = "qcom,sdm670-dc-noc", 1506 .data = &sdm670_dc_noc}, 1507 { .compatible = "qcom,sdm670-gladiator-noc", 1508 .data = &sdm670_gladiator_noc}, 1509 { .compatible = "qcom,sdm670-mem-noc", 1510 .data = &sdm670_mem_noc}, 1511 { .compatible = "qcom,sdm670-mmss-noc", 1512 .data = &sdm670_mmss_noc}, 1513 { .compatible = "qcom,sdm670-system-noc", 1514 .data = &sdm670_system_noc}, 1515 { } 1516 }; 1517 MODULE_DEVICE_TABLE(of, qnoc_of_match); 1518 1519 static struct platform_driver qnoc_driver = { 1520 .probe = qcom_icc_rpmh_probe, 1521 .remove = qcom_icc_rpmh_remove, 1522 .driver = { 1523 .name = "qnoc-sdm670", 1524 .of_match_table = qnoc_of_match, 1525 .sync_state = icc_sync_state, 1526 }, 1527 }; 1528 module_platform_driver(qnoc_driver); 1529 1530 MODULE_DESCRIPTION("Qualcomm SDM670 NoC driver"); 1531 MODULE_LICENSE("GPL"); 1532