1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Linaro Ltd 5 */ 6 7 #include <linux/device.h> 8 #include <linux/interconnect.h> 9 #include <linux/interconnect-provider.h> 10 #include <linux/mod_devicetable.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <dt-bindings/interconnect/qcom,sc8280xp.h> 14 15 #include "bcm-voter.h" 16 #include "icc-rpmh.h" 17 18 static struct qcom_icc_node qhm_qspi; 19 static struct qcom_icc_node qhm_qup1; 20 static struct qcom_icc_node qhm_qup2; 21 static struct qcom_icc_node qnm_a1noc_cfg; 22 static struct qcom_icc_node qxm_ipa; 23 static struct qcom_icc_node xm_emac_1; 24 static struct qcom_icc_node xm_sdc4; 25 static struct qcom_icc_node xm_ufs_mem; 26 static struct qcom_icc_node xm_usb3_0; 27 static struct qcom_icc_node xm_usb3_1; 28 static struct qcom_icc_node xm_usb3_mp; 29 static struct qcom_icc_node xm_usb4_host0; 30 static struct qcom_icc_node xm_usb4_host1; 31 static struct qcom_icc_node qhm_qdss_bam; 32 static struct qcom_icc_node qhm_qup0; 33 static struct qcom_icc_node qnm_a2noc_cfg; 34 static struct qcom_icc_node qxm_crypto; 35 static struct qcom_icc_node qxm_sensorss_q6; 36 static struct qcom_icc_node qxm_sp; 37 static struct qcom_icc_node xm_emac_0; 38 static struct qcom_icc_node xm_pcie3_0; 39 static struct qcom_icc_node xm_pcie3_1; 40 static struct qcom_icc_node xm_pcie3_2a; 41 static struct qcom_icc_node xm_pcie3_2b; 42 static struct qcom_icc_node xm_pcie3_3a; 43 static struct qcom_icc_node xm_pcie3_3b; 44 static struct qcom_icc_node xm_pcie3_4; 45 static struct qcom_icc_node xm_qdss_etr; 46 static struct qcom_icc_node xm_sdc2; 47 static struct qcom_icc_node xm_ufs_card; 48 static struct qcom_icc_node qup0_core_master; 49 static struct qcom_icc_node qup1_core_master; 50 static struct qcom_icc_node qup2_core_master; 51 static struct qcom_icc_node qnm_gemnoc_cnoc; 52 static struct qcom_icc_node qnm_gemnoc_pcie; 53 static struct qcom_icc_node qnm_cnoc_dc_noc; 54 static struct qcom_icc_node alm_gpu_tcu; 55 static struct qcom_icc_node alm_pcie_tcu; 56 static struct qcom_icc_node alm_sys_tcu; 57 static struct qcom_icc_node chm_apps; 58 static struct qcom_icc_node qnm_cmpnoc0; 59 static struct qcom_icc_node qnm_cmpnoc1; 60 static struct qcom_icc_node qnm_gemnoc_cfg; 61 static struct qcom_icc_node qnm_gpu; 62 static struct qcom_icc_node qnm_mnoc_hf; 63 static struct qcom_icc_node qnm_mnoc_sf; 64 static struct qcom_icc_node qnm_pcie; 65 static struct qcom_icc_node qnm_snoc_gc; 66 static struct qcom_icc_node qnm_snoc_sf; 67 static struct qcom_icc_node qhm_config_noc; 68 static struct qcom_icc_node qxm_lpass_dsp; 69 static struct qcom_icc_node llcc_mc; 70 static struct qcom_icc_node qnm_camnoc_hf; 71 static struct qcom_icc_node qnm_mdp0_0; 72 static struct qcom_icc_node qnm_mdp0_1; 73 static struct qcom_icc_node qnm_mdp1_0; 74 static struct qcom_icc_node qnm_mdp1_1; 75 static struct qcom_icc_node qnm_mnoc_cfg; 76 static struct qcom_icc_node qnm_rot_0; 77 static struct qcom_icc_node qnm_rot_1; 78 static struct qcom_icc_node qnm_video0; 79 static struct qcom_icc_node qnm_video1; 80 static struct qcom_icc_node qnm_video_cvp; 81 static struct qcom_icc_node qxm_camnoc_icp; 82 static struct qcom_icc_node qxm_camnoc_sf; 83 static struct qcom_icc_node qhm_nsp_noc_config; 84 static struct qcom_icc_node qxm_nsp; 85 static struct qcom_icc_node qhm_nspb_noc_config; 86 static struct qcom_icc_node qxm_nspb; 87 static struct qcom_icc_node qnm_aggre1_noc; 88 static struct qcom_icc_node qnm_aggre2_noc; 89 static struct qcom_icc_node qnm_aggre_usb_noc; 90 static struct qcom_icc_node qnm_lpass_noc; 91 static struct qcom_icc_node qnm_snoc_cfg; 92 static struct qcom_icc_node qxm_pimem; 93 static struct qcom_icc_node xm_gic; 94 static struct qcom_icc_node qns_a1noc_snoc; 95 static struct qcom_icc_node qns_aggre_usb_snoc; 96 static struct qcom_icc_node srvc_aggre1_noc; 97 static struct qcom_icc_node qns_a2noc_snoc; 98 static struct qcom_icc_node qns_pcie_gem_noc; 99 static struct qcom_icc_node srvc_aggre2_noc; 100 static struct qcom_icc_node qup0_core_slave; 101 static struct qcom_icc_node qup1_core_slave; 102 static struct qcom_icc_node qup2_core_slave; 103 static struct qcom_icc_node qhs_ahb2phy0; 104 static struct qcom_icc_node qhs_ahb2phy1; 105 static struct qcom_icc_node qhs_ahb2phy2; 106 static struct qcom_icc_node qhs_aoss; 107 static struct qcom_icc_node qhs_apss; 108 static struct qcom_icc_node qhs_camera_cfg; 109 static struct qcom_icc_node qhs_clk_ctl; 110 static struct qcom_icc_node qhs_compute0_cfg; 111 static struct qcom_icc_node qhs_compute1_cfg; 112 static struct qcom_icc_node qhs_cpr_cx; 113 static struct qcom_icc_node qhs_cpr_mmcx; 114 static struct qcom_icc_node qhs_cpr_mx; 115 static struct qcom_icc_node qhs_cpr_nspcx; 116 static struct qcom_icc_node qhs_crypto0_cfg; 117 static struct qcom_icc_node qhs_cx_rdpm; 118 static struct qcom_icc_node qhs_dcc_cfg; 119 static struct qcom_icc_node qhs_display0_cfg; 120 static struct qcom_icc_node qhs_display1_cfg; 121 static struct qcom_icc_node qhs_emac0_cfg; 122 static struct qcom_icc_node qhs_emac1_cfg; 123 static struct qcom_icc_node qhs_gpuss_cfg; 124 static struct qcom_icc_node qhs_hwkm; 125 static struct qcom_icc_node qhs_imem_cfg; 126 static struct qcom_icc_node qhs_ipa; 127 static struct qcom_icc_node qhs_ipc_router; 128 static struct qcom_icc_node qhs_lpass_cfg; 129 static struct qcom_icc_node qhs_mx_rdpm; 130 static struct qcom_icc_node qhs_mxc_rdpm; 131 static struct qcom_icc_node qhs_pcie0_cfg; 132 static struct qcom_icc_node qhs_pcie1_cfg; 133 static struct qcom_icc_node qhs_pcie2a_cfg; 134 static struct qcom_icc_node qhs_pcie2b_cfg; 135 static struct qcom_icc_node qhs_pcie3a_cfg; 136 static struct qcom_icc_node qhs_pcie3b_cfg; 137 static struct qcom_icc_node qhs_pcie4_cfg; 138 static struct qcom_icc_node qhs_pcie_rsc_cfg; 139 static struct qcom_icc_node qhs_pdm; 140 static struct qcom_icc_node qhs_pimem_cfg; 141 static struct qcom_icc_node qhs_pka_wrapper_cfg; 142 static struct qcom_icc_node qhs_pmu_wrapper_cfg; 143 static struct qcom_icc_node qhs_qdss_cfg; 144 static struct qcom_icc_node qhs_qspi; 145 static struct qcom_icc_node qhs_qup0; 146 static struct qcom_icc_node qhs_qup1; 147 static struct qcom_icc_node qhs_qup2; 148 static struct qcom_icc_node qhs_sdc2; 149 static struct qcom_icc_node qhs_sdc4; 150 static struct qcom_icc_node qhs_security; 151 static struct qcom_icc_node qhs_smmuv3_cfg; 152 static struct qcom_icc_node qhs_smss_cfg; 153 static struct qcom_icc_node qhs_spss_cfg; 154 static struct qcom_icc_node qhs_tcsr; 155 static struct qcom_icc_node qhs_tlmm; 156 static struct qcom_icc_node qhs_ufs_card_cfg; 157 static struct qcom_icc_node qhs_ufs_mem_cfg; 158 static struct qcom_icc_node qhs_usb3_0; 159 static struct qcom_icc_node qhs_usb3_1; 160 static struct qcom_icc_node qhs_usb3_mp; 161 static struct qcom_icc_node qhs_usb4_host_0; 162 static struct qcom_icc_node qhs_usb4_host_1; 163 static struct qcom_icc_node qhs_venus_cfg; 164 static struct qcom_icc_node qhs_vsense_ctrl_cfg; 165 static struct qcom_icc_node qhs_vsense_ctrl_r_cfg; 166 static struct qcom_icc_node qns_a1_noc_cfg; 167 static struct qcom_icc_node qns_a2_noc_cfg; 168 static struct qcom_icc_node qns_anoc_pcie_bridge_cfg; 169 static struct qcom_icc_node qns_ddrss_cfg; 170 static struct qcom_icc_node qns_mnoc_cfg; 171 static struct qcom_icc_node qns_snoc_cfg; 172 static struct qcom_icc_node qns_snoc_sf_bridge_cfg; 173 static struct qcom_icc_node qxs_imem; 174 static struct qcom_icc_node qxs_pimem; 175 static struct qcom_icc_node srvc_cnoc; 176 static struct qcom_icc_node xs_pcie_0; 177 static struct qcom_icc_node xs_pcie_1; 178 static struct qcom_icc_node xs_pcie_2a; 179 static struct qcom_icc_node xs_pcie_2b; 180 static struct qcom_icc_node xs_pcie_3a; 181 static struct qcom_icc_node xs_pcie_3b; 182 static struct qcom_icc_node xs_pcie_4; 183 static struct qcom_icc_node xs_qdss_stm; 184 static struct qcom_icc_node xs_smss; 185 static struct qcom_icc_node xs_sys_tcu_cfg; 186 static struct qcom_icc_node qhs_llcc; 187 static struct qcom_icc_node qns_gemnoc; 188 static struct qcom_icc_node qns_gem_noc_cnoc; 189 static struct qcom_icc_node qns_llcc; 190 static struct qcom_icc_node qns_pcie; 191 static struct qcom_icc_node srvc_even_gemnoc; 192 static struct qcom_icc_node srvc_odd_gemnoc; 193 static struct qcom_icc_node srvc_sys_gemnoc; 194 static struct qcom_icc_node qhs_lpass_core; 195 static struct qcom_icc_node qhs_lpass_lpi; 196 static struct qcom_icc_node qhs_lpass_mpu; 197 static struct qcom_icc_node qhs_lpass_top; 198 static struct qcom_icc_node qns_sysnoc; 199 static struct qcom_icc_node srvc_niu_aml_noc; 200 static struct qcom_icc_node srvc_niu_lpass_agnoc; 201 static struct qcom_icc_node ebi; 202 static struct qcom_icc_node qns_mem_noc_hf; 203 static struct qcom_icc_node qns_mem_noc_sf; 204 static struct qcom_icc_node srvc_mnoc; 205 static struct qcom_icc_node qns_nsp_gemnoc; 206 static struct qcom_icc_node qxs_nsp_xfr; 207 static struct qcom_icc_node service_nsp_noc; 208 static struct qcom_icc_node qns_nspb_gemnoc; 209 static struct qcom_icc_node qxs_nspb_xfr; 210 static struct qcom_icc_node service_nspb_noc; 211 static struct qcom_icc_node qns_gemnoc_gc; 212 static struct qcom_icc_node qns_gemnoc_sf; 213 static struct qcom_icc_node srvc_snoc; 214 215 static struct qcom_icc_node qhm_qspi = { 216 .name = "qhm_qspi", 217 .channels = 1, 218 .buswidth = 4, 219 .num_links = 1, 220 .link_nodes = { &qns_a1noc_snoc }, 221 }; 222 223 static struct qcom_icc_node qhm_qup1 = { 224 .name = "qhm_qup1", 225 .channels = 1, 226 .buswidth = 4, 227 .num_links = 1, 228 .link_nodes = { &qns_a1noc_snoc }, 229 }; 230 231 static struct qcom_icc_node qhm_qup2 = { 232 .name = "qhm_qup2", 233 .channels = 1, 234 .buswidth = 4, 235 .num_links = 1, 236 .link_nodes = { &qns_a1noc_snoc }, 237 }; 238 239 static struct qcom_icc_node qnm_a1noc_cfg = { 240 .name = "qnm_a1noc_cfg", 241 .channels = 1, 242 .buswidth = 4, 243 .num_links = 1, 244 .link_nodes = { &srvc_aggre1_noc }, 245 }; 246 247 static struct qcom_icc_node qxm_ipa = { 248 .name = "qxm_ipa", 249 .channels = 1, 250 .buswidth = 8, 251 .num_links = 1, 252 .link_nodes = { &qns_a1noc_snoc }, 253 }; 254 255 static struct qcom_icc_node xm_emac_1 = { 256 .name = "xm_emac_1", 257 .channels = 1, 258 .buswidth = 8, 259 .num_links = 1, 260 .link_nodes = { &qns_a1noc_snoc }, 261 }; 262 263 static struct qcom_icc_node xm_sdc4 = { 264 .name = "xm_sdc4", 265 .channels = 1, 266 .buswidth = 8, 267 .num_links = 1, 268 .link_nodes = { &qns_a1noc_snoc }, 269 }; 270 271 static struct qcom_icc_node xm_ufs_mem = { 272 .name = "xm_ufs_mem", 273 .channels = 1, 274 .buswidth = 8, 275 .num_links = 1, 276 .link_nodes = { &qns_a1noc_snoc }, 277 }; 278 279 static struct qcom_icc_node xm_usb3_0 = { 280 .name = "xm_usb3_0", 281 .channels = 1, 282 .buswidth = 8, 283 .num_links = 1, 284 .link_nodes = { &qns_aggre_usb_snoc }, 285 }; 286 287 static struct qcom_icc_node xm_usb3_1 = { 288 .name = "xm_usb3_1", 289 .channels = 1, 290 .buswidth = 8, 291 .num_links = 1, 292 .link_nodes = { &qns_aggre_usb_snoc }, 293 }; 294 295 static struct qcom_icc_node xm_usb3_mp = { 296 .name = "xm_usb3_mp", 297 .channels = 1, 298 .buswidth = 16, 299 .num_links = 1, 300 .link_nodes = { &qns_aggre_usb_snoc }, 301 }; 302 303 static struct qcom_icc_node xm_usb4_host0 = { 304 .name = "xm_usb4_host0", 305 .channels = 1, 306 .buswidth = 16, 307 .num_links = 1, 308 .link_nodes = { &qns_aggre_usb_snoc }, 309 }; 310 311 static struct qcom_icc_node xm_usb4_host1 = { 312 .name = "xm_usb4_host1", 313 .channels = 1, 314 .buswidth = 16, 315 .num_links = 1, 316 .link_nodes = { &qns_aggre_usb_snoc }, 317 }; 318 319 static struct qcom_icc_node qhm_qdss_bam = { 320 .name = "qhm_qdss_bam", 321 .channels = 1, 322 .buswidth = 4, 323 .num_links = 1, 324 .link_nodes = { &qns_a2noc_snoc }, 325 }; 326 327 static struct qcom_icc_node qhm_qup0 = { 328 .name = "qhm_qup0", 329 .channels = 1, 330 .buswidth = 4, 331 .num_links = 1, 332 .link_nodes = { &qns_a2noc_snoc }, 333 }; 334 335 static struct qcom_icc_node qnm_a2noc_cfg = { 336 .name = "qnm_a2noc_cfg", 337 .channels = 1, 338 .buswidth = 4, 339 .num_links = 1, 340 .link_nodes = { &srvc_aggre2_noc }, 341 }; 342 343 static struct qcom_icc_node qxm_crypto = { 344 .name = "qxm_crypto", 345 .channels = 1, 346 .buswidth = 8, 347 .num_links = 1, 348 .link_nodes = { &qns_a2noc_snoc }, 349 }; 350 351 static struct qcom_icc_node qxm_sensorss_q6 = { 352 .name = "qxm_sensorss_q6", 353 .channels = 1, 354 .buswidth = 8, 355 .num_links = 1, 356 .link_nodes = { &qns_a2noc_snoc }, 357 }; 358 359 static struct qcom_icc_node qxm_sp = { 360 .name = "qxm_sp", 361 .channels = 1, 362 .buswidth = 8, 363 .num_links = 1, 364 .link_nodes = { &qns_a2noc_snoc }, 365 }; 366 367 static struct qcom_icc_node xm_emac_0 = { 368 .name = "xm_emac_0", 369 .channels = 1, 370 .buswidth = 8, 371 .num_links = 1, 372 .link_nodes = { &qns_a2noc_snoc }, 373 }; 374 375 static struct qcom_icc_node xm_pcie3_0 = { 376 .name = "xm_pcie3_0", 377 .channels = 1, 378 .buswidth = 16, 379 .num_links = 1, 380 .link_nodes = { &qns_pcie_gem_noc }, 381 }; 382 383 static struct qcom_icc_node xm_pcie3_1 = { 384 .name = "xm_pcie3_1", 385 .channels = 1, 386 .buswidth = 16, 387 .num_links = 1, 388 .link_nodes = { &qns_pcie_gem_noc }, 389 }; 390 391 static struct qcom_icc_node xm_pcie3_2a = { 392 .name = "xm_pcie3_2a", 393 .channels = 1, 394 .buswidth = 16, 395 .num_links = 1, 396 .link_nodes = { &qns_pcie_gem_noc }, 397 }; 398 399 static struct qcom_icc_node xm_pcie3_2b = { 400 .name = "xm_pcie3_2b", 401 .channels = 1, 402 .buswidth = 8, 403 .num_links = 1, 404 .link_nodes = { &qns_pcie_gem_noc }, 405 }; 406 407 static struct qcom_icc_node xm_pcie3_3a = { 408 .name = "xm_pcie3_3a", 409 .channels = 1, 410 .buswidth = 16, 411 .num_links = 1, 412 .link_nodes = { &qns_pcie_gem_noc }, 413 }; 414 415 static struct qcom_icc_node xm_pcie3_3b = { 416 .name = "xm_pcie3_3b", 417 .channels = 1, 418 .buswidth = 8, 419 .num_links = 1, 420 .link_nodes = { &qns_pcie_gem_noc }, 421 }; 422 423 static struct qcom_icc_node xm_pcie3_4 = { 424 .name = "xm_pcie3_4", 425 .channels = 1, 426 .buswidth = 8, 427 .num_links = 1, 428 .link_nodes = { &qns_pcie_gem_noc }, 429 }; 430 431 static struct qcom_icc_node xm_qdss_etr = { 432 .name = "xm_qdss_etr", 433 .channels = 1, 434 .buswidth = 8, 435 .num_links = 1, 436 .link_nodes = { &qns_a2noc_snoc }, 437 }; 438 439 static struct qcom_icc_node xm_sdc2 = { 440 .name = "xm_sdc2", 441 .channels = 1, 442 .buswidth = 8, 443 .num_links = 1, 444 .link_nodes = { &qns_a2noc_snoc }, 445 }; 446 447 static struct qcom_icc_node xm_ufs_card = { 448 .name = "xm_ufs_card", 449 .channels = 1, 450 .buswidth = 8, 451 .num_links = 1, 452 .link_nodes = { &qns_a2noc_snoc }, 453 }; 454 455 static struct qcom_icc_node qup0_core_master = { 456 .name = "qup0_core_master", 457 .channels = 1, 458 .buswidth = 4, 459 .num_links = 1, 460 .link_nodes = { &qup0_core_slave }, 461 }; 462 463 static struct qcom_icc_node qup1_core_master = { 464 .name = "qup1_core_master", 465 .channels = 1, 466 .buswidth = 4, 467 .num_links = 1, 468 .link_nodes = { &qup1_core_slave }, 469 }; 470 471 static struct qcom_icc_node qup2_core_master = { 472 .name = "qup2_core_master", 473 .channels = 1, 474 .buswidth = 4, 475 .num_links = 1, 476 .link_nodes = { &qup2_core_slave }, 477 }; 478 479 static struct qcom_icc_node qnm_gemnoc_cnoc = { 480 .name = "qnm_gemnoc_cnoc", 481 .channels = 1, 482 .buswidth = 16, 483 .num_links = 76, 484 .link_nodes = { &qhs_ahb2phy0, 485 &qhs_ahb2phy1, 486 &qhs_ahb2phy2, 487 &qhs_aoss, 488 &qhs_apss, 489 &qhs_camera_cfg, 490 &qhs_clk_ctl, 491 &qhs_compute0_cfg, 492 &qhs_compute1_cfg, 493 &qhs_cpr_cx, 494 &qhs_cpr_mmcx, 495 &qhs_cpr_mx, 496 &qhs_cpr_nspcx, 497 &qhs_crypto0_cfg, 498 &qhs_cx_rdpm, 499 &qhs_dcc_cfg, 500 &qhs_display0_cfg, 501 &qhs_display1_cfg, 502 &qhs_emac0_cfg, 503 &qhs_emac1_cfg, 504 &qhs_gpuss_cfg, 505 &qhs_hwkm, 506 &qhs_imem_cfg, 507 &qhs_ipa, 508 &qhs_ipc_router, 509 &qhs_lpass_cfg, 510 &qhs_mx_rdpm, 511 &qhs_mxc_rdpm, 512 &qhs_pcie0_cfg, 513 &qhs_pcie1_cfg, 514 &qhs_pcie2a_cfg, 515 &qhs_pcie2b_cfg, 516 &qhs_pcie3a_cfg, 517 &qhs_pcie3b_cfg, 518 &qhs_pcie4_cfg, 519 &qhs_pcie_rsc_cfg, 520 &qhs_pdm, 521 &qhs_pimem_cfg, 522 &qhs_pka_wrapper_cfg, 523 &qhs_pmu_wrapper_cfg, 524 &qhs_qdss_cfg, 525 &qhs_qspi, 526 &qhs_qup0, 527 &qhs_qup1, 528 &qhs_qup2, 529 &qhs_sdc2, 530 &qhs_sdc4, 531 &qhs_security, 532 &qhs_smmuv3_cfg, 533 &qhs_smss_cfg, 534 &qhs_spss_cfg, 535 &qhs_tcsr, 536 &qhs_tlmm, 537 &qhs_ufs_card_cfg, 538 &qhs_ufs_mem_cfg, 539 &qhs_usb3_0, 540 &qhs_usb3_1, 541 &qhs_usb3_mp, 542 &qhs_usb4_host_0, 543 &qhs_usb4_host_1, 544 &qhs_venus_cfg, 545 &qhs_vsense_ctrl_cfg, 546 &qhs_vsense_ctrl_r_cfg, 547 &qns_a1_noc_cfg, 548 &qns_a2_noc_cfg, 549 &qns_anoc_pcie_bridge_cfg, 550 &qns_ddrss_cfg, 551 &qns_mnoc_cfg, 552 &qns_snoc_cfg, 553 &qns_snoc_sf_bridge_cfg, 554 &qxs_imem, 555 &qxs_pimem, 556 &srvc_cnoc, 557 &xs_qdss_stm, 558 &xs_smss, 559 &xs_sys_tcu_cfg, 560 NULL }, 561 }; 562 563 static struct qcom_icc_node qnm_gemnoc_pcie = { 564 .name = "qnm_gemnoc_pcie", 565 .channels = 1, 566 .buswidth = 16, 567 .num_links = 7, 568 .link_nodes = { &xs_pcie_0, 569 &xs_pcie_1, 570 &xs_pcie_2a, 571 &xs_pcie_2b, 572 &xs_pcie_3a, 573 &xs_pcie_3b, 574 &xs_pcie_4 }, 575 }; 576 577 static struct qcom_icc_node qnm_cnoc_dc_noc = { 578 .name = "qnm_cnoc_dc_noc", 579 .channels = 1, 580 .buswidth = 4, 581 .num_links = 2, 582 .link_nodes = { &qhs_llcc, 583 &qns_gemnoc }, 584 }; 585 586 static struct qcom_icc_node alm_gpu_tcu = { 587 .name = "alm_gpu_tcu", 588 .channels = 1, 589 .buswidth = 8, 590 .num_links = 2, 591 .link_nodes = { &qns_gem_noc_cnoc, 592 &qns_llcc }, 593 }; 594 595 static struct qcom_icc_node alm_pcie_tcu = { 596 .name = "alm_pcie_tcu", 597 .channels = 1, 598 .buswidth = 8, 599 .num_links = 2, 600 .link_nodes = { &qns_gem_noc_cnoc, 601 &qns_llcc }, 602 }; 603 604 static struct qcom_icc_node alm_sys_tcu = { 605 .name = "alm_sys_tcu", 606 .channels = 1, 607 .buswidth = 8, 608 .num_links = 2, 609 .link_nodes = { &qns_gem_noc_cnoc, 610 &qns_llcc }, 611 }; 612 613 static struct qcom_icc_node chm_apps = { 614 .name = "chm_apps", 615 .channels = 2, 616 .buswidth = 32, 617 .num_links = 3, 618 .link_nodes = { &qns_gem_noc_cnoc, 619 &qns_llcc, 620 &qns_pcie }, 621 }; 622 623 static struct qcom_icc_node qnm_cmpnoc0 = { 624 .name = "qnm_cmpnoc0", 625 .channels = 2, 626 .buswidth = 32, 627 .num_links = 2, 628 .link_nodes = { &qns_gem_noc_cnoc, 629 &qns_llcc }, 630 }; 631 632 static struct qcom_icc_node qnm_cmpnoc1 = { 633 .name = "qnm_cmpnoc1", 634 .channels = 2, 635 .buswidth = 32, 636 .num_links = 2, 637 .link_nodes = { &qns_gem_noc_cnoc, 638 &qns_llcc }, 639 }; 640 641 static struct qcom_icc_node qnm_gemnoc_cfg = { 642 .name = "qnm_gemnoc_cfg", 643 .channels = 1, 644 .buswidth = 4, 645 .num_links = 3, 646 .link_nodes = { &srvc_even_gemnoc, 647 &srvc_odd_gemnoc, 648 &srvc_sys_gemnoc }, 649 }; 650 651 static struct qcom_icc_node qnm_gpu = { 652 .name = "qnm_gpu", 653 .channels = 4, 654 .buswidth = 32, 655 .num_links = 2, 656 .link_nodes = { &qns_gem_noc_cnoc, 657 &qns_llcc }, 658 }; 659 660 static struct qcom_icc_node qnm_mnoc_hf = { 661 .name = "qnm_mnoc_hf", 662 .channels = 2, 663 .buswidth = 32, 664 .num_links = 2, 665 .link_nodes = { &qns_llcc, 666 &qns_pcie }, 667 }; 668 669 static struct qcom_icc_node qnm_mnoc_sf = { 670 .name = "qnm_mnoc_sf", 671 .channels = 2, 672 .buswidth = 32, 673 .num_links = 2, 674 .link_nodes = { &qns_gem_noc_cnoc, 675 &qns_llcc }, 676 }; 677 678 static struct qcom_icc_node qnm_pcie = { 679 .name = "qnm_pcie", 680 .channels = 1, 681 .buswidth = 32, 682 .num_links = 2, 683 .link_nodes = { &qns_gem_noc_cnoc, 684 &qns_llcc }, 685 }; 686 687 static struct qcom_icc_node qnm_snoc_gc = { 688 .name = "qnm_snoc_gc", 689 .channels = 1, 690 .buswidth = 8, 691 .num_links = 1, 692 .link_nodes = { &qns_llcc }, 693 }; 694 695 static struct qcom_icc_node qnm_snoc_sf = { 696 .name = "qnm_snoc_sf", 697 .channels = 1, 698 .buswidth = 16, 699 .num_links = 3, 700 .link_nodes = { &qns_gem_noc_cnoc, 701 &qns_llcc, 702 &qns_pcie }, 703 }; 704 705 static struct qcom_icc_node qhm_config_noc = { 706 .name = "qhm_config_noc", 707 .channels = 1, 708 .buswidth = 4, 709 .num_links = 6, 710 .link_nodes = { &qhs_lpass_core, 711 &qhs_lpass_lpi, 712 &qhs_lpass_mpu, 713 &qhs_lpass_top, 714 &srvc_niu_aml_noc, 715 &srvc_niu_lpass_agnoc }, 716 }; 717 718 static struct qcom_icc_node qxm_lpass_dsp = { 719 .name = "qxm_lpass_dsp", 720 .channels = 1, 721 .buswidth = 8, 722 .num_links = 4, 723 .link_nodes = { &qhs_lpass_top, 724 &qns_sysnoc, 725 &srvc_niu_aml_noc, 726 &srvc_niu_lpass_agnoc }, 727 }; 728 729 static struct qcom_icc_node llcc_mc = { 730 .name = "llcc_mc", 731 .channels = 8, 732 .buswidth = 4, 733 .num_links = 1, 734 .link_nodes = { &ebi }, 735 }; 736 737 static struct qcom_icc_node qnm_camnoc_hf = { 738 .name = "qnm_camnoc_hf", 739 .channels = 2, 740 .buswidth = 32, 741 .num_links = 1, 742 .link_nodes = { &qns_mem_noc_hf }, 743 }; 744 745 static struct qcom_icc_node qnm_mdp0_0 = { 746 .name = "qnm_mdp0_0", 747 .channels = 1, 748 .buswidth = 32, 749 .num_links = 1, 750 .link_nodes = { &qns_mem_noc_hf }, 751 }; 752 753 static struct qcom_icc_node qnm_mdp0_1 = { 754 .name = "qnm_mdp0_1", 755 .channels = 1, 756 .buswidth = 32, 757 .num_links = 1, 758 .link_nodes = { &qns_mem_noc_hf }, 759 }; 760 761 static struct qcom_icc_node qnm_mdp1_0 = { 762 .name = "qnm_mdp1_0", 763 .channels = 1, 764 .buswidth = 32, 765 .num_links = 1, 766 .link_nodes = { &qns_mem_noc_hf }, 767 }; 768 769 static struct qcom_icc_node qnm_mdp1_1 = { 770 .name = "qnm_mdp1_1", 771 .channels = 1, 772 .buswidth = 32, 773 .num_links = 1, 774 .link_nodes = { &qns_mem_noc_hf }, 775 }; 776 777 static struct qcom_icc_node qnm_mnoc_cfg = { 778 .name = "qnm_mnoc_cfg", 779 .channels = 1, 780 .buswidth = 4, 781 .num_links = 1, 782 .link_nodes = { &srvc_mnoc }, 783 }; 784 785 static struct qcom_icc_node qnm_rot_0 = { 786 .name = "qnm_rot_0", 787 .channels = 1, 788 .buswidth = 32, 789 .num_links = 1, 790 .link_nodes = { &qns_mem_noc_sf }, 791 }; 792 793 static struct qcom_icc_node qnm_rot_1 = { 794 .name = "qnm_rot_1", 795 .channels = 1, 796 .buswidth = 32, 797 .num_links = 1, 798 .link_nodes = { &qns_mem_noc_sf }, 799 }; 800 801 static struct qcom_icc_node qnm_video0 = { 802 .name = "qnm_video0", 803 .channels = 1, 804 .buswidth = 32, 805 .num_links = 1, 806 .link_nodes = { &qns_mem_noc_sf }, 807 }; 808 809 static struct qcom_icc_node qnm_video1 = { 810 .name = "qnm_video1", 811 .channels = 1, 812 .buswidth = 32, 813 .num_links = 1, 814 .link_nodes = { &qns_mem_noc_sf }, 815 }; 816 817 static struct qcom_icc_node qnm_video_cvp = { 818 .name = "qnm_video_cvp", 819 .channels = 1, 820 .buswidth = 32, 821 .num_links = 1, 822 .link_nodes = { &qns_mem_noc_sf }, 823 }; 824 825 static struct qcom_icc_node qxm_camnoc_icp = { 826 .name = "qxm_camnoc_icp", 827 .channels = 1, 828 .buswidth = 8, 829 .num_links = 1, 830 .link_nodes = { &qns_mem_noc_sf }, 831 }; 832 833 static struct qcom_icc_node qxm_camnoc_sf = { 834 .name = "qxm_camnoc_sf", 835 .channels = 1, 836 .buswidth = 32, 837 .num_links = 1, 838 .link_nodes = { &qns_mem_noc_sf }, 839 }; 840 841 static struct qcom_icc_node qhm_nsp_noc_config = { 842 .name = "qhm_nsp_noc_config", 843 .channels = 1, 844 .buswidth = 4, 845 .num_links = 1, 846 .link_nodes = { &service_nsp_noc }, 847 }; 848 849 static struct qcom_icc_node qxm_nsp = { 850 .name = "qxm_nsp", 851 .channels = 2, 852 .buswidth = 32, 853 .num_links = 2, 854 .link_nodes = { &qns_nsp_gemnoc, 855 &qxs_nsp_xfr }, 856 }; 857 858 static struct qcom_icc_node qhm_nspb_noc_config = { 859 .name = "qhm_nspb_noc_config", 860 .channels = 1, 861 .buswidth = 4, 862 .num_links = 1, 863 .link_nodes = { &service_nspb_noc }, 864 }; 865 866 static struct qcom_icc_node qxm_nspb = { 867 .name = "qxm_nspb", 868 .channels = 2, 869 .buswidth = 32, 870 .num_links = 2, 871 .link_nodes = { &qns_nspb_gemnoc, 872 &qxs_nspb_xfr }, 873 }; 874 875 static struct qcom_icc_node qnm_aggre1_noc = { 876 .name = "qnm_aggre1_noc", 877 .channels = 1, 878 .buswidth = 16, 879 .num_links = 1, 880 .link_nodes = { &qns_gemnoc_sf }, 881 }; 882 883 static struct qcom_icc_node qnm_aggre2_noc = { 884 .name = "qnm_aggre2_noc", 885 .channels = 1, 886 .buswidth = 16, 887 .num_links = 1, 888 .link_nodes = { &qns_gemnoc_sf }, 889 }; 890 891 static struct qcom_icc_node qnm_aggre_usb_noc = { 892 .name = "qnm_aggre_usb_noc", 893 .channels = 1, 894 .buswidth = 16, 895 .num_links = 1, 896 .link_nodes = { &qns_gemnoc_sf }, 897 }; 898 899 static struct qcom_icc_node qnm_lpass_noc = { 900 .name = "qnm_lpass_noc", 901 .channels = 1, 902 .buswidth = 16, 903 .num_links = 1, 904 .link_nodes = { &qns_gemnoc_sf }, 905 }; 906 907 static struct qcom_icc_node qnm_snoc_cfg = { 908 .name = "qnm_snoc_cfg", 909 .channels = 1, 910 .buswidth = 4, 911 .num_links = 1, 912 .link_nodes = { &srvc_snoc }, 913 }; 914 915 static struct qcom_icc_node qxm_pimem = { 916 .name = "qxm_pimem", 917 .channels = 1, 918 .buswidth = 8, 919 .num_links = 1, 920 .link_nodes = { &qns_gemnoc_gc }, 921 }; 922 923 static struct qcom_icc_node xm_gic = { 924 .name = "xm_gic", 925 .channels = 1, 926 .buswidth = 8, 927 .num_links = 1, 928 .link_nodes = { &qns_gemnoc_gc }, 929 }; 930 931 static struct qcom_icc_node qns_a1noc_snoc = { 932 .name = "qns_a1noc_snoc", 933 .channels = 1, 934 .buswidth = 16, 935 .num_links = 1, 936 .link_nodes = { &qnm_aggre1_noc }, 937 }; 938 939 static struct qcom_icc_node qns_aggre_usb_snoc = { 940 .name = "qns_aggre_usb_snoc", 941 .channels = 1, 942 .buswidth = 16, 943 .num_links = 1, 944 .link_nodes = { &qnm_aggre_usb_noc }, 945 }; 946 947 static struct qcom_icc_node srvc_aggre1_noc = { 948 .name = "srvc_aggre1_noc", 949 .channels = 1, 950 .buswidth = 4, 951 }; 952 953 static struct qcom_icc_node qns_a2noc_snoc = { 954 .name = "qns_a2noc_snoc", 955 .channels = 1, 956 .buswidth = 16, 957 .num_links = 1, 958 .link_nodes = { &qnm_aggre2_noc }, 959 }; 960 961 static struct qcom_icc_node qns_pcie_gem_noc = { 962 .name = "qns_pcie_gem_noc", 963 .channels = 1, 964 .buswidth = 32, 965 .num_links = 1, 966 .link_nodes = { &qnm_pcie }, 967 }; 968 969 static struct qcom_icc_node srvc_aggre2_noc = { 970 .name = "srvc_aggre2_noc", 971 .channels = 1, 972 .buswidth = 4, 973 }; 974 975 static struct qcom_icc_node qup0_core_slave = { 976 .name = "qup0_core_slave", 977 .channels = 1, 978 .buswidth = 4, 979 }; 980 981 static struct qcom_icc_node qup1_core_slave = { 982 .name = "qup1_core_slave", 983 .channels = 1, 984 .buswidth = 4, 985 }; 986 987 static struct qcom_icc_node qup2_core_slave = { 988 .name = "qup2_core_slave", 989 .channels = 1, 990 .buswidth = 4, 991 }; 992 993 static struct qcom_icc_node qhs_ahb2phy0 = { 994 .name = "qhs_ahb2phy0", 995 .channels = 1, 996 .buswidth = 4, 997 }; 998 999 static struct qcom_icc_node qhs_ahb2phy1 = { 1000 .name = "qhs_ahb2phy1", 1001 .channels = 1, 1002 .buswidth = 4, 1003 }; 1004 1005 static struct qcom_icc_node qhs_ahb2phy2 = { 1006 .name = "qhs_ahb2phy2", 1007 .channels = 1, 1008 .buswidth = 4, 1009 }; 1010 1011 static struct qcom_icc_node qhs_aoss = { 1012 .name = "qhs_aoss", 1013 .channels = 1, 1014 .buswidth = 4, 1015 }; 1016 1017 static struct qcom_icc_node qhs_apss = { 1018 .name = "qhs_apss", 1019 .channels = 1, 1020 .buswidth = 8, 1021 }; 1022 1023 static struct qcom_icc_node qhs_camera_cfg = { 1024 .name = "qhs_camera_cfg", 1025 .channels = 1, 1026 .buswidth = 4, 1027 }; 1028 1029 static struct qcom_icc_node qhs_clk_ctl = { 1030 .name = "qhs_clk_ctl", 1031 .channels = 1, 1032 .buswidth = 4, 1033 }; 1034 1035 static struct qcom_icc_node qhs_compute0_cfg = { 1036 .name = "qhs_compute0_cfg", 1037 .channels = 1, 1038 .buswidth = 4, 1039 .num_links = 1, 1040 .link_nodes = { &qhm_nsp_noc_config }, 1041 }; 1042 1043 static struct qcom_icc_node qhs_compute1_cfg = { 1044 .name = "qhs_compute1_cfg", 1045 .channels = 1, 1046 .buswidth = 4, 1047 .num_links = 1, 1048 .link_nodes = { &qhm_nspb_noc_config }, 1049 }; 1050 1051 static struct qcom_icc_node qhs_cpr_cx = { 1052 .name = "qhs_cpr_cx", 1053 .channels = 1, 1054 .buswidth = 4, 1055 }; 1056 1057 static struct qcom_icc_node qhs_cpr_mmcx = { 1058 .name = "qhs_cpr_mmcx", 1059 .channels = 1, 1060 .buswidth = 4, 1061 }; 1062 1063 static struct qcom_icc_node qhs_cpr_mx = { 1064 .name = "qhs_cpr_mx", 1065 .channels = 1, 1066 .buswidth = 4, 1067 }; 1068 1069 static struct qcom_icc_node qhs_cpr_nspcx = { 1070 .name = "qhs_cpr_nspcx", 1071 .channels = 1, 1072 .buswidth = 4, 1073 }; 1074 1075 static struct qcom_icc_node qhs_crypto0_cfg = { 1076 .name = "qhs_crypto0_cfg", 1077 .channels = 1, 1078 .buswidth = 4, 1079 }; 1080 1081 static struct qcom_icc_node qhs_cx_rdpm = { 1082 .name = "qhs_cx_rdpm", 1083 .channels = 1, 1084 .buswidth = 4, 1085 }; 1086 1087 static struct qcom_icc_node qhs_dcc_cfg = { 1088 .name = "qhs_dcc_cfg", 1089 .channels = 1, 1090 .buswidth = 4, 1091 }; 1092 1093 static struct qcom_icc_node qhs_display0_cfg = { 1094 .name = "qhs_display0_cfg", 1095 .channels = 1, 1096 .buswidth = 4, 1097 }; 1098 1099 static struct qcom_icc_node qhs_display1_cfg = { 1100 .name = "qhs_display1_cfg", 1101 .channels = 1, 1102 .buswidth = 4, 1103 }; 1104 1105 static struct qcom_icc_node qhs_emac0_cfg = { 1106 .name = "qhs_emac0_cfg", 1107 .channels = 1, 1108 .buswidth = 4, 1109 }; 1110 1111 static struct qcom_icc_node qhs_emac1_cfg = { 1112 .name = "qhs_emac1_cfg", 1113 .channels = 1, 1114 .buswidth = 4, 1115 }; 1116 1117 static struct qcom_icc_node qhs_gpuss_cfg = { 1118 .name = "qhs_gpuss_cfg", 1119 .channels = 1, 1120 .buswidth = 8, 1121 }; 1122 1123 static struct qcom_icc_node qhs_hwkm = { 1124 .name = "qhs_hwkm", 1125 .channels = 1, 1126 .buswidth = 4, 1127 }; 1128 1129 static struct qcom_icc_node qhs_imem_cfg = { 1130 .name = "qhs_imem_cfg", 1131 .channels = 1, 1132 .buswidth = 4, 1133 }; 1134 1135 static struct qcom_icc_node qhs_ipa = { 1136 .name = "qhs_ipa", 1137 .channels = 1, 1138 .buswidth = 4, 1139 }; 1140 1141 static struct qcom_icc_node qhs_ipc_router = { 1142 .name = "qhs_ipc_router", 1143 .channels = 1, 1144 .buswidth = 4, 1145 }; 1146 1147 static struct qcom_icc_node qhs_lpass_cfg = { 1148 .name = "qhs_lpass_cfg", 1149 .channels = 1, 1150 .buswidth = 4, 1151 .num_links = 1, 1152 .link_nodes = { &qhm_config_noc }, 1153 }; 1154 1155 static struct qcom_icc_node qhs_mx_rdpm = { 1156 .name = "qhs_mx_rdpm", 1157 .channels = 1, 1158 .buswidth = 4, 1159 }; 1160 1161 static struct qcom_icc_node qhs_mxc_rdpm = { 1162 .name = "qhs_mxc_rdpm", 1163 .channels = 1, 1164 .buswidth = 4, 1165 }; 1166 1167 static struct qcom_icc_node qhs_pcie0_cfg = { 1168 .name = "qhs_pcie0_cfg", 1169 .channels = 1, 1170 .buswidth = 4, 1171 }; 1172 1173 static struct qcom_icc_node qhs_pcie1_cfg = { 1174 .name = "qhs_pcie1_cfg", 1175 .channels = 1, 1176 .buswidth = 4, 1177 }; 1178 1179 static struct qcom_icc_node qhs_pcie2a_cfg = { 1180 .name = "qhs_pcie2a_cfg", 1181 .channels = 1, 1182 .buswidth = 4, 1183 }; 1184 1185 static struct qcom_icc_node qhs_pcie2b_cfg = { 1186 .name = "qhs_pcie2b_cfg", 1187 .channels = 1, 1188 .buswidth = 4, 1189 }; 1190 1191 static struct qcom_icc_node qhs_pcie3a_cfg = { 1192 .name = "qhs_pcie3a_cfg", 1193 .channels = 1, 1194 .buswidth = 4, 1195 }; 1196 1197 static struct qcom_icc_node qhs_pcie3b_cfg = { 1198 .name = "qhs_pcie3b_cfg", 1199 .channels = 1, 1200 .buswidth = 4, 1201 }; 1202 1203 static struct qcom_icc_node qhs_pcie4_cfg = { 1204 .name = "qhs_pcie4_cfg", 1205 .channels = 1, 1206 .buswidth = 4, 1207 }; 1208 1209 static struct qcom_icc_node qhs_pcie_rsc_cfg = { 1210 .name = "qhs_pcie_rsc_cfg", 1211 .channels = 1, 1212 .buswidth = 4, 1213 }; 1214 1215 static struct qcom_icc_node qhs_pdm = { 1216 .name = "qhs_pdm", 1217 .channels = 1, 1218 .buswidth = 4, 1219 }; 1220 1221 static struct qcom_icc_node qhs_pimem_cfg = { 1222 .name = "qhs_pimem_cfg", 1223 .channels = 1, 1224 .buswidth = 4, 1225 }; 1226 1227 static struct qcom_icc_node qhs_pka_wrapper_cfg = { 1228 .name = "qhs_pka_wrapper_cfg", 1229 .channels = 1, 1230 .buswidth = 4, 1231 }; 1232 1233 static struct qcom_icc_node qhs_pmu_wrapper_cfg = { 1234 .name = "qhs_pmu_wrapper_cfg", 1235 .channels = 1, 1236 .buswidth = 4, 1237 }; 1238 1239 static struct qcom_icc_node qhs_qdss_cfg = { 1240 .name = "qhs_qdss_cfg", 1241 .channels = 1, 1242 .buswidth = 4, 1243 }; 1244 1245 static struct qcom_icc_node qhs_qspi = { 1246 .name = "qhs_qspi", 1247 .channels = 1, 1248 .buswidth = 4, 1249 }; 1250 1251 static struct qcom_icc_node qhs_qup0 = { 1252 .name = "qhs_qup0", 1253 .channels = 1, 1254 .buswidth = 4, 1255 }; 1256 1257 static struct qcom_icc_node qhs_qup1 = { 1258 .name = "qhs_qup1", 1259 .channels = 1, 1260 .buswidth = 4, 1261 }; 1262 1263 static struct qcom_icc_node qhs_qup2 = { 1264 .name = "qhs_qup2", 1265 .channels = 1, 1266 .buswidth = 4, 1267 }; 1268 1269 static struct qcom_icc_node qhs_sdc2 = { 1270 .name = "qhs_sdc2", 1271 .channels = 1, 1272 .buswidth = 4, 1273 }; 1274 1275 static struct qcom_icc_node qhs_sdc4 = { 1276 .name = "qhs_sdc4", 1277 .channels = 1, 1278 .buswidth = 4, 1279 }; 1280 1281 static struct qcom_icc_node qhs_security = { 1282 .name = "qhs_security", 1283 .channels = 1, 1284 .buswidth = 4, 1285 }; 1286 1287 static struct qcom_icc_node qhs_smmuv3_cfg = { 1288 .name = "qhs_smmuv3_cfg", 1289 .channels = 1, 1290 .buswidth = 8, 1291 }; 1292 1293 static struct qcom_icc_node qhs_smss_cfg = { 1294 .name = "qhs_smss_cfg", 1295 .channels = 1, 1296 .buswidth = 4, 1297 }; 1298 1299 static struct qcom_icc_node qhs_spss_cfg = { 1300 .name = "qhs_spss_cfg", 1301 .channels = 1, 1302 .buswidth = 4, 1303 }; 1304 1305 static struct qcom_icc_node qhs_tcsr = { 1306 .name = "qhs_tcsr", 1307 .channels = 1, 1308 .buswidth = 4, 1309 }; 1310 1311 static struct qcom_icc_node qhs_tlmm = { 1312 .name = "qhs_tlmm", 1313 .channels = 1, 1314 .buswidth = 4, 1315 }; 1316 1317 static struct qcom_icc_node qhs_ufs_card_cfg = { 1318 .name = "qhs_ufs_card_cfg", 1319 .channels = 1, 1320 .buswidth = 4, 1321 }; 1322 1323 static struct qcom_icc_node qhs_ufs_mem_cfg = { 1324 .name = "qhs_ufs_mem_cfg", 1325 .channels = 1, 1326 .buswidth = 4, 1327 }; 1328 1329 static struct qcom_icc_node qhs_usb3_0 = { 1330 .name = "qhs_usb3_0", 1331 .channels = 1, 1332 .buswidth = 4, 1333 }; 1334 1335 static struct qcom_icc_node qhs_usb3_1 = { 1336 .name = "qhs_usb3_1", 1337 .channels = 1, 1338 .buswidth = 4, 1339 }; 1340 1341 static struct qcom_icc_node qhs_usb3_mp = { 1342 .name = "qhs_usb3_mp", 1343 .channels = 1, 1344 .buswidth = 4, 1345 }; 1346 1347 static struct qcom_icc_node qhs_usb4_host_0 = { 1348 .name = "qhs_usb4_host_0", 1349 .channels = 1, 1350 .buswidth = 4, 1351 }; 1352 1353 static struct qcom_icc_node qhs_usb4_host_1 = { 1354 .name = "qhs_usb4_host_1", 1355 .channels = 1, 1356 .buswidth = 4, 1357 }; 1358 1359 static struct qcom_icc_node qhs_venus_cfg = { 1360 .name = "qhs_venus_cfg", 1361 .channels = 1, 1362 .buswidth = 4, 1363 }; 1364 1365 static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 1366 .name = "qhs_vsense_ctrl_cfg", 1367 .channels = 1, 1368 .buswidth = 4, 1369 }; 1370 1371 static struct qcom_icc_node qhs_vsense_ctrl_r_cfg = { 1372 .name = "qhs_vsense_ctrl_r_cfg", 1373 .channels = 1, 1374 .buswidth = 4, 1375 }; 1376 1377 static struct qcom_icc_node qns_a1_noc_cfg = { 1378 .name = "qns_a1_noc_cfg", 1379 .channels = 1, 1380 .buswidth = 4, 1381 .num_links = 1, 1382 .link_nodes = { &qnm_a1noc_cfg }, 1383 }; 1384 1385 static struct qcom_icc_node qns_a2_noc_cfg = { 1386 .name = "qns_a2_noc_cfg", 1387 .channels = 1, 1388 .buswidth = 4, 1389 .num_links = 1, 1390 .link_nodes = { &qnm_a2noc_cfg }, 1391 }; 1392 1393 static struct qcom_icc_node qns_anoc_pcie_bridge_cfg = { 1394 .name = "qns_anoc_pcie_bridge_cfg", 1395 .channels = 1, 1396 .buswidth = 4, 1397 }; 1398 1399 static struct qcom_icc_node qns_ddrss_cfg = { 1400 .name = "qns_ddrss_cfg", 1401 .channels = 1, 1402 .buswidth = 4, 1403 .num_links = 1, 1404 .link_nodes = { &qnm_cnoc_dc_noc }, 1405 }; 1406 1407 static struct qcom_icc_node qns_mnoc_cfg = { 1408 .name = "qns_mnoc_cfg", 1409 .channels = 1, 1410 .buswidth = 4, 1411 .num_links = 1, 1412 .link_nodes = { &qnm_mnoc_cfg }, 1413 }; 1414 1415 static struct qcom_icc_node qns_snoc_cfg = { 1416 .name = "qns_snoc_cfg", 1417 .channels = 1, 1418 .buswidth = 4, 1419 .num_links = 1, 1420 .link_nodes = { &qnm_snoc_cfg }, 1421 }; 1422 1423 static struct qcom_icc_node qns_snoc_sf_bridge_cfg = { 1424 .name = "qns_snoc_sf_bridge_cfg", 1425 .channels = 1, 1426 .buswidth = 4, 1427 }; 1428 1429 static struct qcom_icc_node qxs_imem = { 1430 .name = "qxs_imem", 1431 .channels = 1, 1432 .buswidth = 8, 1433 }; 1434 1435 static struct qcom_icc_node qxs_pimem = { 1436 .name = "qxs_pimem", 1437 .channels = 1, 1438 .buswidth = 8, 1439 }; 1440 1441 static struct qcom_icc_node srvc_cnoc = { 1442 .name = "srvc_cnoc", 1443 .channels = 1, 1444 .buswidth = 4, 1445 }; 1446 1447 static struct qcom_icc_node xs_pcie_0 = { 1448 .name = "xs_pcie_0", 1449 .channels = 1, 1450 .buswidth = 16, 1451 }; 1452 1453 static struct qcom_icc_node xs_pcie_1 = { 1454 .name = "xs_pcie_1", 1455 .channels = 1, 1456 .buswidth = 16, 1457 }; 1458 1459 static struct qcom_icc_node xs_pcie_2a = { 1460 .name = "xs_pcie_2a", 1461 .channels = 1, 1462 .buswidth = 16, 1463 }; 1464 1465 static struct qcom_icc_node xs_pcie_2b = { 1466 .name = "xs_pcie_2b", 1467 .channels = 1, 1468 .buswidth = 8, 1469 }; 1470 1471 static struct qcom_icc_node xs_pcie_3a = { 1472 .name = "xs_pcie_3a", 1473 .channels = 1, 1474 .buswidth = 16, 1475 }; 1476 1477 static struct qcom_icc_node xs_pcie_3b = { 1478 .name = "xs_pcie_3b", 1479 .channels = 1, 1480 .buswidth = 8, 1481 }; 1482 1483 static struct qcom_icc_node xs_pcie_4 = { 1484 .name = "xs_pcie_4", 1485 .channels = 1, 1486 .buswidth = 8, 1487 }; 1488 1489 static struct qcom_icc_node xs_qdss_stm = { 1490 .name = "xs_qdss_stm", 1491 .channels = 1, 1492 .buswidth = 4, 1493 }; 1494 1495 static struct qcom_icc_node xs_smss = { 1496 .name = "xs_smss", 1497 .channels = 1, 1498 .buswidth = 8, 1499 }; 1500 1501 static struct qcom_icc_node xs_sys_tcu_cfg = { 1502 .name = "xs_sys_tcu_cfg", 1503 .channels = 1, 1504 .buswidth = 8, 1505 }; 1506 1507 static struct qcom_icc_node qhs_llcc = { 1508 .name = "qhs_llcc", 1509 .channels = 1, 1510 .buswidth = 4, 1511 }; 1512 1513 static struct qcom_icc_node qns_gemnoc = { 1514 .name = "qns_gemnoc", 1515 .channels = 1, 1516 .buswidth = 4, 1517 .num_links = 1, 1518 .link_nodes = { &qnm_gemnoc_cfg }, 1519 }; 1520 1521 static struct qcom_icc_node qns_gem_noc_cnoc = { 1522 .name = "qns_gem_noc_cnoc", 1523 .channels = 1, 1524 .buswidth = 16, 1525 .num_links = 1, 1526 .link_nodes = { &qnm_gemnoc_cnoc }, 1527 }; 1528 1529 static struct qcom_icc_node qns_llcc = { 1530 .name = "qns_llcc", 1531 .channels = 8, 1532 .buswidth = 16, 1533 .num_links = 1, 1534 .link_nodes = { &llcc_mc }, 1535 }; 1536 1537 static struct qcom_icc_node qns_pcie = { 1538 .name = "qns_pcie", 1539 .channels = 1, 1540 .buswidth = 16, 1541 .num_links = 1, 1542 .link_nodes = { &qnm_gemnoc_pcie }, 1543 }; 1544 1545 static struct qcom_icc_node srvc_even_gemnoc = { 1546 .name = "srvc_even_gemnoc", 1547 .channels = 1, 1548 .buswidth = 4, 1549 }; 1550 1551 static struct qcom_icc_node srvc_odd_gemnoc = { 1552 .name = "srvc_odd_gemnoc", 1553 .channels = 1, 1554 .buswidth = 4, 1555 }; 1556 1557 static struct qcom_icc_node srvc_sys_gemnoc = { 1558 .name = "srvc_sys_gemnoc", 1559 .channels = 1, 1560 .buswidth = 4, 1561 }; 1562 1563 static struct qcom_icc_node qhs_lpass_core = { 1564 .name = "qhs_lpass_core", 1565 .channels = 1, 1566 .buswidth = 4, 1567 }; 1568 1569 static struct qcom_icc_node qhs_lpass_lpi = { 1570 .name = "qhs_lpass_lpi", 1571 .channels = 1, 1572 .buswidth = 4, 1573 }; 1574 1575 static struct qcom_icc_node qhs_lpass_mpu = { 1576 .name = "qhs_lpass_mpu", 1577 .channels = 1, 1578 .buswidth = 4, 1579 }; 1580 1581 static struct qcom_icc_node qhs_lpass_top = { 1582 .name = "qhs_lpass_top", 1583 .channels = 1, 1584 .buswidth = 4, 1585 }; 1586 1587 static struct qcom_icc_node qns_sysnoc = { 1588 .name = "qns_sysnoc", 1589 .channels = 1, 1590 .buswidth = 16, 1591 .num_links = 1, 1592 .link_nodes = { &qnm_lpass_noc }, 1593 }; 1594 1595 static struct qcom_icc_node srvc_niu_aml_noc = { 1596 .name = "srvc_niu_aml_noc", 1597 .channels = 1, 1598 .buswidth = 4, 1599 }; 1600 1601 static struct qcom_icc_node srvc_niu_lpass_agnoc = { 1602 .name = "srvc_niu_lpass_agnoc", 1603 .channels = 1, 1604 .buswidth = 4, 1605 }; 1606 1607 static struct qcom_icc_node ebi = { 1608 .name = "ebi", 1609 .channels = 8, 1610 .buswidth = 4, 1611 }; 1612 1613 static struct qcom_icc_node qns_mem_noc_hf = { 1614 .name = "qns_mem_noc_hf", 1615 .channels = 2, 1616 .buswidth = 32, 1617 .num_links = 1, 1618 .link_nodes = { &qnm_mnoc_hf }, 1619 }; 1620 1621 static struct qcom_icc_node qns_mem_noc_sf = { 1622 .name = "qns_mem_noc_sf", 1623 .channels = 2, 1624 .buswidth = 32, 1625 .num_links = 1, 1626 .link_nodes = { &qnm_mnoc_sf }, 1627 }; 1628 1629 static struct qcom_icc_node srvc_mnoc = { 1630 .name = "srvc_mnoc", 1631 .channels = 1, 1632 .buswidth = 4, 1633 }; 1634 1635 static struct qcom_icc_node qns_nsp_gemnoc = { 1636 .name = "qns_nsp_gemnoc", 1637 .channels = 2, 1638 .buswidth = 32, 1639 .num_links = 1, 1640 .link_nodes = { &qnm_cmpnoc0 }, 1641 }; 1642 1643 static struct qcom_icc_node qxs_nsp_xfr = { 1644 .name = "qxs_nsp_xfr", 1645 .channels = 1, 1646 .buswidth = 32, 1647 }; 1648 1649 static struct qcom_icc_node service_nsp_noc = { 1650 .name = "service_nsp_noc", 1651 .channels = 1, 1652 .buswidth = 4, 1653 }; 1654 1655 static struct qcom_icc_node qns_nspb_gemnoc = { 1656 .name = "qns_nspb_gemnoc", 1657 .channels = 2, 1658 .buswidth = 32, 1659 .num_links = 1, 1660 .link_nodes = { &qnm_cmpnoc1 }, 1661 }; 1662 1663 static struct qcom_icc_node qxs_nspb_xfr = { 1664 .name = "qxs_nspb_xfr", 1665 .channels = 1, 1666 .buswidth = 32, 1667 }; 1668 1669 static struct qcom_icc_node service_nspb_noc = { 1670 .name = "service_nspb_noc", 1671 .channels = 1, 1672 .buswidth = 4, 1673 }; 1674 1675 static struct qcom_icc_node qns_gemnoc_gc = { 1676 .name = "qns_gemnoc_gc", 1677 .channels = 1, 1678 .buswidth = 8, 1679 .num_links = 1, 1680 .link_nodes = { &qnm_snoc_gc }, 1681 }; 1682 1683 static struct qcom_icc_node qns_gemnoc_sf = { 1684 .name = "qns_gemnoc_sf", 1685 .channels = 1, 1686 .buswidth = 16, 1687 .num_links = 1, 1688 .link_nodes = { &qnm_snoc_sf }, 1689 }; 1690 1691 static struct qcom_icc_node srvc_snoc = { 1692 .name = "srvc_snoc", 1693 .channels = 1, 1694 .buswidth = 4, 1695 }; 1696 1697 static struct qcom_icc_bcm bcm_acv = { 1698 .name = "ACV", 1699 .enable_mask = BIT(3), 1700 .num_nodes = 1, 1701 .nodes = { &ebi }, 1702 }; 1703 1704 static struct qcom_icc_bcm bcm_ce0 = { 1705 .name = "CE0", 1706 .num_nodes = 1, 1707 .nodes = { &qxm_crypto }, 1708 }; 1709 1710 static struct qcom_icc_bcm bcm_cn0 = { 1711 .name = "CN0", 1712 .keepalive = true, 1713 .num_nodes = 9, 1714 .nodes = { &qnm_gemnoc_cnoc, 1715 &qnm_gemnoc_pcie, 1716 &xs_pcie_0, 1717 &xs_pcie_1, 1718 &xs_pcie_2a, 1719 &xs_pcie_2b, 1720 &xs_pcie_3a, 1721 &xs_pcie_3b, 1722 &xs_pcie_4 1723 }, 1724 }; 1725 1726 static struct qcom_icc_bcm bcm_cn1 = { 1727 .name = "CN1", 1728 .num_nodes = 67, 1729 .nodes = { &qhs_ahb2phy0, 1730 &qhs_ahb2phy1, 1731 &qhs_ahb2phy2, 1732 &qhs_aoss, 1733 &qhs_apss, 1734 &qhs_camera_cfg, 1735 &qhs_clk_ctl, 1736 &qhs_compute0_cfg, 1737 &qhs_compute1_cfg, 1738 &qhs_cpr_cx, 1739 &qhs_cpr_mmcx, 1740 &qhs_cpr_mx, 1741 &qhs_cpr_nspcx, 1742 &qhs_crypto0_cfg, 1743 &qhs_cx_rdpm, 1744 &qhs_dcc_cfg, 1745 &qhs_display0_cfg, 1746 &qhs_display1_cfg, 1747 &qhs_emac0_cfg, 1748 &qhs_emac1_cfg, 1749 &qhs_gpuss_cfg, 1750 &qhs_hwkm, 1751 &qhs_imem_cfg, 1752 &qhs_ipa, 1753 &qhs_ipc_router, 1754 &qhs_lpass_cfg, 1755 &qhs_mx_rdpm, 1756 &qhs_mxc_rdpm, 1757 &qhs_pcie0_cfg, 1758 &qhs_pcie1_cfg, 1759 &qhs_pcie2a_cfg, 1760 &qhs_pcie2b_cfg, 1761 &qhs_pcie3a_cfg, 1762 &qhs_pcie3b_cfg, 1763 &qhs_pcie4_cfg, 1764 &qhs_pcie_rsc_cfg, 1765 &qhs_pdm, 1766 &qhs_pimem_cfg, 1767 &qhs_pka_wrapper_cfg, 1768 &qhs_pmu_wrapper_cfg, 1769 &qhs_qdss_cfg, 1770 &qhs_sdc2, 1771 &qhs_sdc4, 1772 &qhs_security, 1773 &qhs_smmuv3_cfg, 1774 &qhs_smss_cfg, 1775 &qhs_spss_cfg, 1776 &qhs_tcsr, 1777 &qhs_tlmm, 1778 &qhs_ufs_card_cfg, 1779 &qhs_ufs_mem_cfg, 1780 &qhs_usb3_0, 1781 &qhs_usb3_1, 1782 &qhs_usb3_mp, 1783 &qhs_usb4_host_0, 1784 &qhs_usb4_host_1, 1785 &qhs_venus_cfg, 1786 &qhs_vsense_ctrl_cfg, 1787 &qhs_vsense_ctrl_r_cfg, 1788 &qns_a1_noc_cfg, 1789 &qns_a2_noc_cfg, 1790 &qns_anoc_pcie_bridge_cfg, 1791 &qns_ddrss_cfg, 1792 &qns_mnoc_cfg, 1793 &qns_snoc_cfg, 1794 &qns_snoc_sf_bridge_cfg, 1795 &srvc_cnoc 1796 }, 1797 }; 1798 1799 static struct qcom_icc_bcm bcm_cn2 = { 1800 .name = "CN2", 1801 .num_nodes = 4, 1802 .nodes = { &qhs_qspi, 1803 &qhs_qup0, 1804 &qhs_qup1, 1805 &qhs_qup2 1806 }, 1807 }; 1808 1809 static struct qcom_icc_bcm bcm_cn3 = { 1810 .name = "CN3", 1811 .num_nodes = 3, 1812 .nodes = { &qxs_imem, 1813 &xs_smss, 1814 &xs_sys_tcu_cfg 1815 }, 1816 }; 1817 1818 static struct qcom_icc_bcm bcm_mc0 = { 1819 .name = "MC0", 1820 .keepalive = true, 1821 .num_nodes = 1, 1822 .nodes = { &ebi }, 1823 }; 1824 1825 static struct qcom_icc_bcm bcm_mm0 = { 1826 .name = "MM0", 1827 .keepalive = true, 1828 .num_nodes = 5, 1829 .nodes = { &qnm_camnoc_hf, 1830 &qnm_mdp0_0, 1831 &qnm_mdp0_1, 1832 &qnm_mdp1_0, 1833 &qns_mem_noc_hf 1834 }, 1835 }; 1836 1837 static struct qcom_icc_bcm bcm_mm1 = { 1838 .name = "MM1", 1839 .num_nodes = 8, 1840 .nodes = { &qnm_rot_0, 1841 &qnm_rot_1, 1842 &qnm_video0, 1843 &qnm_video1, 1844 &qnm_video_cvp, 1845 &qxm_camnoc_icp, 1846 &qxm_camnoc_sf, 1847 &qns_mem_noc_sf 1848 }, 1849 }; 1850 1851 static struct qcom_icc_bcm bcm_nsa0 = { 1852 .name = "NSA0", 1853 .num_nodes = 2, 1854 .nodes = { &qns_nsp_gemnoc, 1855 &qxs_nsp_xfr 1856 }, 1857 }; 1858 1859 static struct qcom_icc_bcm bcm_nsa1 = { 1860 .name = "NSA1", 1861 .num_nodes = 1, 1862 .nodes = { &qxm_nsp }, 1863 }; 1864 1865 static struct qcom_icc_bcm bcm_nsb0 = { 1866 .name = "NSB0", 1867 .num_nodes = 2, 1868 .nodes = { &qns_nspb_gemnoc, 1869 &qxs_nspb_xfr 1870 }, 1871 }; 1872 1873 static struct qcom_icc_bcm bcm_nsb1 = { 1874 .name = "NSB1", 1875 .num_nodes = 1, 1876 .nodes = { &qxm_nspb }, 1877 }; 1878 1879 static struct qcom_icc_bcm bcm_pci0 = { 1880 .name = "PCI0", 1881 .num_nodes = 1, 1882 .nodes = { &qns_pcie_gem_noc }, 1883 }; 1884 1885 static struct qcom_icc_bcm bcm_qup0 = { 1886 .name = "QUP0", 1887 .vote_scale = 1, 1888 .num_nodes = 1, 1889 .nodes = { &qup0_core_slave }, 1890 }; 1891 1892 static struct qcom_icc_bcm bcm_qup1 = { 1893 .name = "QUP1", 1894 .vote_scale = 1, 1895 .num_nodes = 1, 1896 .nodes = { &qup1_core_slave }, 1897 }; 1898 1899 static struct qcom_icc_bcm bcm_qup2 = { 1900 .name = "QUP2", 1901 .vote_scale = 1, 1902 .num_nodes = 1, 1903 .nodes = { &qup2_core_slave }, 1904 }; 1905 1906 static struct qcom_icc_bcm bcm_sh0 = { 1907 .name = "SH0", 1908 .keepalive = true, 1909 .num_nodes = 1, 1910 .nodes = { &qns_llcc }, 1911 }; 1912 1913 static struct qcom_icc_bcm bcm_sh2 = { 1914 .name = "SH2", 1915 .num_nodes = 1, 1916 .nodes = { &chm_apps }, 1917 }; 1918 1919 static struct qcom_icc_bcm bcm_sn0 = { 1920 .name = "SN0", 1921 .keepalive = true, 1922 .num_nodes = 1, 1923 .nodes = { &qns_gemnoc_sf }, 1924 }; 1925 1926 static struct qcom_icc_bcm bcm_sn1 = { 1927 .name = "SN1", 1928 .num_nodes = 1, 1929 .nodes = { &qns_gemnoc_gc }, 1930 }; 1931 1932 static struct qcom_icc_bcm bcm_sn2 = { 1933 .name = "SN2", 1934 .num_nodes = 1, 1935 .nodes = { &qxs_pimem }, 1936 }; 1937 1938 static struct qcom_icc_bcm bcm_sn3 = { 1939 .name = "SN3", 1940 .num_nodes = 2, 1941 .nodes = { &qns_a1noc_snoc, 1942 &qnm_aggre1_noc 1943 }, 1944 }; 1945 1946 static struct qcom_icc_bcm bcm_sn4 = { 1947 .name = "SN4", 1948 .num_nodes = 2, 1949 .nodes = { &qns_a2noc_snoc, 1950 &qnm_aggre2_noc 1951 }, 1952 }; 1953 1954 static struct qcom_icc_bcm bcm_sn5 = { 1955 .name = "SN5", 1956 .num_nodes = 2, 1957 .nodes = { &qns_aggre_usb_snoc, 1958 &qnm_aggre_usb_noc 1959 }, 1960 }; 1961 1962 static struct qcom_icc_bcm bcm_sn9 = { 1963 .name = "SN9", 1964 .num_nodes = 2, 1965 .nodes = { &qns_sysnoc, 1966 &qnm_lpass_noc 1967 }, 1968 }; 1969 1970 static struct qcom_icc_bcm bcm_sn10 = { 1971 .name = "SN10", 1972 .num_nodes = 1, 1973 .nodes = { &xs_qdss_stm }, 1974 }; 1975 1976 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 1977 &bcm_sn3, 1978 &bcm_sn5, 1979 }; 1980 1981 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1982 [MASTER_QSPI_0] = &qhm_qspi, 1983 [MASTER_QUP_1] = &qhm_qup1, 1984 [MASTER_QUP_2] = &qhm_qup2, 1985 [MASTER_A1NOC_CFG] = &qnm_a1noc_cfg, 1986 [MASTER_IPA] = &qxm_ipa, 1987 [MASTER_EMAC_1] = &xm_emac_1, 1988 [MASTER_SDCC_4] = &xm_sdc4, 1989 [MASTER_UFS_MEM] = &xm_ufs_mem, 1990 [MASTER_USB3_0] = &xm_usb3_0, 1991 [MASTER_USB3_1] = &xm_usb3_1, 1992 [MASTER_USB3_MP] = &xm_usb3_mp, 1993 [MASTER_USB4_0] = &xm_usb4_host0, 1994 [MASTER_USB4_1] = &xm_usb4_host1, 1995 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, 1996 [SLAVE_USB_NOC_SNOC] = &qns_aggre_usb_snoc, 1997 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, 1998 }; 1999 2000 static const struct qcom_icc_desc sc8280xp_aggre1_noc = { 2001 .nodes = aggre1_noc_nodes, 2002 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 2003 .bcms = aggre1_noc_bcms, 2004 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 2005 }; 2006 2007 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 2008 &bcm_ce0, 2009 &bcm_pci0, 2010 &bcm_sn4, 2011 }; 2012 2013 static struct qcom_icc_node * const aggre2_noc_nodes[] = { 2014 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 2015 [MASTER_QUP_0] = &qhm_qup0, 2016 [MASTER_A2NOC_CFG] = &qnm_a2noc_cfg, 2017 [MASTER_CRYPTO] = &qxm_crypto, 2018 [MASTER_SENSORS_PROC] = &qxm_sensorss_q6, 2019 [MASTER_SP] = &qxm_sp, 2020 [MASTER_EMAC] = &xm_emac_0, 2021 [MASTER_PCIE_0] = &xm_pcie3_0, 2022 [MASTER_PCIE_1] = &xm_pcie3_1, 2023 [MASTER_PCIE_2A] = &xm_pcie3_2a, 2024 [MASTER_PCIE_2B] = &xm_pcie3_2b, 2025 [MASTER_PCIE_3A] = &xm_pcie3_3a, 2026 [MASTER_PCIE_3B] = &xm_pcie3_3b, 2027 [MASTER_PCIE_4] = &xm_pcie3_4, 2028 [MASTER_QDSS_ETR] = &xm_qdss_etr, 2029 [MASTER_SDCC_2] = &xm_sdc2, 2030 [MASTER_UFS_CARD] = &xm_ufs_card, 2031 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, 2032 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_gem_noc, 2033 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, 2034 }; 2035 2036 static const struct qcom_icc_desc sc8280xp_aggre2_noc = { 2037 .nodes = aggre2_noc_nodes, 2038 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 2039 .bcms = aggre2_noc_bcms, 2040 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 2041 }; 2042 2043 static struct qcom_icc_bcm * const clk_virt_bcms[] = { 2044 &bcm_qup0, 2045 &bcm_qup1, 2046 &bcm_qup2, 2047 }; 2048 2049 static struct qcom_icc_node * const clk_virt_nodes[] = { 2050 [MASTER_QUP_CORE_0] = &qup0_core_master, 2051 [MASTER_QUP_CORE_1] = &qup1_core_master, 2052 [MASTER_QUP_CORE_2] = &qup2_core_master, 2053 [SLAVE_QUP_CORE_0] = &qup0_core_slave, 2054 [SLAVE_QUP_CORE_1] = &qup1_core_slave, 2055 [SLAVE_QUP_CORE_2] = &qup2_core_slave, 2056 }; 2057 2058 static const struct qcom_icc_desc sc8280xp_clk_virt = { 2059 .nodes = clk_virt_nodes, 2060 .num_nodes = ARRAY_SIZE(clk_virt_nodes), 2061 .bcms = clk_virt_bcms, 2062 .num_bcms = ARRAY_SIZE(clk_virt_bcms), 2063 }; 2064 2065 static struct qcom_icc_bcm * const config_noc_bcms[] = { 2066 &bcm_cn0, 2067 &bcm_cn1, 2068 &bcm_cn2, 2069 &bcm_cn3, 2070 &bcm_sn2, 2071 &bcm_sn10, 2072 }; 2073 2074 static struct qcom_icc_node * const config_noc_nodes[] = { 2075 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, 2076 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, 2077 [SLAVE_AHB2PHY_0] = &qhs_ahb2phy0, 2078 [SLAVE_AHB2PHY_1] = &qhs_ahb2phy1, 2079 [SLAVE_AHB2PHY_2] = &qhs_ahb2phy2, 2080 [SLAVE_AOSS] = &qhs_aoss, 2081 [SLAVE_APPSS] = &qhs_apss, 2082 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 2083 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 2084 [SLAVE_CDSP_CFG] = &qhs_compute0_cfg, 2085 [SLAVE_CDSP1_CFG] = &qhs_compute1_cfg, 2086 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 2087 [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx, 2088 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, 2089 [SLAVE_CPR_NSPCX] = &qhs_cpr_nspcx, 2090 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 2091 [SLAVE_CX_RDPM] = &qhs_cx_rdpm, 2092 [SLAVE_DCC_CFG] = &qhs_dcc_cfg, 2093 [SLAVE_DISPLAY_CFG] = &qhs_display0_cfg, 2094 [SLAVE_DISPLAY1_CFG] = &qhs_display1_cfg, 2095 [SLAVE_EMAC_CFG] = &qhs_emac0_cfg, 2096 [SLAVE_EMAC1_CFG] = &qhs_emac1_cfg, 2097 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, 2098 [SLAVE_HWKM] = &qhs_hwkm, 2099 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 2100 [SLAVE_IPA_CFG] = &qhs_ipa, 2101 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, 2102 [SLAVE_LPASS] = &qhs_lpass_cfg, 2103 [SLAVE_MX_RDPM] = &qhs_mx_rdpm, 2104 [SLAVE_MXC_RDPM] = &qhs_mxc_rdpm, 2105 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, 2106 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, 2107 [SLAVE_PCIE_2A_CFG] = &qhs_pcie2a_cfg, 2108 [SLAVE_PCIE_2B_CFG] = &qhs_pcie2b_cfg, 2109 [SLAVE_PCIE_3A_CFG] = &qhs_pcie3a_cfg, 2110 [SLAVE_PCIE_3B_CFG] = &qhs_pcie3b_cfg, 2111 [SLAVE_PCIE_4_CFG] = &qhs_pcie4_cfg, 2112 [SLAVE_PCIE_RSC_CFG] = &qhs_pcie_rsc_cfg, 2113 [SLAVE_PDM] = &qhs_pdm, 2114 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 2115 [SLAVE_PKA_WRAPPER_CFG] = &qhs_pka_wrapper_cfg, 2116 [SLAVE_PMU_WRAPPER_CFG] = &qhs_pmu_wrapper_cfg, 2117 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 2118 [SLAVE_QSPI_0] = &qhs_qspi, 2119 [SLAVE_QUP_0] = &qhs_qup0, 2120 [SLAVE_QUP_1] = &qhs_qup1, 2121 [SLAVE_QUP_2] = &qhs_qup2, 2122 [SLAVE_SDCC_2] = &qhs_sdc2, 2123 [SLAVE_SDCC_4] = &qhs_sdc4, 2124 [SLAVE_SECURITY] = &qhs_security, 2125 [SLAVE_SMMUV3_CFG] = &qhs_smmuv3_cfg, 2126 [SLAVE_SMSS_CFG] = &qhs_smss_cfg, 2127 [SLAVE_SPSS_CFG] = &qhs_spss_cfg, 2128 [SLAVE_TCSR] = &qhs_tcsr, 2129 [SLAVE_TLMM] = &qhs_tlmm, 2130 [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg, 2131 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 2132 [SLAVE_USB3_0] = &qhs_usb3_0, 2133 [SLAVE_USB3_1] = &qhs_usb3_1, 2134 [SLAVE_USB3_MP] = &qhs_usb3_mp, 2135 [SLAVE_USB4_0] = &qhs_usb4_host_0, 2136 [SLAVE_USB4_1] = &qhs_usb4_host_1, 2137 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 2138 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 2139 [SLAVE_VSENSE_CTRL_R_CFG] = &qhs_vsense_ctrl_r_cfg, 2140 [SLAVE_A1NOC_CFG] = &qns_a1_noc_cfg, 2141 [SLAVE_A2NOC_CFG] = &qns_a2_noc_cfg, 2142 [SLAVE_ANOC_PCIE_BRIDGE_CFG] = &qns_anoc_pcie_bridge_cfg, 2143 [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg, 2144 [SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg, 2145 [SLAVE_SNOC_CFG] = &qns_snoc_cfg, 2146 [SLAVE_SNOC_SF_BRIDGE_CFG] = &qns_snoc_sf_bridge_cfg, 2147 [SLAVE_IMEM] = &qxs_imem, 2148 [SLAVE_PIMEM] = &qxs_pimem, 2149 [SLAVE_SERVICE_CNOC] = &srvc_cnoc, 2150 [SLAVE_PCIE_0] = &xs_pcie_0, 2151 [SLAVE_PCIE_1] = &xs_pcie_1, 2152 [SLAVE_PCIE_2A] = &xs_pcie_2a, 2153 [SLAVE_PCIE_2B] = &xs_pcie_2b, 2154 [SLAVE_PCIE_3A] = &xs_pcie_3a, 2155 [SLAVE_PCIE_3B] = &xs_pcie_3b, 2156 [SLAVE_PCIE_4] = &xs_pcie_4, 2157 [SLAVE_QDSS_STM] = &xs_qdss_stm, 2158 [SLAVE_SMSS] = &xs_smss, 2159 [SLAVE_TCU] = &xs_sys_tcu_cfg, 2160 }; 2161 2162 static const struct qcom_icc_desc sc8280xp_config_noc = { 2163 .nodes = config_noc_nodes, 2164 .num_nodes = ARRAY_SIZE(config_noc_nodes), 2165 .bcms = config_noc_bcms, 2166 .num_bcms = ARRAY_SIZE(config_noc_bcms), 2167 }; 2168 2169 static struct qcom_icc_bcm * const dc_noc_bcms[] = { 2170 }; 2171 2172 static struct qcom_icc_node * const dc_noc_nodes[] = { 2173 [MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc, 2174 [SLAVE_LLCC_CFG] = &qhs_llcc, 2175 [SLAVE_GEM_NOC_CFG] = &qns_gemnoc, 2176 }; 2177 2178 static const struct qcom_icc_desc sc8280xp_dc_noc = { 2179 .nodes = dc_noc_nodes, 2180 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 2181 .bcms = dc_noc_bcms, 2182 .num_bcms = ARRAY_SIZE(dc_noc_bcms), 2183 }; 2184 2185 static struct qcom_icc_bcm * const gem_noc_bcms[] = { 2186 &bcm_sh0, 2187 &bcm_sh2, 2188 }; 2189 2190 static struct qcom_icc_node * const gem_noc_nodes[] = { 2191 [MASTER_GPU_TCU] = &alm_gpu_tcu, 2192 [MASTER_PCIE_TCU] = &alm_pcie_tcu, 2193 [MASTER_SYS_TCU] = &alm_sys_tcu, 2194 [MASTER_APPSS_PROC] = &chm_apps, 2195 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc0, 2196 [MASTER_COMPUTE_NOC_1] = &qnm_cmpnoc1, 2197 [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg, 2198 [MASTER_GFX3D] = &qnm_gpu, 2199 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 2200 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 2201 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, 2202 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 2203 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 2204 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, 2205 [SLAVE_LLCC] = &qns_llcc, 2206 [SLAVE_GEM_NOC_PCIE_CNOC] = &qns_pcie, 2207 [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc, 2208 [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc, 2209 [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc, 2210 }; 2211 2212 static const struct qcom_icc_desc sc8280xp_gem_noc = { 2213 .nodes = gem_noc_nodes, 2214 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 2215 .bcms = gem_noc_bcms, 2216 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 2217 }; 2218 2219 static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = { 2220 &bcm_sn9, 2221 }; 2222 2223 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { 2224 [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc, 2225 [MASTER_LPASS_PROC] = &qxm_lpass_dsp, 2226 [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core, 2227 [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi, 2228 [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu, 2229 [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top, 2230 [SLAVE_LPASS_SNOC] = &qns_sysnoc, 2231 [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc, 2232 [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, 2233 }; 2234 2235 static const struct qcom_icc_desc sc8280xp_lpass_ag_noc = { 2236 .nodes = lpass_ag_noc_nodes, 2237 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), 2238 .bcms = lpass_ag_noc_bcms, 2239 .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms), 2240 }; 2241 2242 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 2243 &bcm_acv, 2244 &bcm_mc0, 2245 }; 2246 2247 static struct qcom_icc_node * const mc_virt_nodes[] = { 2248 [MASTER_LLCC] = &llcc_mc, 2249 [SLAVE_EBI1] = &ebi, 2250 }; 2251 2252 static const struct qcom_icc_desc sc8280xp_mc_virt = { 2253 .nodes = mc_virt_nodes, 2254 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 2255 .bcms = mc_virt_bcms, 2256 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 2257 }; 2258 2259 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 2260 &bcm_mm0, 2261 &bcm_mm1, 2262 }; 2263 2264 static struct qcom_icc_node * const mmss_noc_nodes[] = { 2265 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, 2266 [MASTER_MDP0] = &qnm_mdp0_0, 2267 [MASTER_MDP1] = &qnm_mdp0_1, 2268 [MASTER_MDP_CORE1_0] = &qnm_mdp1_0, 2269 [MASTER_MDP_CORE1_1] = &qnm_mdp1_1, 2270 [MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg, 2271 [MASTER_ROTATOR] = &qnm_rot_0, 2272 [MASTER_ROTATOR_1] = &qnm_rot_1, 2273 [MASTER_VIDEO_P0] = &qnm_video0, 2274 [MASTER_VIDEO_P1] = &qnm_video1, 2275 [MASTER_VIDEO_PROC] = &qnm_video_cvp, 2276 [MASTER_CAMNOC_ICP] = &qxm_camnoc_icp, 2277 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf, 2278 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 2279 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, 2280 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 2281 }; 2282 2283 static const struct qcom_icc_desc sc8280xp_mmss_noc = { 2284 .nodes = mmss_noc_nodes, 2285 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 2286 .bcms = mmss_noc_bcms, 2287 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 2288 }; 2289 2290 static struct qcom_icc_bcm * const nspa_noc_bcms[] = { 2291 &bcm_nsa0, 2292 &bcm_nsa1, 2293 }; 2294 2295 static struct qcom_icc_node * const nspa_noc_nodes[] = { 2296 [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config, 2297 [MASTER_CDSP_PROC] = &qxm_nsp, 2298 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, 2299 [SLAVE_NSP_XFR] = &qxs_nsp_xfr, 2300 [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, 2301 }; 2302 2303 static const struct qcom_icc_desc sc8280xp_nspa_noc = { 2304 .nodes = nspa_noc_nodes, 2305 .num_nodes = ARRAY_SIZE(nspa_noc_nodes), 2306 .bcms = nspa_noc_bcms, 2307 .num_bcms = ARRAY_SIZE(nspa_noc_bcms), 2308 }; 2309 2310 static struct qcom_icc_bcm * const nspb_noc_bcms[] = { 2311 &bcm_nsb0, 2312 &bcm_nsb1, 2313 }; 2314 2315 static struct qcom_icc_node * const nspb_noc_nodes[] = { 2316 [MASTER_CDSPB_NOC_CFG] = &qhm_nspb_noc_config, 2317 [MASTER_CDSP_PROC_B] = &qxm_nspb, 2318 [SLAVE_CDSPB_MEM_NOC] = &qns_nspb_gemnoc, 2319 [SLAVE_NSPB_XFR] = &qxs_nspb_xfr, 2320 [SLAVE_SERVICE_NSPB_NOC] = &service_nspb_noc, 2321 }; 2322 2323 static const struct qcom_icc_desc sc8280xp_nspb_noc = { 2324 .nodes = nspb_noc_nodes, 2325 .num_nodes = ARRAY_SIZE(nspb_noc_nodes), 2326 .bcms = nspb_noc_bcms, 2327 .num_bcms = ARRAY_SIZE(nspb_noc_bcms), 2328 }; 2329 2330 static struct qcom_icc_bcm * const system_noc_main_bcms[] = { 2331 &bcm_sn0, 2332 &bcm_sn1, 2333 &bcm_sn3, 2334 &bcm_sn4, 2335 &bcm_sn5, 2336 &bcm_sn9, 2337 }; 2338 2339 static struct qcom_icc_node * const system_noc_main_nodes[] = { 2340 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, 2341 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, 2342 [MASTER_USB_NOC_SNOC] = &qnm_aggre_usb_noc, 2343 [MASTER_LPASS_ANOC] = &qnm_lpass_noc, 2344 [MASTER_SNOC_CFG] = &qnm_snoc_cfg, 2345 [MASTER_PIMEM] = &qxm_pimem, 2346 [MASTER_GIC] = &xm_gic, 2347 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, 2348 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 2349 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 2350 }; 2351 2352 static const struct qcom_icc_desc sc8280xp_system_noc_main = { 2353 .nodes = system_noc_main_nodes, 2354 .num_nodes = ARRAY_SIZE(system_noc_main_nodes), 2355 .bcms = system_noc_main_bcms, 2356 .num_bcms = ARRAY_SIZE(system_noc_main_bcms), 2357 }; 2358 2359 static const struct of_device_id qnoc_of_match[] = { 2360 { .compatible = "qcom,sc8280xp-aggre1-noc", .data = &sc8280xp_aggre1_noc, }, 2361 { .compatible = "qcom,sc8280xp-aggre2-noc", .data = &sc8280xp_aggre2_noc, }, 2362 { .compatible = "qcom,sc8280xp-clk-virt", .data = &sc8280xp_clk_virt, }, 2363 { .compatible = "qcom,sc8280xp-config-noc", .data = &sc8280xp_config_noc, }, 2364 { .compatible = "qcom,sc8280xp-dc-noc", .data = &sc8280xp_dc_noc, }, 2365 { .compatible = "qcom,sc8280xp-gem-noc", .data = &sc8280xp_gem_noc, }, 2366 { .compatible = "qcom,sc8280xp-lpass-ag-noc", .data = &sc8280xp_lpass_ag_noc, }, 2367 { .compatible = "qcom,sc8280xp-mc-virt", .data = &sc8280xp_mc_virt, }, 2368 { .compatible = "qcom,sc8280xp-mmss-noc", .data = &sc8280xp_mmss_noc, }, 2369 { .compatible = "qcom,sc8280xp-nspa-noc", .data = &sc8280xp_nspa_noc, }, 2370 { .compatible = "qcom,sc8280xp-nspb-noc", .data = &sc8280xp_nspb_noc, }, 2371 { .compatible = "qcom,sc8280xp-system-noc", .data = &sc8280xp_system_noc_main, }, 2372 { } 2373 }; 2374 MODULE_DEVICE_TABLE(of, qnoc_of_match); 2375 2376 static struct platform_driver qnoc_driver = { 2377 .probe = qcom_icc_rpmh_probe, 2378 .remove = qcom_icc_rpmh_remove, 2379 .driver = { 2380 .name = "qnoc-sc8280xp", 2381 .of_match_table = qnoc_of_match, 2382 .sync_state = icc_sync_state, 2383 }, 2384 }; 2385 2386 static int __init qnoc_driver_init(void) 2387 { 2388 return platform_driver_register(&qnoc_driver); 2389 } 2390 core_initcall(qnoc_driver_init); 2391 2392 static void __exit qnoc_driver_exit(void) 2393 { 2394 platform_driver_unregister(&qnoc_driver); 2395 } 2396 module_exit(qnoc_driver_exit); 2397 2398 MODULE_DESCRIPTION("Qualcomm SC8280XP NoC driver"); 2399 MODULE_LICENSE("GPL"); 2400