1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Linaro Ltd 5 */ 6 7 #include <linux/device.h> 8 #include <linux/interconnect.h> 9 #include <linux/interconnect-provider.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include <dt-bindings/interconnect/qcom,sc8280xp.h> 13 14 #include "bcm-voter.h" 15 #include "icc-rpmh.h" 16 17 static struct qcom_icc_node qhm_qspi; 18 static struct qcom_icc_node qhm_qup1; 19 static struct qcom_icc_node qhm_qup2; 20 static struct qcom_icc_node qnm_a1noc_cfg; 21 static struct qcom_icc_node qxm_ipa; 22 static struct qcom_icc_node xm_emac_1; 23 static struct qcom_icc_node xm_sdc4; 24 static struct qcom_icc_node xm_ufs_mem; 25 static struct qcom_icc_node xm_usb3_0; 26 static struct qcom_icc_node xm_usb3_1; 27 static struct qcom_icc_node xm_usb3_mp; 28 static struct qcom_icc_node xm_usb4_host0; 29 static struct qcom_icc_node xm_usb4_host1; 30 static struct qcom_icc_node qhm_qdss_bam; 31 static struct qcom_icc_node qhm_qup0; 32 static struct qcom_icc_node qnm_a2noc_cfg; 33 static struct qcom_icc_node qxm_crypto; 34 static struct qcom_icc_node qxm_sensorss_q6; 35 static struct qcom_icc_node qxm_sp; 36 static struct qcom_icc_node xm_emac_0; 37 static struct qcom_icc_node xm_pcie3_0; 38 static struct qcom_icc_node xm_pcie3_1; 39 static struct qcom_icc_node xm_pcie3_2a; 40 static struct qcom_icc_node xm_pcie3_2b; 41 static struct qcom_icc_node xm_pcie3_3a; 42 static struct qcom_icc_node xm_pcie3_3b; 43 static struct qcom_icc_node xm_pcie3_4; 44 static struct qcom_icc_node xm_qdss_etr; 45 static struct qcom_icc_node xm_sdc2; 46 static struct qcom_icc_node xm_ufs_card; 47 static struct qcom_icc_node qup0_core_master; 48 static struct qcom_icc_node qup1_core_master; 49 static struct qcom_icc_node qup2_core_master; 50 static struct qcom_icc_node qnm_gemnoc_cnoc; 51 static struct qcom_icc_node qnm_gemnoc_pcie; 52 static struct qcom_icc_node qnm_cnoc_dc_noc; 53 static struct qcom_icc_node alm_gpu_tcu; 54 static struct qcom_icc_node alm_pcie_tcu; 55 static struct qcom_icc_node alm_sys_tcu; 56 static struct qcom_icc_node chm_apps; 57 static struct qcom_icc_node qnm_cmpnoc0; 58 static struct qcom_icc_node qnm_cmpnoc1; 59 static struct qcom_icc_node qnm_gemnoc_cfg; 60 static struct qcom_icc_node qnm_gpu; 61 static struct qcom_icc_node qnm_mnoc_hf; 62 static struct qcom_icc_node qnm_mnoc_sf; 63 static struct qcom_icc_node qnm_pcie; 64 static struct qcom_icc_node qnm_snoc_gc; 65 static struct qcom_icc_node qnm_snoc_sf; 66 static struct qcom_icc_node qhm_config_noc; 67 static struct qcom_icc_node qxm_lpass_dsp; 68 static struct qcom_icc_node llcc_mc; 69 static struct qcom_icc_node qnm_camnoc_hf; 70 static struct qcom_icc_node qnm_mdp0_0; 71 static struct qcom_icc_node qnm_mdp0_1; 72 static struct qcom_icc_node qnm_mdp1_0; 73 static struct qcom_icc_node qnm_mdp1_1; 74 static struct qcom_icc_node qnm_mnoc_cfg; 75 static struct qcom_icc_node qnm_rot_0; 76 static struct qcom_icc_node qnm_rot_1; 77 static struct qcom_icc_node qnm_video0; 78 static struct qcom_icc_node qnm_video1; 79 static struct qcom_icc_node qnm_video_cvp; 80 static struct qcom_icc_node qxm_camnoc_icp; 81 static struct qcom_icc_node qxm_camnoc_sf; 82 static struct qcom_icc_node qhm_nsp_noc_config; 83 static struct qcom_icc_node qxm_nsp; 84 static struct qcom_icc_node qhm_nspb_noc_config; 85 static struct qcom_icc_node qxm_nspb; 86 static struct qcom_icc_node qnm_aggre1_noc; 87 static struct qcom_icc_node qnm_aggre2_noc; 88 static struct qcom_icc_node qnm_aggre_usb_noc; 89 static struct qcom_icc_node qnm_lpass_noc; 90 static struct qcom_icc_node qnm_snoc_cfg; 91 static struct qcom_icc_node qxm_pimem; 92 static struct qcom_icc_node xm_gic; 93 static struct qcom_icc_node qns_a1noc_snoc; 94 static struct qcom_icc_node qns_aggre_usb_snoc; 95 static struct qcom_icc_node srvc_aggre1_noc; 96 static struct qcom_icc_node qns_a2noc_snoc; 97 static struct qcom_icc_node qns_pcie_gem_noc; 98 static struct qcom_icc_node srvc_aggre2_noc; 99 static struct qcom_icc_node qup0_core_slave; 100 static struct qcom_icc_node qup1_core_slave; 101 static struct qcom_icc_node qup2_core_slave; 102 static struct qcom_icc_node qhs_ahb2phy0; 103 static struct qcom_icc_node qhs_ahb2phy1; 104 static struct qcom_icc_node qhs_ahb2phy2; 105 static struct qcom_icc_node qhs_aoss; 106 static struct qcom_icc_node qhs_apss; 107 static struct qcom_icc_node qhs_camera_cfg; 108 static struct qcom_icc_node qhs_clk_ctl; 109 static struct qcom_icc_node qhs_compute0_cfg; 110 static struct qcom_icc_node qhs_compute1_cfg; 111 static struct qcom_icc_node qhs_cpr_cx; 112 static struct qcom_icc_node qhs_cpr_mmcx; 113 static struct qcom_icc_node qhs_cpr_mx; 114 static struct qcom_icc_node qhs_cpr_nspcx; 115 static struct qcom_icc_node qhs_crypto0_cfg; 116 static struct qcom_icc_node qhs_cx_rdpm; 117 static struct qcom_icc_node qhs_dcc_cfg; 118 static struct qcom_icc_node qhs_display0_cfg; 119 static struct qcom_icc_node qhs_display1_cfg; 120 static struct qcom_icc_node qhs_emac0_cfg; 121 static struct qcom_icc_node qhs_emac1_cfg; 122 static struct qcom_icc_node qhs_gpuss_cfg; 123 static struct qcom_icc_node qhs_hwkm; 124 static struct qcom_icc_node qhs_imem_cfg; 125 static struct qcom_icc_node qhs_ipa; 126 static struct qcom_icc_node qhs_ipc_router; 127 static struct qcom_icc_node qhs_lpass_cfg; 128 static struct qcom_icc_node qhs_mx_rdpm; 129 static struct qcom_icc_node qhs_mxc_rdpm; 130 static struct qcom_icc_node qhs_pcie0_cfg; 131 static struct qcom_icc_node qhs_pcie1_cfg; 132 static struct qcom_icc_node qhs_pcie2a_cfg; 133 static struct qcom_icc_node qhs_pcie2b_cfg; 134 static struct qcom_icc_node qhs_pcie3a_cfg; 135 static struct qcom_icc_node qhs_pcie3b_cfg; 136 static struct qcom_icc_node qhs_pcie4_cfg; 137 static struct qcom_icc_node qhs_pcie_rsc_cfg; 138 static struct qcom_icc_node qhs_pdm; 139 static struct qcom_icc_node qhs_pimem_cfg; 140 static struct qcom_icc_node qhs_pka_wrapper_cfg; 141 static struct qcom_icc_node qhs_pmu_wrapper_cfg; 142 static struct qcom_icc_node qhs_qdss_cfg; 143 static struct qcom_icc_node qhs_qspi; 144 static struct qcom_icc_node qhs_qup0; 145 static struct qcom_icc_node qhs_qup1; 146 static struct qcom_icc_node qhs_qup2; 147 static struct qcom_icc_node qhs_sdc2; 148 static struct qcom_icc_node qhs_sdc4; 149 static struct qcom_icc_node qhs_security; 150 static struct qcom_icc_node qhs_smmuv3_cfg; 151 static struct qcom_icc_node qhs_smss_cfg; 152 static struct qcom_icc_node qhs_spss_cfg; 153 static struct qcom_icc_node qhs_tcsr; 154 static struct qcom_icc_node qhs_tlmm; 155 static struct qcom_icc_node qhs_ufs_card_cfg; 156 static struct qcom_icc_node qhs_ufs_mem_cfg; 157 static struct qcom_icc_node qhs_usb3_0; 158 static struct qcom_icc_node qhs_usb3_1; 159 static struct qcom_icc_node qhs_usb3_mp; 160 static struct qcom_icc_node qhs_usb4_host_0; 161 static struct qcom_icc_node qhs_usb4_host_1; 162 static struct qcom_icc_node qhs_venus_cfg; 163 static struct qcom_icc_node qhs_vsense_ctrl_cfg; 164 static struct qcom_icc_node qhs_vsense_ctrl_r_cfg; 165 static struct qcom_icc_node qns_a1_noc_cfg; 166 static struct qcom_icc_node qns_a2_noc_cfg; 167 static struct qcom_icc_node qns_anoc_pcie_bridge_cfg; 168 static struct qcom_icc_node qns_ddrss_cfg; 169 static struct qcom_icc_node qns_mnoc_cfg; 170 static struct qcom_icc_node qns_snoc_cfg; 171 static struct qcom_icc_node qns_snoc_sf_bridge_cfg; 172 static struct qcom_icc_node qxs_imem; 173 static struct qcom_icc_node qxs_pimem; 174 static struct qcom_icc_node srvc_cnoc; 175 static struct qcom_icc_node xs_pcie_0; 176 static struct qcom_icc_node xs_pcie_1; 177 static struct qcom_icc_node xs_pcie_2a; 178 static struct qcom_icc_node xs_pcie_2b; 179 static struct qcom_icc_node xs_pcie_3a; 180 static struct qcom_icc_node xs_pcie_3b; 181 static struct qcom_icc_node xs_pcie_4; 182 static struct qcom_icc_node xs_qdss_stm; 183 static struct qcom_icc_node xs_smss; 184 static struct qcom_icc_node xs_sys_tcu_cfg; 185 static struct qcom_icc_node qhs_llcc; 186 static struct qcom_icc_node qns_gemnoc; 187 static struct qcom_icc_node qns_gem_noc_cnoc; 188 static struct qcom_icc_node qns_llcc; 189 static struct qcom_icc_node qns_pcie; 190 static struct qcom_icc_node srvc_even_gemnoc; 191 static struct qcom_icc_node srvc_odd_gemnoc; 192 static struct qcom_icc_node srvc_sys_gemnoc; 193 static struct qcom_icc_node qhs_lpass_core; 194 static struct qcom_icc_node qhs_lpass_lpi; 195 static struct qcom_icc_node qhs_lpass_mpu; 196 static struct qcom_icc_node qhs_lpass_top; 197 static struct qcom_icc_node qns_sysnoc; 198 static struct qcom_icc_node srvc_niu_aml_noc; 199 static struct qcom_icc_node srvc_niu_lpass_agnoc; 200 static struct qcom_icc_node ebi; 201 static struct qcom_icc_node qns_mem_noc_hf; 202 static struct qcom_icc_node qns_mem_noc_sf; 203 static struct qcom_icc_node srvc_mnoc; 204 static struct qcom_icc_node qns_nsp_gemnoc; 205 static struct qcom_icc_node qxs_nsp_xfr; 206 static struct qcom_icc_node service_nsp_noc; 207 static struct qcom_icc_node qns_nspb_gemnoc; 208 static struct qcom_icc_node qxs_nspb_xfr; 209 static struct qcom_icc_node service_nspb_noc; 210 static struct qcom_icc_node qns_gemnoc_gc; 211 static struct qcom_icc_node qns_gemnoc_sf; 212 static struct qcom_icc_node srvc_snoc; 213 214 static struct qcom_icc_node qhm_qspi = { 215 .name = "qhm_qspi", 216 .channels = 1, 217 .buswidth = 4, 218 .num_links = 1, 219 .link_nodes = { &qns_a1noc_snoc }, 220 }; 221 222 static struct qcom_icc_node qhm_qup1 = { 223 .name = "qhm_qup1", 224 .channels = 1, 225 .buswidth = 4, 226 .num_links = 1, 227 .link_nodes = { &qns_a1noc_snoc }, 228 }; 229 230 static struct qcom_icc_node qhm_qup2 = { 231 .name = "qhm_qup2", 232 .channels = 1, 233 .buswidth = 4, 234 .num_links = 1, 235 .link_nodes = { &qns_a1noc_snoc }, 236 }; 237 238 static struct qcom_icc_node qnm_a1noc_cfg = { 239 .name = "qnm_a1noc_cfg", 240 .channels = 1, 241 .buswidth = 4, 242 .num_links = 1, 243 .link_nodes = { &srvc_aggre1_noc }, 244 }; 245 246 static struct qcom_icc_node qxm_ipa = { 247 .name = "qxm_ipa", 248 .channels = 1, 249 .buswidth = 8, 250 .num_links = 1, 251 .link_nodes = { &qns_a1noc_snoc }, 252 }; 253 254 static struct qcom_icc_node xm_emac_1 = { 255 .name = "xm_emac_1", 256 .channels = 1, 257 .buswidth = 8, 258 .num_links = 1, 259 .link_nodes = { &qns_a1noc_snoc }, 260 }; 261 262 static struct qcom_icc_node xm_sdc4 = { 263 .name = "xm_sdc4", 264 .channels = 1, 265 .buswidth = 8, 266 .num_links = 1, 267 .link_nodes = { &qns_a1noc_snoc }, 268 }; 269 270 static struct qcom_icc_node xm_ufs_mem = { 271 .name = "xm_ufs_mem", 272 .channels = 1, 273 .buswidth = 8, 274 .num_links = 1, 275 .link_nodes = { &qns_a1noc_snoc }, 276 }; 277 278 static struct qcom_icc_node xm_usb3_0 = { 279 .name = "xm_usb3_0", 280 .channels = 1, 281 .buswidth = 8, 282 .num_links = 1, 283 .link_nodes = { &qns_aggre_usb_snoc }, 284 }; 285 286 static struct qcom_icc_node xm_usb3_1 = { 287 .name = "xm_usb3_1", 288 .channels = 1, 289 .buswidth = 8, 290 .num_links = 1, 291 .link_nodes = { &qns_aggre_usb_snoc }, 292 }; 293 294 static struct qcom_icc_node xm_usb3_mp = { 295 .name = "xm_usb3_mp", 296 .channels = 1, 297 .buswidth = 16, 298 .num_links = 1, 299 .link_nodes = { &qns_aggre_usb_snoc }, 300 }; 301 302 static struct qcom_icc_node xm_usb4_host0 = { 303 .name = "xm_usb4_host0", 304 .channels = 1, 305 .buswidth = 16, 306 .num_links = 1, 307 .link_nodes = { &qns_aggre_usb_snoc }, 308 }; 309 310 static struct qcom_icc_node xm_usb4_host1 = { 311 .name = "xm_usb4_host1", 312 .channels = 1, 313 .buswidth = 16, 314 .num_links = 1, 315 .link_nodes = { &qns_aggre_usb_snoc }, 316 }; 317 318 static struct qcom_icc_node qhm_qdss_bam = { 319 .name = "qhm_qdss_bam", 320 .channels = 1, 321 .buswidth = 4, 322 .num_links = 1, 323 .link_nodes = { &qns_a2noc_snoc }, 324 }; 325 326 static struct qcom_icc_node qhm_qup0 = { 327 .name = "qhm_qup0", 328 .channels = 1, 329 .buswidth = 4, 330 .num_links = 1, 331 .link_nodes = { &qns_a2noc_snoc }, 332 }; 333 334 static struct qcom_icc_node qnm_a2noc_cfg = { 335 .name = "qnm_a2noc_cfg", 336 .channels = 1, 337 .buswidth = 4, 338 .num_links = 1, 339 .link_nodes = { &srvc_aggre2_noc }, 340 }; 341 342 static struct qcom_icc_node qxm_crypto = { 343 .name = "qxm_crypto", 344 .channels = 1, 345 .buswidth = 8, 346 .num_links = 1, 347 .link_nodes = { &qns_a2noc_snoc }, 348 }; 349 350 static struct qcom_icc_node qxm_sensorss_q6 = { 351 .name = "qxm_sensorss_q6", 352 .channels = 1, 353 .buswidth = 8, 354 .num_links = 1, 355 .link_nodes = { &qns_a2noc_snoc }, 356 }; 357 358 static struct qcom_icc_node qxm_sp = { 359 .name = "qxm_sp", 360 .channels = 1, 361 .buswidth = 8, 362 .num_links = 1, 363 .link_nodes = { &qns_a2noc_snoc }, 364 }; 365 366 static struct qcom_icc_node xm_emac_0 = { 367 .name = "xm_emac_0", 368 .channels = 1, 369 .buswidth = 8, 370 .num_links = 1, 371 .link_nodes = { &qns_a2noc_snoc }, 372 }; 373 374 static struct qcom_icc_node xm_pcie3_0 = { 375 .name = "xm_pcie3_0", 376 .channels = 1, 377 .buswidth = 16, 378 .num_links = 1, 379 .link_nodes = { &qns_pcie_gem_noc }, 380 }; 381 382 static struct qcom_icc_node xm_pcie3_1 = { 383 .name = "xm_pcie3_1", 384 .channels = 1, 385 .buswidth = 16, 386 .num_links = 1, 387 .link_nodes = { &qns_pcie_gem_noc }, 388 }; 389 390 static struct qcom_icc_node xm_pcie3_2a = { 391 .name = "xm_pcie3_2a", 392 .channels = 1, 393 .buswidth = 16, 394 .num_links = 1, 395 .link_nodes = { &qns_pcie_gem_noc }, 396 }; 397 398 static struct qcom_icc_node xm_pcie3_2b = { 399 .name = "xm_pcie3_2b", 400 .channels = 1, 401 .buswidth = 8, 402 .num_links = 1, 403 .link_nodes = { &qns_pcie_gem_noc }, 404 }; 405 406 static struct qcom_icc_node xm_pcie3_3a = { 407 .name = "xm_pcie3_3a", 408 .channels = 1, 409 .buswidth = 16, 410 .num_links = 1, 411 .link_nodes = { &qns_pcie_gem_noc }, 412 }; 413 414 static struct qcom_icc_node xm_pcie3_3b = { 415 .name = "xm_pcie3_3b", 416 .channels = 1, 417 .buswidth = 8, 418 .num_links = 1, 419 .link_nodes = { &qns_pcie_gem_noc }, 420 }; 421 422 static struct qcom_icc_node xm_pcie3_4 = { 423 .name = "xm_pcie3_4", 424 .channels = 1, 425 .buswidth = 8, 426 .num_links = 1, 427 .link_nodes = { &qns_pcie_gem_noc }, 428 }; 429 430 static struct qcom_icc_node xm_qdss_etr = { 431 .name = "xm_qdss_etr", 432 .channels = 1, 433 .buswidth = 8, 434 .num_links = 1, 435 .link_nodes = { &qns_a2noc_snoc }, 436 }; 437 438 static struct qcom_icc_node xm_sdc2 = { 439 .name = "xm_sdc2", 440 .channels = 1, 441 .buswidth = 8, 442 .num_links = 1, 443 .link_nodes = { &qns_a2noc_snoc }, 444 }; 445 446 static struct qcom_icc_node xm_ufs_card = { 447 .name = "xm_ufs_card", 448 .channels = 1, 449 .buswidth = 8, 450 .num_links = 1, 451 .link_nodes = { &qns_a2noc_snoc }, 452 }; 453 454 static struct qcom_icc_node qup0_core_master = { 455 .name = "qup0_core_master", 456 .channels = 1, 457 .buswidth = 4, 458 .num_links = 1, 459 .link_nodes = { &qup0_core_slave }, 460 }; 461 462 static struct qcom_icc_node qup1_core_master = { 463 .name = "qup1_core_master", 464 .channels = 1, 465 .buswidth = 4, 466 .num_links = 1, 467 .link_nodes = { &qup1_core_slave }, 468 }; 469 470 static struct qcom_icc_node qup2_core_master = { 471 .name = "qup2_core_master", 472 .channels = 1, 473 .buswidth = 4, 474 .num_links = 1, 475 .link_nodes = { &qup2_core_slave }, 476 }; 477 478 static struct qcom_icc_node qnm_gemnoc_cnoc = { 479 .name = "qnm_gemnoc_cnoc", 480 .channels = 1, 481 .buswidth = 16, 482 .num_links = 76, 483 .link_nodes = { &qhs_ahb2phy0, 484 &qhs_ahb2phy1, 485 &qhs_ahb2phy2, 486 &qhs_aoss, 487 &qhs_apss, 488 &qhs_camera_cfg, 489 &qhs_clk_ctl, 490 &qhs_compute0_cfg, 491 &qhs_compute1_cfg, 492 &qhs_cpr_cx, 493 &qhs_cpr_mmcx, 494 &qhs_cpr_mx, 495 &qhs_cpr_nspcx, 496 &qhs_crypto0_cfg, 497 &qhs_cx_rdpm, 498 &qhs_dcc_cfg, 499 &qhs_display0_cfg, 500 &qhs_display1_cfg, 501 &qhs_emac0_cfg, 502 &qhs_emac1_cfg, 503 &qhs_gpuss_cfg, 504 &qhs_hwkm, 505 &qhs_imem_cfg, 506 &qhs_ipa, 507 &qhs_ipc_router, 508 &qhs_lpass_cfg, 509 &qhs_mx_rdpm, 510 &qhs_mxc_rdpm, 511 &qhs_pcie0_cfg, 512 &qhs_pcie1_cfg, 513 &qhs_pcie2a_cfg, 514 &qhs_pcie2b_cfg, 515 &qhs_pcie3a_cfg, 516 &qhs_pcie3b_cfg, 517 &qhs_pcie4_cfg, 518 &qhs_pcie_rsc_cfg, 519 &qhs_pdm, 520 &qhs_pimem_cfg, 521 &qhs_pka_wrapper_cfg, 522 &qhs_pmu_wrapper_cfg, 523 &qhs_qdss_cfg, 524 &qhs_qspi, 525 &qhs_qup0, 526 &qhs_qup1, 527 &qhs_qup2, 528 &qhs_sdc2, 529 &qhs_sdc4, 530 &qhs_security, 531 &qhs_smmuv3_cfg, 532 &qhs_smss_cfg, 533 &qhs_spss_cfg, 534 &qhs_tcsr, 535 &qhs_tlmm, 536 &qhs_ufs_card_cfg, 537 &qhs_ufs_mem_cfg, 538 &qhs_usb3_0, 539 &qhs_usb3_1, 540 &qhs_usb3_mp, 541 &qhs_usb4_host_0, 542 &qhs_usb4_host_1, 543 &qhs_venus_cfg, 544 &qhs_vsense_ctrl_cfg, 545 &qhs_vsense_ctrl_r_cfg, 546 &qns_a1_noc_cfg, 547 &qns_a2_noc_cfg, 548 &qns_anoc_pcie_bridge_cfg, 549 &qns_ddrss_cfg, 550 &qns_mnoc_cfg, 551 &qns_snoc_cfg, 552 &qns_snoc_sf_bridge_cfg, 553 &qxs_imem, 554 &qxs_pimem, 555 &srvc_cnoc, 556 &xs_qdss_stm, 557 &xs_smss, 558 &xs_sys_tcu_cfg, 559 NULL }, 560 }; 561 562 static struct qcom_icc_node qnm_gemnoc_pcie = { 563 .name = "qnm_gemnoc_pcie", 564 .channels = 1, 565 .buswidth = 16, 566 .num_links = 7, 567 .link_nodes = { &xs_pcie_0, 568 &xs_pcie_1, 569 &xs_pcie_2a, 570 &xs_pcie_2b, 571 &xs_pcie_3a, 572 &xs_pcie_3b, 573 &xs_pcie_4 }, 574 }; 575 576 static struct qcom_icc_node qnm_cnoc_dc_noc = { 577 .name = "qnm_cnoc_dc_noc", 578 .channels = 1, 579 .buswidth = 4, 580 .num_links = 2, 581 .link_nodes = { &qhs_llcc, 582 &qns_gemnoc }, 583 }; 584 585 static struct qcom_icc_node alm_gpu_tcu = { 586 .name = "alm_gpu_tcu", 587 .channels = 1, 588 .buswidth = 8, 589 .num_links = 2, 590 .link_nodes = { &qns_gem_noc_cnoc, 591 &qns_llcc }, 592 }; 593 594 static struct qcom_icc_node alm_pcie_tcu = { 595 .name = "alm_pcie_tcu", 596 .channels = 1, 597 .buswidth = 8, 598 .num_links = 2, 599 .link_nodes = { &qns_gem_noc_cnoc, 600 &qns_llcc }, 601 }; 602 603 static struct qcom_icc_node alm_sys_tcu = { 604 .name = "alm_sys_tcu", 605 .channels = 1, 606 .buswidth = 8, 607 .num_links = 2, 608 .link_nodes = { &qns_gem_noc_cnoc, 609 &qns_llcc }, 610 }; 611 612 static struct qcom_icc_node chm_apps = { 613 .name = "chm_apps", 614 .channels = 2, 615 .buswidth = 32, 616 .num_links = 3, 617 .link_nodes = { &qns_gem_noc_cnoc, 618 &qns_llcc, 619 &qns_pcie }, 620 }; 621 622 static struct qcom_icc_node qnm_cmpnoc0 = { 623 .name = "qnm_cmpnoc0", 624 .channels = 2, 625 .buswidth = 32, 626 .num_links = 2, 627 .link_nodes = { &qns_gem_noc_cnoc, 628 &qns_llcc }, 629 }; 630 631 static struct qcom_icc_node qnm_cmpnoc1 = { 632 .name = "qnm_cmpnoc1", 633 .channels = 2, 634 .buswidth = 32, 635 .num_links = 2, 636 .link_nodes = { &qns_gem_noc_cnoc, 637 &qns_llcc }, 638 }; 639 640 static struct qcom_icc_node qnm_gemnoc_cfg = { 641 .name = "qnm_gemnoc_cfg", 642 .channels = 1, 643 .buswidth = 4, 644 .num_links = 3, 645 .link_nodes = { &srvc_even_gemnoc, 646 &srvc_odd_gemnoc, 647 &srvc_sys_gemnoc }, 648 }; 649 650 static struct qcom_icc_node qnm_gpu = { 651 .name = "qnm_gpu", 652 .channels = 4, 653 .buswidth = 32, 654 .num_links = 2, 655 .link_nodes = { &qns_gem_noc_cnoc, 656 &qns_llcc }, 657 }; 658 659 static struct qcom_icc_node qnm_mnoc_hf = { 660 .name = "qnm_mnoc_hf", 661 .channels = 2, 662 .buswidth = 32, 663 .num_links = 2, 664 .link_nodes = { &qns_llcc, 665 &qns_pcie }, 666 }; 667 668 static struct qcom_icc_node qnm_mnoc_sf = { 669 .name = "qnm_mnoc_sf", 670 .channels = 2, 671 .buswidth = 32, 672 .num_links = 2, 673 .link_nodes = { &qns_gem_noc_cnoc, 674 &qns_llcc }, 675 }; 676 677 static struct qcom_icc_node qnm_pcie = { 678 .name = "qnm_pcie", 679 .channels = 1, 680 .buswidth = 32, 681 .num_links = 2, 682 .link_nodes = { &qns_gem_noc_cnoc, 683 &qns_llcc }, 684 }; 685 686 static struct qcom_icc_node qnm_snoc_gc = { 687 .name = "qnm_snoc_gc", 688 .channels = 1, 689 .buswidth = 8, 690 .num_links = 1, 691 .link_nodes = { &qns_llcc }, 692 }; 693 694 static struct qcom_icc_node qnm_snoc_sf = { 695 .name = "qnm_snoc_sf", 696 .channels = 1, 697 .buswidth = 16, 698 .num_links = 3, 699 .link_nodes = { &qns_gem_noc_cnoc, 700 &qns_llcc, 701 &qns_pcie }, 702 }; 703 704 static struct qcom_icc_node qhm_config_noc = { 705 .name = "qhm_config_noc", 706 .channels = 1, 707 .buswidth = 4, 708 .num_links = 6, 709 .link_nodes = { &qhs_lpass_core, 710 &qhs_lpass_lpi, 711 &qhs_lpass_mpu, 712 &qhs_lpass_top, 713 &srvc_niu_aml_noc, 714 &srvc_niu_lpass_agnoc }, 715 }; 716 717 static struct qcom_icc_node qxm_lpass_dsp = { 718 .name = "qxm_lpass_dsp", 719 .channels = 1, 720 .buswidth = 8, 721 .num_links = 4, 722 .link_nodes = { &qhs_lpass_top, 723 &qns_sysnoc, 724 &srvc_niu_aml_noc, 725 &srvc_niu_lpass_agnoc }, 726 }; 727 728 static struct qcom_icc_node llcc_mc = { 729 .name = "llcc_mc", 730 .channels = 8, 731 .buswidth = 4, 732 .num_links = 1, 733 .link_nodes = { &ebi }, 734 }; 735 736 static struct qcom_icc_node qnm_camnoc_hf = { 737 .name = "qnm_camnoc_hf", 738 .channels = 2, 739 .buswidth = 32, 740 .num_links = 1, 741 .link_nodes = { &qns_mem_noc_hf }, 742 }; 743 744 static struct qcom_icc_node qnm_mdp0_0 = { 745 .name = "qnm_mdp0_0", 746 .channels = 1, 747 .buswidth = 32, 748 .num_links = 1, 749 .link_nodes = { &qns_mem_noc_hf }, 750 }; 751 752 static struct qcom_icc_node qnm_mdp0_1 = { 753 .name = "qnm_mdp0_1", 754 .channels = 1, 755 .buswidth = 32, 756 .num_links = 1, 757 .link_nodes = { &qns_mem_noc_hf }, 758 }; 759 760 static struct qcom_icc_node qnm_mdp1_0 = { 761 .name = "qnm_mdp1_0", 762 .channels = 1, 763 .buswidth = 32, 764 .num_links = 1, 765 .link_nodes = { &qns_mem_noc_hf }, 766 }; 767 768 static struct qcom_icc_node qnm_mdp1_1 = { 769 .name = "qnm_mdp1_1", 770 .channels = 1, 771 .buswidth = 32, 772 .num_links = 1, 773 .link_nodes = { &qns_mem_noc_hf }, 774 }; 775 776 static struct qcom_icc_node qnm_mnoc_cfg = { 777 .name = "qnm_mnoc_cfg", 778 .channels = 1, 779 .buswidth = 4, 780 .num_links = 1, 781 .link_nodes = { &srvc_mnoc }, 782 }; 783 784 static struct qcom_icc_node qnm_rot_0 = { 785 .name = "qnm_rot_0", 786 .channels = 1, 787 .buswidth = 32, 788 .num_links = 1, 789 .link_nodes = { &qns_mem_noc_sf }, 790 }; 791 792 static struct qcom_icc_node qnm_rot_1 = { 793 .name = "qnm_rot_1", 794 .channels = 1, 795 .buswidth = 32, 796 .num_links = 1, 797 .link_nodes = { &qns_mem_noc_sf }, 798 }; 799 800 static struct qcom_icc_node qnm_video0 = { 801 .name = "qnm_video0", 802 .channels = 1, 803 .buswidth = 32, 804 .num_links = 1, 805 .link_nodes = { &qns_mem_noc_sf }, 806 }; 807 808 static struct qcom_icc_node qnm_video1 = { 809 .name = "qnm_video1", 810 .channels = 1, 811 .buswidth = 32, 812 .num_links = 1, 813 .link_nodes = { &qns_mem_noc_sf }, 814 }; 815 816 static struct qcom_icc_node qnm_video_cvp = { 817 .name = "qnm_video_cvp", 818 .channels = 1, 819 .buswidth = 32, 820 .num_links = 1, 821 .link_nodes = { &qns_mem_noc_sf }, 822 }; 823 824 static struct qcom_icc_node qxm_camnoc_icp = { 825 .name = "qxm_camnoc_icp", 826 .channels = 1, 827 .buswidth = 8, 828 .num_links = 1, 829 .link_nodes = { &qns_mem_noc_sf }, 830 }; 831 832 static struct qcom_icc_node qxm_camnoc_sf = { 833 .name = "qxm_camnoc_sf", 834 .channels = 1, 835 .buswidth = 32, 836 .num_links = 1, 837 .link_nodes = { &qns_mem_noc_sf }, 838 }; 839 840 static struct qcom_icc_node qhm_nsp_noc_config = { 841 .name = "qhm_nsp_noc_config", 842 .channels = 1, 843 .buswidth = 4, 844 .num_links = 1, 845 .link_nodes = { &service_nsp_noc }, 846 }; 847 848 static struct qcom_icc_node qxm_nsp = { 849 .name = "qxm_nsp", 850 .channels = 2, 851 .buswidth = 32, 852 .num_links = 2, 853 .link_nodes = { &qns_nsp_gemnoc, 854 &qxs_nsp_xfr }, 855 }; 856 857 static struct qcom_icc_node qhm_nspb_noc_config = { 858 .name = "qhm_nspb_noc_config", 859 .channels = 1, 860 .buswidth = 4, 861 .num_links = 1, 862 .link_nodes = { &service_nspb_noc }, 863 }; 864 865 static struct qcom_icc_node qxm_nspb = { 866 .name = "qxm_nspb", 867 .channels = 2, 868 .buswidth = 32, 869 .num_links = 2, 870 .link_nodes = { &qns_nspb_gemnoc, 871 &qxs_nspb_xfr }, 872 }; 873 874 static struct qcom_icc_node qnm_aggre1_noc = { 875 .name = "qnm_aggre1_noc", 876 .channels = 1, 877 .buswidth = 16, 878 .num_links = 1, 879 .link_nodes = { &qns_gemnoc_sf }, 880 }; 881 882 static struct qcom_icc_node qnm_aggre2_noc = { 883 .name = "qnm_aggre2_noc", 884 .channels = 1, 885 .buswidth = 16, 886 .num_links = 1, 887 .link_nodes = { &qns_gemnoc_sf }, 888 }; 889 890 static struct qcom_icc_node qnm_aggre_usb_noc = { 891 .name = "qnm_aggre_usb_noc", 892 .channels = 1, 893 .buswidth = 16, 894 .num_links = 1, 895 .link_nodes = { &qns_gemnoc_sf }, 896 }; 897 898 static struct qcom_icc_node qnm_lpass_noc = { 899 .name = "qnm_lpass_noc", 900 .channels = 1, 901 .buswidth = 16, 902 .num_links = 1, 903 .link_nodes = { &qns_gemnoc_sf }, 904 }; 905 906 static struct qcom_icc_node qnm_snoc_cfg = { 907 .name = "qnm_snoc_cfg", 908 .channels = 1, 909 .buswidth = 4, 910 .num_links = 1, 911 .link_nodes = { &srvc_snoc }, 912 }; 913 914 static struct qcom_icc_node qxm_pimem = { 915 .name = "qxm_pimem", 916 .channels = 1, 917 .buswidth = 8, 918 .num_links = 1, 919 .link_nodes = { &qns_gemnoc_gc }, 920 }; 921 922 static struct qcom_icc_node xm_gic = { 923 .name = "xm_gic", 924 .channels = 1, 925 .buswidth = 8, 926 .num_links = 1, 927 .link_nodes = { &qns_gemnoc_gc }, 928 }; 929 930 static struct qcom_icc_node qns_a1noc_snoc = { 931 .name = "qns_a1noc_snoc", 932 .channels = 1, 933 .buswidth = 16, 934 .num_links = 1, 935 .link_nodes = { &qnm_aggre1_noc }, 936 }; 937 938 static struct qcom_icc_node qns_aggre_usb_snoc = { 939 .name = "qns_aggre_usb_snoc", 940 .channels = 1, 941 .buswidth = 16, 942 .num_links = 1, 943 .link_nodes = { &qnm_aggre_usb_noc }, 944 }; 945 946 static struct qcom_icc_node srvc_aggre1_noc = { 947 .name = "srvc_aggre1_noc", 948 .channels = 1, 949 .buswidth = 4, 950 }; 951 952 static struct qcom_icc_node qns_a2noc_snoc = { 953 .name = "qns_a2noc_snoc", 954 .channels = 1, 955 .buswidth = 16, 956 .num_links = 1, 957 .link_nodes = { &qnm_aggre2_noc }, 958 }; 959 960 static struct qcom_icc_node qns_pcie_gem_noc = { 961 .name = "qns_pcie_gem_noc", 962 .channels = 1, 963 .buswidth = 32, 964 .num_links = 1, 965 .link_nodes = { &qnm_pcie }, 966 }; 967 968 static struct qcom_icc_node srvc_aggre2_noc = { 969 .name = "srvc_aggre2_noc", 970 .channels = 1, 971 .buswidth = 4, 972 }; 973 974 static struct qcom_icc_node qup0_core_slave = { 975 .name = "qup0_core_slave", 976 .channels = 1, 977 .buswidth = 4, 978 }; 979 980 static struct qcom_icc_node qup1_core_slave = { 981 .name = "qup1_core_slave", 982 .channels = 1, 983 .buswidth = 4, 984 }; 985 986 static struct qcom_icc_node qup2_core_slave = { 987 .name = "qup2_core_slave", 988 .channels = 1, 989 .buswidth = 4, 990 }; 991 992 static struct qcom_icc_node qhs_ahb2phy0 = { 993 .name = "qhs_ahb2phy0", 994 .channels = 1, 995 .buswidth = 4, 996 }; 997 998 static struct qcom_icc_node qhs_ahb2phy1 = { 999 .name = "qhs_ahb2phy1", 1000 .channels = 1, 1001 .buswidth = 4, 1002 }; 1003 1004 static struct qcom_icc_node qhs_ahb2phy2 = { 1005 .name = "qhs_ahb2phy2", 1006 .channels = 1, 1007 .buswidth = 4, 1008 }; 1009 1010 static struct qcom_icc_node qhs_aoss = { 1011 .name = "qhs_aoss", 1012 .channels = 1, 1013 .buswidth = 4, 1014 }; 1015 1016 static struct qcom_icc_node qhs_apss = { 1017 .name = "qhs_apss", 1018 .channels = 1, 1019 .buswidth = 8, 1020 }; 1021 1022 static struct qcom_icc_node qhs_camera_cfg = { 1023 .name = "qhs_camera_cfg", 1024 .channels = 1, 1025 .buswidth = 4, 1026 }; 1027 1028 static struct qcom_icc_node qhs_clk_ctl = { 1029 .name = "qhs_clk_ctl", 1030 .channels = 1, 1031 .buswidth = 4, 1032 }; 1033 1034 static struct qcom_icc_node qhs_compute0_cfg = { 1035 .name = "qhs_compute0_cfg", 1036 .channels = 1, 1037 .buswidth = 4, 1038 .num_links = 1, 1039 .link_nodes = { &qhm_nsp_noc_config }, 1040 }; 1041 1042 static struct qcom_icc_node qhs_compute1_cfg = { 1043 .name = "qhs_compute1_cfg", 1044 .channels = 1, 1045 .buswidth = 4, 1046 .num_links = 1, 1047 .link_nodes = { &qhm_nspb_noc_config }, 1048 }; 1049 1050 static struct qcom_icc_node qhs_cpr_cx = { 1051 .name = "qhs_cpr_cx", 1052 .channels = 1, 1053 .buswidth = 4, 1054 }; 1055 1056 static struct qcom_icc_node qhs_cpr_mmcx = { 1057 .name = "qhs_cpr_mmcx", 1058 .channels = 1, 1059 .buswidth = 4, 1060 }; 1061 1062 static struct qcom_icc_node qhs_cpr_mx = { 1063 .name = "qhs_cpr_mx", 1064 .channels = 1, 1065 .buswidth = 4, 1066 }; 1067 1068 static struct qcom_icc_node qhs_cpr_nspcx = { 1069 .name = "qhs_cpr_nspcx", 1070 .channels = 1, 1071 .buswidth = 4, 1072 }; 1073 1074 static struct qcom_icc_node qhs_crypto0_cfg = { 1075 .name = "qhs_crypto0_cfg", 1076 .channels = 1, 1077 .buswidth = 4, 1078 }; 1079 1080 static struct qcom_icc_node qhs_cx_rdpm = { 1081 .name = "qhs_cx_rdpm", 1082 .channels = 1, 1083 .buswidth = 4, 1084 }; 1085 1086 static struct qcom_icc_node qhs_dcc_cfg = { 1087 .name = "qhs_dcc_cfg", 1088 .channels = 1, 1089 .buswidth = 4, 1090 }; 1091 1092 static struct qcom_icc_node qhs_display0_cfg = { 1093 .name = "qhs_display0_cfg", 1094 .channels = 1, 1095 .buswidth = 4, 1096 }; 1097 1098 static struct qcom_icc_node qhs_display1_cfg = { 1099 .name = "qhs_display1_cfg", 1100 .channels = 1, 1101 .buswidth = 4, 1102 }; 1103 1104 static struct qcom_icc_node qhs_emac0_cfg = { 1105 .name = "qhs_emac0_cfg", 1106 .channels = 1, 1107 .buswidth = 4, 1108 }; 1109 1110 static struct qcom_icc_node qhs_emac1_cfg = { 1111 .name = "qhs_emac1_cfg", 1112 .channels = 1, 1113 .buswidth = 4, 1114 }; 1115 1116 static struct qcom_icc_node qhs_gpuss_cfg = { 1117 .name = "qhs_gpuss_cfg", 1118 .channels = 1, 1119 .buswidth = 8, 1120 }; 1121 1122 static struct qcom_icc_node qhs_hwkm = { 1123 .name = "qhs_hwkm", 1124 .channels = 1, 1125 .buswidth = 4, 1126 }; 1127 1128 static struct qcom_icc_node qhs_imem_cfg = { 1129 .name = "qhs_imem_cfg", 1130 .channels = 1, 1131 .buswidth = 4, 1132 }; 1133 1134 static struct qcom_icc_node qhs_ipa = { 1135 .name = "qhs_ipa", 1136 .channels = 1, 1137 .buswidth = 4, 1138 }; 1139 1140 static struct qcom_icc_node qhs_ipc_router = { 1141 .name = "qhs_ipc_router", 1142 .channels = 1, 1143 .buswidth = 4, 1144 }; 1145 1146 static struct qcom_icc_node qhs_lpass_cfg = { 1147 .name = "qhs_lpass_cfg", 1148 .channels = 1, 1149 .buswidth = 4, 1150 .num_links = 1, 1151 .link_nodes = { &qhm_config_noc }, 1152 }; 1153 1154 static struct qcom_icc_node qhs_mx_rdpm = { 1155 .name = "qhs_mx_rdpm", 1156 .channels = 1, 1157 .buswidth = 4, 1158 }; 1159 1160 static struct qcom_icc_node qhs_mxc_rdpm = { 1161 .name = "qhs_mxc_rdpm", 1162 .channels = 1, 1163 .buswidth = 4, 1164 }; 1165 1166 static struct qcom_icc_node qhs_pcie0_cfg = { 1167 .name = "qhs_pcie0_cfg", 1168 .channels = 1, 1169 .buswidth = 4, 1170 }; 1171 1172 static struct qcom_icc_node qhs_pcie1_cfg = { 1173 .name = "qhs_pcie1_cfg", 1174 .channels = 1, 1175 .buswidth = 4, 1176 }; 1177 1178 static struct qcom_icc_node qhs_pcie2a_cfg = { 1179 .name = "qhs_pcie2a_cfg", 1180 .channels = 1, 1181 .buswidth = 4, 1182 }; 1183 1184 static struct qcom_icc_node qhs_pcie2b_cfg = { 1185 .name = "qhs_pcie2b_cfg", 1186 .channels = 1, 1187 .buswidth = 4, 1188 }; 1189 1190 static struct qcom_icc_node qhs_pcie3a_cfg = { 1191 .name = "qhs_pcie3a_cfg", 1192 .channels = 1, 1193 .buswidth = 4, 1194 }; 1195 1196 static struct qcom_icc_node qhs_pcie3b_cfg = { 1197 .name = "qhs_pcie3b_cfg", 1198 .channels = 1, 1199 .buswidth = 4, 1200 }; 1201 1202 static struct qcom_icc_node qhs_pcie4_cfg = { 1203 .name = "qhs_pcie4_cfg", 1204 .channels = 1, 1205 .buswidth = 4, 1206 }; 1207 1208 static struct qcom_icc_node qhs_pcie_rsc_cfg = { 1209 .name = "qhs_pcie_rsc_cfg", 1210 .channels = 1, 1211 .buswidth = 4, 1212 }; 1213 1214 static struct qcom_icc_node qhs_pdm = { 1215 .name = "qhs_pdm", 1216 .channels = 1, 1217 .buswidth = 4, 1218 }; 1219 1220 static struct qcom_icc_node qhs_pimem_cfg = { 1221 .name = "qhs_pimem_cfg", 1222 .channels = 1, 1223 .buswidth = 4, 1224 }; 1225 1226 static struct qcom_icc_node qhs_pka_wrapper_cfg = { 1227 .name = "qhs_pka_wrapper_cfg", 1228 .channels = 1, 1229 .buswidth = 4, 1230 }; 1231 1232 static struct qcom_icc_node qhs_pmu_wrapper_cfg = { 1233 .name = "qhs_pmu_wrapper_cfg", 1234 .channels = 1, 1235 .buswidth = 4, 1236 }; 1237 1238 static struct qcom_icc_node qhs_qdss_cfg = { 1239 .name = "qhs_qdss_cfg", 1240 .channels = 1, 1241 .buswidth = 4, 1242 }; 1243 1244 static struct qcom_icc_node qhs_qspi = { 1245 .name = "qhs_qspi", 1246 .channels = 1, 1247 .buswidth = 4, 1248 }; 1249 1250 static struct qcom_icc_node qhs_qup0 = { 1251 .name = "qhs_qup0", 1252 .channels = 1, 1253 .buswidth = 4, 1254 }; 1255 1256 static struct qcom_icc_node qhs_qup1 = { 1257 .name = "qhs_qup1", 1258 .channels = 1, 1259 .buswidth = 4, 1260 }; 1261 1262 static struct qcom_icc_node qhs_qup2 = { 1263 .name = "qhs_qup2", 1264 .channels = 1, 1265 .buswidth = 4, 1266 }; 1267 1268 static struct qcom_icc_node qhs_sdc2 = { 1269 .name = "qhs_sdc2", 1270 .channels = 1, 1271 .buswidth = 4, 1272 }; 1273 1274 static struct qcom_icc_node qhs_sdc4 = { 1275 .name = "qhs_sdc4", 1276 .channels = 1, 1277 .buswidth = 4, 1278 }; 1279 1280 static struct qcom_icc_node qhs_security = { 1281 .name = "qhs_security", 1282 .channels = 1, 1283 .buswidth = 4, 1284 }; 1285 1286 static struct qcom_icc_node qhs_smmuv3_cfg = { 1287 .name = "qhs_smmuv3_cfg", 1288 .channels = 1, 1289 .buswidth = 8, 1290 }; 1291 1292 static struct qcom_icc_node qhs_smss_cfg = { 1293 .name = "qhs_smss_cfg", 1294 .channels = 1, 1295 .buswidth = 4, 1296 }; 1297 1298 static struct qcom_icc_node qhs_spss_cfg = { 1299 .name = "qhs_spss_cfg", 1300 .channels = 1, 1301 .buswidth = 4, 1302 }; 1303 1304 static struct qcom_icc_node qhs_tcsr = { 1305 .name = "qhs_tcsr", 1306 .channels = 1, 1307 .buswidth = 4, 1308 }; 1309 1310 static struct qcom_icc_node qhs_tlmm = { 1311 .name = "qhs_tlmm", 1312 .channels = 1, 1313 .buswidth = 4, 1314 }; 1315 1316 static struct qcom_icc_node qhs_ufs_card_cfg = { 1317 .name = "qhs_ufs_card_cfg", 1318 .channels = 1, 1319 .buswidth = 4, 1320 }; 1321 1322 static struct qcom_icc_node qhs_ufs_mem_cfg = { 1323 .name = "qhs_ufs_mem_cfg", 1324 .channels = 1, 1325 .buswidth = 4, 1326 }; 1327 1328 static struct qcom_icc_node qhs_usb3_0 = { 1329 .name = "qhs_usb3_0", 1330 .channels = 1, 1331 .buswidth = 4, 1332 }; 1333 1334 static struct qcom_icc_node qhs_usb3_1 = { 1335 .name = "qhs_usb3_1", 1336 .channels = 1, 1337 .buswidth = 4, 1338 }; 1339 1340 static struct qcom_icc_node qhs_usb3_mp = { 1341 .name = "qhs_usb3_mp", 1342 .channels = 1, 1343 .buswidth = 4, 1344 }; 1345 1346 static struct qcom_icc_node qhs_usb4_host_0 = { 1347 .name = "qhs_usb4_host_0", 1348 .channels = 1, 1349 .buswidth = 4, 1350 }; 1351 1352 static struct qcom_icc_node qhs_usb4_host_1 = { 1353 .name = "qhs_usb4_host_1", 1354 .channels = 1, 1355 .buswidth = 4, 1356 }; 1357 1358 static struct qcom_icc_node qhs_venus_cfg = { 1359 .name = "qhs_venus_cfg", 1360 .channels = 1, 1361 .buswidth = 4, 1362 }; 1363 1364 static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 1365 .name = "qhs_vsense_ctrl_cfg", 1366 .channels = 1, 1367 .buswidth = 4, 1368 }; 1369 1370 static struct qcom_icc_node qhs_vsense_ctrl_r_cfg = { 1371 .name = "qhs_vsense_ctrl_r_cfg", 1372 .channels = 1, 1373 .buswidth = 4, 1374 }; 1375 1376 static struct qcom_icc_node qns_a1_noc_cfg = { 1377 .name = "qns_a1_noc_cfg", 1378 .channels = 1, 1379 .buswidth = 4, 1380 .num_links = 1, 1381 .link_nodes = { &qnm_a1noc_cfg }, 1382 }; 1383 1384 static struct qcom_icc_node qns_a2_noc_cfg = { 1385 .name = "qns_a2_noc_cfg", 1386 .channels = 1, 1387 .buswidth = 4, 1388 .num_links = 1, 1389 .link_nodes = { &qnm_a2noc_cfg }, 1390 }; 1391 1392 static struct qcom_icc_node qns_anoc_pcie_bridge_cfg = { 1393 .name = "qns_anoc_pcie_bridge_cfg", 1394 .channels = 1, 1395 .buswidth = 4, 1396 }; 1397 1398 static struct qcom_icc_node qns_ddrss_cfg = { 1399 .name = "qns_ddrss_cfg", 1400 .channels = 1, 1401 .buswidth = 4, 1402 .num_links = 1, 1403 .link_nodes = { &qnm_cnoc_dc_noc }, 1404 }; 1405 1406 static struct qcom_icc_node qns_mnoc_cfg = { 1407 .name = "qns_mnoc_cfg", 1408 .channels = 1, 1409 .buswidth = 4, 1410 .num_links = 1, 1411 .link_nodes = { &qnm_mnoc_cfg }, 1412 }; 1413 1414 static struct qcom_icc_node qns_snoc_cfg = { 1415 .name = "qns_snoc_cfg", 1416 .channels = 1, 1417 .buswidth = 4, 1418 .num_links = 1, 1419 .link_nodes = { &qnm_snoc_cfg }, 1420 }; 1421 1422 static struct qcom_icc_node qns_snoc_sf_bridge_cfg = { 1423 .name = "qns_snoc_sf_bridge_cfg", 1424 .channels = 1, 1425 .buswidth = 4, 1426 }; 1427 1428 static struct qcom_icc_node qxs_imem = { 1429 .name = "qxs_imem", 1430 .channels = 1, 1431 .buswidth = 8, 1432 }; 1433 1434 static struct qcom_icc_node qxs_pimem = { 1435 .name = "qxs_pimem", 1436 .channels = 1, 1437 .buswidth = 8, 1438 }; 1439 1440 static struct qcom_icc_node srvc_cnoc = { 1441 .name = "srvc_cnoc", 1442 .channels = 1, 1443 .buswidth = 4, 1444 }; 1445 1446 static struct qcom_icc_node xs_pcie_0 = { 1447 .name = "xs_pcie_0", 1448 .channels = 1, 1449 .buswidth = 16, 1450 }; 1451 1452 static struct qcom_icc_node xs_pcie_1 = { 1453 .name = "xs_pcie_1", 1454 .channels = 1, 1455 .buswidth = 16, 1456 }; 1457 1458 static struct qcom_icc_node xs_pcie_2a = { 1459 .name = "xs_pcie_2a", 1460 .channels = 1, 1461 .buswidth = 16, 1462 }; 1463 1464 static struct qcom_icc_node xs_pcie_2b = { 1465 .name = "xs_pcie_2b", 1466 .channels = 1, 1467 .buswidth = 8, 1468 }; 1469 1470 static struct qcom_icc_node xs_pcie_3a = { 1471 .name = "xs_pcie_3a", 1472 .channels = 1, 1473 .buswidth = 16, 1474 }; 1475 1476 static struct qcom_icc_node xs_pcie_3b = { 1477 .name = "xs_pcie_3b", 1478 .channels = 1, 1479 .buswidth = 8, 1480 }; 1481 1482 static struct qcom_icc_node xs_pcie_4 = { 1483 .name = "xs_pcie_4", 1484 .channels = 1, 1485 .buswidth = 8, 1486 }; 1487 1488 static struct qcom_icc_node xs_qdss_stm = { 1489 .name = "xs_qdss_stm", 1490 .channels = 1, 1491 .buswidth = 4, 1492 }; 1493 1494 static struct qcom_icc_node xs_smss = { 1495 .name = "xs_smss", 1496 .channels = 1, 1497 .buswidth = 8, 1498 }; 1499 1500 static struct qcom_icc_node xs_sys_tcu_cfg = { 1501 .name = "xs_sys_tcu_cfg", 1502 .channels = 1, 1503 .buswidth = 8, 1504 }; 1505 1506 static struct qcom_icc_node qhs_llcc = { 1507 .name = "qhs_llcc", 1508 .channels = 1, 1509 .buswidth = 4, 1510 }; 1511 1512 static struct qcom_icc_node qns_gemnoc = { 1513 .name = "qns_gemnoc", 1514 .channels = 1, 1515 .buswidth = 4, 1516 .num_links = 1, 1517 .link_nodes = { &qnm_gemnoc_cfg }, 1518 }; 1519 1520 static struct qcom_icc_node qns_gem_noc_cnoc = { 1521 .name = "qns_gem_noc_cnoc", 1522 .channels = 1, 1523 .buswidth = 16, 1524 .num_links = 1, 1525 .link_nodes = { &qnm_gemnoc_cnoc }, 1526 }; 1527 1528 static struct qcom_icc_node qns_llcc = { 1529 .name = "qns_llcc", 1530 .channels = 8, 1531 .buswidth = 16, 1532 .num_links = 1, 1533 .link_nodes = { &llcc_mc }, 1534 }; 1535 1536 static struct qcom_icc_node qns_pcie = { 1537 .name = "qns_pcie", 1538 .channels = 1, 1539 .buswidth = 16, 1540 .num_links = 1, 1541 .link_nodes = { &qnm_gemnoc_pcie }, 1542 }; 1543 1544 static struct qcom_icc_node srvc_even_gemnoc = { 1545 .name = "srvc_even_gemnoc", 1546 .channels = 1, 1547 .buswidth = 4, 1548 }; 1549 1550 static struct qcom_icc_node srvc_odd_gemnoc = { 1551 .name = "srvc_odd_gemnoc", 1552 .channels = 1, 1553 .buswidth = 4, 1554 }; 1555 1556 static struct qcom_icc_node srvc_sys_gemnoc = { 1557 .name = "srvc_sys_gemnoc", 1558 .channels = 1, 1559 .buswidth = 4, 1560 }; 1561 1562 static struct qcom_icc_node qhs_lpass_core = { 1563 .name = "qhs_lpass_core", 1564 .channels = 1, 1565 .buswidth = 4, 1566 }; 1567 1568 static struct qcom_icc_node qhs_lpass_lpi = { 1569 .name = "qhs_lpass_lpi", 1570 .channels = 1, 1571 .buswidth = 4, 1572 }; 1573 1574 static struct qcom_icc_node qhs_lpass_mpu = { 1575 .name = "qhs_lpass_mpu", 1576 .channels = 1, 1577 .buswidth = 4, 1578 }; 1579 1580 static struct qcom_icc_node qhs_lpass_top = { 1581 .name = "qhs_lpass_top", 1582 .channels = 1, 1583 .buswidth = 4, 1584 }; 1585 1586 static struct qcom_icc_node qns_sysnoc = { 1587 .name = "qns_sysnoc", 1588 .channels = 1, 1589 .buswidth = 16, 1590 .num_links = 1, 1591 .link_nodes = { &qnm_lpass_noc }, 1592 }; 1593 1594 static struct qcom_icc_node srvc_niu_aml_noc = { 1595 .name = "srvc_niu_aml_noc", 1596 .channels = 1, 1597 .buswidth = 4, 1598 }; 1599 1600 static struct qcom_icc_node srvc_niu_lpass_agnoc = { 1601 .name = "srvc_niu_lpass_agnoc", 1602 .channels = 1, 1603 .buswidth = 4, 1604 }; 1605 1606 static struct qcom_icc_node ebi = { 1607 .name = "ebi", 1608 .channels = 8, 1609 .buswidth = 4, 1610 }; 1611 1612 static struct qcom_icc_node qns_mem_noc_hf = { 1613 .name = "qns_mem_noc_hf", 1614 .channels = 2, 1615 .buswidth = 32, 1616 .num_links = 1, 1617 .link_nodes = { &qnm_mnoc_hf }, 1618 }; 1619 1620 static struct qcom_icc_node qns_mem_noc_sf = { 1621 .name = "qns_mem_noc_sf", 1622 .channels = 2, 1623 .buswidth = 32, 1624 .num_links = 1, 1625 .link_nodes = { &qnm_mnoc_sf }, 1626 }; 1627 1628 static struct qcom_icc_node srvc_mnoc = { 1629 .name = "srvc_mnoc", 1630 .channels = 1, 1631 .buswidth = 4, 1632 }; 1633 1634 static struct qcom_icc_node qns_nsp_gemnoc = { 1635 .name = "qns_nsp_gemnoc", 1636 .channels = 2, 1637 .buswidth = 32, 1638 .num_links = 1, 1639 .link_nodes = { &qnm_cmpnoc0 }, 1640 }; 1641 1642 static struct qcom_icc_node qxs_nsp_xfr = { 1643 .name = "qxs_nsp_xfr", 1644 .channels = 1, 1645 .buswidth = 32, 1646 }; 1647 1648 static struct qcom_icc_node service_nsp_noc = { 1649 .name = "service_nsp_noc", 1650 .channels = 1, 1651 .buswidth = 4, 1652 }; 1653 1654 static struct qcom_icc_node qns_nspb_gemnoc = { 1655 .name = "qns_nspb_gemnoc", 1656 .channels = 2, 1657 .buswidth = 32, 1658 .num_links = 1, 1659 .link_nodes = { &qnm_cmpnoc1 }, 1660 }; 1661 1662 static struct qcom_icc_node qxs_nspb_xfr = { 1663 .name = "qxs_nspb_xfr", 1664 .channels = 1, 1665 .buswidth = 32, 1666 }; 1667 1668 static struct qcom_icc_node service_nspb_noc = { 1669 .name = "service_nspb_noc", 1670 .channels = 1, 1671 .buswidth = 4, 1672 }; 1673 1674 static struct qcom_icc_node qns_gemnoc_gc = { 1675 .name = "qns_gemnoc_gc", 1676 .channels = 1, 1677 .buswidth = 8, 1678 .num_links = 1, 1679 .link_nodes = { &qnm_snoc_gc }, 1680 }; 1681 1682 static struct qcom_icc_node qns_gemnoc_sf = { 1683 .name = "qns_gemnoc_sf", 1684 .channels = 1, 1685 .buswidth = 16, 1686 .num_links = 1, 1687 .link_nodes = { &qnm_snoc_sf }, 1688 }; 1689 1690 static struct qcom_icc_node srvc_snoc = { 1691 .name = "srvc_snoc", 1692 .channels = 1, 1693 .buswidth = 4, 1694 }; 1695 1696 static struct qcom_icc_bcm bcm_acv = { 1697 .name = "ACV", 1698 .enable_mask = BIT(3), 1699 .num_nodes = 1, 1700 .nodes = { &ebi }, 1701 }; 1702 1703 static struct qcom_icc_bcm bcm_ce0 = { 1704 .name = "CE0", 1705 .num_nodes = 1, 1706 .nodes = { &qxm_crypto }, 1707 }; 1708 1709 static struct qcom_icc_bcm bcm_cn0 = { 1710 .name = "CN0", 1711 .keepalive = true, 1712 .num_nodes = 9, 1713 .nodes = { &qnm_gemnoc_cnoc, 1714 &qnm_gemnoc_pcie, 1715 &xs_pcie_0, 1716 &xs_pcie_1, 1717 &xs_pcie_2a, 1718 &xs_pcie_2b, 1719 &xs_pcie_3a, 1720 &xs_pcie_3b, 1721 &xs_pcie_4 1722 }, 1723 }; 1724 1725 static struct qcom_icc_bcm bcm_cn1 = { 1726 .name = "CN1", 1727 .num_nodes = 67, 1728 .nodes = { &qhs_ahb2phy0, 1729 &qhs_ahb2phy1, 1730 &qhs_ahb2phy2, 1731 &qhs_aoss, 1732 &qhs_apss, 1733 &qhs_camera_cfg, 1734 &qhs_clk_ctl, 1735 &qhs_compute0_cfg, 1736 &qhs_compute1_cfg, 1737 &qhs_cpr_cx, 1738 &qhs_cpr_mmcx, 1739 &qhs_cpr_mx, 1740 &qhs_cpr_nspcx, 1741 &qhs_crypto0_cfg, 1742 &qhs_cx_rdpm, 1743 &qhs_dcc_cfg, 1744 &qhs_display0_cfg, 1745 &qhs_display1_cfg, 1746 &qhs_emac0_cfg, 1747 &qhs_emac1_cfg, 1748 &qhs_gpuss_cfg, 1749 &qhs_hwkm, 1750 &qhs_imem_cfg, 1751 &qhs_ipa, 1752 &qhs_ipc_router, 1753 &qhs_lpass_cfg, 1754 &qhs_mx_rdpm, 1755 &qhs_mxc_rdpm, 1756 &qhs_pcie0_cfg, 1757 &qhs_pcie1_cfg, 1758 &qhs_pcie2a_cfg, 1759 &qhs_pcie2b_cfg, 1760 &qhs_pcie3a_cfg, 1761 &qhs_pcie3b_cfg, 1762 &qhs_pcie4_cfg, 1763 &qhs_pcie_rsc_cfg, 1764 &qhs_pdm, 1765 &qhs_pimem_cfg, 1766 &qhs_pka_wrapper_cfg, 1767 &qhs_pmu_wrapper_cfg, 1768 &qhs_qdss_cfg, 1769 &qhs_sdc2, 1770 &qhs_sdc4, 1771 &qhs_security, 1772 &qhs_smmuv3_cfg, 1773 &qhs_smss_cfg, 1774 &qhs_spss_cfg, 1775 &qhs_tcsr, 1776 &qhs_tlmm, 1777 &qhs_ufs_card_cfg, 1778 &qhs_ufs_mem_cfg, 1779 &qhs_usb3_0, 1780 &qhs_usb3_1, 1781 &qhs_usb3_mp, 1782 &qhs_usb4_host_0, 1783 &qhs_usb4_host_1, 1784 &qhs_venus_cfg, 1785 &qhs_vsense_ctrl_cfg, 1786 &qhs_vsense_ctrl_r_cfg, 1787 &qns_a1_noc_cfg, 1788 &qns_a2_noc_cfg, 1789 &qns_anoc_pcie_bridge_cfg, 1790 &qns_ddrss_cfg, 1791 &qns_mnoc_cfg, 1792 &qns_snoc_cfg, 1793 &qns_snoc_sf_bridge_cfg, 1794 &srvc_cnoc 1795 }, 1796 }; 1797 1798 static struct qcom_icc_bcm bcm_cn2 = { 1799 .name = "CN2", 1800 .num_nodes = 4, 1801 .nodes = { &qhs_qspi, 1802 &qhs_qup0, 1803 &qhs_qup1, 1804 &qhs_qup2 1805 }, 1806 }; 1807 1808 static struct qcom_icc_bcm bcm_cn3 = { 1809 .name = "CN3", 1810 .num_nodes = 3, 1811 .nodes = { &qxs_imem, 1812 &xs_smss, 1813 &xs_sys_tcu_cfg 1814 }, 1815 }; 1816 1817 static struct qcom_icc_bcm bcm_mc0 = { 1818 .name = "MC0", 1819 .keepalive = true, 1820 .num_nodes = 1, 1821 .nodes = { &ebi }, 1822 }; 1823 1824 static struct qcom_icc_bcm bcm_mm0 = { 1825 .name = "MM0", 1826 .keepalive = true, 1827 .num_nodes = 5, 1828 .nodes = { &qnm_camnoc_hf, 1829 &qnm_mdp0_0, 1830 &qnm_mdp0_1, 1831 &qnm_mdp1_0, 1832 &qns_mem_noc_hf 1833 }, 1834 }; 1835 1836 static struct qcom_icc_bcm bcm_mm1 = { 1837 .name = "MM1", 1838 .num_nodes = 8, 1839 .nodes = { &qnm_rot_0, 1840 &qnm_rot_1, 1841 &qnm_video0, 1842 &qnm_video1, 1843 &qnm_video_cvp, 1844 &qxm_camnoc_icp, 1845 &qxm_camnoc_sf, 1846 &qns_mem_noc_sf 1847 }, 1848 }; 1849 1850 static struct qcom_icc_bcm bcm_nsa0 = { 1851 .name = "NSA0", 1852 .num_nodes = 2, 1853 .nodes = { &qns_nsp_gemnoc, 1854 &qxs_nsp_xfr 1855 }, 1856 }; 1857 1858 static struct qcom_icc_bcm bcm_nsa1 = { 1859 .name = "NSA1", 1860 .num_nodes = 1, 1861 .nodes = { &qxm_nsp }, 1862 }; 1863 1864 static struct qcom_icc_bcm bcm_nsb0 = { 1865 .name = "NSB0", 1866 .num_nodes = 2, 1867 .nodes = { &qns_nspb_gemnoc, 1868 &qxs_nspb_xfr 1869 }, 1870 }; 1871 1872 static struct qcom_icc_bcm bcm_nsb1 = { 1873 .name = "NSB1", 1874 .num_nodes = 1, 1875 .nodes = { &qxm_nspb }, 1876 }; 1877 1878 static struct qcom_icc_bcm bcm_pci0 = { 1879 .name = "PCI0", 1880 .num_nodes = 1, 1881 .nodes = { &qns_pcie_gem_noc }, 1882 }; 1883 1884 static struct qcom_icc_bcm bcm_qup0 = { 1885 .name = "QUP0", 1886 .vote_scale = 1, 1887 .num_nodes = 1, 1888 .nodes = { &qup0_core_slave }, 1889 }; 1890 1891 static struct qcom_icc_bcm bcm_qup1 = { 1892 .name = "QUP1", 1893 .vote_scale = 1, 1894 .num_nodes = 1, 1895 .nodes = { &qup1_core_slave }, 1896 }; 1897 1898 static struct qcom_icc_bcm bcm_qup2 = { 1899 .name = "QUP2", 1900 .vote_scale = 1, 1901 .num_nodes = 1, 1902 .nodes = { &qup2_core_slave }, 1903 }; 1904 1905 static struct qcom_icc_bcm bcm_sh0 = { 1906 .name = "SH0", 1907 .keepalive = true, 1908 .num_nodes = 1, 1909 .nodes = { &qns_llcc }, 1910 }; 1911 1912 static struct qcom_icc_bcm bcm_sh2 = { 1913 .name = "SH2", 1914 .num_nodes = 1, 1915 .nodes = { &chm_apps }, 1916 }; 1917 1918 static struct qcom_icc_bcm bcm_sn0 = { 1919 .name = "SN0", 1920 .keepalive = true, 1921 .num_nodes = 1, 1922 .nodes = { &qns_gemnoc_sf }, 1923 }; 1924 1925 static struct qcom_icc_bcm bcm_sn1 = { 1926 .name = "SN1", 1927 .num_nodes = 1, 1928 .nodes = { &qns_gemnoc_gc }, 1929 }; 1930 1931 static struct qcom_icc_bcm bcm_sn2 = { 1932 .name = "SN2", 1933 .num_nodes = 1, 1934 .nodes = { &qxs_pimem }, 1935 }; 1936 1937 static struct qcom_icc_bcm bcm_sn3 = { 1938 .name = "SN3", 1939 .num_nodes = 2, 1940 .nodes = { &qns_a1noc_snoc, 1941 &qnm_aggre1_noc 1942 }, 1943 }; 1944 1945 static struct qcom_icc_bcm bcm_sn4 = { 1946 .name = "SN4", 1947 .num_nodes = 2, 1948 .nodes = { &qns_a2noc_snoc, 1949 &qnm_aggre2_noc 1950 }, 1951 }; 1952 1953 static struct qcom_icc_bcm bcm_sn5 = { 1954 .name = "SN5", 1955 .num_nodes = 2, 1956 .nodes = { &qns_aggre_usb_snoc, 1957 &qnm_aggre_usb_noc 1958 }, 1959 }; 1960 1961 static struct qcom_icc_bcm bcm_sn9 = { 1962 .name = "SN9", 1963 .num_nodes = 2, 1964 .nodes = { &qns_sysnoc, 1965 &qnm_lpass_noc 1966 }, 1967 }; 1968 1969 static struct qcom_icc_bcm bcm_sn10 = { 1970 .name = "SN10", 1971 .num_nodes = 1, 1972 .nodes = { &xs_qdss_stm }, 1973 }; 1974 1975 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 1976 &bcm_sn3, 1977 &bcm_sn5, 1978 }; 1979 1980 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1981 [MASTER_QSPI_0] = &qhm_qspi, 1982 [MASTER_QUP_1] = &qhm_qup1, 1983 [MASTER_QUP_2] = &qhm_qup2, 1984 [MASTER_A1NOC_CFG] = &qnm_a1noc_cfg, 1985 [MASTER_IPA] = &qxm_ipa, 1986 [MASTER_EMAC_1] = &xm_emac_1, 1987 [MASTER_SDCC_4] = &xm_sdc4, 1988 [MASTER_UFS_MEM] = &xm_ufs_mem, 1989 [MASTER_USB3_0] = &xm_usb3_0, 1990 [MASTER_USB3_1] = &xm_usb3_1, 1991 [MASTER_USB3_MP] = &xm_usb3_mp, 1992 [MASTER_USB4_0] = &xm_usb4_host0, 1993 [MASTER_USB4_1] = &xm_usb4_host1, 1994 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, 1995 [SLAVE_USB_NOC_SNOC] = &qns_aggre_usb_snoc, 1996 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, 1997 }; 1998 1999 static const struct qcom_icc_desc sc8280xp_aggre1_noc = { 2000 .nodes = aggre1_noc_nodes, 2001 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 2002 .bcms = aggre1_noc_bcms, 2003 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 2004 }; 2005 2006 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 2007 &bcm_ce0, 2008 &bcm_pci0, 2009 &bcm_sn4, 2010 }; 2011 2012 static struct qcom_icc_node * const aggre2_noc_nodes[] = { 2013 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 2014 [MASTER_QUP_0] = &qhm_qup0, 2015 [MASTER_A2NOC_CFG] = &qnm_a2noc_cfg, 2016 [MASTER_CRYPTO] = &qxm_crypto, 2017 [MASTER_SENSORS_PROC] = &qxm_sensorss_q6, 2018 [MASTER_SP] = &qxm_sp, 2019 [MASTER_EMAC] = &xm_emac_0, 2020 [MASTER_PCIE_0] = &xm_pcie3_0, 2021 [MASTER_PCIE_1] = &xm_pcie3_1, 2022 [MASTER_PCIE_2A] = &xm_pcie3_2a, 2023 [MASTER_PCIE_2B] = &xm_pcie3_2b, 2024 [MASTER_PCIE_3A] = &xm_pcie3_3a, 2025 [MASTER_PCIE_3B] = &xm_pcie3_3b, 2026 [MASTER_PCIE_4] = &xm_pcie3_4, 2027 [MASTER_QDSS_ETR] = &xm_qdss_etr, 2028 [MASTER_SDCC_2] = &xm_sdc2, 2029 [MASTER_UFS_CARD] = &xm_ufs_card, 2030 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, 2031 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_gem_noc, 2032 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, 2033 }; 2034 2035 static const struct qcom_icc_desc sc8280xp_aggre2_noc = { 2036 .nodes = aggre2_noc_nodes, 2037 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 2038 .bcms = aggre2_noc_bcms, 2039 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 2040 }; 2041 2042 static struct qcom_icc_bcm * const clk_virt_bcms[] = { 2043 &bcm_qup0, 2044 &bcm_qup1, 2045 &bcm_qup2, 2046 }; 2047 2048 static struct qcom_icc_node * const clk_virt_nodes[] = { 2049 [MASTER_QUP_CORE_0] = &qup0_core_master, 2050 [MASTER_QUP_CORE_1] = &qup1_core_master, 2051 [MASTER_QUP_CORE_2] = &qup2_core_master, 2052 [SLAVE_QUP_CORE_0] = &qup0_core_slave, 2053 [SLAVE_QUP_CORE_1] = &qup1_core_slave, 2054 [SLAVE_QUP_CORE_2] = &qup2_core_slave, 2055 }; 2056 2057 static const struct qcom_icc_desc sc8280xp_clk_virt = { 2058 .nodes = clk_virt_nodes, 2059 .num_nodes = ARRAY_SIZE(clk_virt_nodes), 2060 .bcms = clk_virt_bcms, 2061 .num_bcms = ARRAY_SIZE(clk_virt_bcms), 2062 }; 2063 2064 static struct qcom_icc_bcm * const config_noc_bcms[] = { 2065 &bcm_cn0, 2066 &bcm_cn1, 2067 &bcm_cn2, 2068 &bcm_cn3, 2069 &bcm_sn2, 2070 &bcm_sn10, 2071 }; 2072 2073 static struct qcom_icc_node * const config_noc_nodes[] = { 2074 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, 2075 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, 2076 [SLAVE_AHB2PHY_0] = &qhs_ahb2phy0, 2077 [SLAVE_AHB2PHY_1] = &qhs_ahb2phy1, 2078 [SLAVE_AHB2PHY_2] = &qhs_ahb2phy2, 2079 [SLAVE_AOSS] = &qhs_aoss, 2080 [SLAVE_APPSS] = &qhs_apss, 2081 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 2082 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 2083 [SLAVE_CDSP_CFG] = &qhs_compute0_cfg, 2084 [SLAVE_CDSP1_CFG] = &qhs_compute1_cfg, 2085 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 2086 [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx, 2087 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, 2088 [SLAVE_CPR_NSPCX] = &qhs_cpr_nspcx, 2089 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 2090 [SLAVE_CX_RDPM] = &qhs_cx_rdpm, 2091 [SLAVE_DCC_CFG] = &qhs_dcc_cfg, 2092 [SLAVE_DISPLAY_CFG] = &qhs_display0_cfg, 2093 [SLAVE_DISPLAY1_CFG] = &qhs_display1_cfg, 2094 [SLAVE_EMAC_CFG] = &qhs_emac0_cfg, 2095 [SLAVE_EMAC1_CFG] = &qhs_emac1_cfg, 2096 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, 2097 [SLAVE_HWKM] = &qhs_hwkm, 2098 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 2099 [SLAVE_IPA_CFG] = &qhs_ipa, 2100 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, 2101 [SLAVE_LPASS] = &qhs_lpass_cfg, 2102 [SLAVE_MX_RDPM] = &qhs_mx_rdpm, 2103 [SLAVE_MXC_RDPM] = &qhs_mxc_rdpm, 2104 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, 2105 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, 2106 [SLAVE_PCIE_2A_CFG] = &qhs_pcie2a_cfg, 2107 [SLAVE_PCIE_2B_CFG] = &qhs_pcie2b_cfg, 2108 [SLAVE_PCIE_3A_CFG] = &qhs_pcie3a_cfg, 2109 [SLAVE_PCIE_3B_CFG] = &qhs_pcie3b_cfg, 2110 [SLAVE_PCIE_4_CFG] = &qhs_pcie4_cfg, 2111 [SLAVE_PCIE_RSC_CFG] = &qhs_pcie_rsc_cfg, 2112 [SLAVE_PDM] = &qhs_pdm, 2113 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 2114 [SLAVE_PKA_WRAPPER_CFG] = &qhs_pka_wrapper_cfg, 2115 [SLAVE_PMU_WRAPPER_CFG] = &qhs_pmu_wrapper_cfg, 2116 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 2117 [SLAVE_QSPI_0] = &qhs_qspi, 2118 [SLAVE_QUP_0] = &qhs_qup0, 2119 [SLAVE_QUP_1] = &qhs_qup1, 2120 [SLAVE_QUP_2] = &qhs_qup2, 2121 [SLAVE_SDCC_2] = &qhs_sdc2, 2122 [SLAVE_SDCC_4] = &qhs_sdc4, 2123 [SLAVE_SECURITY] = &qhs_security, 2124 [SLAVE_SMMUV3_CFG] = &qhs_smmuv3_cfg, 2125 [SLAVE_SMSS_CFG] = &qhs_smss_cfg, 2126 [SLAVE_SPSS_CFG] = &qhs_spss_cfg, 2127 [SLAVE_TCSR] = &qhs_tcsr, 2128 [SLAVE_TLMM] = &qhs_tlmm, 2129 [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg, 2130 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 2131 [SLAVE_USB3_0] = &qhs_usb3_0, 2132 [SLAVE_USB3_1] = &qhs_usb3_1, 2133 [SLAVE_USB3_MP] = &qhs_usb3_mp, 2134 [SLAVE_USB4_0] = &qhs_usb4_host_0, 2135 [SLAVE_USB4_1] = &qhs_usb4_host_1, 2136 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 2137 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 2138 [SLAVE_VSENSE_CTRL_R_CFG] = &qhs_vsense_ctrl_r_cfg, 2139 [SLAVE_A1NOC_CFG] = &qns_a1_noc_cfg, 2140 [SLAVE_A2NOC_CFG] = &qns_a2_noc_cfg, 2141 [SLAVE_ANOC_PCIE_BRIDGE_CFG] = &qns_anoc_pcie_bridge_cfg, 2142 [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg, 2143 [SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg, 2144 [SLAVE_SNOC_CFG] = &qns_snoc_cfg, 2145 [SLAVE_SNOC_SF_BRIDGE_CFG] = &qns_snoc_sf_bridge_cfg, 2146 [SLAVE_IMEM] = &qxs_imem, 2147 [SLAVE_PIMEM] = &qxs_pimem, 2148 [SLAVE_SERVICE_CNOC] = &srvc_cnoc, 2149 [SLAVE_PCIE_0] = &xs_pcie_0, 2150 [SLAVE_PCIE_1] = &xs_pcie_1, 2151 [SLAVE_PCIE_2A] = &xs_pcie_2a, 2152 [SLAVE_PCIE_2B] = &xs_pcie_2b, 2153 [SLAVE_PCIE_3A] = &xs_pcie_3a, 2154 [SLAVE_PCIE_3B] = &xs_pcie_3b, 2155 [SLAVE_PCIE_4] = &xs_pcie_4, 2156 [SLAVE_QDSS_STM] = &xs_qdss_stm, 2157 [SLAVE_SMSS] = &xs_smss, 2158 [SLAVE_TCU] = &xs_sys_tcu_cfg, 2159 }; 2160 2161 static const struct qcom_icc_desc sc8280xp_config_noc = { 2162 .nodes = config_noc_nodes, 2163 .num_nodes = ARRAY_SIZE(config_noc_nodes), 2164 .bcms = config_noc_bcms, 2165 .num_bcms = ARRAY_SIZE(config_noc_bcms), 2166 }; 2167 2168 static struct qcom_icc_bcm * const dc_noc_bcms[] = { 2169 }; 2170 2171 static struct qcom_icc_node * const dc_noc_nodes[] = { 2172 [MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc, 2173 [SLAVE_LLCC_CFG] = &qhs_llcc, 2174 [SLAVE_GEM_NOC_CFG] = &qns_gemnoc, 2175 }; 2176 2177 static const struct qcom_icc_desc sc8280xp_dc_noc = { 2178 .nodes = dc_noc_nodes, 2179 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 2180 .bcms = dc_noc_bcms, 2181 .num_bcms = ARRAY_SIZE(dc_noc_bcms), 2182 }; 2183 2184 static struct qcom_icc_bcm * const gem_noc_bcms[] = { 2185 &bcm_sh0, 2186 &bcm_sh2, 2187 }; 2188 2189 static struct qcom_icc_node * const gem_noc_nodes[] = { 2190 [MASTER_GPU_TCU] = &alm_gpu_tcu, 2191 [MASTER_PCIE_TCU] = &alm_pcie_tcu, 2192 [MASTER_SYS_TCU] = &alm_sys_tcu, 2193 [MASTER_APPSS_PROC] = &chm_apps, 2194 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc0, 2195 [MASTER_COMPUTE_NOC_1] = &qnm_cmpnoc1, 2196 [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg, 2197 [MASTER_GFX3D] = &qnm_gpu, 2198 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 2199 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 2200 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, 2201 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 2202 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 2203 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, 2204 [SLAVE_LLCC] = &qns_llcc, 2205 [SLAVE_GEM_NOC_PCIE_CNOC] = &qns_pcie, 2206 [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc, 2207 [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc, 2208 [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc, 2209 }; 2210 2211 static const struct qcom_icc_desc sc8280xp_gem_noc = { 2212 .nodes = gem_noc_nodes, 2213 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 2214 .bcms = gem_noc_bcms, 2215 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 2216 }; 2217 2218 static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = { 2219 &bcm_sn9, 2220 }; 2221 2222 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { 2223 [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc, 2224 [MASTER_LPASS_PROC] = &qxm_lpass_dsp, 2225 [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core, 2226 [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi, 2227 [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu, 2228 [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top, 2229 [SLAVE_LPASS_SNOC] = &qns_sysnoc, 2230 [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc, 2231 [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, 2232 }; 2233 2234 static const struct qcom_icc_desc sc8280xp_lpass_ag_noc = { 2235 .nodes = lpass_ag_noc_nodes, 2236 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), 2237 .bcms = lpass_ag_noc_bcms, 2238 .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms), 2239 }; 2240 2241 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 2242 &bcm_acv, 2243 &bcm_mc0, 2244 }; 2245 2246 static struct qcom_icc_node * const mc_virt_nodes[] = { 2247 [MASTER_LLCC] = &llcc_mc, 2248 [SLAVE_EBI1] = &ebi, 2249 }; 2250 2251 static const struct qcom_icc_desc sc8280xp_mc_virt = { 2252 .nodes = mc_virt_nodes, 2253 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 2254 .bcms = mc_virt_bcms, 2255 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 2256 }; 2257 2258 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 2259 &bcm_mm0, 2260 &bcm_mm1, 2261 }; 2262 2263 static struct qcom_icc_node * const mmss_noc_nodes[] = { 2264 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, 2265 [MASTER_MDP0] = &qnm_mdp0_0, 2266 [MASTER_MDP1] = &qnm_mdp0_1, 2267 [MASTER_MDP_CORE1_0] = &qnm_mdp1_0, 2268 [MASTER_MDP_CORE1_1] = &qnm_mdp1_1, 2269 [MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg, 2270 [MASTER_ROTATOR] = &qnm_rot_0, 2271 [MASTER_ROTATOR_1] = &qnm_rot_1, 2272 [MASTER_VIDEO_P0] = &qnm_video0, 2273 [MASTER_VIDEO_P1] = &qnm_video1, 2274 [MASTER_VIDEO_PROC] = &qnm_video_cvp, 2275 [MASTER_CAMNOC_ICP] = &qxm_camnoc_icp, 2276 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf, 2277 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 2278 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, 2279 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 2280 }; 2281 2282 static const struct qcom_icc_desc sc8280xp_mmss_noc = { 2283 .nodes = mmss_noc_nodes, 2284 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 2285 .bcms = mmss_noc_bcms, 2286 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 2287 }; 2288 2289 static struct qcom_icc_bcm * const nspa_noc_bcms[] = { 2290 &bcm_nsa0, 2291 &bcm_nsa1, 2292 }; 2293 2294 static struct qcom_icc_node * const nspa_noc_nodes[] = { 2295 [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config, 2296 [MASTER_CDSP_PROC] = &qxm_nsp, 2297 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, 2298 [SLAVE_NSP_XFR] = &qxs_nsp_xfr, 2299 [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, 2300 }; 2301 2302 static const struct qcom_icc_desc sc8280xp_nspa_noc = { 2303 .nodes = nspa_noc_nodes, 2304 .num_nodes = ARRAY_SIZE(nspa_noc_nodes), 2305 .bcms = nspa_noc_bcms, 2306 .num_bcms = ARRAY_SIZE(nspa_noc_bcms), 2307 }; 2308 2309 static struct qcom_icc_bcm * const nspb_noc_bcms[] = { 2310 &bcm_nsb0, 2311 &bcm_nsb1, 2312 }; 2313 2314 static struct qcom_icc_node * const nspb_noc_nodes[] = { 2315 [MASTER_CDSPB_NOC_CFG] = &qhm_nspb_noc_config, 2316 [MASTER_CDSP_PROC_B] = &qxm_nspb, 2317 [SLAVE_CDSPB_MEM_NOC] = &qns_nspb_gemnoc, 2318 [SLAVE_NSPB_XFR] = &qxs_nspb_xfr, 2319 [SLAVE_SERVICE_NSPB_NOC] = &service_nspb_noc, 2320 }; 2321 2322 static const struct qcom_icc_desc sc8280xp_nspb_noc = { 2323 .nodes = nspb_noc_nodes, 2324 .num_nodes = ARRAY_SIZE(nspb_noc_nodes), 2325 .bcms = nspb_noc_bcms, 2326 .num_bcms = ARRAY_SIZE(nspb_noc_bcms), 2327 }; 2328 2329 static struct qcom_icc_bcm * const system_noc_main_bcms[] = { 2330 &bcm_sn0, 2331 &bcm_sn1, 2332 &bcm_sn3, 2333 &bcm_sn4, 2334 &bcm_sn5, 2335 &bcm_sn9, 2336 }; 2337 2338 static struct qcom_icc_node * const system_noc_main_nodes[] = { 2339 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, 2340 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, 2341 [MASTER_USB_NOC_SNOC] = &qnm_aggre_usb_noc, 2342 [MASTER_LPASS_ANOC] = &qnm_lpass_noc, 2343 [MASTER_SNOC_CFG] = &qnm_snoc_cfg, 2344 [MASTER_PIMEM] = &qxm_pimem, 2345 [MASTER_GIC] = &xm_gic, 2346 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, 2347 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 2348 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 2349 }; 2350 2351 static const struct qcom_icc_desc sc8280xp_system_noc_main = { 2352 .nodes = system_noc_main_nodes, 2353 .num_nodes = ARRAY_SIZE(system_noc_main_nodes), 2354 .bcms = system_noc_main_bcms, 2355 .num_bcms = ARRAY_SIZE(system_noc_main_bcms), 2356 }; 2357 2358 static const struct of_device_id qnoc_of_match[] = { 2359 { .compatible = "qcom,sc8280xp-aggre1-noc", .data = &sc8280xp_aggre1_noc, }, 2360 { .compatible = "qcom,sc8280xp-aggre2-noc", .data = &sc8280xp_aggre2_noc, }, 2361 { .compatible = "qcom,sc8280xp-clk-virt", .data = &sc8280xp_clk_virt, }, 2362 { .compatible = "qcom,sc8280xp-config-noc", .data = &sc8280xp_config_noc, }, 2363 { .compatible = "qcom,sc8280xp-dc-noc", .data = &sc8280xp_dc_noc, }, 2364 { .compatible = "qcom,sc8280xp-gem-noc", .data = &sc8280xp_gem_noc, }, 2365 { .compatible = "qcom,sc8280xp-lpass-ag-noc", .data = &sc8280xp_lpass_ag_noc, }, 2366 { .compatible = "qcom,sc8280xp-mc-virt", .data = &sc8280xp_mc_virt, }, 2367 { .compatible = "qcom,sc8280xp-mmss-noc", .data = &sc8280xp_mmss_noc, }, 2368 { .compatible = "qcom,sc8280xp-nspa-noc", .data = &sc8280xp_nspa_noc, }, 2369 { .compatible = "qcom,sc8280xp-nspb-noc", .data = &sc8280xp_nspb_noc, }, 2370 { .compatible = "qcom,sc8280xp-system-noc", .data = &sc8280xp_system_noc_main, }, 2371 { } 2372 }; 2373 MODULE_DEVICE_TABLE(of, qnoc_of_match); 2374 2375 static struct platform_driver qnoc_driver = { 2376 .probe = qcom_icc_rpmh_probe, 2377 .remove = qcom_icc_rpmh_remove, 2378 .driver = { 2379 .name = "qnoc-sc8280xp", 2380 .of_match_table = qnoc_of_match, 2381 .sync_state = icc_sync_state, 2382 }, 2383 }; 2384 2385 static int __init qnoc_driver_init(void) 2386 { 2387 return platform_driver_register(&qnoc_driver); 2388 } 2389 core_initcall(qnoc_driver_init); 2390 2391 static void __exit qnoc_driver_exit(void) 2392 { 2393 platform_driver_unregister(&qnoc_driver); 2394 } 2395 module_exit(qnoc_driver_exit); 2396 2397 MODULE_DESCRIPTION("Qualcomm SC8280XP NoC driver"); 2398 MODULE_LICENSE("GPL"); 2399