1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Linaro Ltd 5 */ 6 7 #include <linux/device.h> 8 #include <linux/interconnect.h> 9 #include <linux/interconnect-provider.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include <dt-bindings/interconnect/qcom,sc8280xp.h> 13 14 #include "bcm-voter.h" 15 #include "icc-rpmh.h" 16 17 static struct qcom_icc_node qhm_qspi; 18 static struct qcom_icc_node qhm_qup1; 19 static struct qcom_icc_node qhm_qup2; 20 static struct qcom_icc_node qnm_a1noc_cfg; 21 static struct qcom_icc_node qxm_ipa; 22 static struct qcom_icc_node xm_emac_1; 23 static struct qcom_icc_node xm_sdc4; 24 static struct qcom_icc_node xm_ufs_mem; 25 static struct qcom_icc_node xm_usb3_0; 26 static struct qcom_icc_node xm_usb3_1; 27 static struct qcom_icc_node xm_usb3_mp; 28 static struct qcom_icc_node xm_usb4_host0; 29 static struct qcom_icc_node xm_usb4_host1; 30 static struct qcom_icc_node qhm_qdss_bam; 31 static struct qcom_icc_node qhm_qup0; 32 static struct qcom_icc_node qnm_a2noc_cfg; 33 static struct qcom_icc_node qxm_crypto; 34 static struct qcom_icc_node qxm_sensorss_q6; 35 static struct qcom_icc_node qxm_sp; 36 static struct qcom_icc_node xm_emac_0; 37 static struct qcom_icc_node xm_pcie3_0; 38 static struct qcom_icc_node xm_pcie3_1; 39 static struct qcom_icc_node xm_pcie3_2a; 40 static struct qcom_icc_node xm_pcie3_2b; 41 static struct qcom_icc_node xm_pcie3_3a; 42 static struct qcom_icc_node xm_pcie3_3b; 43 static struct qcom_icc_node xm_pcie3_4; 44 static struct qcom_icc_node xm_qdss_etr; 45 static struct qcom_icc_node xm_sdc2; 46 static struct qcom_icc_node xm_ufs_card; 47 static struct qcom_icc_node qup0_core_master; 48 static struct qcom_icc_node qup1_core_master; 49 static struct qcom_icc_node qup2_core_master; 50 static struct qcom_icc_node qnm_gemnoc_cnoc; 51 static struct qcom_icc_node qnm_gemnoc_pcie; 52 static struct qcom_icc_node qnm_cnoc_dc_noc; 53 static struct qcom_icc_node alm_gpu_tcu; 54 static struct qcom_icc_node alm_pcie_tcu; 55 static struct qcom_icc_node alm_sys_tcu; 56 static struct qcom_icc_node chm_apps; 57 static struct qcom_icc_node qnm_cmpnoc0; 58 static struct qcom_icc_node qnm_cmpnoc1; 59 static struct qcom_icc_node qnm_gemnoc_cfg; 60 static struct qcom_icc_node qnm_gpu; 61 static struct qcom_icc_node qnm_mnoc_hf; 62 static struct qcom_icc_node qnm_mnoc_sf; 63 static struct qcom_icc_node qnm_pcie; 64 static struct qcom_icc_node qnm_snoc_gc; 65 static struct qcom_icc_node qnm_snoc_sf; 66 static struct qcom_icc_node qhm_config_noc; 67 static struct qcom_icc_node qxm_lpass_dsp; 68 static struct qcom_icc_node llcc_mc; 69 static struct qcom_icc_node qnm_camnoc_hf; 70 static struct qcom_icc_node qnm_mdp0_0; 71 static struct qcom_icc_node qnm_mdp0_1; 72 static struct qcom_icc_node qnm_mdp1_0; 73 static struct qcom_icc_node qnm_mdp1_1; 74 static struct qcom_icc_node qnm_mnoc_cfg; 75 static struct qcom_icc_node qnm_rot_0; 76 static struct qcom_icc_node qnm_rot_1; 77 static struct qcom_icc_node qnm_video0; 78 static struct qcom_icc_node qnm_video1; 79 static struct qcom_icc_node qnm_video_cvp; 80 static struct qcom_icc_node qxm_camnoc_icp; 81 static struct qcom_icc_node qxm_camnoc_sf; 82 static struct qcom_icc_node qhm_nsp_noc_config; 83 static struct qcom_icc_node qxm_nsp; 84 static struct qcom_icc_node qhm_nspb_noc_config; 85 static struct qcom_icc_node qxm_nspb; 86 static struct qcom_icc_node qnm_aggre1_noc; 87 static struct qcom_icc_node qnm_aggre2_noc; 88 static struct qcom_icc_node qnm_aggre_usb_noc; 89 static struct qcom_icc_node qnm_lpass_noc; 90 static struct qcom_icc_node qnm_snoc_cfg; 91 static struct qcom_icc_node qxm_pimem; 92 static struct qcom_icc_node xm_gic; 93 static struct qcom_icc_node qns_a1noc_snoc; 94 static struct qcom_icc_node qns_aggre_usb_snoc; 95 static struct qcom_icc_node srvc_aggre1_noc; 96 static struct qcom_icc_node qns_a2noc_snoc; 97 static struct qcom_icc_node qns_pcie_gem_noc; 98 static struct qcom_icc_node srvc_aggre2_noc; 99 static struct qcom_icc_node qup0_core_slave; 100 static struct qcom_icc_node qup1_core_slave; 101 static struct qcom_icc_node qup2_core_slave; 102 static struct qcom_icc_node qhs_ahb2phy0; 103 static struct qcom_icc_node qhs_ahb2phy1; 104 static struct qcom_icc_node qhs_ahb2phy2; 105 static struct qcom_icc_node qhs_aoss; 106 static struct qcom_icc_node qhs_apss; 107 static struct qcom_icc_node qhs_camera_cfg; 108 static struct qcom_icc_node qhs_clk_ctl; 109 static struct qcom_icc_node qhs_compute0_cfg; 110 static struct qcom_icc_node qhs_compute1_cfg; 111 static struct qcom_icc_node qhs_cpr_cx; 112 static struct qcom_icc_node qhs_cpr_mmcx; 113 static struct qcom_icc_node qhs_cpr_mx; 114 static struct qcom_icc_node qhs_cpr_nspcx; 115 static struct qcom_icc_node qhs_crypto0_cfg; 116 static struct qcom_icc_node qhs_cx_rdpm; 117 static struct qcom_icc_node qhs_dcc_cfg; 118 static struct qcom_icc_node qhs_display0_cfg; 119 static struct qcom_icc_node qhs_display1_cfg; 120 static struct qcom_icc_node qhs_emac0_cfg; 121 static struct qcom_icc_node qhs_emac1_cfg; 122 static struct qcom_icc_node qhs_gpuss_cfg; 123 static struct qcom_icc_node qhs_hwkm; 124 static struct qcom_icc_node qhs_imem_cfg; 125 static struct qcom_icc_node qhs_ipa; 126 static struct qcom_icc_node qhs_ipc_router; 127 static struct qcom_icc_node qhs_lpass_cfg; 128 static struct qcom_icc_node qhs_mx_rdpm; 129 static struct qcom_icc_node qhs_mxc_rdpm; 130 static struct qcom_icc_node qhs_pcie0_cfg; 131 static struct qcom_icc_node qhs_pcie1_cfg; 132 static struct qcom_icc_node qhs_pcie2a_cfg; 133 static struct qcom_icc_node qhs_pcie2b_cfg; 134 static struct qcom_icc_node qhs_pcie3a_cfg; 135 static struct qcom_icc_node qhs_pcie3b_cfg; 136 static struct qcom_icc_node qhs_pcie4_cfg; 137 static struct qcom_icc_node qhs_pcie_rsc_cfg; 138 static struct qcom_icc_node qhs_pdm; 139 static struct qcom_icc_node qhs_pimem_cfg; 140 static struct qcom_icc_node qhs_pka_wrapper_cfg; 141 static struct qcom_icc_node qhs_pmu_wrapper_cfg; 142 static struct qcom_icc_node qhs_qdss_cfg; 143 static struct qcom_icc_node qhs_qspi; 144 static struct qcom_icc_node qhs_qup0; 145 static struct qcom_icc_node qhs_qup1; 146 static struct qcom_icc_node qhs_qup2; 147 static struct qcom_icc_node qhs_sdc2; 148 static struct qcom_icc_node qhs_sdc4; 149 static struct qcom_icc_node qhs_security; 150 static struct qcom_icc_node qhs_smmuv3_cfg; 151 static struct qcom_icc_node qhs_smss_cfg; 152 static struct qcom_icc_node qhs_spss_cfg; 153 static struct qcom_icc_node qhs_tcsr; 154 static struct qcom_icc_node qhs_tlmm; 155 static struct qcom_icc_node qhs_ufs_card_cfg; 156 static struct qcom_icc_node qhs_ufs_mem_cfg; 157 static struct qcom_icc_node qhs_usb3_0; 158 static struct qcom_icc_node qhs_usb3_1; 159 static struct qcom_icc_node qhs_usb3_mp; 160 static struct qcom_icc_node qhs_usb4_host_0; 161 static struct qcom_icc_node qhs_usb4_host_1; 162 static struct qcom_icc_node qhs_venus_cfg; 163 static struct qcom_icc_node qhs_vsense_ctrl_cfg; 164 static struct qcom_icc_node qhs_vsense_ctrl_r_cfg; 165 static struct qcom_icc_node qns_a1_noc_cfg; 166 static struct qcom_icc_node qns_a2_noc_cfg; 167 static struct qcom_icc_node qns_anoc_pcie_bridge_cfg; 168 static struct qcom_icc_node qns_ddrss_cfg; 169 static struct qcom_icc_node qns_mnoc_cfg; 170 static struct qcom_icc_node qns_snoc_cfg; 171 static struct qcom_icc_node qns_snoc_sf_bridge_cfg; 172 static struct qcom_icc_node qxs_imem; 173 static struct qcom_icc_node qxs_pimem; 174 static struct qcom_icc_node srvc_cnoc; 175 static struct qcom_icc_node xs_pcie_0; 176 static struct qcom_icc_node xs_pcie_1; 177 static struct qcom_icc_node xs_pcie_2a; 178 static struct qcom_icc_node xs_pcie_2b; 179 static struct qcom_icc_node xs_pcie_3a; 180 static struct qcom_icc_node xs_pcie_3b; 181 static struct qcom_icc_node xs_pcie_4; 182 static struct qcom_icc_node xs_qdss_stm; 183 static struct qcom_icc_node xs_smss; 184 static struct qcom_icc_node xs_sys_tcu_cfg; 185 static struct qcom_icc_node qhs_llcc; 186 static struct qcom_icc_node qns_gemnoc; 187 static struct qcom_icc_node qns_gem_noc_cnoc; 188 static struct qcom_icc_node qns_llcc; 189 static struct qcom_icc_node qns_pcie; 190 static struct qcom_icc_node srvc_even_gemnoc; 191 static struct qcom_icc_node srvc_odd_gemnoc; 192 static struct qcom_icc_node srvc_sys_gemnoc; 193 static struct qcom_icc_node qhs_lpass_core; 194 static struct qcom_icc_node qhs_lpass_lpi; 195 static struct qcom_icc_node qhs_lpass_mpu; 196 static struct qcom_icc_node qhs_lpass_top; 197 static struct qcom_icc_node qns_sysnoc; 198 static struct qcom_icc_node srvc_niu_aml_noc; 199 static struct qcom_icc_node srvc_niu_lpass_agnoc; 200 static struct qcom_icc_node ebi; 201 static struct qcom_icc_node qns_mem_noc_hf; 202 static struct qcom_icc_node qns_mem_noc_sf; 203 static struct qcom_icc_node srvc_mnoc; 204 static struct qcom_icc_node qns_nsp_gemnoc; 205 static struct qcom_icc_node qxs_nsp_xfr; 206 static struct qcom_icc_node service_nsp_noc; 207 static struct qcom_icc_node qns_nspb_gemnoc; 208 static struct qcom_icc_node qxs_nspb_xfr; 209 static struct qcom_icc_node service_nspb_noc; 210 static struct qcom_icc_node qns_gemnoc_gc; 211 static struct qcom_icc_node qns_gemnoc_sf; 212 static struct qcom_icc_node srvc_snoc; 213 214 static struct qcom_icc_node qhm_qspi = { 215 .name = "qhm_qspi", 216 .channels = 1, 217 .buswidth = 4, 218 .qosbox = &(const struct qcom_icc_qosbox) { 219 .num_ports = 1, 220 .port_offsets = { 0x5000 }, 221 .prio = 2, 222 }, 223 .num_links = 1, 224 .link_nodes = { &qns_a1noc_snoc }, 225 }; 226 227 static struct qcom_icc_node qhm_qup1 = { 228 .name = "qhm_qup1", 229 .channels = 1, 230 .buswidth = 4, 231 .qosbox = &(const struct qcom_icc_qosbox) { 232 .num_ports = 1, 233 .port_offsets = { 0x6000 }, 234 .prio = 2, 235 }, 236 .num_links = 1, 237 .link_nodes = { &qns_a1noc_snoc }, 238 }; 239 240 static struct qcom_icc_node qhm_qup2 = { 241 .name = "qhm_qup2", 242 .channels = 1, 243 .buswidth = 4, 244 .qosbox = &(const struct qcom_icc_qosbox) { 245 .num_ports = 1, 246 .port_offsets = { 0xc000 }, 247 .prio = 2, 248 }, 249 .num_links = 1, 250 .link_nodes = { &qns_a1noc_snoc }, 251 }; 252 253 static struct qcom_icc_node qnm_a1noc_cfg = { 254 .name = "qnm_a1noc_cfg", 255 .channels = 1, 256 .buswidth = 4, 257 .num_links = 1, 258 .link_nodes = { &srvc_aggre1_noc }, 259 }; 260 261 static struct qcom_icc_node qxm_ipa = { 262 .name = "qxm_ipa", 263 .channels = 1, 264 .buswidth = 8, 265 .qosbox = &(const struct qcom_icc_qosbox) { 266 .num_ports = 1, 267 .port_offsets = { 0x8000 }, 268 .prio = 2, 269 .urg_fwd = 1, 270 }, 271 .num_links = 1, 272 .link_nodes = { &qns_a1noc_snoc }, 273 }; 274 275 static struct qcom_icc_node xm_emac_1 = { 276 .name = "xm_emac_1", 277 .channels = 1, 278 .buswidth = 8, 279 .qosbox = &(const struct qcom_icc_qosbox) { 280 .num_ports = 1, 281 .port_offsets = { 0xd000 }, 282 .prio = 2, 283 }, 284 .num_links = 1, 285 .link_nodes = { &qns_a1noc_snoc }, 286 }; 287 288 static struct qcom_icc_node xm_sdc4 = { 289 .name = "xm_sdc4", 290 .channels = 1, 291 .buswidth = 8, 292 .qosbox = &(const struct qcom_icc_qosbox) { 293 .num_ports = 1, 294 .port_offsets = { 0x7000 }, 295 .prio = 2, 296 }, 297 .num_links = 1, 298 .link_nodes = { &qns_a1noc_snoc }, 299 }; 300 301 static struct qcom_icc_node xm_ufs_mem = { 302 .name = "xm_ufs_mem", 303 .channels = 1, 304 .buswidth = 8, 305 .qosbox = &(const struct qcom_icc_qosbox) { 306 .num_ports = 1, 307 .port_offsets = { 0x9000 }, 308 .prio = 2, 309 }, 310 .num_links = 1, 311 .link_nodes = { &qns_a1noc_snoc }, 312 }; 313 314 static struct qcom_icc_node xm_usb3_0 = { 315 .name = "xm_usb3_0", 316 .channels = 1, 317 .buswidth = 8, 318 .qosbox = &(const struct qcom_icc_qosbox) { 319 .num_ports = 1, 320 .port_offsets = { 0xb000 }, 321 .prio = 2, 322 }, 323 .num_links = 1, 324 .link_nodes = { &qns_aggre_usb_snoc }, 325 }; 326 327 static struct qcom_icc_node xm_usb3_1 = { 328 .name = "xm_usb3_1", 329 .channels = 1, 330 .buswidth = 8, 331 .qosbox = &(const struct qcom_icc_qosbox) { 332 .num_ports = 1, 333 .port_offsets = { 0xa000 }, 334 .prio = 2, 335 }, 336 .num_links = 1, 337 .link_nodes = { &qns_aggre_usb_snoc }, 338 }; 339 340 static struct qcom_icc_node xm_usb3_mp = { 341 .name = "xm_usb3_mp", 342 .channels = 1, 343 .buswidth = 16, 344 .qosbox = &(const struct qcom_icc_qosbox) { 345 .num_ports = 1, 346 .port_offsets = { 0xe000 }, 347 .prio = 2, 348 }, 349 .num_links = 1, 350 .link_nodes = { &qns_aggre_usb_snoc }, 351 }; 352 353 static struct qcom_icc_node xm_usb4_host0 = { 354 .name = "xm_usb4_host0", 355 .channels = 1, 356 .buswidth = 16, 357 .qosbox = &(const struct qcom_icc_qosbox) { 358 .num_ports = 1, 359 .port_offsets = { 0xf000 }, 360 .prio = 2, 361 }, 362 .num_links = 1, 363 .link_nodes = { &qns_aggre_usb_snoc }, 364 }; 365 366 static struct qcom_icc_node xm_usb4_host1 = { 367 .name = "xm_usb4_host1", 368 .channels = 1, 369 .buswidth = 16, 370 .qosbox = &(const struct qcom_icc_qosbox) { 371 .num_ports = 1, 372 .port_offsets = { 0x10000 }, 373 .prio = 2, 374 }, 375 .num_links = 1, 376 .link_nodes = { &qns_aggre_usb_snoc }, 377 }; 378 379 static struct qcom_icc_node qhm_qdss_bam = { 380 .name = "qhm_qdss_bam", 381 .channels = 1, 382 .buswidth = 4, 383 .qosbox = &(const struct qcom_icc_qosbox) { 384 .num_ports = 1, 385 .port_offsets = { 0xa000 }, 386 .prio = 2, 387 }, 388 .num_links = 1, 389 .link_nodes = { &qns_a2noc_snoc }, 390 }; 391 392 static struct qcom_icc_node qhm_qup0 = { 393 .name = "qhm_qup0", 394 .channels = 1, 395 .buswidth = 4, 396 .qosbox = &(const struct qcom_icc_qosbox) { 397 .num_ports = 1, 398 .port_offsets = { 0xb000 }, 399 .prio = 2, 400 }, 401 .num_links = 1, 402 .link_nodes = { &qns_a2noc_snoc }, 403 }; 404 405 static struct qcom_icc_node qnm_a2noc_cfg = { 406 .name = "qnm_a2noc_cfg", 407 .channels = 1, 408 .buswidth = 4, 409 .num_links = 1, 410 .link_nodes = { &srvc_aggre2_noc }, 411 }; 412 413 static struct qcom_icc_node qxm_crypto = { 414 .name = "qxm_crypto", 415 .channels = 1, 416 .buswidth = 8, 417 .qosbox = &(const struct qcom_icc_qosbox) { 418 .num_ports = 1, 419 .port_offsets = { 0xe000 }, 420 .prio = 2, 421 .urg_fwd = 1, 422 }, 423 .num_links = 1, 424 .link_nodes = { &qns_a2noc_snoc }, 425 }; 426 427 static struct qcom_icc_node qxm_sensorss_q6 = { 428 .name = "qxm_sensorss_q6", 429 .channels = 1, 430 .buswidth = 8, 431 .num_links = 1, 432 .link_nodes = { &qns_a2noc_snoc }, 433 }; 434 435 static struct qcom_icc_node qxm_sp = { 436 .name = "qxm_sp", 437 .channels = 1, 438 .buswidth = 8, 439 .num_links = 1, 440 .link_nodes = { &qns_a2noc_snoc }, 441 }; 442 443 static struct qcom_icc_node xm_emac_0 = { 444 .name = "xm_emac_0", 445 .channels = 1, 446 .buswidth = 8, 447 .qosbox = &(const struct qcom_icc_qosbox) { 448 .num_ports = 1, 449 .port_offsets = { 0x11000 }, 450 .prio = 2, 451 }, 452 .num_links = 1, 453 .link_nodes = { &qns_a2noc_snoc }, 454 }; 455 456 static struct qcom_icc_node xm_pcie3_0 = { 457 .name = "xm_pcie3_0", 458 .channels = 1, 459 .buswidth = 16, 460 .qosbox = &(const struct qcom_icc_qosbox) { 461 .num_ports = 1, 462 .port_offsets = { 0x12000 }, 463 .prio = 2, 464 }, 465 .num_links = 1, 466 .link_nodes = { &qns_pcie_gem_noc }, 467 }; 468 469 static struct qcom_icc_node xm_pcie3_1 = { 470 .name = "xm_pcie3_1", 471 .channels = 1, 472 .buswidth = 16, 473 .qosbox = &(const struct qcom_icc_qosbox) { 474 .num_ports = 1, 475 .port_offsets = { 0xf000 }, 476 .prio = 2, 477 }, 478 .num_links = 1, 479 .link_nodes = { &qns_pcie_gem_noc }, 480 }; 481 482 static struct qcom_icc_node xm_pcie3_2a = { 483 .name = "xm_pcie3_2a", 484 .channels = 1, 485 .buswidth = 16, 486 .qosbox = &(const struct qcom_icc_qosbox) { 487 .num_ports = 1, 488 .port_offsets = { 0x13000 }, 489 .prio = 2, 490 }, 491 .num_links = 1, 492 .link_nodes = { &qns_pcie_gem_noc }, 493 }; 494 495 static struct qcom_icc_node xm_pcie3_2b = { 496 .name = "xm_pcie3_2b", 497 .channels = 1, 498 .buswidth = 8, 499 .qosbox = &(const struct qcom_icc_qosbox) { 500 .num_ports = 1, 501 .port_offsets = { 0x14000 }, 502 .prio = 2, 503 }, 504 .num_links = 1, 505 .link_nodes = { &qns_pcie_gem_noc }, 506 }; 507 508 static struct qcom_icc_node xm_pcie3_3a = { 509 .name = "xm_pcie3_3a", 510 .channels = 1, 511 .buswidth = 16, 512 .qosbox = &(const struct qcom_icc_qosbox) { 513 .num_ports = 1, 514 .port_offsets = { 0x15000 }, 515 .prio = 2, 516 }, 517 .num_links = 1, 518 .link_nodes = { &qns_pcie_gem_noc }, 519 }; 520 521 static struct qcom_icc_node xm_pcie3_3b = { 522 .name = "xm_pcie3_3b", 523 .channels = 1, 524 .buswidth = 8, 525 .qosbox = &(const struct qcom_icc_qosbox) { 526 .num_ports = 1, 527 .port_offsets = { 0x16000 }, 528 .prio = 2, 529 }, 530 .num_links = 1, 531 .link_nodes = { &qns_pcie_gem_noc }, 532 }; 533 534 static struct qcom_icc_node xm_pcie3_4 = { 535 .name = "xm_pcie3_4", 536 .channels = 1, 537 .buswidth = 8, 538 .qosbox = &(const struct qcom_icc_qosbox) { 539 .num_ports = 1, 540 .port_offsets = { 0x10000 }, 541 .prio = 2, 542 }, 543 .num_links = 1, 544 .link_nodes = { &qns_pcie_gem_noc }, 545 }; 546 547 static struct qcom_icc_node xm_qdss_etr = { 548 .name = "xm_qdss_etr", 549 .channels = 1, 550 .buswidth = 8, 551 .qosbox = &(const struct qcom_icc_qosbox) { 552 .num_ports = 1, 553 .port_offsets = { 0x7000 }, 554 .prio = 2, 555 }, 556 .num_links = 1, 557 .link_nodes = { &qns_a2noc_snoc }, 558 }; 559 560 static struct qcom_icc_node xm_sdc2 = { 561 .name = "xm_sdc2", 562 .channels = 1, 563 .buswidth = 8, 564 .qosbox = &(const struct qcom_icc_qosbox) { 565 .num_ports = 1, 566 .port_offsets = { 0x8000 }, 567 .prio = 2, 568 }, 569 .num_links = 1, 570 .link_nodes = { &qns_a2noc_snoc }, 571 }; 572 573 static struct qcom_icc_node xm_ufs_card = { 574 .name = "xm_ufs_card", 575 .channels = 1, 576 .buswidth = 8, 577 .qosbox = &(const struct qcom_icc_qosbox) { 578 .num_ports = 1, 579 .port_offsets = { 0x9000 }, 580 .prio = 2, 581 }, 582 .num_links = 1, 583 .link_nodes = { &qns_a2noc_snoc }, 584 }; 585 586 static struct qcom_icc_node qup0_core_master = { 587 .name = "qup0_core_master", 588 .channels = 1, 589 .buswidth = 4, 590 .num_links = 1, 591 .link_nodes = { &qup0_core_slave }, 592 }; 593 594 static struct qcom_icc_node qup1_core_master = { 595 .name = "qup1_core_master", 596 .channels = 1, 597 .buswidth = 4, 598 .num_links = 1, 599 .link_nodes = { &qup1_core_slave }, 600 }; 601 602 static struct qcom_icc_node qup2_core_master = { 603 .name = "qup2_core_master", 604 .channels = 1, 605 .buswidth = 4, 606 .num_links = 1, 607 .link_nodes = { &qup2_core_slave }, 608 }; 609 610 static struct qcom_icc_node qnm_gemnoc_cnoc = { 611 .name = "qnm_gemnoc_cnoc", 612 .channels = 1, 613 .buswidth = 16, 614 .num_links = 76, 615 .link_nodes = { &qhs_ahb2phy0, 616 &qhs_ahb2phy1, 617 &qhs_ahb2phy2, 618 &qhs_aoss, 619 &qhs_apss, 620 &qhs_camera_cfg, 621 &qhs_clk_ctl, 622 &qhs_compute0_cfg, 623 &qhs_compute1_cfg, 624 &qhs_cpr_cx, 625 &qhs_cpr_mmcx, 626 &qhs_cpr_mx, 627 &qhs_cpr_nspcx, 628 &qhs_crypto0_cfg, 629 &qhs_cx_rdpm, 630 &qhs_dcc_cfg, 631 &qhs_display0_cfg, 632 &qhs_display1_cfg, 633 &qhs_emac0_cfg, 634 &qhs_emac1_cfg, 635 &qhs_gpuss_cfg, 636 &qhs_hwkm, 637 &qhs_imem_cfg, 638 &qhs_ipa, 639 &qhs_ipc_router, 640 &qhs_lpass_cfg, 641 &qhs_mx_rdpm, 642 &qhs_mxc_rdpm, 643 &qhs_pcie0_cfg, 644 &qhs_pcie1_cfg, 645 &qhs_pcie2a_cfg, 646 &qhs_pcie2b_cfg, 647 &qhs_pcie3a_cfg, 648 &qhs_pcie3b_cfg, 649 &qhs_pcie4_cfg, 650 &qhs_pcie_rsc_cfg, 651 &qhs_pdm, 652 &qhs_pimem_cfg, 653 &qhs_pka_wrapper_cfg, 654 &qhs_pmu_wrapper_cfg, 655 &qhs_qdss_cfg, 656 &qhs_qspi, 657 &qhs_qup0, 658 &qhs_qup1, 659 &qhs_qup2, 660 &qhs_sdc2, 661 &qhs_sdc4, 662 &qhs_security, 663 &qhs_smmuv3_cfg, 664 &qhs_smss_cfg, 665 &qhs_spss_cfg, 666 &qhs_tcsr, 667 &qhs_tlmm, 668 &qhs_ufs_card_cfg, 669 &qhs_ufs_mem_cfg, 670 &qhs_usb3_0, 671 &qhs_usb3_1, 672 &qhs_usb3_mp, 673 &qhs_usb4_host_0, 674 &qhs_usb4_host_1, 675 &qhs_venus_cfg, 676 &qhs_vsense_ctrl_cfg, 677 &qhs_vsense_ctrl_r_cfg, 678 &qns_a1_noc_cfg, 679 &qns_a2_noc_cfg, 680 &qns_anoc_pcie_bridge_cfg, 681 &qns_ddrss_cfg, 682 &qns_mnoc_cfg, 683 &qns_snoc_cfg, 684 &qns_snoc_sf_bridge_cfg, 685 &qxs_imem, 686 &qxs_pimem, 687 &srvc_cnoc, 688 &xs_qdss_stm, 689 &xs_smss, 690 &xs_sys_tcu_cfg, 691 NULL }, 692 }; 693 694 static struct qcom_icc_node qnm_gemnoc_pcie = { 695 .name = "qnm_gemnoc_pcie", 696 .channels = 1, 697 .buswidth = 16, 698 .num_links = 7, 699 .link_nodes = { &xs_pcie_0, 700 &xs_pcie_1, 701 &xs_pcie_2a, 702 &xs_pcie_2b, 703 &xs_pcie_3a, 704 &xs_pcie_3b, 705 &xs_pcie_4 }, 706 }; 707 708 static struct qcom_icc_node qnm_cnoc_dc_noc = { 709 .name = "qnm_cnoc_dc_noc", 710 .channels = 1, 711 .buswidth = 4, 712 .num_links = 2, 713 .link_nodes = { &qhs_llcc, 714 &qns_gemnoc }, 715 }; 716 717 static struct qcom_icc_node alm_gpu_tcu = { 718 .name = "alm_gpu_tcu", 719 .channels = 1, 720 .buswidth = 8, 721 .qosbox = &(const struct qcom_icc_qosbox) { 722 .num_ports = 1, 723 .port_offsets = { 0xa0000 }, 724 .prio = 1, 725 }, 726 .num_links = 2, 727 .link_nodes = { &qns_gem_noc_cnoc, 728 &qns_llcc }, 729 }; 730 731 static struct qcom_icc_node alm_pcie_tcu = { 732 .name = "alm_pcie_tcu", 733 .channels = 1, 734 .buswidth = 8, 735 .qosbox = &(const struct qcom_icc_qosbox) { 736 .num_ports = 1, 737 .port_offsets = { 0xa1000 }, 738 .prio = 3, 739 }, 740 .num_links = 2, 741 .link_nodes = { &qns_gem_noc_cnoc, 742 &qns_llcc }, 743 }; 744 745 static struct qcom_icc_node alm_sys_tcu = { 746 .name = "alm_sys_tcu", 747 .channels = 1, 748 .buswidth = 8, 749 .qosbox = &(const struct qcom_icc_qosbox) { 750 .num_ports = 1, 751 .port_offsets = { 0xa2000 }, 752 .prio = 6, 753 }, 754 .num_links = 2, 755 .link_nodes = { &qns_gem_noc_cnoc, 756 &qns_llcc }, 757 }; 758 759 static struct qcom_icc_node chm_apps = { 760 .name = "chm_apps", 761 .channels = 2, 762 .buswidth = 32, 763 .num_links = 3, 764 .link_nodes = { &qns_gem_noc_cnoc, 765 &qns_llcc, 766 &qns_pcie }, 767 }; 768 769 static struct qcom_icc_node qnm_cmpnoc0 = { 770 .name = "qnm_cmpnoc0", 771 .channels = 2, 772 .buswidth = 32, 773 .qosbox = &(const struct qcom_icc_qosbox) { 774 .num_ports = 2, 775 .port_offsets = { 0x1b000, 0x66000 }, 776 .urg_fwd = 1, 777 }, 778 .num_links = 2, 779 .link_nodes = { &qns_gem_noc_cnoc, 780 &qns_llcc }, 781 }; 782 783 static struct qcom_icc_node qnm_cmpnoc1 = { 784 .name = "qnm_cmpnoc1", 785 .channels = 2, 786 .buswidth = 32, 787 .qosbox = &(const struct qcom_icc_qosbox) { 788 .num_ports = 2, 789 .port_offsets = { 0x24000, 0x6f000 }, 790 .urg_fwd = 1, 791 }, 792 .num_links = 2, 793 .link_nodes = { &qns_gem_noc_cnoc, 794 &qns_llcc }, 795 }; 796 797 static struct qcom_icc_node qnm_gemnoc_cfg = { 798 .name = "qnm_gemnoc_cfg", 799 .channels = 1, 800 .buswidth = 4, 801 .num_links = 3, 802 .link_nodes = { &srvc_even_gemnoc, 803 &srvc_odd_gemnoc, 804 &srvc_sys_gemnoc }, 805 }; 806 807 static struct qcom_icc_node qnm_gpu = { 808 .name = "qnm_gpu", 809 .channels = 4, 810 .buswidth = 32, 811 .qosbox = &(const struct qcom_icc_qosbox) { 812 .num_ports = 4, 813 .port_offsets = { 0x1c000, 0x1d000, 0x67000, 0x68000 }, 814 .urg_fwd = 1, 815 }, 816 .num_links = 2, 817 .link_nodes = { &qns_gem_noc_cnoc, 818 &qns_llcc }, 819 }; 820 821 static struct qcom_icc_node qnm_mnoc_hf = { 822 .name = "qnm_mnoc_hf", 823 .channels = 2, 824 .buswidth = 32, 825 .qosbox = &(const struct qcom_icc_qosbox) { 826 .num_ports = 2, 827 .port_offsets = { 0x1e000, 0x69000 }, 828 .urg_fwd = 1, 829 }, 830 .num_links = 2, 831 .link_nodes = { &qns_llcc, 832 &qns_pcie }, 833 }; 834 835 static struct qcom_icc_node qnm_mnoc_sf = { 836 .name = "qnm_mnoc_sf", 837 .channels = 2, 838 .buswidth = 32, 839 .qosbox = &(const struct qcom_icc_qosbox) { 840 .num_ports = 2, 841 .port_offsets = { 0x1f000, 0x6a000 }, 842 .urg_fwd = 1, 843 }, 844 .num_links = 2, 845 .link_nodes = { &qns_gem_noc_cnoc, 846 &qns_llcc }, 847 }; 848 849 static struct qcom_icc_node qnm_pcie = { 850 .name = "qnm_pcie", 851 .channels = 1, 852 .buswidth = 32, 853 .qosbox = &(const struct qcom_icc_qosbox) { 854 .num_ports = 1, 855 .port_offsets = { 0xa3000 }, 856 .prio = 2, 857 .urg_fwd = 1, 858 }, 859 .num_links = 2, 860 .link_nodes = { &qns_gem_noc_cnoc, 861 &qns_llcc }, 862 }; 863 864 static struct qcom_icc_node qnm_snoc_gc = { 865 .name = "qnm_snoc_gc", 866 .channels = 1, 867 .buswidth = 8, 868 .qosbox = &(const struct qcom_icc_qosbox) { 869 .num_ports = 1, 870 .port_offsets = { 0xa4000 }, 871 .urg_fwd = 1, 872 }, 873 .num_links = 1, 874 .link_nodes = { &qns_llcc }, 875 }; 876 877 static struct qcom_icc_node qnm_snoc_sf = { 878 .name = "qnm_snoc_sf", 879 .channels = 1, 880 .buswidth = 16, 881 .qosbox = &(const struct qcom_icc_qosbox) { 882 .num_ports = 1, 883 .port_offsets = { 0xa5000 }, 884 .urg_fwd = 1, 885 }, 886 .num_links = 3, 887 .link_nodes = { &qns_gem_noc_cnoc, 888 &qns_llcc, 889 &qns_pcie }, 890 }; 891 892 static struct qcom_icc_node qhm_config_noc = { 893 .name = "qhm_config_noc", 894 .channels = 1, 895 .buswidth = 4, 896 .num_links = 6, 897 .link_nodes = { &qhs_lpass_core, 898 &qhs_lpass_lpi, 899 &qhs_lpass_mpu, 900 &qhs_lpass_top, 901 &srvc_niu_aml_noc, 902 &srvc_niu_lpass_agnoc }, 903 }; 904 905 static struct qcom_icc_node qxm_lpass_dsp = { 906 .name = "qxm_lpass_dsp", 907 .channels = 1, 908 .buswidth = 8, 909 .num_links = 4, 910 .link_nodes = { &qhs_lpass_top, 911 &qns_sysnoc, 912 &srvc_niu_aml_noc, 913 &srvc_niu_lpass_agnoc }, 914 }; 915 916 static struct qcom_icc_node llcc_mc = { 917 .name = "llcc_mc", 918 .channels = 8, 919 .buswidth = 4, 920 .num_links = 1, 921 .link_nodes = { &ebi }, 922 }; 923 924 static struct qcom_icc_node qnm_camnoc_hf = { 925 .name = "qnm_camnoc_hf", 926 .channels = 2, 927 .buswidth = 32, 928 .qosbox = &(const struct qcom_icc_qosbox) { 929 .num_ports = 2, 930 .port_offsets = { 0x10000, 0x10180 }, 931 .urg_fwd = 1, 932 }, 933 .num_links = 1, 934 .link_nodes = { &qns_mem_noc_hf }, 935 }; 936 937 static struct qcom_icc_node qnm_mdp0_0 = { 938 .name = "qnm_mdp0_0", 939 .channels = 1, 940 .buswidth = 32, 941 .qosbox = &(const struct qcom_icc_qosbox) { 942 .num_ports = 1, 943 .port_offsets = { 0x16000 }, 944 .urg_fwd = 1, 945 }, 946 .num_links = 1, 947 .link_nodes = { &qns_mem_noc_hf }, 948 }; 949 950 static struct qcom_icc_node qnm_mdp0_1 = { 951 .name = "qnm_mdp0_1", 952 .channels = 1, 953 .buswidth = 32, 954 .qosbox = &(const struct qcom_icc_qosbox) { 955 .num_ports = 1, 956 .port_offsets = { 0x16080 }, 957 .urg_fwd = 1, 958 }, 959 .num_links = 1, 960 .link_nodes = { &qns_mem_noc_hf }, 961 }; 962 963 static struct qcom_icc_node qnm_mdp1_0 = { 964 .name = "qnm_mdp1_0", 965 .channels = 1, 966 .buswidth = 32, 967 .qosbox = &(const struct qcom_icc_qosbox) { 968 .num_ports = 1, 969 .port_offsets = { 0xf000 }, 970 .urg_fwd = 1, 971 }, 972 .num_links = 1, 973 .link_nodes = { &qns_mem_noc_hf }, 974 }; 975 976 static struct qcom_icc_node qnm_mdp1_1 = { 977 .name = "qnm_mdp1_1", 978 .channels = 1, 979 .buswidth = 32, 980 .qosbox = &(const struct qcom_icc_qosbox) { 981 .num_ports = 1, 982 .port_offsets = { 0xf800 }, 983 .urg_fwd = 1, 984 }, 985 .num_links = 1, 986 .link_nodes = { &qns_mem_noc_hf }, 987 }; 988 989 static struct qcom_icc_node qnm_mnoc_cfg = { 990 .name = "qnm_mnoc_cfg", 991 .channels = 1, 992 .buswidth = 4, 993 .num_links = 1, 994 .link_nodes = { &srvc_mnoc }, 995 }; 996 997 static struct qcom_icc_node qnm_rot_0 = { 998 .name = "qnm_rot_0", 999 .channels = 1, 1000 .buswidth = 32, 1001 .qosbox = &(const struct qcom_icc_qosbox) { 1002 .num_ports = 1, 1003 .port_offsets = { 0x17000 }, 1004 .urg_fwd = 1, 1005 }, 1006 .num_links = 1, 1007 .link_nodes = { &qns_mem_noc_sf }, 1008 }; 1009 1010 static struct qcom_icc_node qnm_rot_1 = { 1011 .name = "qnm_rot_1", 1012 .channels = 1, 1013 .buswidth = 32, 1014 .qosbox = &(const struct qcom_icc_qosbox) { 1015 .num_ports = 1, 1016 .port_offsets = { 0xe000 }, 1017 .urg_fwd = 1, 1018 }, 1019 .num_links = 1, 1020 .link_nodes = { &qns_mem_noc_sf }, 1021 }; 1022 1023 static struct qcom_icc_node qnm_video0 = { 1024 .name = "qnm_video0", 1025 .channels = 1, 1026 .buswidth = 32, 1027 .qosbox = &(const struct qcom_icc_qosbox) { 1028 .num_ports = 1, 1029 .port_offsets = { 0x14000 }, 1030 .urg_fwd = 1, 1031 }, 1032 .num_links = 1, 1033 .link_nodes = { &qns_mem_noc_sf }, 1034 }; 1035 1036 static struct qcom_icc_node qnm_video1 = { 1037 .name = "qnm_video1", 1038 .channels = 1, 1039 .buswidth = 32, 1040 .qosbox = &(const struct qcom_icc_qosbox) { 1041 .num_ports = 1, 1042 .port_offsets = { 0x14080 }, 1043 .urg_fwd = 1, 1044 }, 1045 .num_links = 1, 1046 .link_nodes = { &qns_mem_noc_sf }, 1047 }; 1048 1049 static struct qcom_icc_node qnm_video_cvp = { 1050 .name = "qnm_video_cvp", 1051 .channels = 1, 1052 .buswidth = 32, 1053 .qosbox = &(const struct qcom_icc_qosbox) { 1054 .num_ports = 1, 1055 .port_offsets = { 0x15000 }, 1056 .urg_fwd = 1, 1057 }, 1058 .num_links = 1, 1059 .link_nodes = { &qns_mem_noc_sf }, 1060 }; 1061 1062 static struct qcom_icc_node qxm_camnoc_icp = { 1063 .name = "qxm_camnoc_icp", 1064 .channels = 1, 1065 .buswidth = 8, 1066 .qosbox = &(const struct qcom_icc_qosbox) { 1067 .num_ports = 1, 1068 .port_offsets = { 0x11000 }, 1069 .urg_fwd = 1, 1070 }, 1071 .num_links = 1, 1072 .link_nodes = { &qns_mem_noc_sf }, 1073 }; 1074 1075 static struct qcom_icc_node qxm_camnoc_sf = { 1076 .name = "qxm_camnoc_sf", 1077 .channels = 1, 1078 .buswidth = 32, 1079 .qosbox = &(const struct qcom_icc_qosbox) { 1080 .num_ports = 1, 1081 .port_offsets = { 0x12000 }, 1082 .urg_fwd = 1, 1083 }, 1084 .num_links = 1, 1085 .link_nodes = { &qns_mem_noc_sf }, 1086 }; 1087 1088 static struct qcom_icc_node qhm_nsp_noc_config = { 1089 .name = "qhm_nsp_noc_config", 1090 .channels = 1, 1091 .buswidth = 4, 1092 .num_links = 1, 1093 .link_nodes = { &service_nsp_noc }, 1094 }; 1095 1096 static struct qcom_icc_node qxm_nsp = { 1097 .name = "qxm_nsp", 1098 .channels = 2, 1099 .buswidth = 32, 1100 .num_links = 2, 1101 .link_nodes = { &qns_nsp_gemnoc, 1102 &qxs_nsp_xfr }, 1103 }; 1104 1105 static struct qcom_icc_node qhm_nspb_noc_config = { 1106 .name = "qhm_nspb_noc_config", 1107 .channels = 1, 1108 .buswidth = 4, 1109 .num_links = 1, 1110 .link_nodes = { &service_nspb_noc }, 1111 }; 1112 1113 static struct qcom_icc_node qxm_nspb = { 1114 .name = "qxm_nspb", 1115 .channels = 2, 1116 .buswidth = 32, 1117 .num_links = 2, 1118 .link_nodes = { &qns_nspb_gemnoc, 1119 &qxs_nspb_xfr }, 1120 }; 1121 1122 static struct qcom_icc_node qnm_aggre1_noc = { 1123 .name = "qnm_aggre1_noc", 1124 .channels = 1, 1125 .buswidth = 16, 1126 .num_links = 1, 1127 .link_nodes = { &qns_gemnoc_sf }, 1128 }; 1129 1130 static struct qcom_icc_node qnm_aggre2_noc = { 1131 .name = "qnm_aggre2_noc", 1132 .channels = 1, 1133 .buswidth = 16, 1134 .num_links = 1, 1135 .link_nodes = { &qns_gemnoc_sf }, 1136 }; 1137 1138 static struct qcom_icc_node qnm_aggre_usb_noc = { 1139 .name = "qnm_aggre_usb_noc", 1140 .channels = 1, 1141 .buswidth = 16, 1142 .num_links = 1, 1143 .link_nodes = { &qns_gemnoc_sf }, 1144 }; 1145 1146 static struct qcom_icc_node qnm_lpass_noc = { 1147 .name = "qnm_lpass_noc", 1148 .channels = 1, 1149 .buswidth = 16, 1150 .qosbox = &(const struct qcom_icc_qosbox) { 1151 .num_ports = 1, 1152 .port_offsets = { 0xe000 }, 1153 .urg_fwd = 1, 1154 }, 1155 .num_links = 1, 1156 .link_nodes = { &qns_gemnoc_sf }, 1157 }; 1158 1159 static struct qcom_icc_node qnm_snoc_cfg = { 1160 .name = "qnm_snoc_cfg", 1161 .channels = 1, 1162 .buswidth = 4, 1163 .num_links = 1, 1164 .link_nodes = { &srvc_snoc }, 1165 }; 1166 1167 static struct qcom_icc_node qxm_pimem = { 1168 .name = "qxm_pimem", 1169 .channels = 1, 1170 .buswidth = 8, 1171 .qosbox = &(const struct qcom_icc_qosbox) { 1172 .num_ports = 1, 1173 .port_offsets = { 0x10000 }, 1174 .prio = 2, 1175 .urg_fwd = 1, 1176 }, 1177 .num_links = 1, 1178 .link_nodes = { &qns_gemnoc_gc }, 1179 }; 1180 1181 static struct qcom_icc_node xm_gic = { 1182 .name = "xm_gic", 1183 .channels = 1, 1184 .buswidth = 8, 1185 .qosbox = &(const struct qcom_icc_qosbox) { 1186 .num_ports = 1, 1187 .port_offsets = { 0x12000 }, 1188 .prio = 2, 1189 }, 1190 .num_links = 1, 1191 .link_nodes = { &qns_gemnoc_gc }, 1192 }; 1193 1194 static struct qcom_icc_node qns_a1noc_snoc = { 1195 .name = "qns_a1noc_snoc", 1196 .channels = 1, 1197 .buswidth = 16, 1198 .num_links = 1, 1199 .link_nodes = { &qnm_aggre1_noc }, 1200 }; 1201 1202 static struct qcom_icc_node qns_aggre_usb_snoc = { 1203 .name = "qns_aggre_usb_snoc", 1204 .channels = 1, 1205 .buswidth = 16, 1206 .num_links = 1, 1207 .link_nodes = { &qnm_aggre_usb_noc }, 1208 }; 1209 1210 static struct qcom_icc_node srvc_aggre1_noc = { 1211 .name = "srvc_aggre1_noc", 1212 .channels = 1, 1213 .buswidth = 4, 1214 }; 1215 1216 static struct qcom_icc_node qns_a2noc_snoc = { 1217 .name = "qns_a2noc_snoc", 1218 .channels = 1, 1219 .buswidth = 16, 1220 .num_links = 1, 1221 .link_nodes = { &qnm_aggre2_noc }, 1222 }; 1223 1224 static struct qcom_icc_node qns_pcie_gem_noc = { 1225 .name = "qns_pcie_gem_noc", 1226 .channels = 1, 1227 .buswidth = 32, 1228 .num_links = 1, 1229 .link_nodes = { &qnm_pcie }, 1230 }; 1231 1232 static struct qcom_icc_node srvc_aggre2_noc = { 1233 .name = "srvc_aggre2_noc", 1234 .channels = 1, 1235 .buswidth = 4, 1236 }; 1237 1238 static struct qcom_icc_node qup0_core_slave = { 1239 .name = "qup0_core_slave", 1240 .channels = 1, 1241 .buswidth = 4, 1242 }; 1243 1244 static struct qcom_icc_node qup1_core_slave = { 1245 .name = "qup1_core_slave", 1246 .channels = 1, 1247 .buswidth = 4, 1248 }; 1249 1250 static struct qcom_icc_node qup2_core_slave = { 1251 .name = "qup2_core_slave", 1252 .channels = 1, 1253 .buswidth = 4, 1254 }; 1255 1256 static struct qcom_icc_node qhs_ahb2phy0 = { 1257 .name = "qhs_ahb2phy0", 1258 .channels = 1, 1259 .buswidth = 4, 1260 }; 1261 1262 static struct qcom_icc_node qhs_ahb2phy1 = { 1263 .name = "qhs_ahb2phy1", 1264 .channels = 1, 1265 .buswidth = 4, 1266 }; 1267 1268 static struct qcom_icc_node qhs_ahb2phy2 = { 1269 .name = "qhs_ahb2phy2", 1270 .channels = 1, 1271 .buswidth = 4, 1272 }; 1273 1274 static struct qcom_icc_node qhs_aoss = { 1275 .name = "qhs_aoss", 1276 .channels = 1, 1277 .buswidth = 4, 1278 }; 1279 1280 static struct qcom_icc_node qhs_apss = { 1281 .name = "qhs_apss", 1282 .channels = 1, 1283 .buswidth = 8, 1284 }; 1285 1286 static struct qcom_icc_node qhs_camera_cfg = { 1287 .name = "qhs_camera_cfg", 1288 .channels = 1, 1289 .buswidth = 4, 1290 }; 1291 1292 static struct qcom_icc_node qhs_clk_ctl = { 1293 .name = "qhs_clk_ctl", 1294 .channels = 1, 1295 .buswidth = 4, 1296 }; 1297 1298 static struct qcom_icc_node qhs_compute0_cfg = { 1299 .name = "qhs_compute0_cfg", 1300 .channels = 1, 1301 .buswidth = 4, 1302 .num_links = 1, 1303 .link_nodes = { &qhm_nsp_noc_config }, 1304 }; 1305 1306 static struct qcom_icc_node qhs_compute1_cfg = { 1307 .name = "qhs_compute1_cfg", 1308 .channels = 1, 1309 .buswidth = 4, 1310 .num_links = 1, 1311 .link_nodes = { &qhm_nspb_noc_config }, 1312 }; 1313 1314 static struct qcom_icc_node qhs_cpr_cx = { 1315 .name = "qhs_cpr_cx", 1316 .channels = 1, 1317 .buswidth = 4, 1318 }; 1319 1320 static struct qcom_icc_node qhs_cpr_mmcx = { 1321 .name = "qhs_cpr_mmcx", 1322 .channels = 1, 1323 .buswidth = 4, 1324 }; 1325 1326 static struct qcom_icc_node qhs_cpr_mx = { 1327 .name = "qhs_cpr_mx", 1328 .channels = 1, 1329 .buswidth = 4, 1330 }; 1331 1332 static struct qcom_icc_node qhs_cpr_nspcx = { 1333 .name = "qhs_cpr_nspcx", 1334 .channels = 1, 1335 .buswidth = 4, 1336 }; 1337 1338 static struct qcom_icc_node qhs_crypto0_cfg = { 1339 .name = "qhs_crypto0_cfg", 1340 .channels = 1, 1341 .buswidth = 4, 1342 }; 1343 1344 static struct qcom_icc_node qhs_cx_rdpm = { 1345 .name = "qhs_cx_rdpm", 1346 .channels = 1, 1347 .buswidth = 4, 1348 }; 1349 1350 static struct qcom_icc_node qhs_dcc_cfg = { 1351 .name = "qhs_dcc_cfg", 1352 .channels = 1, 1353 .buswidth = 4, 1354 }; 1355 1356 static struct qcom_icc_node qhs_display0_cfg = { 1357 .name = "qhs_display0_cfg", 1358 .channels = 1, 1359 .buswidth = 4, 1360 }; 1361 1362 static struct qcom_icc_node qhs_display1_cfg = { 1363 .name = "qhs_display1_cfg", 1364 .channels = 1, 1365 .buswidth = 4, 1366 }; 1367 1368 static struct qcom_icc_node qhs_emac0_cfg = { 1369 .name = "qhs_emac0_cfg", 1370 .channels = 1, 1371 .buswidth = 4, 1372 }; 1373 1374 static struct qcom_icc_node qhs_emac1_cfg = { 1375 .name = "qhs_emac1_cfg", 1376 .channels = 1, 1377 .buswidth = 4, 1378 }; 1379 1380 static struct qcom_icc_node qhs_gpuss_cfg = { 1381 .name = "qhs_gpuss_cfg", 1382 .channels = 1, 1383 .buswidth = 8, 1384 }; 1385 1386 static struct qcom_icc_node qhs_hwkm = { 1387 .name = "qhs_hwkm", 1388 .channels = 1, 1389 .buswidth = 4, 1390 }; 1391 1392 static struct qcom_icc_node qhs_imem_cfg = { 1393 .name = "qhs_imem_cfg", 1394 .channels = 1, 1395 .buswidth = 4, 1396 }; 1397 1398 static struct qcom_icc_node qhs_ipa = { 1399 .name = "qhs_ipa", 1400 .channels = 1, 1401 .buswidth = 4, 1402 }; 1403 1404 static struct qcom_icc_node qhs_ipc_router = { 1405 .name = "qhs_ipc_router", 1406 .channels = 1, 1407 .buswidth = 4, 1408 }; 1409 1410 static struct qcom_icc_node qhs_lpass_cfg = { 1411 .name = "qhs_lpass_cfg", 1412 .channels = 1, 1413 .buswidth = 4, 1414 .num_links = 1, 1415 .link_nodes = { &qhm_config_noc }, 1416 }; 1417 1418 static struct qcom_icc_node qhs_mx_rdpm = { 1419 .name = "qhs_mx_rdpm", 1420 .channels = 1, 1421 .buswidth = 4, 1422 }; 1423 1424 static struct qcom_icc_node qhs_mxc_rdpm = { 1425 .name = "qhs_mxc_rdpm", 1426 .channels = 1, 1427 .buswidth = 4, 1428 }; 1429 1430 static struct qcom_icc_node qhs_pcie0_cfg = { 1431 .name = "qhs_pcie0_cfg", 1432 .channels = 1, 1433 .buswidth = 4, 1434 }; 1435 1436 static struct qcom_icc_node qhs_pcie1_cfg = { 1437 .name = "qhs_pcie1_cfg", 1438 .channels = 1, 1439 .buswidth = 4, 1440 }; 1441 1442 static struct qcom_icc_node qhs_pcie2a_cfg = { 1443 .name = "qhs_pcie2a_cfg", 1444 .channels = 1, 1445 .buswidth = 4, 1446 }; 1447 1448 static struct qcom_icc_node qhs_pcie2b_cfg = { 1449 .name = "qhs_pcie2b_cfg", 1450 .channels = 1, 1451 .buswidth = 4, 1452 }; 1453 1454 static struct qcom_icc_node qhs_pcie3a_cfg = { 1455 .name = "qhs_pcie3a_cfg", 1456 .channels = 1, 1457 .buswidth = 4, 1458 }; 1459 1460 static struct qcom_icc_node qhs_pcie3b_cfg = { 1461 .name = "qhs_pcie3b_cfg", 1462 .channels = 1, 1463 .buswidth = 4, 1464 }; 1465 1466 static struct qcom_icc_node qhs_pcie4_cfg = { 1467 .name = "qhs_pcie4_cfg", 1468 .channels = 1, 1469 .buswidth = 4, 1470 }; 1471 1472 static struct qcom_icc_node qhs_pcie_rsc_cfg = { 1473 .name = "qhs_pcie_rsc_cfg", 1474 .channels = 1, 1475 .buswidth = 4, 1476 }; 1477 1478 static struct qcom_icc_node qhs_pdm = { 1479 .name = "qhs_pdm", 1480 .channels = 1, 1481 .buswidth = 4, 1482 }; 1483 1484 static struct qcom_icc_node qhs_pimem_cfg = { 1485 .name = "qhs_pimem_cfg", 1486 .channels = 1, 1487 .buswidth = 4, 1488 }; 1489 1490 static struct qcom_icc_node qhs_pka_wrapper_cfg = { 1491 .name = "qhs_pka_wrapper_cfg", 1492 .channels = 1, 1493 .buswidth = 4, 1494 }; 1495 1496 static struct qcom_icc_node qhs_pmu_wrapper_cfg = { 1497 .name = "qhs_pmu_wrapper_cfg", 1498 .channels = 1, 1499 .buswidth = 4, 1500 }; 1501 1502 static struct qcom_icc_node qhs_qdss_cfg = { 1503 .name = "qhs_qdss_cfg", 1504 .channels = 1, 1505 .buswidth = 4, 1506 }; 1507 1508 static struct qcom_icc_node qhs_qspi = { 1509 .name = "qhs_qspi", 1510 .channels = 1, 1511 .buswidth = 4, 1512 }; 1513 1514 static struct qcom_icc_node qhs_qup0 = { 1515 .name = "qhs_qup0", 1516 .channels = 1, 1517 .buswidth = 4, 1518 }; 1519 1520 static struct qcom_icc_node qhs_qup1 = { 1521 .name = "qhs_qup1", 1522 .channels = 1, 1523 .buswidth = 4, 1524 }; 1525 1526 static struct qcom_icc_node qhs_qup2 = { 1527 .name = "qhs_qup2", 1528 .channels = 1, 1529 .buswidth = 4, 1530 }; 1531 1532 static struct qcom_icc_node qhs_sdc2 = { 1533 .name = "qhs_sdc2", 1534 .channels = 1, 1535 .buswidth = 4, 1536 }; 1537 1538 static struct qcom_icc_node qhs_sdc4 = { 1539 .name = "qhs_sdc4", 1540 .channels = 1, 1541 .buswidth = 4, 1542 }; 1543 1544 static struct qcom_icc_node qhs_security = { 1545 .name = "qhs_security", 1546 .channels = 1, 1547 .buswidth = 4, 1548 }; 1549 1550 static struct qcom_icc_node qhs_smmuv3_cfg = { 1551 .name = "qhs_smmuv3_cfg", 1552 .channels = 1, 1553 .buswidth = 8, 1554 }; 1555 1556 static struct qcom_icc_node qhs_smss_cfg = { 1557 .name = "qhs_smss_cfg", 1558 .channels = 1, 1559 .buswidth = 4, 1560 }; 1561 1562 static struct qcom_icc_node qhs_spss_cfg = { 1563 .name = "qhs_spss_cfg", 1564 .channels = 1, 1565 .buswidth = 4, 1566 }; 1567 1568 static struct qcom_icc_node qhs_tcsr = { 1569 .name = "qhs_tcsr", 1570 .channels = 1, 1571 .buswidth = 4, 1572 }; 1573 1574 static struct qcom_icc_node qhs_tlmm = { 1575 .name = "qhs_tlmm", 1576 .channels = 1, 1577 .buswidth = 4, 1578 }; 1579 1580 static struct qcom_icc_node qhs_ufs_card_cfg = { 1581 .name = "qhs_ufs_card_cfg", 1582 .channels = 1, 1583 .buswidth = 4, 1584 }; 1585 1586 static struct qcom_icc_node qhs_ufs_mem_cfg = { 1587 .name = "qhs_ufs_mem_cfg", 1588 .channels = 1, 1589 .buswidth = 4, 1590 }; 1591 1592 static struct qcom_icc_node qhs_usb3_0 = { 1593 .name = "qhs_usb3_0", 1594 .channels = 1, 1595 .buswidth = 4, 1596 }; 1597 1598 static struct qcom_icc_node qhs_usb3_1 = { 1599 .name = "qhs_usb3_1", 1600 .channels = 1, 1601 .buswidth = 4, 1602 }; 1603 1604 static struct qcom_icc_node qhs_usb3_mp = { 1605 .name = "qhs_usb3_mp", 1606 .channels = 1, 1607 .buswidth = 4, 1608 }; 1609 1610 static struct qcom_icc_node qhs_usb4_host_0 = { 1611 .name = "qhs_usb4_host_0", 1612 .channels = 1, 1613 .buswidth = 4, 1614 }; 1615 1616 static struct qcom_icc_node qhs_usb4_host_1 = { 1617 .name = "qhs_usb4_host_1", 1618 .channels = 1, 1619 .buswidth = 4, 1620 }; 1621 1622 static struct qcom_icc_node qhs_venus_cfg = { 1623 .name = "qhs_venus_cfg", 1624 .channels = 1, 1625 .buswidth = 4, 1626 }; 1627 1628 static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 1629 .name = "qhs_vsense_ctrl_cfg", 1630 .channels = 1, 1631 .buswidth = 4, 1632 }; 1633 1634 static struct qcom_icc_node qhs_vsense_ctrl_r_cfg = { 1635 .name = "qhs_vsense_ctrl_r_cfg", 1636 .channels = 1, 1637 .buswidth = 4, 1638 }; 1639 1640 static struct qcom_icc_node qns_a1_noc_cfg = { 1641 .name = "qns_a1_noc_cfg", 1642 .channels = 1, 1643 .buswidth = 4, 1644 .num_links = 1, 1645 .link_nodes = { &qnm_a1noc_cfg }, 1646 }; 1647 1648 static struct qcom_icc_node qns_a2_noc_cfg = { 1649 .name = "qns_a2_noc_cfg", 1650 .channels = 1, 1651 .buswidth = 4, 1652 .num_links = 1, 1653 .link_nodes = { &qnm_a2noc_cfg }, 1654 }; 1655 1656 static struct qcom_icc_node qns_anoc_pcie_bridge_cfg = { 1657 .name = "qns_anoc_pcie_bridge_cfg", 1658 .channels = 1, 1659 .buswidth = 4, 1660 }; 1661 1662 static struct qcom_icc_node qns_ddrss_cfg = { 1663 .name = "qns_ddrss_cfg", 1664 .channels = 1, 1665 .buswidth = 4, 1666 .num_links = 1, 1667 .link_nodes = { &qnm_cnoc_dc_noc }, 1668 }; 1669 1670 static struct qcom_icc_node qns_mnoc_cfg = { 1671 .name = "qns_mnoc_cfg", 1672 .channels = 1, 1673 .buswidth = 4, 1674 .num_links = 1, 1675 .link_nodes = { &qnm_mnoc_cfg }, 1676 }; 1677 1678 static struct qcom_icc_node qns_snoc_cfg = { 1679 .name = "qns_snoc_cfg", 1680 .channels = 1, 1681 .buswidth = 4, 1682 .num_links = 1, 1683 .link_nodes = { &qnm_snoc_cfg }, 1684 }; 1685 1686 static struct qcom_icc_node qns_snoc_sf_bridge_cfg = { 1687 .name = "qns_snoc_sf_bridge_cfg", 1688 .channels = 1, 1689 .buswidth = 4, 1690 }; 1691 1692 static struct qcom_icc_node qxs_imem = { 1693 .name = "qxs_imem", 1694 .channels = 1, 1695 .buswidth = 8, 1696 }; 1697 1698 static struct qcom_icc_node qxs_pimem = { 1699 .name = "qxs_pimem", 1700 .channels = 1, 1701 .buswidth = 8, 1702 }; 1703 1704 static struct qcom_icc_node srvc_cnoc = { 1705 .name = "srvc_cnoc", 1706 .channels = 1, 1707 .buswidth = 4, 1708 }; 1709 1710 static struct qcom_icc_node xs_pcie_0 = { 1711 .name = "xs_pcie_0", 1712 .channels = 1, 1713 .buswidth = 16, 1714 }; 1715 1716 static struct qcom_icc_node xs_pcie_1 = { 1717 .name = "xs_pcie_1", 1718 .channels = 1, 1719 .buswidth = 16, 1720 }; 1721 1722 static struct qcom_icc_node xs_pcie_2a = { 1723 .name = "xs_pcie_2a", 1724 .channels = 1, 1725 .buswidth = 16, 1726 }; 1727 1728 static struct qcom_icc_node xs_pcie_2b = { 1729 .name = "xs_pcie_2b", 1730 .channels = 1, 1731 .buswidth = 8, 1732 }; 1733 1734 static struct qcom_icc_node xs_pcie_3a = { 1735 .name = "xs_pcie_3a", 1736 .channels = 1, 1737 .buswidth = 16, 1738 }; 1739 1740 static struct qcom_icc_node xs_pcie_3b = { 1741 .name = "xs_pcie_3b", 1742 .channels = 1, 1743 .buswidth = 8, 1744 }; 1745 1746 static struct qcom_icc_node xs_pcie_4 = { 1747 .name = "xs_pcie_4", 1748 .channels = 1, 1749 .buswidth = 8, 1750 }; 1751 1752 static struct qcom_icc_node xs_qdss_stm = { 1753 .name = "xs_qdss_stm", 1754 .channels = 1, 1755 .buswidth = 4, 1756 }; 1757 1758 static struct qcom_icc_node xs_smss = { 1759 .name = "xs_smss", 1760 .channels = 1, 1761 .buswidth = 8, 1762 }; 1763 1764 static struct qcom_icc_node xs_sys_tcu_cfg = { 1765 .name = "xs_sys_tcu_cfg", 1766 .channels = 1, 1767 .buswidth = 8, 1768 }; 1769 1770 static struct qcom_icc_node qhs_llcc = { 1771 .name = "qhs_llcc", 1772 .channels = 1, 1773 .buswidth = 4, 1774 }; 1775 1776 static struct qcom_icc_node qns_gemnoc = { 1777 .name = "qns_gemnoc", 1778 .channels = 1, 1779 .buswidth = 4, 1780 .num_links = 1, 1781 .link_nodes = { &qnm_gemnoc_cfg }, 1782 }; 1783 1784 static struct qcom_icc_node qns_gem_noc_cnoc = { 1785 .name = "qns_gem_noc_cnoc", 1786 .channels = 1, 1787 .buswidth = 16, 1788 .num_links = 1, 1789 .link_nodes = { &qnm_gemnoc_cnoc }, 1790 }; 1791 1792 static struct qcom_icc_node qns_llcc = { 1793 .name = "qns_llcc", 1794 .channels = 8, 1795 .buswidth = 16, 1796 .num_links = 1, 1797 .link_nodes = { &llcc_mc }, 1798 }; 1799 1800 static struct qcom_icc_node qns_pcie = { 1801 .name = "qns_pcie", 1802 .channels = 1, 1803 .buswidth = 16, 1804 .num_links = 1, 1805 .link_nodes = { &qnm_gemnoc_pcie }, 1806 }; 1807 1808 static struct qcom_icc_node srvc_even_gemnoc = { 1809 .name = "srvc_even_gemnoc", 1810 .channels = 1, 1811 .buswidth = 4, 1812 }; 1813 1814 static struct qcom_icc_node srvc_odd_gemnoc = { 1815 .name = "srvc_odd_gemnoc", 1816 .channels = 1, 1817 .buswidth = 4, 1818 }; 1819 1820 static struct qcom_icc_node srvc_sys_gemnoc = { 1821 .name = "srvc_sys_gemnoc", 1822 .channels = 1, 1823 .buswidth = 4, 1824 }; 1825 1826 static struct qcom_icc_node qhs_lpass_core = { 1827 .name = "qhs_lpass_core", 1828 .channels = 1, 1829 .buswidth = 4, 1830 }; 1831 1832 static struct qcom_icc_node qhs_lpass_lpi = { 1833 .name = "qhs_lpass_lpi", 1834 .channels = 1, 1835 .buswidth = 4, 1836 }; 1837 1838 static struct qcom_icc_node qhs_lpass_mpu = { 1839 .name = "qhs_lpass_mpu", 1840 .channels = 1, 1841 .buswidth = 4, 1842 }; 1843 1844 static struct qcom_icc_node qhs_lpass_top = { 1845 .name = "qhs_lpass_top", 1846 .channels = 1, 1847 .buswidth = 4, 1848 }; 1849 1850 static struct qcom_icc_node qns_sysnoc = { 1851 .name = "qns_sysnoc", 1852 .channels = 1, 1853 .buswidth = 16, 1854 .num_links = 1, 1855 .link_nodes = { &qnm_lpass_noc }, 1856 }; 1857 1858 static struct qcom_icc_node srvc_niu_aml_noc = { 1859 .name = "srvc_niu_aml_noc", 1860 .channels = 1, 1861 .buswidth = 4, 1862 }; 1863 1864 static struct qcom_icc_node srvc_niu_lpass_agnoc = { 1865 .name = "srvc_niu_lpass_agnoc", 1866 .channels = 1, 1867 .buswidth = 4, 1868 }; 1869 1870 static struct qcom_icc_node ebi = { 1871 .name = "ebi", 1872 .channels = 8, 1873 .buswidth = 4, 1874 }; 1875 1876 static struct qcom_icc_node qns_mem_noc_hf = { 1877 .name = "qns_mem_noc_hf", 1878 .channels = 2, 1879 .buswidth = 32, 1880 .num_links = 1, 1881 .link_nodes = { &qnm_mnoc_hf }, 1882 }; 1883 1884 static struct qcom_icc_node qns_mem_noc_sf = { 1885 .name = "qns_mem_noc_sf", 1886 .channels = 2, 1887 .buswidth = 32, 1888 .num_links = 1, 1889 .link_nodes = { &qnm_mnoc_sf }, 1890 }; 1891 1892 static struct qcom_icc_node srvc_mnoc = { 1893 .name = "srvc_mnoc", 1894 .channels = 1, 1895 .buswidth = 4, 1896 }; 1897 1898 static struct qcom_icc_node qns_nsp_gemnoc = { 1899 .name = "qns_nsp_gemnoc", 1900 .channels = 2, 1901 .buswidth = 32, 1902 .num_links = 1, 1903 .link_nodes = { &qnm_cmpnoc0 }, 1904 }; 1905 1906 static struct qcom_icc_node qxs_nsp_xfr = { 1907 .name = "qxs_nsp_xfr", 1908 .channels = 1, 1909 .buswidth = 32, 1910 }; 1911 1912 static struct qcom_icc_node service_nsp_noc = { 1913 .name = "service_nsp_noc", 1914 .channels = 1, 1915 .buswidth = 4, 1916 }; 1917 1918 static struct qcom_icc_node qns_nspb_gemnoc = { 1919 .name = "qns_nspb_gemnoc", 1920 .channels = 2, 1921 .buswidth = 32, 1922 .num_links = 1, 1923 .link_nodes = { &qnm_cmpnoc1 }, 1924 }; 1925 1926 static struct qcom_icc_node qxs_nspb_xfr = { 1927 .name = "qxs_nspb_xfr", 1928 .channels = 1, 1929 .buswidth = 32, 1930 }; 1931 1932 static struct qcom_icc_node service_nspb_noc = { 1933 .name = "service_nspb_noc", 1934 .channels = 1, 1935 .buswidth = 4, 1936 }; 1937 1938 static struct qcom_icc_node qns_gemnoc_gc = { 1939 .name = "qns_gemnoc_gc", 1940 .channels = 1, 1941 .buswidth = 8, 1942 .num_links = 1, 1943 .link_nodes = { &qnm_snoc_gc }, 1944 }; 1945 1946 static struct qcom_icc_node qns_gemnoc_sf = { 1947 .name = "qns_gemnoc_sf", 1948 .channels = 1, 1949 .buswidth = 16, 1950 .num_links = 1, 1951 .link_nodes = { &qnm_snoc_sf }, 1952 }; 1953 1954 static struct qcom_icc_node srvc_snoc = { 1955 .name = "srvc_snoc", 1956 .channels = 1, 1957 .buswidth = 4, 1958 }; 1959 1960 static struct qcom_icc_bcm bcm_acv = { 1961 .name = "ACV", 1962 .enable_mask = BIT(3), 1963 .num_nodes = 1, 1964 .nodes = { &ebi }, 1965 }; 1966 1967 static struct qcom_icc_bcm bcm_ce0 = { 1968 .name = "CE0", 1969 .num_nodes = 1, 1970 .nodes = { &qxm_crypto }, 1971 }; 1972 1973 static struct qcom_icc_bcm bcm_cn0 = { 1974 .name = "CN0", 1975 .keepalive = true, 1976 .num_nodes = 9, 1977 .nodes = { &qnm_gemnoc_cnoc, 1978 &qnm_gemnoc_pcie, 1979 &xs_pcie_0, 1980 &xs_pcie_1, 1981 &xs_pcie_2a, 1982 &xs_pcie_2b, 1983 &xs_pcie_3a, 1984 &xs_pcie_3b, 1985 &xs_pcie_4 1986 }, 1987 }; 1988 1989 static struct qcom_icc_bcm bcm_cn1 = { 1990 .name = "CN1", 1991 .num_nodes = 67, 1992 .nodes = { &qhs_ahb2phy0, 1993 &qhs_ahb2phy1, 1994 &qhs_ahb2phy2, 1995 &qhs_aoss, 1996 &qhs_apss, 1997 &qhs_camera_cfg, 1998 &qhs_clk_ctl, 1999 &qhs_compute0_cfg, 2000 &qhs_compute1_cfg, 2001 &qhs_cpr_cx, 2002 &qhs_cpr_mmcx, 2003 &qhs_cpr_mx, 2004 &qhs_cpr_nspcx, 2005 &qhs_crypto0_cfg, 2006 &qhs_cx_rdpm, 2007 &qhs_dcc_cfg, 2008 &qhs_display0_cfg, 2009 &qhs_display1_cfg, 2010 &qhs_emac0_cfg, 2011 &qhs_emac1_cfg, 2012 &qhs_gpuss_cfg, 2013 &qhs_hwkm, 2014 &qhs_imem_cfg, 2015 &qhs_ipa, 2016 &qhs_ipc_router, 2017 &qhs_lpass_cfg, 2018 &qhs_mx_rdpm, 2019 &qhs_mxc_rdpm, 2020 &qhs_pcie0_cfg, 2021 &qhs_pcie1_cfg, 2022 &qhs_pcie2a_cfg, 2023 &qhs_pcie2b_cfg, 2024 &qhs_pcie3a_cfg, 2025 &qhs_pcie3b_cfg, 2026 &qhs_pcie4_cfg, 2027 &qhs_pcie_rsc_cfg, 2028 &qhs_pdm, 2029 &qhs_pimem_cfg, 2030 &qhs_pka_wrapper_cfg, 2031 &qhs_pmu_wrapper_cfg, 2032 &qhs_qdss_cfg, 2033 &qhs_sdc2, 2034 &qhs_sdc4, 2035 &qhs_security, 2036 &qhs_smmuv3_cfg, 2037 &qhs_smss_cfg, 2038 &qhs_spss_cfg, 2039 &qhs_tcsr, 2040 &qhs_tlmm, 2041 &qhs_ufs_card_cfg, 2042 &qhs_ufs_mem_cfg, 2043 &qhs_usb3_0, 2044 &qhs_usb3_1, 2045 &qhs_usb3_mp, 2046 &qhs_usb4_host_0, 2047 &qhs_usb4_host_1, 2048 &qhs_venus_cfg, 2049 &qhs_vsense_ctrl_cfg, 2050 &qhs_vsense_ctrl_r_cfg, 2051 &qns_a1_noc_cfg, 2052 &qns_a2_noc_cfg, 2053 &qns_anoc_pcie_bridge_cfg, 2054 &qns_ddrss_cfg, 2055 &qns_mnoc_cfg, 2056 &qns_snoc_cfg, 2057 &qns_snoc_sf_bridge_cfg, 2058 &srvc_cnoc 2059 }, 2060 }; 2061 2062 static struct qcom_icc_bcm bcm_cn2 = { 2063 .name = "CN2", 2064 .num_nodes = 4, 2065 .nodes = { &qhs_qspi, 2066 &qhs_qup0, 2067 &qhs_qup1, 2068 &qhs_qup2 2069 }, 2070 }; 2071 2072 static struct qcom_icc_bcm bcm_cn3 = { 2073 .name = "CN3", 2074 .num_nodes = 3, 2075 .nodes = { &qxs_imem, 2076 &xs_smss, 2077 &xs_sys_tcu_cfg 2078 }, 2079 }; 2080 2081 static struct qcom_icc_bcm bcm_mc0 = { 2082 .name = "MC0", 2083 .keepalive = true, 2084 .num_nodes = 1, 2085 .nodes = { &ebi }, 2086 }; 2087 2088 static struct qcom_icc_bcm bcm_mm0 = { 2089 .name = "MM0", 2090 .keepalive = true, 2091 .num_nodes = 5, 2092 .nodes = { &qnm_camnoc_hf, 2093 &qnm_mdp0_0, 2094 &qnm_mdp0_1, 2095 &qnm_mdp1_0, 2096 &qns_mem_noc_hf 2097 }, 2098 }; 2099 2100 static struct qcom_icc_bcm bcm_mm1 = { 2101 .name = "MM1", 2102 .num_nodes = 8, 2103 .nodes = { &qnm_rot_0, 2104 &qnm_rot_1, 2105 &qnm_video0, 2106 &qnm_video1, 2107 &qnm_video_cvp, 2108 &qxm_camnoc_icp, 2109 &qxm_camnoc_sf, 2110 &qns_mem_noc_sf 2111 }, 2112 }; 2113 2114 static struct qcom_icc_bcm bcm_nsa0 = { 2115 .name = "NSA0", 2116 .num_nodes = 2, 2117 .nodes = { &qns_nsp_gemnoc, 2118 &qxs_nsp_xfr 2119 }, 2120 }; 2121 2122 static struct qcom_icc_bcm bcm_nsa1 = { 2123 .name = "NSA1", 2124 .num_nodes = 1, 2125 .nodes = { &qxm_nsp }, 2126 }; 2127 2128 static struct qcom_icc_bcm bcm_nsb0 = { 2129 .name = "NSB0", 2130 .num_nodes = 2, 2131 .nodes = { &qns_nspb_gemnoc, 2132 &qxs_nspb_xfr 2133 }, 2134 }; 2135 2136 static struct qcom_icc_bcm bcm_nsb1 = { 2137 .name = "NSB1", 2138 .num_nodes = 1, 2139 .nodes = { &qxm_nspb }, 2140 }; 2141 2142 static struct qcom_icc_bcm bcm_pci0 = { 2143 .name = "PCI0", 2144 .num_nodes = 1, 2145 .nodes = { &qns_pcie_gem_noc }, 2146 }; 2147 2148 static struct qcom_icc_bcm bcm_qup0 = { 2149 .name = "QUP0", 2150 .vote_scale = 1, 2151 .num_nodes = 1, 2152 .nodes = { &qup0_core_slave }, 2153 }; 2154 2155 static struct qcom_icc_bcm bcm_qup1 = { 2156 .name = "QUP1", 2157 .vote_scale = 1, 2158 .num_nodes = 1, 2159 .nodes = { &qup1_core_slave }, 2160 }; 2161 2162 static struct qcom_icc_bcm bcm_qup2 = { 2163 .name = "QUP2", 2164 .vote_scale = 1, 2165 .num_nodes = 1, 2166 .nodes = { &qup2_core_slave }, 2167 }; 2168 2169 static struct qcom_icc_bcm bcm_sh0 = { 2170 .name = "SH0", 2171 .keepalive = true, 2172 .num_nodes = 1, 2173 .nodes = { &qns_llcc }, 2174 }; 2175 2176 static struct qcom_icc_bcm bcm_sh2 = { 2177 .name = "SH2", 2178 .num_nodes = 1, 2179 .nodes = { &chm_apps }, 2180 }; 2181 2182 static struct qcom_icc_bcm bcm_sn0 = { 2183 .name = "SN0", 2184 .keepalive = true, 2185 .num_nodes = 1, 2186 .nodes = { &qns_gemnoc_sf }, 2187 }; 2188 2189 static struct qcom_icc_bcm bcm_sn1 = { 2190 .name = "SN1", 2191 .num_nodes = 1, 2192 .nodes = { &qns_gemnoc_gc }, 2193 }; 2194 2195 static struct qcom_icc_bcm bcm_sn2 = { 2196 .name = "SN2", 2197 .num_nodes = 1, 2198 .nodes = { &qxs_pimem }, 2199 }; 2200 2201 static struct qcom_icc_bcm bcm_sn3 = { 2202 .name = "SN3", 2203 .num_nodes = 2, 2204 .nodes = { &qns_a1noc_snoc, 2205 &qnm_aggre1_noc 2206 }, 2207 }; 2208 2209 static struct qcom_icc_bcm bcm_sn4 = { 2210 .name = "SN4", 2211 .num_nodes = 2, 2212 .nodes = { &qns_a2noc_snoc, 2213 &qnm_aggre2_noc 2214 }, 2215 }; 2216 2217 static struct qcom_icc_bcm bcm_sn5 = { 2218 .name = "SN5", 2219 .num_nodes = 2, 2220 .nodes = { &qns_aggre_usb_snoc, 2221 &qnm_aggre_usb_noc 2222 }, 2223 }; 2224 2225 static struct qcom_icc_bcm bcm_sn9 = { 2226 .name = "SN9", 2227 .num_nodes = 2, 2228 .nodes = { &qns_sysnoc, 2229 &qnm_lpass_noc 2230 }, 2231 }; 2232 2233 static struct qcom_icc_bcm bcm_sn10 = { 2234 .name = "SN10", 2235 .num_nodes = 1, 2236 .nodes = { &xs_qdss_stm }, 2237 }; 2238 2239 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 2240 &bcm_sn3, 2241 &bcm_sn5, 2242 }; 2243 2244 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 2245 [MASTER_QSPI_0] = &qhm_qspi, 2246 [MASTER_QUP_1] = &qhm_qup1, 2247 [MASTER_QUP_2] = &qhm_qup2, 2248 [MASTER_A1NOC_CFG] = &qnm_a1noc_cfg, 2249 [MASTER_IPA] = &qxm_ipa, 2250 [MASTER_EMAC_1] = &xm_emac_1, 2251 [MASTER_SDCC_4] = &xm_sdc4, 2252 [MASTER_UFS_MEM] = &xm_ufs_mem, 2253 [MASTER_USB3_0] = &xm_usb3_0, 2254 [MASTER_USB3_1] = &xm_usb3_1, 2255 [MASTER_USB3_MP] = &xm_usb3_mp, 2256 [MASTER_USB4_0] = &xm_usb4_host0, 2257 [MASTER_USB4_1] = &xm_usb4_host1, 2258 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, 2259 [SLAVE_USB_NOC_SNOC] = &qns_aggre_usb_snoc, 2260 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, 2261 }; 2262 2263 static const struct regmap_config sc8280xp_aggre1_noc_regmap_config = { 2264 .reg_bits = 32, 2265 .reg_stride = 4, 2266 .val_bits = 32, 2267 .max_register = 0x3af80, 2268 .fast_io = true, 2269 }; 2270 2271 static const struct qcom_icc_desc sc8280xp_aggre1_noc = { 2272 .config = &sc8280xp_aggre1_noc_regmap_config, 2273 .nodes = aggre1_noc_nodes, 2274 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 2275 .bcms = aggre1_noc_bcms, 2276 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 2277 .qos_requires_clocks = true, 2278 }; 2279 2280 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 2281 &bcm_ce0, 2282 &bcm_pci0, 2283 &bcm_sn4, 2284 }; 2285 2286 static struct qcom_icc_node * const aggre2_noc_nodes[] = { 2287 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 2288 [MASTER_QUP_0] = &qhm_qup0, 2289 [MASTER_A2NOC_CFG] = &qnm_a2noc_cfg, 2290 [MASTER_CRYPTO] = &qxm_crypto, 2291 [MASTER_SENSORS_PROC] = &qxm_sensorss_q6, 2292 [MASTER_SP] = &qxm_sp, 2293 [MASTER_EMAC] = &xm_emac_0, 2294 [MASTER_PCIE_0] = &xm_pcie3_0, 2295 [MASTER_PCIE_1] = &xm_pcie3_1, 2296 [MASTER_PCIE_2A] = &xm_pcie3_2a, 2297 [MASTER_PCIE_2B] = &xm_pcie3_2b, 2298 [MASTER_PCIE_3A] = &xm_pcie3_3a, 2299 [MASTER_PCIE_3B] = &xm_pcie3_3b, 2300 [MASTER_PCIE_4] = &xm_pcie3_4, 2301 [MASTER_QDSS_ETR] = &xm_qdss_etr, 2302 [MASTER_SDCC_2] = &xm_sdc2, 2303 [MASTER_UFS_CARD] = &xm_ufs_card, 2304 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, 2305 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_gem_noc, 2306 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, 2307 }; 2308 2309 static const struct regmap_config sc8280xp_aggre2_noc_regmap_config = { 2310 .reg_bits = 32, 2311 .reg_stride = 4, 2312 .val_bits = 32, 2313 .max_register = 0x3af80, 2314 .fast_io = true, 2315 }; 2316 2317 static const struct qcom_icc_desc sc8280xp_aggre2_noc = { 2318 .config = &sc8280xp_aggre2_noc_regmap_config, 2319 .nodes = aggre2_noc_nodes, 2320 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 2321 .bcms = aggre2_noc_bcms, 2322 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 2323 .qos_requires_clocks = true, 2324 }; 2325 2326 static struct qcom_icc_bcm * const clk_virt_bcms[] = { 2327 &bcm_qup0, 2328 &bcm_qup1, 2329 &bcm_qup2, 2330 }; 2331 2332 static struct qcom_icc_node * const clk_virt_nodes[] = { 2333 [MASTER_QUP_CORE_0] = &qup0_core_master, 2334 [MASTER_QUP_CORE_1] = &qup1_core_master, 2335 [MASTER_QUP_CORE_2] = &qup2_core_master, 2336 [SLAVE_QUP_CORE_0] = &qup0_core_slave, 2337 [SLAVE_QUP_CORE_1] = &qup1_core_slave, 2338 [SLAVE_QUP_CORE_2] = &qup2_core_slave, 2339 }; 2340 2341 static const struct qcom_icc_desc sc8280xp_clk_virt = { 2342 .nodes = clk_virt_nodes, 2343 .num_nodes = ARRAY_SIZE(clk_virt_nodes), 2344 .bcms = clk_virt_bcms, 2345 .num_bcms = ARRAY_SIZE(clk_virt_bcms), 2346 }; 2347 2348 static struct qcom_icc_bcm * const config_noc_bcms[] = { 2349 &bcm_cn0, 2350 &bcm_cn1, 2351 &bcm_cn2, 2352 &bcm_cn3, 2353 &bcm_sn2, 2354 &bcm_sn10, 2355 }; 2356 2357 static struct qcom_icc_node * const config_noc_nodes[] = { 2358 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, 2359 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, 2360 [SLAVE_AHB2PHY_0] = &qhs_ahb2phy0, 2361 [SLAVE_AHB2PHY_1] = &qhs_ahb2phy1, 2362 [SLAVE_AHB2PHY_2] = &qhs_ahb2phy2, 2363 [SLAVE_AOSS] = &qhs_aoss, 2364 [SLAVE_APPSS] = &qhs_apss, 2365 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 2366 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 2367 [SLAVE_CDSP_CFG] = &qhs_compute0_cfg, 2368 [SLAVE_CDSP1_CFG] = &qhs_compute1_cfg, 2369 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 2370 [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx, 2371 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, 2372 [SLAVE_CPR_NSPCX] = &qhs_cpr_nspcx, 2373 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 2374 [SLAVE_CX_RDPM] = &qhs_cx_rdpm, 2375 [SLAVE_DCC_CFG] = &qhs_dcc_cfg, 2376 [SLAVE_DISPLAY_CFG] = &qhs_display0_cfg, 2377 [SLAVE_DISPLAY1_CFG] = &qhs_display1_cfg, 2378 [SLAVE_EMAC_CFG] = &qhs_emac0_cfg, 2379 [SLAVE_EMAC1_CFG] = &qhs_emac1_cfg, 2380 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, 2381 [SLAVE_HWKM] = &qhs_hwkm, 2382 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 2383 [SLAVE_IPA_CFG] = &qhs_ipa, 2384 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, 2385 [SLAVE_LPASS] = &qhs_lpass_cfg, 2386 [SLAVE_MX_RDPM] = &qhs_mx_rdpm, 2387 [SLAVE_MXC_RDPM] = &qhs_mxc_rdpm, 2388 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, 2389 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, 2390 [SLAVE_PCIE_2A_CFG] = &qhs_pcie2a_cfg, 2391 [SLAVE_PCIE_2B_CFG] = &qhs_pcie2b_cfg, 2392 [SLAVE_PCIE_3A_CFG] = &qhs_pcie3a_cfg, 2393 [SLAVE_PCIE_3B_CFG] = &qhs_pcie3b_cfg, 2394 [SLAVE_PCIE_4_CFG] = &qhs_pcie4_cfg, 2395 [SLAVE_PCIE_RSC_CFG] = &qhs_pcie_rsc_cfg, 2396 [SLAVE_PDM] = &qhs_pdm, 2397 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 2398 [SLAVE_PKA_WRAPPER_CFG] = &qhs_pka_wrapper_cfg, 2399 [SLAVE_PMU_WRAPPER_CFG] = &qhs_pmu_wrapper_cfg, 2400 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 2401 [SLAVE_QSPI_0] = &qhs_qspi, 2402 [SLAVE_QUP_0] = &qhs_qup0, 2403 [SLAVE_QUP_1] = &qhs_qup1, 2404 [SLAVE_QUP_2] = &qhs_qup2, 2405 [SLAVE_SDCC_2] = &qhs_sdc2, 2406 [SLAVE_SDCC_4] = &qhs_sdc4, 2407 [SLAVE_SECURITY] = &qhs_security, 2408 [SLAVE_SMMUV3_CFG] = &qhs_smmuv3_cfg, 2409 [SLAVE_SMSS_CFG] = &qhs_smss_cfg, 2410 [SLAVE_SPSS_CFG] = &qhs_spss_cfg, 2411 [SLAVE_TCSR] = &qhs_tcsr, 2412 [SLAVE_TLMM] = &qhs_tlmm, 2413 [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg, 2414 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 2415 [SLAVE_USB3_0] = &qhs_usb3_0, 2416 [SLAVE_USB3_1] = &qhs_usb3_1, 2417 [SLAVE_USB3_MP] = &qhs_usb3_mp, 2418 [SLAVE_USB4_0] = &qhs_usb4_host_0, 2419 [SLAVE_USB4_1] = &qhs_usb4_host_1, 2420 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 2421 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 2422 [SLAVE_VSENSE_CTRL_R_CFG] = &qhs_vsense_ctrl_r_cfg, 2423 [SLAVE_A1NOC_CFG] = &qns_a1_noc_cfg, 2424 [SLAVE_A2NOC_CFG] = &qns_a2_noc_cfg, 2425 [SLAVE_ANOC_PCIE_BRIDGE_CFG] = &qns_anoc_pcie_bridge_cfg, 2426 [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg, 2427 [SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg, 2428 [SLAVE_SNOC_CFG] = &qns_snoc_cfg, 2429 [SLAVE_SNOC_SF_BRIDGE_CFG] = &qns_snoc_sf_bridge_cfg, 2430 [SLAVE_IMEM] = &qxs_imem, 2431 [SLAVE_PIMEM] = &qxs_pimem, 2432 [SLAVE_SERVICE_CNOC] = &srvc_cnoc, 2433 [SLAVE_PCIE_0] = &xs_pcie_0, 2434 [SLAVE_PCIE_1] = &xs_pcie_1, 2435 [SLAVE_PCIE_2A] = &xs_pcie_2a, 2436 [SLAVE_PCIE_2B] = &xs_pcie_2b, 2437 [SLAVE_PCIE_3A] = &xs_pcie_3a, 2438 [SLAVE_PCIE_3B] = &xs_pcie_3b, 2439 [SLAVE_PCIE_4] = &xs_pcie_4, 2440 [SLAVE_QDSS_STM] = &xs_qdss_stm, 2441 [SLAVE_SMSS] = &xs_smss, 2442 [SLAVE_TCU] = &xs_sys_tcu_cfg, 2443 }; 2444 2445 static const struct regmap_config sc8280xp_config_noc_regmap_config = { 2446 .reg_bits = 32, 2447 .reg_stride = 4, 2448 .val_bits = 32, 2449 .max_register = 0x2c000, 2450 .fast_io = true, 2451 }; 2452 2453 static const struct qcom_icc_desc sc8280xp_config_noc = { 2454 .config = &sc8280xp_config_noc_regmap_config, 2455 .nodes = config_noc_nodes, 2456 .num_nodes = ARRAY_SIZE(config_noc_nodes), 2457 .bcms = config_noc_bcms, 2458 .num_bcms = ARRAY_SIZE(config_noc_bcms), 2459 }; 2460 2461 static struct qcom_icc_bcm * const dc_noc_bcms[] = { 2462 }; 2463 2464 static struct qcom_icc_node * const dc_noc_nodes[] = { 2465 [MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc, 2466 [SLAVE_LLCC_CFG] = &qhs_llcc, 2467 [SLAVE_GEM_NOC_CFG] = &qns_gemnoc, 2468 }; 2469 2470 static const struct regmap_config sc8280xp_dc_noc_regmap_config = { 2471 .reg_bits = 32, 2472 .reg_stride = 4, 2473 .val_bits = 32, 2474 .max_register = 0x5080, 2475 .fast_io = true, 2476 }; 2477 2478 static const struct qcom_icc_desc sc8280xp_dc_noc = { 2479 .config = &sc8280xp_dc_noc_regmap_config, 2480 .nodes = dc_noc_nodes, 2481 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 2482 .bcms = dc_noc_bcms, 2483 .num_bcms = ARRAY_SIZE(dc_noc_bcms), 2484 }; 2485 2486 static struct qcom_icc_bcm * const gem_noc_bcms[] = { 2487 &bcm_sh0, 2488 &bcm_sh2, 2489 }; 2490 2491 static struct qcom_icc_node * const gem_noc_nodes[] = { 2492 [MASTER_GPU_TCU] = &alm_gpu_tcu, 2493 [MASTER_PCIE_TCU] = &alm_pcie_tcu, 2494 [MASTER_SYS_TCU] = &alm_sys_tcu, 2495 [MASTER_APPSS_PROC] = &chm_apps, 2496 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc0, 2497 [MASTER_COMPUTE_NOC_1] = &qnm_cmpnoc1, 2498 [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg, 2499 [MASTER_GFX3D] = &qnm_gpu, 2500 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 2501 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 2502 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, 2503 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 2504 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 2505 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, 2506 [SLAVE_LLCC] = &qns_llcc, 2507 [SLAVE_GEM_NOC_PCIE_CNOC] = &qns_pcie, 2508 [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc, 2509 [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc, 2510 [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc, 2511 }; 2512 2513 static const struct regmap_config sc8280xp_gem_noc_regmap_config = { 2514 .reg_bits = 32, 2515 .reg_stride = 4, 2516 .val_bits = 32, 2517 .max_register = 0xb8400, 2518 .fast_io = true, 2519 }; 2520 2521 static const struct qcom_icc_desc sc8280xp_gem_noc = { 2522 .config = &sc8280xp_gem_noc_regmap_config, 2523 .nodes = gem_noc_nodes, 2524 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 2525 .bcms = gem_noc_bcms, 2526 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 2527 }; 2528 2529 static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = { 2530 &bcm_sn9, 2531 }; 2532 2533 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { 2534 [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc, 2535 [MASTER_LPASS_PROC] = &qxm_lpass_dsp, 2536 [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core, 2537 [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi, 2538 [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu, 2539 [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top, 2540 [SLAVE_LPASS_SNOC] = &qns_sysnoc, 2541 [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc, 2542 [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, 2543 }; 2544 2545 static const struct regmap_config sc8280xp_lpass_ag_noc_regmap_config = { 2546 .reg_bits = 32, 2547 .reg_stride = 4, 2548 .val_bits = 32, 2549 .max_register = 0xf080, 2550 .fast_io = true, 2551 }; 2552 2553 static const struct qcom_icc_desc sc8280xp_lpass_ag_noc = { 2554 .config = &sc8280xp_lpass_ag_noc_regmap_config, 2555 .nodes = lpass_ag_noc_nodes, 2556 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), 2557 .bcms = lpass_ag_noc_bcms, 2558 .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms), 2559 }; 2560 2561 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 2562 &bcm_acv, 2563 &bcm_mc0, 2564 }; 2565 2566 static struct qcom_icc_node * const mc_virt_nodes[] = { 2567 [MASTER_LLCC] = &llcc_mc, 2568 [SLAVE_EBI1] = &ebi, 2569 }; 2570 2571 static const struct qcom_icc_desc sc8280xp_mc_virt = { 2572 .nodes = mc_virt_nodes, 2573 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 2574 .bcms = mc_virt_bcms, 2575 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 2576 }; 2577 2578 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 2579 &bcm_mm0, 2580 &bcm_mm1, 2581 }; 2582 2583 static struct qcom_icc_node * const mmss_noc_nodes[] = { 2584 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, 2585 [MASTER_MDP0] = &qnm_mdp0_0, 2586 [MASTER_MDP1] = &qnm_mdp0_1, 2587 [MASTER_MDP_CORE1_0] = &qnm_mdp1_0, 2588 [MASTER_MDP_CORE1_1] = &qnm_mdp1_1, 2589 [MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg, 2590 [MASTER_ROTATOR] = &qnm_rot_0, 2591 [MASTER_ROTATOR_1] = &qnm_rot_1, 2592 [MASTER_VIDEO_P0] = &qnm_video0, 2593 [MASTER_VIDEO_P1] = &qnm_video1, 2594 [MASTER_VIDEO_PROC] = &qnm_video_cvp, 2595 [MASTER_CAMNOC_ICP] = &qxm_camnoc_icp, 2596 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf, 2597 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 2598 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, 2599 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 2600 }; 2601 2602 static const struct regmap_config sc8280xp_mmss_noc_regmap_config = { 2603 .reg_bits = 32, 2604 .reg_stride = 4, 2605 .val_bits = 32, 2606 .max_register = 0x1fa80, 2607 .fast_io = true, 2608 }; 2609 2610 static const struct qcom_icc_desc sc8280xp_mmss_noc = { 2611 .config = &sc8280xp_mmss_noc_regmap_config, 2612 .nodes = mmss_noc_nodes, 2613 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 2614 .bcms = mmss_noc_bcms, 2615 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 2616 }; 2617 2618 static struct qcom_icc_bcm * const nspa_noc_bcms[] = { 2619 &bcm_nsa0, 2620 &bcm_nsa1, 2621 }; 2622 2623 static struct qcom_icc_node * const nspa_noc_nodes[] = { 2624 [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config, 2625 [MASTER_CDSP_PROC] = &qxm_nsp, 2626 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, 2627 [SLAVE_NSP_XFR] = &qxs_nsp_xfr, 2628 [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, 2629 }; 2630 2631 static const struct regmap_config sc8280xp_nspa_noc_regmap_config = { 2632 .reg_bits = 32, 2633 .reg_stride = 4, 2634 .val_bits = 32, 2635 .max_register = 0x10000, 2636 .fast_io = true, 2637 }; 2638 2639 static const struct qcom_icc_desc sc8280xp_nspa_noc = { 2640 .config = &sc8280xp_nspa_noc_regmap_config, 2641 .nodes = nspa_noc_nodes, 2642 .num_nodes = ARRAY_SIZE(nspa_noc_nodes), 2643 .bcms = nspa_noc_bcms, 2644 .num_bcms = ARRAY_SIZE(nspa_noc_bcms), 2645 }; 2646 2647 static struct qcom_icc_bcm * const nspb_noc_bcms[] = { 2648 &bcm_nsb0, 2649 &bcm_nsb1, 2650 }; 2651 2652 static struct qcom_icc_node * const nspb_noc_nodes[] = { 2653 [MASTER_CDSPB_NOC_CFG] = &qhm_nspb_noc_config, 2654 [MASTER_CDSP_PROC_B] = &qxm_nspb, 2655 [SLAVE_CDSPB_MEM_NOC] = &qns_nspb_gemnoc, 2656 [SLAVE_NSPB_XFR] = &qxs_nspb_xfr, 2657 [SLAVE_SERVICE_NSPB_NOC] = &service_nspb_noc, 2658 }; 2659 2660 static const struct regmap_config sc8280xp_nspb_noc_regmap_config = { 2661 .reg_bits = 32, 2662 .reg_stride = 4, 2663 .val_bits = 32, 2664 .max_register = 0x10000, 2665 .fast_io = true, 2666 }; 2667 2668 static const struct qcom_icc_desc sc8280xp_nspb_noc = { 2669 .config = &sc8280xp_nspb_noc_regmap_config, 2670 .nodes = nspb_noc_nodes, 2671 .num_nodes = ARRAY_SIZE(nspb_noc_nodes), 2672 .bcms = nspb_noc_bcms, 2673 .num_bcms = ARRAY_SIZE(nspb_noc_bcms), 2674 }; 2675 2676 static struct qcom_icc_bcm * const system_noc_main_bcms[] = { 2677 &bcm_sn0, 2678 &bcm_sn1, 2679 &bcm_sn3, 2680 &bcm_sn4, 2681 &bcm_sn5, 2682 &bcm_sn9, 2683 }; 2684 2685 static struct qcom_icc_node * const system_noc_main_nodes[] = { 2686 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, 2687 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, 2688 [MASTER_USB_NOC_SNOC] = &qnm_aggre_usb_noc, 2689 [MASTER_LPASS_ANOC] = &qnm_lpass_noc, 2690 [MASTER_SNOC_CFG] = &qnm_snoc_cfg, 2691 [MASTER_PIMEM] = &qxm_pimem, 2692 [MASTER_GIC] = &xm_gic, 2693 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, 2694 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 2695 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 2696 }; 2697 2698 static const struct regmap_config sc8280xp_system_noc_regmap_config = { 2699 .reg_bits = 32, 2700 .reg_stride = 4, 2701 .val_bits = 32, 2702 .max_register = 0x1a400, 2703 .fast_io = true, 2704 }; 2705 2706 static const struct qcom_icc_desc sc8280xp_system_noc_main = { 2707 .config = &sc8280xp_system_noc_regmap_config, 2708 .nodes = system_noc_main_nodes, 2709 .num_nodes = ARRAY_SIZE(system_noc_main_nodes), 2710 .bcms = system_noc_main_bcms, 2711 .num_bcms = ARRAY_SIZE(system_noc_main_bcms), 2712 }; 2713 2714 static const struct of_device_id qnoc_of_match[] = { 2715 { .compatible = "qcom,sc8280xp-aggre1-noc", .data = &sc8280xp_aggre1_noc, }, 2716 { .compatible = "qcom,sc8280xp-aggre2-noc", .data = &sc8280xp_aggre2_noc, }, 2717 { .compatible = "qcom,sc8280xp-clk-virt", .data = &sc8280xp_clk_virt, }, 2718 { .compatible = "qcom,sc8280xp-config-noc", .data = &sc8280xp_config_noc, }, 2719 { .compatible = "qcom,sc8280xp-dc-noc", .data = &sc8280xp_dc_noc, }, 2720 { .compatible = "qcom,sc8280xp-gem-noc", .data = &sc8280xp_gem_noc, }, 2721 { .compatible = "qcom,sc8280xp-lpass-ag-noc", .data = &sc8280xp_lpass_ag_noc, }, 2722 { .compatible = "qcom,sc8280xp-mc-virt", .data = &sc8280xp_mc_virt, }, 2723 { .compatible = "qcom,sc8280xp-mmss-noc", .data = &sc8280xp_mmss_noc, }, 2724 { .compatible = "qcom,sc8280xp-nspa-noc", .data = &sc8280xp_nspa_noc, }, 2725 { .compatible = "qcom,sc8280xp-nspb-noc", .data = &sc8280xp_nspb_noc, }, 2726 { .compatible = "qcom,sc8280xp-system-noc", .data = &sc8280xp_system_noc_main, }, 2727 { } 2728 }; 2729 MODULE_DEVICE_TABLE(of, qnoc_of_match); 2730 2731 static struct platform_driver qnoc_driver = { 2732 .probe = qcom_icc_rpmh_probe, 2733 .remove = qcom_icc_rpmh_remove, 2734 .driver = { 2735 .name = "qnoc-sc8280xp", 2736 .of_match_table = qnoc_of_match, 2737 .sync_state = icc_sync_state, 2738 }, 2739 }; 2740 2741 static int __init qnoc_driver_init(void) 2742 { 2743 return platform_driver_register(&qnoc_driver); 2744 } 2745 core_initcall(qnoc_driver_init); 2746 2747 static void __exit qnoc_driver_exit(void) 2748 { 2749 platform_driver_unregister(&qnoc_driver); 2750 } 2751 module_exit(qnoc_driver_exit); 2752 2753 MODULE_DESCRIPTION("Qualcomm SC8280XP NoC driver"); 2754 MODULE_LICENSE("GPL"); 2755