1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021, Linaro Ltd. 5 */ 6 7 #include <linux/device.h> 8 #include <linux/interconnect-provider.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 12 #include <dt-bindings/interconnect/qcom,sc8180x.h> 13 14 #include "bcm-voter.h" 15 #include "icc-rpmh.h" 16 17 static struct qcom_icc_node mas_qhm_a1noc_cfg; 18 static struct qcom_icc_node mas_xm_ufs_card; 19 static struct qcom_icc_node mas_xm_ufs_g4; 20 static struct qcom_icc_node mas_xm_ufs_mem; 21 static struct qcom_icc_node mas_xm_usb3_0; 22 static struct qcom_icc_node mas_xm_usb3_1; 23 static struct qcom_icc_node mas_xm_usb3_2; 24 static struct qcom_icc_node mas_qhm_a2noc_cfg; 25 static struct qcom_icc_node mas_qhm_qdss_bam; 26 static struct qcom_icc_node mas_qhm_qspi; 27 static struct qcom_icc_node mas_qhm_qspi1; 28 static struct qcom_icc_node mas_qhm_qup0; 29 static struct qcom_icc_node mas_qhm_qup1; 30 static struct qcom_icc_node mas_qhm_qup2; 31 static struct qcom_icc_node mas_qhm_sensorss_ahb; 32 static struct qcom_icc_node mas_qxm_crypto; 33 static struct qcom_icc_node mas_qxm_ipa; 34 static struct qcom_icc_node mas_xm_emac; 35 static struct qcom_icc_node mas_xm_pcie3_0; 36 static struct qcom_icc_node mas_xm_pcie3_1; 37 static struct qcom_icc_node mas_xm_pcie3_2; 38 static struct qcom_icc_node mas_xm_pcie3_3; 39 static struct qcom_icc_node mas_xm_qdss_etr; 40 static struct qcom_icc_node mas_xm_sdc2; 41 static struct qcom_icc_node mas_xm_sdc4; 42 static struct qcom_icc_node mas_qxm_camnoc_hf0_uncomp; 43 static struct qcom_icc_node mas_qxm_camnoc_hf1_uncomp; 44 static struct qcom_icc_node mas_qxm_camnoc_sf_uncomp; 45 static struct qcom_icc_node mas_qnm_npu; 46 static struct qcom_icc_node mas_qnm_snoc; 47 static struct qcom_icc_node mas_qhm_cnoc_dc_noc; 48 static struct qcom_icc_node mas_acm_apps; 49 static struct qcom_icc_node mas_acm_gpu_tcu; 50 static struct qcom_icc_node mas_acm_sys_tcu; 51 static struct qcom_icc_node mas_qhm_gemnoc_cfg; 52 static struct qcom_icc_node mas_qnm_cmpnoc; 53 static struct qcom_icc_node mas_qnm_gpu; 54 static struct qcom_icc_node mas_qnm_mnoc_hf; 55 static struct qcom_icc_node mas_qnm_mnoc_sf; 56 static struct qcom_icc_node mas_qnm_pcie; 57 static struct qcom_icc_node mas_qnm_snoc_gc; 58 static struct qcom_icc_node mas_qnm_snoc_sf; 59 static struct qcom_icc_node mas_qxm_ecc; 60 static struct qcom_icc_node mas_llcc_mc; 61 static struct qcom_icc_node mas_qhm_mnoc_cfg; 62 static struct qcom_icc_node mas_qxm_camnoc_hf0; 63 static struct qcom_icc_node mas_qxm_camnoc_hf1; 64 static struct qcom_icc_node mas_qxm_camnoc_sf; 65 static struct qcom_icc_node mas_qxm_mdp0; 66 static struct qcom_icc_node mas_qxm_mdp1; 67 static struct qcom_icc_node mas_qxm_rot; 68 static struct qcom_icc_node mas_qxm_venus0; 69 static struct qcom_icc_node mas_qxm_venus1; 70 static struct qcom_icc_node mas_qxm_venus_arm9; 71 static struct qcom_icc_node mas_qhm_snoc_cfg; 72 static struct qcom_icc_node mas_qnm_aggre1_noc; 73 static struct qcom_icc_node mas_qnm_aggre2_noc; 74 static struct qcom_icc_node mas_qnm_gemnoc; 75 static struct qcom_icc_node mas_qxm_pimem; 76 static struct qcom_icc_node mas_xm_gic; 77 static struct qcom_icc_node mas_qup_core_0; 78 static struct qcom_icc_node mas_qup_core_1; 79 static struct qcom_icc_node mas_qup_core_2; 80 static struct qcom_icc_node slv_qns_a1noc_snoc; 81 static struct qcom_icc_node slv_srvc_aggre1_noc; 82 static struct qcom_icc_node slv_qns_a2noc_snoc; 83 static struct qcom_icc_node slv_qns_pcie_mem_noc; 84 static struct qcom_icc_node slv_srvc_aggre2_noc; 85 static struct qcom_icc_node slv_qns_camnoc_uncomp; 86 static struct qcom_icc_node slv_qns_cdsp_mem_noc; 87 static struct qcom_icc_node slv_qhs_a1_noc_cfg; 88 static struct qcom_icc_node slv_qhs_a2_noc_cfg; 89 static struct qcom_icc_node slv_qhs_ahb2phy_refgen_center; 90 static struct qcom_icc_node slv_qhs_ahb2phy_refgen_east; 91 static struct qcom_icc_node slv_qhs_ahb2phy_refgen_west; 92 static struct qcom_icc_node slv_qhs_ahb2phy_south; 93 static struct qcom_icc_node slv_qhs_aop; 94 static struct qcom_icc_node slv_qhs_aoss; 95 static struct qcom_icc_node slv_qhs_camera_cfg; 96 static struct qcom_icc_node slv_qhs_clk_ctl; 97 static struct qcom_icc_node slv_qhs_compute_dsp; 98 static struct qcom_icc_node slv_qhs_cpr_cx; 99 static struct qcom_icc_node slv_qhs_cpr_mmcx; 100 static struct qcom_icc_node slv_qhs_cpr_mx; 101 static struct qcom_icc_node slv_qhs_crypto0_cfg; 102 static struct qcom_icc_node slv_qhs_ddrss_cfg; 103 static struct qcom_icc_node slv_qhs_display_cfg; 104 static struct qcom_icc_node slv_qhs_emac_cfg; 105 static struct qcom_icc_node slv_qhs_glm; 106 static struct qcom_icc_node slv_qhs_gpuss_cfg; 107 static struct qcom_icc_node slv_qhs_imem_cfg; 108 static struct qcom_icc_node slv_qhs_ipa; 109 static struct qcom_icc_node slv_qhs_mnoc_cfg; 110 static struct qcom_icc_node slv_qhs_npu_cfg; 111 static struct qcom_icc_node slv_qhs_pcie0_cfg; 112 static struct qcom_icc_node slv_qhs_pcie1_cfg; 113 static struct qcom_icc_node slv_qhs_pcie2_cfg; 114 static struct qcom_icc_node slv_qhs_pcie3_cfg; 115 static struct qcom_icc_node slv_qhs_pdm; 116 static struct qcom_icc_node slv_qhs_pimem_cfg; 117 static struct qcom_icc_node slv_qhs_prng; 118 static struct qcom_icc_node slv_qhs_qdss_cfg; 119 static struct qcom_icc_node slv_qhs_qspi_0; 120 static struct qcom_icc_node slv_qhs_qspi_1; 121 static struct qcom_icc_node slv_qhs_qupv3_east0; 122 static struct qcom_icc_node slv_qhs_qupv3_east1; 123 static struct qcom_icc_node slv_qhs_qupv3_west; 124 static struct qcom_icc_node slv_qhs_sdc2; 125 static struct qcom_icc_node slv_qhs_sdc4; 126 static struct qcom_icc_node slv_qhs_security; 127 static struct qcom_icc_node slv_qhs_snoc_cfg; 128 static struct qcom_icc_node slv_qhs_spss_cfg; 129 static struct qcom_icc_node slv_qhs_tcsr; 130 static struct qcom_icc_node slv_qhs_tlmm_east; 131 static struct qcom_icc_node slv_qhs_tlmm_south; 132 static struct qcom_icc_node slv_qhs_tlmm_west; 133 static struct qcom_icc_node slv_qhs_tsif; 134 static struct qcom_icc_node slv_qhs_ufs_card_cfg; 135 static struct qcom_icc_node slv_qhs_ufs_mem0_cfg; 136 static struct qcom_icc_node slv_qhs_ufs_mem1_cfg; 137 static struct qcom_icc_node slv_qhs_usb3_0; 138 static struct qcom_icc_node slv_qhs_usb3_1; 139 static struct qcom_icc_node slv_qhs_usb3_2; 140 static struct qcom_icc_node slv_qhs_venus_cfg; 141 static struct qcom_icc_node slv_qhs_vsense_ctrl_cfg; 142 static struct qcom_icc_node slv_srvc_cnoc; 143 static struct qcom_icc_node slv_qhs_gemnoc; 144 static struct qcom_icc_node slv_qhs_llcc; 145 static struct qcom_icc_node slv_qhs_mdsp_ms_mpu_cfg; 146 static struct qcom_icc_node slv_qns_ecc; 147 static struct qcom_icc_node slv_qns_gem_noc_snoc; 148 static struct qcom_icc_node slv_qns_llcc; 149 static struct qcom_icc_node slv_srvc_gemnoc; 150 static struct qcom_icc_node slv_srvc_gemnoc1; 151 static struct qcom_icc_node slv_ebi; 152 static struct qcom_icc_node slv_qns2_mem_noc; 153 static struct qcom_icc_node slv_qns_mem_noc_hf; 154 static struct qcom_icc_node slv_srvc_mnoc; 155 static struct qcom_icc_node slv_qhs_apss; 156 static struct qcom_icc_node slv_qns_cnoc; 157 static struct qcom_icc_node slv_qns_gemnoc_gc; 158 static struct qcom_icc_node slv_qns_gemnoc_sf; 159 static struct qcom_icc_node slv_qxs_imem; 160 static struct qcom_icc_node slv_qxs_pimem; 161 static struct qcom_icc_node slv_srvc_snoc; 162 static struct qcom_icc_node slv_xs_pcie_0; 163 static struct qcom_icc_node slv_xs_pcie_1; 164 static struct qcom_icc_node slv_xs_pcie_2; 165 static struct qcom_icc_node slv_xs_pcie_3; 166 static struct qcom_icc_node slv_xs_qdss_stm; 167 static struct qcom_icc_node slv_xs_sys_tcu_cfg; 168 static struct qcom_icc_node slv_qup_core_0; 169 static struct qcom_icc_node slv_qup_core_1; 170 static struct qcom_icc_node slv_qup_core_2; 171 172 static struct qcom_icc_node mas_qhm_a1noc_cfg = { 173 .name = "mas_qhm_a1noc_cfg", 174 .channels = 1, 175 .buswidth = 4, 176 .num_links = 1, 177 .link_nodes = { &slv_srvc_aggre1_noc }, 178 }; 179 180 static struct qcom_icc_node mas_xm_ufs_card = { 181 .name = "mas_xm_ufs_card", 182 .channels = 1, 183 .buswidth = 8, 184 .num_links = 1, 185 .link_nodes = { &slv_qns_a1noc_snoc }, 186 }; 187 188 static struct qcom_icc_node mas_xm_ufs_g4 = { 189 .name = "mas_xm_ufs_g4", 190 .channels = 1, 191 .buswidth = 8, 192 .num_links = 1, 193 .link_nodes = { &slv_qns_a1noc_snoc }, 194 }; 195 196 static struct qcom_icc_node mas_xm_ufs_mem = { 197 .name = "mas_xm_ufs_mem", 198 .channels = 1, 199 .buswidth = 8, 200 .num_links = 1, 201 .link_nodes = { &slv_qns_a1noc_snoc }, 202 }; 203 204 static struct qcom_icc_node mas_xm_usb3_0 = { 205 .name = "mas_xm_usb3_0", 206 .channels = 1, 207 .buswidth = 8, 208 .num_links = 1, 209 .link_nodes = { &slv_qns_a1noc_snoc }, 210 }; 211 212 static struct qcom_icc_node mas_xm_usb3_1 = { 213 .name = "mas_xm_usb3_1", 214 .channels = 1, 215 .buswidth = 8, 216 .num_links = 1, 217 .link_nodes = { &slv_qns_a1noc_snoc }, 218 }; 219 220 static struct qcom_icc_node mas_xm_usb3_2 = { 221 .name = "mas_xm_usb3_2", 222 .channels = 1, 223 .buswidth = 16, 224 .num_links = 1, 225 .link_nodes = { &slv_qns_a1noc_snoc }, 226 }; 227 228 static struct qcom_icc_node mas_qhm_a2noc_cfg = { 229 .name = "mas_qhm_a2noc_cfg", 230 .channels = 1, 231 .buswidth = 4, 232 .num_links = 1, 233 .link_nodes = { &slv_srvc_aggre2_noc }, 234 }; 235 236 static struct qcom_icc_node mas_qhm_qdss_bam = { 237 .name = "mas_qhm_qdss_bam", 238 .channels = 1, 239 .buswidth = 4, 240 .num_links = 1, 241 .link_nodes = { &slv_qns_a2noc_snoc }, 242 }; 243 244 static struct qcom_icc_node mas_qhm_qspi = { 245 .name = "mas_qhm_qspi", 246 .channels = 1, 247 .buswidth = 4, 248 .num_links = 1, 249 .link_nodes = { &slv_qns_a2noc_snoc }, 250 }; 251 252 static struct qcom_icc_node mas_qhm_qspi1 = { 253 .name = "mas_qhm_qspi1", 254 .channels = 1, 255 .buswidth = 4, 256 .num_links = 1, 257 .link_nodes = { &slv_qns_a2noc_snoc }, 258 }; 259 260 static struct qcom_icc_node mas_qhm_qup0 = { 261 .name = "mas_qhm_qup0", 262 .channels = 1, 263 .buswidth = 4, 264 .num_links = 1, 265 .link_nodes = { &slv_qns_a2noc_snoc }, 266 }; 267 268 static struct qcom_icc_node mas_qhm_qup1 = { 269 .name = "mas_qhm_qup1", 270 .channels = 1, 271 .buswidth = 4, 272 .num_links = 1, 273 .link_nodes = { &slv_qns_a2noc_snoc }, 274 }; 275 276 static struct qcom_icc_node mas_qhm_qup2 = { 277 .name = "mas_qhm_qup2", 278 .channels = 1, 279 .buswidth = 4, 280 .num_links = 1, 281 .link_nodes = { &slv_qns_a2noc_snoc }, 282 }; 283 284 static struct qcom_icc_node mas_qhm_sensorss_ahb = { 285 .name = "mas_qhm_sensorss_ahb", 286 .channels = 1, 287 .buswidth = 4, 288 .num_links = 1, 289 .link_nodes = { &slv_qns_a2noc_snoc }, 290 }; 291 292 static struct qcom_icc_node mas_qxm_crypto = { 293 .name = "mas_qxm_crypto", 294 .channels = 1, 295 .buswidth = 8, 296 .num_links = 1, 297 .link_nodes = { &slv_qns_a2noc_snoc }, 298 }; 299 300 static struct qcom_icc_node mas_qxm_ipa = { 301 .name = "mas_qxm_ipa", 302 .channels = 1, 303 .buswidth = 8, 304 .num_links = 1, 305 .link_nodes = { &slv_qns_a2noc_snoc }, 306 }; 307 308 static struct qcom_icc_node mas_xm_emac = { 309 .name = "mas_xm_emac", 310 .channels = 1, 311 .buswidth = 8, 312 .num_links = 1, 313 .link_nodes = { &slv_qns_a2noc_snoc }, 314 }; 315 316 static struct qcom_icc_node mas_xm_pcie3_0 = { 317 .name = "mas_xm_pcie3_0", 318 .channels = 1, 319 .buswidth = 8, 320 .num_links = 1, 321 .link_nodes = { &slv_qns_pcie_mem_noc }, 322 }; 323 324 static struct qcom_icc_node mas_xm_pcie3_1 = { 325 .name = "mas_xm_pcie3_1", 326 .channels = 1, 327 .buswidth = 16, 328 .num_links = 1, 329 .link_nodes = { &slv_qns_pcie_mem_noc }, 330 }; 331 332 static struct qcom_icc_node mas_xm_pcie3_2 = { 333 .name = "mas_xm_pcie3_2", 334 .channels = 1, 335 .buswidth = 8, 336 .num_links = 1, 337 .link_nodes = { &slv_qns_pcie_mem_noc }, 338 }; 339 340 static struct qcom_icc_node mas_xm_pcie3_3 = { 341 .name = "mas_xm_pcie3_3", 342 .channels = 1, 343 .buswidth = 16, 344 .num_links = 1, 345 .link_nodes = { &slv_qns_pcie_mem_noc }, 346 }; 347 348 static struct qcom_icc_node mas_xm_qdss_etr = { 349 .name = "mas_xm_qdss_etr", 350 .channels = 1, 351 .buswidth = 8, 352 .num_links = 1, 353 .link_nodes = { &slv_qns_a2noc_snoc }, 354 }; 355 356 static struct qcom_icc_node mas_xm_sdc2 = { 357 .name = "mas_xm_sdc2", 358 .channels = 1, 359 .buswidth = 8, 360 .num_links = 1, 361 .link_nodes = { &slv_qns_a2noc_snoc }, 362 }; 363 364 static struct qcom_icc_node mas_xm_sdc4 = { 365 .name = "mas_xm_sdc4", 366 .channels = 1, 367 .buswidth = 8, 368 .num_links = 1, 369 .link_nodes = { &slv_qns_a2noc_snoc }, 370 }; 371 372 static struct qcom_icc_node mas_qxm_camnoc_hf0_uncomp = { 373 .name = "mas_qxm_camnoc_hf0_uncomp", 374 .channels = 1, 375 .buswidth = 32, 376 .num_links = 1, 377 .link_nodes = { &slv_qns_camnoc_uncomp }, 378 }; 379 380 static struct qcom_icc_node mas_qxm_camnoc_hf1_uncomp = { 381 .name = "mas_qxm_camnoc_hf1_uncomp", 382 .channels = 1, 383 .buswidth = 32, 384 .num_links = 1, 385 .link_nodes = { &slv_qns_camnoc_uncomp }, 386 }; 387 388 static struct qcom_icc_node mas_qxm_camnoc_sf_uncomp = { 389 .name = "mas_qxm_camnoc_sf_uncomp", 390 .channels = 1, 391 .buswidth = 32, 392 .num_links = 1, 393 .link_nodes = { &slv_qns_camnoc_uncomp }, 394 }; 395 396 static struct qcom_icc_node mas_qnm_npu = { 397 .name = "mas_qnm_npu", 398 .channels = 1, 399 .buswidth = 32, 400 .num_links = 1, 401 .link_nodes = { &slv_qns_cdsp_mem_noc }, 402 }; 403 404 static struct qcom_icc_node mas_qnm_snoc = { 405 .name = "mas_qnm_snoc", 406 .channels = 1, 407 .buswidth = 8, 408 .num_links = 56, 409 .link_nodes = { &slv_qhs_tlmm_south, 410 &slv_qhs_compute_dsp, 411 &slv_qhs_spss_cfg, 412 &slv_qhs_camera_cfg, 413 &slv_qhs_sdc4, 414 &slv_qhs_ahb2phy_refgen_center, 415 &slv_qhs_sdc2, 416 &slv_qhs_pcie2_cfg, 417 &slv_qhs_mnoc_cfg, 418 &slv_qhs_emac_cfg, 419 &slv_qhs_qspi_0, 420 &slv_qhs_qspi_1, 421 &slv_qhs_tlmm_east, 422 &slv_qhs_snoc_cfg, 423 &slv_qhs_ahb2phy_refgen_east, 424 &slv_qhs_glm, 425 &slv_qhs_pdm, 426 &slv_qhs_pcie1_cfg, 427 &slv_qhs_a2_noc_cfg, 428 &slv_qhs_qdss_cfg, 429 &slv_qhs_display_cfg, 430 &slv_qhs_tcsr, 431 &slv_qhs_ufs_mem0_cfg, 432 &slv_qhs_ddrss_cfg, 433 &slv_qhs_pcie0_cfg, 434 &slv_qhs_qupv3_east0, 435 &slv_qhs_qupv3_east1, 436 &slv_qhs_npu_cfg, 437 &slv_qhs_crypto0_cfg, 438 &slv_qhs_gpuss_cfg, 439 &slv_qhs_venus_cfg, 440 &slv_qhs_tsif, 441 &slv_qhs_ipa, 442 &slv_qhs_clk_ctl, 443 &slv_qhs_security, 444 &slv_qhs_aop, 445 &slv_qhs_ahb2phy_refgen_west, 446 &slv_qhs_ahb2phy_south, 447 &slv_srvc_cnoc, 448 &slv_qhs_ufs_card_cfg, 449 &slv_qhs_usb3_1, 450 &slv_qhs_usb3_2, 451 &slv_qhs_pcie3_cfg, 452 &slv_qhs_cpr_cx, 453 &slv_qhs_tlmm_west, 454 &slv_qhs_a1_noc_cfg, 455 &slv_qhs_aoss, 456 &slv_qhs_prng, 457 &slv_qhs_vsense_ctrl_cfg, 458 &slv_qhs_qupv3_west, 459 &slv_qhs_usb3_0, 460 &slv_qhs_cpr_mmcx, 461 &slv_qhs_pimem_cfg, 462 &slv_qhs_ufs_mem1_cfg, 463 &slv_qhs_cpr_mx, 464 &slv_qhs_imem_cfg }, 465 }; 466 467 static struct qcom_icc_node mas_qhm_cnoc_dc_noc = { 468 .name = "mas_qhm_cnoc_dc_noc", 469 .channels = 1, 470 .buswidth = 4, 471 .num_links = 2, 472 .link_nodes = { &slv_qhs_llcc, 473 &slv_qhs_gemnoc }, 474 }; 475 476 static struct qcom_icc_node mas_acm_apps = { 477 .name = "mas_acm_apps", 478 .channels = 4, 479 .buswidth = 64, 480 .num_links = 3, 481 .link_nodes = { &slv_qns_ecc, 482 &slv_qns_llcc, 483 &slv_qns_gem_noc_snoc }, 484 }; 485 486 static struct qcom_icc_node mas_acm_gpu_tcu = { 487 .name = "mas_acm_gpu_tcu", 488 .channels = 1, 489 .buswidth = 8, 490 .num_links = 2, 491 .link_nodes = { &slv_qns_llcc, 492 &slv_qns_gem_noc_snoc }, 493 }; 494 495 static struct qcom_icc_node mas_acm_sys_tcu = { 496 .name = "mas_acm_sys_tcu", 497 .channels = 1, 498 .buswidth = 8, 499 .num_links = 2, 500 .link_nodes = { &slv_qns_llcc, 501 &slv_qns_gem_noc_snoc }, 502 }; 503 504 static struct qcom_icc_node mas_qhm_gemnoc_cfg = { 505 .name = "mas_qhm_gemnoc_cfg", 506 .channels = 1, 507 .buswidth = 4, 508 .num_links = 3, 509 .link_nodes = { &slv_srvc_gemnoc1, 510 &slv_srvc_gemnoc, 511 &slv_qhs_mdsp_ms_mpu_cfg }, 512 }; 513 514 static struct qcom_icc_node mas_qnm_cmpnoc = { 515 .name = "mas_qnm_cmpnoc", 516 .channels = 2, 517 .buswidth = 32, 518 .num_links = 3, 519 .link_nodes = { &slv_qns_ecc, 520 &slv_qns_llcc, 521 &slv_qns_gem_noc_snoc }, 522 }; 523 524 static struct qcom_icc_node mas_qnm_gpu = { 525 .name = "mas_qnm_gpu", 526 .channels = 4, 527 .buswidth = 32, 528 .num_links = 2, 529 .link_nodes = { &slv_qns_llcc, 530 &slv_qns_gem_noc_snoc }, 531 }; 532 533 static struct qcom_icc_node mas_qnm_mnoc_hf = { 534 .name = "mas_qnm_mnoc_hf", 535 .channels = 2, 536 .buswidth = 32, 537 .num_links = 1, 538 .link_nodes = { &slv_qns_llcc }, 539 }; 540 541 static struct qcom_icc_node mas_qnm_mnoc_sf = { 542 .name = "mas_qnm_mnoc_sf", 543 .channels = 1, 544 .buswidth = 32, 545 .num_links = 2, 546 .link_nodes = { &slv_qns_llcc, 547 &slv_qns_gem_noc_snoc }, 548 }; 549 550 static struct qcom_icc_node mas_qnm_pcie = { 551 .name = "mas_qnm_pcie", 552 .channels = 1, 553 .buswidth = 32, 554 .num_links = 2, 555 .link_nodes = { &slv_qns_llcc, 556 &slv_qns_gem_noc_snoc }, 557 }; 558 559 static struct qcom_icc_node mas_qnm_snoc_gc = { 560 .name = "mas_qnm_snoc_gc", 561 .channels = 1, 562 .buswidth = 8, 563 .num_links = 1, 564 .link_nodes = { &slv_qns_llcc }, 565 }; 566 567 static struct qcom_icc_node mas_qnm_snoc_sf = { 568 .name = "mas_qnm_snoc_sf", 569 .channels = 1, 570 .buswidth = 32, 571 .num_links = 1, 572 .link_nodes = { &slv_qns_llcc }, 573 }; 574 575 static struct qcom_icc_node mas_qxm_ecc = { 576 .name = "mas_qxm_ecc", 577 .channels = 2, 578 .buswidth = 32, 579 .num_links = 1, 580 .link_nodes = { &slv_qns_llcc }, 581 }; 582 583 static struct qcom_icc_node mas_llcc_mc = { 584 .name = "mas_llcc_mc", 585 .channels = 8, 586 .buswidth = 4, 587 .num_links = 1, 588 .link_nodes = { &slv_ebi }, 589 }; 590 591 static struct qcom_icc_node mas_qhm_mnoc_cfg = { 592 .name = "mas_qhm_mnoc_cfg", 593 .channels = 1, 594 .buswidth = 4, 595 .num_links = 1, 596 .link_nodes = { &slv_srvc_mnoc }, 597 }; 598 599 static struct qcom_icc_node mas_qxm_camnoc_hf0 = { 600 .name = "mas_qxm_camnoc_hf0", 601 .channels = 1, 602 .buswidth = 32, 603 .num_links = 1, 604 .link_nodes = { &slv_qns_mem_noc_hf }, 605 }; 606 607 static struct qcom_icc_node mas_qxm_camnoc_hf1 = { 608 .name = "mas_qxm_camnoc_hf1", 609 .channels = 1, 610 .buswidth = 32, 611 .num_links = 1, 612 .link_nodes = { &slv_qns_mem_noc_hf }, 613 }; 614 615 static struct qcom_icc_node mas_qxm_camnoc_sf = { 616 .name = "mas_qxm_camnoc_sf", 617 .channels = 1, 618 .buswidth = 32, 619 .num_links = 1, 620 .link_nodes = { &slv_qns2_mem_noc }, 621 }; 622 623 static struct qcom_icc_node mas_qxm_mdp0 = { 624 .name = "mas_qxm_mdp0", 625 .channels = 1, 626 .buswidth = 32, 627 .num_links = 1, 628 .link_nodes = { &slv_qns_mem_noc_hf }, 629 }; 630 631 static struct qcom_icc_node mas_qxm_mdp1 = { 632 .name = "mas_qxm_mdp1", 633 .channels = 1, 634 .buswidth = 32, 635 .num_links = 1, 636 .link_nodes = { &slv_qns_mem_noc_hf }, 637 }; 638 639 static struct qcom_icc_node mas_qxm_rot = { 640 .name = "mas_qxm_rot", 641 .channels = 1, 642 .buswidth = 32, 643 .num_links = 1, 644 .link_nodes = { &slv_qns2_mem_noc }, 645 }; 646 647 static struct qcom_icc_node mas_qxm_venus0 = { 648 .name = "mas_qxm_venus0", 649 .channels = 1, 650 .buswidth = 32, 651 .num_links = 1, 652 .link_nodes = { &slv_qns2_mem_noc }, 653 }; 654 655 static struct qcom_icc_node mas_qxm_venus1 = { 656 .name = "mas_qxm_venus1", 657 .channels = 1, 658 .buswidth = 32, 659 .num_links = 1, 660 .link_nodes = { &slv_qns2_mem_noc }, 661 }; 662 663 static struct qcom_icc_node mas_qxm_venus_arm9 = { 664 .name = "mas_qxm_venus_arm9", 665 .channels = 1, 666 .buswidth = 8, 667 .num_links = 1, 668 .link_nodes = { &slv_qns2_mem_noc }, 669 }; 670 671 static struct qcom_icc_node mas_qhm_snoc_cfg = { 672 .name = "mas_qhm_snoc_cfg", 673 .channels = 1, 674 .buswidth = 4, 675 .num_links = 1, 676 .link_nodes = { &slv_srvc_snoc }, 677 }; 678 679 static struct qcom_icc_node mas_qnm_aggre1_noc = { 680 .name = "mas_qnm_aggre1_noc", 681 .channels = 1, 682 .buswidth = 32, 683 .num_links = 6, 684 .link_nodes = { &slv_qns_gemnoc_sf, 685 &slv_qxs_pimem, 686 &slv_qxs_imem, 687 &slv_qhs_apss, 688 &slv_qns_cnoc, 689 &slv_xs_qdss_stm }, 690 }; 691 692 static struct qcom_icc_node mas_qnm_aggre2_noc = { 693 .name = "mas_qnm_aggre2_noc", 694 .channels = 1, 695 .buswidth = 16, 696 .num_links = 11, 697 .link_nodes = { &slv_qns_gemnoc_sf, 698 &slv_qxs_pimem, 699 &slv_xs_pcie_3, 700 &slv_qxs_imem, 701 &slv_qhs_apss, 702 &slv_xs_pcie_2, 703 &slv_qns_cnoc, 704 &slv_xs_pcie_0, 705 &slv_xs_pcie_1, 706 &slv_xs_sys_tcu_cfg, 707 &slv_xs_qdss_stm }, 708 }; 709 710 static struct qcom_icc_node mas_qnm_gemnoc = { 711 .name = "mas_qnm_gemnoc", 712 .channels = 1, 713 .buswidth = 8, 714 .num_links = 6, 715 .link_nodes = { &slv_qxs_pimem, 716 &slv_qxs_imem, 717 &slv_qhs_apss, 718 &slv_qns_cnoc, 719 &slv_xs_sys_tcu_cfg, 720 &slv_xs_qdss_stm }, 721 }; 722 723 static struct qcom_icc_node mas_qxm_pimem = { 724 .name = "mas_qxm_pimem", 725 .channels = 1, 726 .buswidth = 8, 727 .num_links = 2, 728 .link_nodes = { &slv_qns_gemnoc_gc, 729 &slv_qxs_imem }, 730 }; 731 732 static struct qcom_icc_node mas_xm_gic = { 733 .name = "mas_xm_gic", 734 .channels = 1, 735 .buswidth = 8, 736 .num_links = 2, 737 .link_nodes = { &slv_qns_gemnoc_gc, 738 &slv_qxs_imem }, 739 }; 740 741 static struct qcom_icc_node mas_qup_core_0 = { 742 .name = "mas_qup_core_0", 743 .channels = 1, 744 .buswidth = 4, 745 .num_links = 1, 746 .link_nodes = { &slv_qup_core_0 }, 747 }; 748 749 static struct qcom_icc_node mas_qup_core_1 = { 750 .name = "mas_qup_core_1", 751 .channels = 1, 752 .buswidth = 4, 753 .num_links = 1, 754 .link_nodes = { &slv_qup_core_1 }, 755 }; 756 757 static struct qcom_icc_node mas_qup_core_2 = { 758 .name = "mas_qup_core_2", 759 .channels = 1, 760 .buswidth = 4, 761 .num_links = 1, 762 .link_nodes = { &slv_qup_core_2 }, 763 }; 764 765 static struct qcom_icc_node slv_qns_a1noc_snoc = { 766 .name = "slv_qns_a1noc_snoc", 767 .channels = 1, 768 .buswidth = 32, 769 .num_links = 1, 770 .link_nodes = { &mas_qnm_aggre1_noc }, 771 }; 772 773 static struct qcom_icc_node slv_srvc_aggre1_noc = { 774 .name = "slv_srvc_aggre1_noc", 775 .channels = 1, 776 .buswidth = 4 777 }; 778 779 static struct qcom_icc_node slv_qns_a2noc_snoc = { 780 .name = "slv_qns_a2noc_snoc", 781 .channels = 1, 782 .buswidth = 16, 783 .num_links = 1, 784 .link_nodes = { &mas_qnm_aggre2_noc }, 785 }; 786 787 static struct qcom_icc_node slv_qns_pcie_mem_noc = { 788 .name = "slv_qns_pcie_mem_noc", 789 .channels = 1, 790 .buswidth = 32, 791 .num_links = 1, 792 .link_nodes = { &mas_qnm_pcie }, 793 }; 794 795 static struct qcom_icc_node slv_srvc_aggre2_noc = { 796 .name = "slv_srvc_aggre2_noc", 797 .channels = 1, 798 .buswidth = 4 799 }; 800 801 static struct qcom_icc_node slv_qns_camnoc_uncomp = { 802 .name = "slv_qns_camnoc_uncomp", 803 .channels = 1, 804 .buswidth = 32 805 }; 806 807 static struct qcom_icc_node slv_qns_cdsp_mem_noc = { 808 .name = "slv_qns_cdsp_mem_noc", 809 .channels = 2, 810 .buswidth = 32, 811 .num_links = 1, 812 .link_nodes = { &mas_qnm_cmpnoc }, 813 }; 814 815 static struct qcom_icc_node slv_qhs_a1_noc_cfg = { 816 .name = "slv_qhs_a1_noc_cfg", 817 .channels = 1, 818 .buswidth = 4, 819 .num_links = 1, 820 .link_nodes = { &mas_qhm_a1noc_cfg }, 821 }; 822 823 static struct qcom_icc_node slv_qhs_a2_noc_cfg = { 824 .name = "slv_qhs_a2_noc_cfg", 825 .channels = 1, 826 .buswidth = 4, 827 .num_links = 1, 828 .link_nodes = { &mas_qhm_a2noc_cfg }, 829 }; 830 831 static struct qcom_icc_node slv_qhs_ahb2phy_refgen_center = { 832 .name = "slv_qhs_ahb2phy_refgen_center", 833 .channels = 1, 834 .buswidth = 4 835 }; 836 837 static struct qcom_icc_node slv_qhs_ahb2phy_refgen_east = { 838 .name = "slv_qhs_ahb2phy_refgen_east", 839 .channels = 1, 840 .buswidth = 4 841 }; 842 843 static struct qcom_icc_node slv_qhs_ahb2phy_refgen_west = { 844 .name = "slv_qhs_ahb2phy_refgen_west", 845 .channels = 1, 846 .buswidth = 4 847 }; 848 849 static struct qcom_icc_node slv_qhs_ahb2phy_south = { 850 .name = "slv_qhs_ahb2phy_south", 851 .channels = 1, 852 .buswidth = 4 853 }; 854 855 static struct qcom_icc_node slv_qhs_aop = { 856 .name = "slv_qhs_aop", 857 .channels = 1, 858 .buswidth = 4 859 }; 860 861 static struct qcom_icc_node slv_qhs_aoss = { 862 .name = "slv_qhs_aoss", 863 .channels = 1, 864 .buswidth = 4 865 }; 866 867 static struct qcom_icc_node slv_qhs_camera_cfg = { 868 .name = "slv_qhs_camera_cfg", 869 .channels = 1, 870 .buswidth = 4 871 }; 872 873 static struct qcom_icc_node slv_qhs_clk_ctl = { 874 .name = "slv_qhs_clk_ctl", 875 .channels = 1, 876 .buswidth = 4 877 }; 878 879 static struct qcom_icc_node slv_qhs_compute_dsp = { 880 .name = "slv_qhs_compute_dsp", 881 .channels = 1, 882 .buswidth = 4 883 }; 884 885 static struct qcom_icc_node slv_qhs_cpr_cx = { 886 .name = "slv_qhs_cpr_cx", 887 .channels = 1, 888 .buswidth = 4 889 }; 890 891 static struct qcom_icc_node slv_qhs_cpr_mmcx = { 892 .name = "slv_qhs_cpr_mmcx", 893 .channels = 1, 894 .buswidth = 4 895 }; 896 897 static struct qcom_icc_node slv_qhs_cpr_mx = { 898 .name = "slv_qhs_cpr_mx", 899 .channels = 1, 900 .buswidth = 4 901 }; 902 903 static struct qcom_icc_node slv_qhs_crypto0_cfg = { 904 .name = "slv_qhs_crypto0_cfg", 905 .channels = 1, 906 .buswidth = 4 907 }; 908 909 static struct qcom_icc_node slv_qhs_ddrss_cfg = { 910 .name = "slv_qhs_ddrss_cfg", 911 .channels = 1, 912 .buswidth = 4, 913 .num_links = 1, 914 .link_nodes = { &mas_qhm_cnoc_dc_noc }, 915 }; 916 917 static struct qcom_icc_node slv_qhs_display_cfg = { 918 .name = "slv_qhs_display_cfg", 919 .channels = 1, 920 .buswidth = 4 921 }; 922 923 static struct qcom_icc_node slv_qhs_emac_cfg = { 924 .name = "slv_qhs_emac_cfg", 925 .channels = 1, 926 .buswidth = 4 927 }; 928 929 static struct qcom_icc_node slv_qhs_glm = { 930 .name = "slv_qhs_glm", 931 .channels = 1, 932 .buswidth = 4 933 }; 934 935 static struct qcom_icc_node slv_qhs_gpuss_cfg = { 936 .name = "slv_qhs_gpuss_cfg", 937 .channels = 1, 938 .buswidth = 8 939 }; 940 941 static struct qcom_icc_node slv_qhs_imem_cfg = { 942 .name = "slv_qhs_imem_cfg", 943 .channels = 1, 944 .buswidth = 4 945 }; 946 947 static struct qcom_icc_node slv_qhs_ipa = { 948 .name = "slv_qhs_ipa", 949 .channels = 1, 950 .buswidth = 4 951 }; 952 953 static struct qcom_icc_node slv_qhs_mnoc_cfg = { 954 .name = "slv_qhs_mnoc_cfg", 955 .channels = 1, 956 .buswidth = 4, 957 .num_links = 1, 958 .link_nodes = { &mas_qhm_mnoc_cfg }, 959 }; 960 961 static struct qcom_icc_node slv_qhs_npu_cfg = { 962 .name = "slv_qhs_npu_cfg", 963 .channels = 1, 964 .buswidth = 4 965 }; 966 967 static struct qcom_icc_node slv_qhs_pcie0_cfg = { 968 .name = "slv_qhs_pcie0_cfg", 969 .channels = 1, 970 .buswidth = 4 971 }; 972 973 static struct qcom_icc_node slv_qhs_pcie1_cfg = { 974 .name = "slv_qhs_pcie1_cfg", 975 .channels = 1, 976 .buswidth = 4 977 }; 978 979 static struct qcom_icc_node slv_qhs_pcie2_cfg = { 980 .name = "slv_qhs_pcie2_cfg", 981 .channels = 1, 982 .buswidth = 4 983 }; 984 985 static struct qcom_icc_node slv_qhs_pcie3_cfg = { 986 .name = "slv_qhs_pcie3_cfg", 987 .channels = 1, 988 .buswidth = 4 989 }; 990 991 static struct qcom_icc_node slv_qhs_pdm = { 992 .name = "slv_qhs_pdm", 993 .channels = 1, 994 .buswidth = 4 995 }; 996 997 static struct qcom_icc_node slv_qhs_pimem_cfg = { 998 .name = "slv_qhs_pimem_cfg", 999 .channels = 1, 1000 .buswidth = 4 1001 }; 1002 1003 static struct qcom_icc_node slv_qhs_prng = { 1004 .name = "slv_qhs_prng", 1005 .channels = 1, 1006 .buswidth = 4 1007 }; 1008 1009 static struct qcom_icc_node slv_qhs_qdss_cfg = { 1010 .name = "slv_qhs_qdss_cfg", 1011 .channels = 1, 1012 .buswidth = 4 1013 }; 1014 1015 static struct qcom_icc_node slv_qhs_qspi_0 = { 1016 .name = "slv_qhs_qspi_0", 1017 .channels = 1, 1018 .buswidth = 4 1019 }; 1020 1021 static struct qcom_icc_node slv_qhs_qspi_1 = { 1022 .name = "slv_qhs_qspi_1", 1023 .channels = 1, 1024 .buswidth = 4 1025 }; 1026 1027 static struct qcom_icc_node slv_qhs_qupv3_east0 = { 1028 .name = "slv_qhs_qupv3_east0", 1029 .channels = 1, 1030 .buswidth = 4 1031 }; 1032 1033 static struct qcom_icc_node slv_qhs_qupv3_east1 = { 1034 .name = "slv_qhs_qupv3_east1", 1035 .channels = 1, 1036 .buswidth = 4 1037 }; 1038 1039 static struct qcom_icc_node slv_qhs_qupv3_west = { 1040 .name = "slv_qhs_qupv3_west", 1041 .channels = 1, 1042 .buswidth = 4 1043 }; 1044 1045 static struct qcom_icc_node slv_qhs_sdc2 = { 1046 .name = "slv_qhs_sdc2", 1047 .channels = 1, 1048 .buswidth = 4 1049 }; 1050 1051 static struct qcom_icc_node slv_qhs_sdc4 = { 1052 .name = "slv_qhs_sdc4", 1053 .channels = 1, 1054 .buswidth = 4 1055 }; 1056 1057 static struct qcom_icc_node slv_qhs_security = { 1058 .name = "slv_qhs_security", 1059 .channels = 1, 1060 .buswidth = 4 1061 }; 1062 1063 static struct qcom_icc_node slv_qhs_snoc_cfg = { 1064 .name = "slv_qhs_snoc_cfg", 1065 .channels = 1, 1066 .buswidth = 4, 1067 .num_links = 1, 1068 .link_nodes = { &mas_qhm_snoc_cfg }, 1069 }; 1070 1071 static struct qcom_icc_node slv_qhs_spss_cfg = { 1072 .name = "slv_qhs_spss_cfg", 1073 .channels = 1, 1074 .buswidth = 4 1075 }; 1076 1077 static struct qcom_icc_node slv_qhs_tcsr = { 1078 .name = "slv_qhs_tcsr", 1079 .channels = 1, 1080 .buswidth = 4 1081 }; 1082 1083 static struct qcom_icc_node slv_qhs_tlmm_east = { 1084 .name = "slv_qhs_tlmm_east", 1085 .channels = 1, 1086 .buswidth = 4 1087 }; 1088 1089 static struct qcom_icc_node slv_qhs_tlmm_south = { 1090 .name = "slv_qhs_tlmm_south", 1091 .channels = 1, 1092 .buswidth = 4 1093 }; 1094 1095 static struct qcom_icc_node slv_qhs_tlmm_west = { 1096 .name = "slv_qhs_tlmm_west", 1097 .channels = 1, 1098 .buswidth = 4 1099 }; 1100 1101 static struct qcom_icc_node slv_qhs_tsif = { 1102 .name = "slv_qhs_tsif", 1103 .channels = 1, 1104 .buswidth = 4 1105 }; 1106 1107 static struct qcom_icc_node slv_qhs_ufs_card_cfg = { 1108 .name = "slv_qhs_ufs_card_cfg", 1109 .channels = 1, 1110 .buswidth = 4 1111 }; 1112 1113 static struct qcom_icc_node slv_qhs_ufs_mem0_cfg = { 1114 .name = "slv_qhs_ufs_mem0_cfg", 1115 .channels = 1, 1116 .buswidth = 4 1117 }; 1118 1119 static struct qcom_icc_node slv_qhs_ufs_mem1_cfg = { 1120 .name = "slv_qhs_ufs_mem1_cfg", 1121 .channels = 1, 1122 .buswidth = 4 1123 }; 1124 1125 static struct qcom_icc_node slv_qhs_usb3_0 = { 1126 .name = "slv_qhs_usb3_0", 1127 .channels = 1, 1128 .buswidth = 4 1129 }; 1130 1131 static struct qcom_icc_node slv_qhs_usb3_1 = { 1132 .name = "slv_qhs_usb3_1", 1133 .channels = 1, 1134 .buswidth = 4 1135 }; 1136 1137 static struct qcom_icc_node slv_qhs_usb3_2 = { 1138 .name = "slv_qhs_usb3_2", 1139 .channels = 1, 1140 .buswidth = 4 1141 }; 1142 1143 static struct qcom_icc_node slv_qhs_venus_cfg = { 1144 .name = "slv_qhs_venus_cfg", 1145 .channels = 1, 1146 .buswidth = 4 1147 }; 1148 1149 static struct qcom_icc_node slv_qhs_vsense_ctrl_cfg = { 1150 .name = "slv_qhs_vsense_ctrl_cfg", 1151 .channels = 1, 1152 .buswidth = 4 1153 }; 1154 1155 static struct qcom_icc_node slv_srvc_cnoc = { 1156 .name = "slv_srvc_cnoc", 1157 .channels = 1, 1158 .buswidth = 4 1159 }; 1160 1161 static struct qcom_icc_node slv_qhs_gemnoc = { 1162 .name = "slv_qhs_gemnoc", 1163 .channels = 1, 1164 .buswidth = 4, 1165 .num_links = 1, 1166 .link_nodes = { &mas_qhm_gemnoc_cfg }, 1167 }; 1168 1169 static struct qcom_icc_node slv_qhs_llcc = { 1170 .name = "slv_qhs_llcc", 1171 .channels = 1, 1172 .buswidth = 4 1173 }; 1174 1175 static struct qcom_icc_node slv_qhs_mdsp_ms_mpu_cfg = { 1176 .name = "slv_qhs_mdsp_ms_mpu_cfg", 1177 .channels = 1, 1178 .buswidth = 4 1179 }; 1180 1181 static struct qcom_icc_node slv_qns_ecc = { 1182 .name = "slv_qns_ecc", 1183 .channels = 1, 1184 .buswidth = 32 1185 }; 1186 1187 static struct qcom_icc_node slv_qns_gem_noc_snoc = { 1188 .name = "slv_qns_gem_noc_snoc", 1189 .channels = 1, 1190 .buswidth = 8, 1191 .num_links = 1, 1192 .link_nodes = { &mas_qnm_gemnoc }, 1193 }; 1194 1195 static struct qcom_icc_node slv_qns_llcc = { 1196 .name = "slv_qns_llcc", 1197 .channels = 8, 1198 .buswidth = 16, 1199 .num_links = 1, 1200 .link_nodes = { &mas_llcc_mc }, 1201 }; 1202 1203 static struct qcom_icc_node slv_srvc_gemnoc = { 1204 .name = "slv_srvc_gemnoc", 1205 .channels = 1, 1206 .buswidth = 4 1207 }; 1208 1209 static struct qcom_icc_node slv_srvc_gemnoc1 = { 1210 .name = "slv_srvc_gemnoc1", 1211 .channels = 1, 1212 .buswidth = 4 1213 }; 1214 1215 static struct qcom_icc_node slv_ebi = { 1216 .name = "slv_ebi", 1217 .channels = 8, 1218 .buswidth = 4 1219 }; 1220 1221 static struct qcom_icc_node slv_qns2_mem_noc = { 1222 .name = "slv_qns2_mem_noc", 1223 .channels = 1, 1224 .buswidth = 32, 1225 .num_links = 1, 1226 .link_nodes = { &mas_qnm_mnoc_sf }, 1227 }; 1228 1229 static struct qcom_icc_node slv_qns_mem_noc_hf = { 1230 .name = "slv_qns_mem_noc_hf", 1231 .channels = 2, 1232 .buswidth = 32, 1233 .num_links = 1, 1234 .link_nodes = { &mas_qnm_mnoc_hf }, 1235 }; 1236 1237 static struct qcom_icc_node slv_srvc_mnoc = { 1238 .name = "slv_srvc_mnoc", 1239 .channels = 1, 1240 .buswidth = 4 1241 }; 1242 1243 static struct qcom_icc_node slv_qhs_apss = { 1244 .name = "slv_qhs_apss", 1245 .channels = 1, 1246 .buswidth = 8 1247 }; 1248 1249 static struct qcom_icc_node slv_qns_cnoc = { 1250 .name = "slv_qns_cnoc", 1251 .channels = 1, 1252 .buswidth = 8, 1253 .num_links = 1, 1254 .link_nodes = { &mas_qnm_snoc }, 1255 }; 1256 1257 static struct qcom_icc_node slv_qns_gemnoc_gc = { 1258 .name = "slv_qns_gemnoc_gc", 1259 .channels = 1, 1260 .buswidth = 8, 1261 .num_links = 1, 1262 .link_nodes = { &mas_qnm_snoc_gc }, 1263 }; 1264 1265 static struct qcom_icc_node slv_qns_gemnoc_sf = { 1266 .name = "slv_qns_gemnoc_sf", 1267 .channels = 1, 1268 .buswidth = 32, 1269 .num_links = 1, 1270 .link_nodes = { &mas_qnm_snoc_sf }, 1271 }; 1272 1273 static struct qcom_icc_node slv_qxs_imem = { 1274 .name = "slv_qxs_imem", 1275 .channels = 1, 1276 .buswidth = 8 1277 }; 1278 1279 static struct qcom_icc_node slv_qxs_pimem = { 1280 .name = "slv_qxs_pimem", 1281 .channels = 1, 1282 .buswidth = 8 1283 }; 1284 1285 static struct qcom_icc_node slv_srvc_snoc = { 1286 .name = "slv_srvc_snoc", 1287 .channels = 1, 1288 .buswidth = 4 1289 }; 1290 1291 static struct qcom_icc_node slv_xs_pcie_0 = { 1292 .name = "slv_xs_pcie_0", 1293 .channels = 1, 1294 .buswidth = 8 1295 }; 1296 1297 static struct qcom_icc_node slv_xs_pcie_1 = { 1298 .name = "slv_xs_pcie_1", 1299 .channels = 1, 1300 .buswidth = 8 1301 }; 1302 1303 static struct qcom_icc_node slv_xs_pcie_2 = { 1304 .name = "slv_xs_pcie_2", 1305 .channels = 1, 1306 .buswidth = 8 1307 }; 1308 1309 static struct qcom_icc_node slv_xs_pcie_3 = { 1310 .name = "slv_xs_pcie_3", 1311 .channels = 1, 1312 .buswidth = 8 1313 }; 1314 1315 static struct qcom_icc_node slv_xs_qdss_stm = { 1316 .name = "slv_xs_qdss_stm", 1317 .channels = 1, 1318 .buswidth = 4 1319 }; 1320 1321 static struct qcom_icc_node slv_xs_sys_tcu_cfg = { 1322 .name = "slv_xs_sys_tcu_cfg", 1323 .channels = 1, 1324 .buswidth = 8 1325 }; 1326 1327 static struct qcom_icc_node slv_qup_core_0 = { 1328 .name = "slv_qup_core_0", 1329 .channels = 1, 1330 .buswidth = 4 1331 }; 1332 1333 static struct qcom_icc_node slv_qup_core_1 = { 1334 .name = "slv_qup_core_1", 1335 .channels = 1, 1336 .buswidth = 4 1337 }; 1338 1339 static struct qcom_icc_node slv_qup_core_2 = { 1340 .name = "slv_qup_core_2", 1341 .channels = 1, 1342 .buswidth = 4 1343 }; 1344 1345 static struct qcom_icc_bcm bcm_acv = { 1346 .name = "ACV", 1347 .enable_mask = BIT(3), 1348 .num_nodes = 1, 1349 .nodes = { &slv_ebi } 1350 }; 1351 1352 static struct qcom_icc_bcm bcm_mc0 = { 1353 .name = "MC0", 1354 .keepalive = true, 1355 .num_nodes = 1, 1356 .nodes = { &slv_ebi } 1357 }; 1358 1359 static struct qcom_icc_bcm bcm_sh0 = { 1360 .name = "SH0", 1361 .keepalive = true, 1362 .num_nodes = 1, 1363 .nodes = { &slv_qns_llcc } 1364 }; 1365 1366 static struct qcom_icc_bcm bcm_mm0 = { 1367 .name = "MM0", 1368 .num_nodes = 1, 1369 .nodes = { &slv_qns_mem_noc_hf } 1370 }; 1371 1372 static struct qcom_icc_bcm bcm_co0 = { 1373 .name = "CO0", 1374 .keepalive = true, 1375 .num_nodes = 1, 1376 .nodes = { &slv_qns_cdsp_mem_noc } 1377 }; 1378 1379 static struct qcom_icc_bcm bcm_ce0 = { 1380 .name = "CE0", 1381 .num_nodes = 1, 1382 .nodes = { &mas_qxm_crypto } 1383 }; 1384 1385 static struct qcom_icc_bcm bcm_cn0 = { 1386 .name = "CN0", 1387 .keepalive = true, 1388 .num_nodes = 57, 1389 .nodes = { &mas_qnm_snoc, 1390 &slv_qhs_a1_noc_cfg, 1391 &slv_qhs_a2_noc_cfg, 1392 &slv_qhs_ahb2phy_refgen_center, 1393 &slv_qhs_ahb2phy_refgen_east, 1394 &slv_qhs_ahb2phy_refgen_west, 1395 &slv_qhs_ahb2phy_south, 1396 &slv_qhs_aop, 1397 &slv_qhs_aoss, 1398 &slv_qhs_camera_cfg, 1399 &slv_qhs_clk_ctl, 1400 &slv_qhs_compute_dsp, 1401 &slv_qhs_cpr_cx, 1402 &slv_qhs_cpr_mmcx, 1403 &slv_qhs_cpr_mx, 1404 &slv_qhs_crypto0_cfg, 1405 &slv_qhs_ddrss_cfg, 1406 &slv_qhs_display_cfg, 1407 &slv_qhs_emac_cfg, 1408 &slv_qhs_glm, 1409 &slv_qhs_gpuss_cfg, 1410 &slv_qhs_imem_cfg, 1411 &slv_qhs_ipa, 1412 &slv_qhs_mnoc_cfg, 1413 &slv_qhs_npu_cfg, 1414 &slv_qhs_pcie0_cfg, 1415 &slv_qhs_pcie1_cfg, 1416 &slv_qhs_pcie2_cfg, 1417 &slv_qhs_pcie3_cfg, 1418 &slv_qhs_pdm, 1419 &slv_qhs_pimem_cfg, 1420 &slv_qhs_prng, 1421 &slv_qhs_qdss_cfg, 1422 &slv_qhs_qspi_0, 1423 &slv_qhs_qspi_1, 1424 &slv_qhs_qupv3_east0, 1425 &slv_qhs_qupv3_east1, 1426 &slv_qhs_qupv3_west, 1427 &slv_qhs_sdc2, 1428 &slv_qhs_sdc4, 1429 &slv_qhs_security, 1430 &slv_qhs_snoc_cfg, 1431 &slv_qhs_spss_cfg, 1432 &slv_qhs_tcsr, 1433 &slv_qhs_tlmm_east, 1434 &slv_qhs_tlmm_south, 1435 &slv_qhs_tlmm_west, 1436 &slv_qhs_tsif, 1437 &slv_qhs_ufs_card_cfg, 1438 &slv_qhs_ufs_mem0_cfg, 1439 &slv_qhs_ufs_mem1_cfg, 1440 &slv_qhs_usb3_0, 1441 &slv_qhs_usb3_1, 1442 &slv_qhs_usb3_2, 1443 &slv_qhs_venus_cfg, 1444 &slv_qhs_vsense_ctrl_cfg, 1445 &slv_srvc_cnoc } 1446 }; 1447 1448 static struct qcom_icc_bcm bcm_mm1 = { 1449 .name = "MM1", 1450 .num_nodes = 7, 1451 .nodes = { &mas_qxm_camnoc_hf0_uncomp, 1452 &mas_qxm_camnoc_hf1_uncomp, 1453 &mas_qxm_camnoc_sf_uncomp, 1454 &mas_qxm_camnoc_hf0, 1455 &mas_qxm_camnoc_hf1, 1456 &mas_qxm_mdp0, 1457 &mas_qxm_mdp1 } 1458 }; 1459 1460 static struct qcom_icc_bcm bcm_qup0 = { 1461 .name = "QUP0", 1462 .num_nodes = 3, 1463 .nodes = { &mas_qup_core_0, 1464 &mas_qup_core_1, 1465 &mas_qup_core_2 } 1466 }; 1467 1468 static struct qcom_icc_bcm bcm_sh2 = { 1469 .name = "SH2", 1470 .num_nodes = 1, 1471 .nodes = { &slv_qns_gem_noc_snoc } 1472 }; 1473 1474 static struct qcom_icc_bcm bcm_mm2 = { 1475 .name = "MM2", 1476 .num_nodes = 6, 1477 .nodes = { &mas_qxm_camnoc_sf, 1478 &mas_qxm_rot, 1479 &mas_qxm_venus0, 1480 &mas_qxm_venus1, 1481 &mas_qxm_venus_arm9, 1482 &slv_qns2_mem_noc } 1483 }; 1484 1485 static struct qcom_icc_bcm bcm_sh3 = { 1486 .name = "SH3", 1487 .keepalive = true, 1488 .num_nodes = 1, 1489 .nodes = { &mas_acm_apps } 1490 }; 1491 1492 static struct qcom_icc_bcm bcm_sn0 = { 1493 .name = "SN0", 1494 .num_nodes = 1, 1495 .nodes = { &slv_qns_gemnoc_sf } 1496 }; 1497 1498 static struct qcom_icc_bcm bcm_sn1 = { 1499 .name = "SN1", 1500 .num_nodes = 1, 1501 .nodes = { &slv_qxs_imem } 1502 }; 1503 1504 static struct qcom_icc_bcm bcm_sn2 = { 1505 .name = "SN2", 1506 .keepalive = true, 1507 .num_nodes = 1, 1508 .nodes = { &slv_qns_gemnoc_gc } 1509 }; 1510 1511 static struct qcom_icc_bcm bcm_co2 = { 1512 .name = "CO2", 1513 .num_nodes = 1, 1514 .nodes = { &mas_qnm_npu } 1515 }; 1516 1517 static struct qcom_icc_bcm bcm_sn3 = { 1518 .name = "SN3", 1519 .keepalive = true, 1520 .num_nodes = 2, 1521 .nodes = { &slv_srvc_aggre1_noc, 1522 &slv_qns_cnoc } 1523 }; 1524 1525 static struct qcom_icc_bcm bcm_sn4 = { 1526 .name = "SN4", 1527 .num_nodes = 1, 1528 .nodes = { &slv_qxs_pimem } 1529 }; 1530 1531 static struct qcom_icc_bcm bcm_sn8 = { 1532 .name = "SN8", 1533 .num_nodes = 4, 1534 .nodes = { &slv_xs_pcie_0, 1535 &slv_xs_pcie_1, 1536 &slv_xs_pcie_2, 1537 &slv_xs_pcie_3 } 1538 }; 1539 1540 static struct qcom_icc_bcm bcm_sn9 = { 1541 .name = "SN9", 1542 .num_nodes = 1, 1543 .nodes = { &mas_qnm_aggre1_noc } 1544 }; 1545 1546 static struct qcom_icc_bcm bcm_sn11 = { 1547 .name = "SN11", 1548 .num_nodes = 1, 1549 .nodes = { &mas_qnm_aggre2_noc } 1550 }; 1551 1552 static struct qcom_icc_bcm bcm_sn14 = { 1553 .name = "SN14", 1554 .num_nodes = 1, 1555 .nodes = { &slv_qns_pcie_mem_noc } 1556 }; 1557 1558 static struct qcom_icc_bcm bcm_sn15 = { 1559 .name = "SN15", 1560 .keepalive = true, 1561 .num_nodes = 1, 1562 .nodes = { &mas_qnm_gemnoc } 1563 }; 1564 1565 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 1566 &bcm_sn3, 1567 &bcm_ce0, 1568 }; 1569 1570 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 1571 &bcm_sn14, 1572 &bcm_ce0, 1573 }; 1574 1575 static struct qcom_icc_bcm * const camnoc_virt_bcms[] = { 1576 &bcm_mm1, 1577 }; 1578 1579 static struct qcom_icc_bcm * const compute_noc_bcms[] = { 1580 &bcm_co0, 1581 &bcm_co2, 1582 }; 1583 1584 static struct qcom_icc_bcm * const config_noc_bcms[] = { 1585 &bcm_cn0, 1586 }; 1587 1588 static struct qcom_icc_bcm * const gem_noc_bcms[] = { 1589 &bcm_sh0, 1590 &bcm_sh2, 1591 &bcm_sh3, 1592 }; 1593 1594 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 1595 &bcm_mc0, 1596 &bcm_acv, 1597 }; 1598 1599 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 1600 &bcm_mm0, 1601 &bcm_mm1, 1602 &bcm_mm2, 1603 }; 1604 1605 static struct qcom_icc_bcm * const system_noc_bcms[] = { 1606 &bcm_sn0, 1607 &bcm_sn1, 1608 &bcm_sn2, 1609 &bcm_sn3, 1610 &bcm_sn4, 1611 &bcm_sn8, 1612 &bcm_sn9, 1613 &bcm_sn11, 1614 &bcm_sn15, 1615 }; 1616 1617 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1618 [MASTER_A1NOC_CFG] = &mas_qhm_a1noc_cfg, 1619 [MASTER_UFS_CARD] = &mas_xm_ufs_card, 1620 [MASTER_UFS_GEN4] = &mas_xm_ufs_g4, 1621 [MASTER_UFS_MEM] = &mas_xm_ufs_mem, 1622 [MASTER_USB3] = &mas_xm_usb3_0, 1623 [MASTER_USB3_1] = &mas_xm_usb3_1, 1624 [MASTER_USB3_2] = &mas_xm_usb3_2, 1625 [A1NOC_SNOC_SLV] = &slv_qns_a1noc_snoc, 1626 [SLAVE_SERVICE_A1NOC] = &slv_srvc_aggre1_noc, 1627 }; 1628 1629 static struct qcom_icc_node * const aggre2_noc_nodes[] = { 1630 [MASTER_A2NOC_CFG] = &mas_qhm_a2noc_cfg, 1631 [MASTER_QDSS_BAM] = &mas_qhm_qdss_bam, 1632 [MASTER_QSPI_0] = &mas_qhm_qspi, 1633 [MASTER_QSPI_1] = &mas_qhm_qspi1, 1634 [MASTER_QUP_0] = &mas_qhm_qup0, 1635 [MASTER_QUP_1] = &mas_qhm_qup1, 1636 [MASTER_QUP_2] = &mas_qhm_qup2, 1637 [MASTER_SENSORS_AHB] = &mas_qhm_sensorss_ahb, 1638 [MASTER_CRYPTO_CORE_0] = &mas_qxm_crypto, 1639 [MASTER_IPA] = &mas_qxm_ipa, 1640 [MASTER_EMAC] = &mas_xm_emac, 1641 [MASTER_PCIE] = &mas_xm_pcie3_0, 1642 [MASTER_PCIE_1] = &mas_xm_pcie3_1, 1643 [MASTER_PCIE_2] = &mas_xm_pcie3_2, 1644 [MASTER_PCIE_3] = &mas_xm_pcie3_3, 1645 [MASTER_QDSS_ETR] = &mas_xm_qdss_etr, 1646 [MASTER_SDCC_2] = &mas_xm_sdc2, 1647 [MASTER_SDCC_4] = &mas_xm_sdc4, 1648 [A2NOC_SNOC_SLV] = &slv_qns_a2noc_snoc, 1649 [SLAVE_ANOC_PCIE_GEM_NOC] = &slv_qns_pcie_mem_noc, 1650 [SLAVE_SERVICE_A2NOC] = &slv_srvc_aggre2_noc, 1651 }; 1652 1653 static struct qcom_icc_node * const camnoc_virt_nodes[] = { 1654 [MASTER_CAMNOC_HF0_UNCOMP] = &mas_qxm_camnoc_hf0_uncomp, 1655 [MASTER_CAMNOC_HF1_UNCOMP] = &mas_qxm_camnoc_hf1_uncomp, 1656 [MASTER_CAMNOC_SF_UNCOMP] = &mas_qxm_camnoc_sf_uncomp, 1657 [SLAVE_CAMNOC_UNCOMP] = &slv_qns_camnoc_uncomp, 1658 }; 1659 1660 static struct qcom_icc_node * const compute_noc_nodes[] = { 1661 [MASTER_NPU] = &mas_qnm_npu, 1662 [SLAVE_CDSP_MEM_NOC] = &slv_qns_cdsp_mem_noc, 1663 }; 1664 1665 static struct qcom_icc_node * const config_noc_nodes[] = { 1666 [SNOC_CNOC_MAS] = &mas_qnm_snoc, 1667 [SLAVE_A1NOC_CFG] = &slv_qhs_a1_noc_cfg, 1668 [SLAVE_A2NOC_CFG] = &slv_qhs_a2_noc_cfg, 1669 [SLAVE_AHB2PHY_CENTER] = &slv_qhs_ahb2phy_refgen_center, 1670 [SLAVE_AHB2PHY_EAST] = &slv_qhs_ahb2phy_refgen_east, 1671 [SLAVE_AHB2PHY_WEST] = &slv_qhs_ahb2phy_refgen_west, 1672 [SLAVE_AHB2PHY_SOUTH] = &slv_qhs_ahb2phy_south, 1673 [SLAVE_AOP] = &slv_qhs_aop, 1674 [SLAVE_AOSS] = &slv_qhs_aoss, 1675 [SLAVE_CAMERA_CFG] = &slv_qhs_camera_cfg, 1676 [SLAVE_CLK_CTL] = &slv_qhs_clk_ctl, 1677 [SLAVE_CDSP_CFG] = &slv_qhs_compute_dsp, 1678 [SLAVE_RBCPR_CX_CFG] = &slv_qhs_cpr_cx, 1679 [SLAVE_RBCPR_MMCX_CFG] = &slv_qhs_cpr_mmcx, 1680 [SLAVE_RBCPR_MX_CFG] = &slv_qhs_cpr_mx, 1681 [SLAVE_CRYPTO_0_CFG] = &slv_qhs_crypto0_cfg, 1682 [SLAVE_CNOC_DDRSS] = &slv_qhs_ddrss_cfg, 1683 [SLAVE_DISPLAY_CFG] = &slv_qhs_display_cfg, 1684 [SLAVE_EMAC_CFG] = &slv_qhs_emac_cfg, 1685 [SLAVE_GLM] = &slv_qhs_glm, 1686 [SLAVE_GRAPHICS_3D_CFG] = &slv_qhs_gpuss_cfg, 1687 [SLAVE_IMEM_CFG] = &slv_qhs_imem_cfg, 1688 [SLAVE_IPA_CFG] = &slv_qhs_ipa, 1689 [SLAVE_CNOC_MNOC_CFG] = &slv_qhs_mnoc_cfg, 1690 [SLAVE_NPU_CFG] = &slv_qhs_npu_cfg, 1691 [SLAVE_PCIE_0_CFG] = &slv_qhs_pcie0_cfg, 1692 [SLAVE_PCIE_1_CFG] = &slv_qhs_pcie1_cfg, 1693 [SLAVE_PCIE_2_CFG] = &slv_qhs_pcie2_cfg, 1694 [SLAVE_PCIE_3_CFG] = &slv_qhs_pcie3_cfg, 1695 [SLAVE_PDM] = &slv_qhs_pdm, 1696 [SLAVE_PIMEM_CFG] = &slv_qhs_pimem_cfg, 1697 [SLAVE_PRNG] = &slv_qhs_prng, 1698 [SLAVE_QDSS_CFG] = &slv_qhs_qdss_cfg, 1699 [SLAVE_QSPI_0] = &slv_qhs_qspi_0, 1700 [SLAVE_QSPI_1] = &slv_qhs_qspi_1, 1701 [SLAVE_QUP_1] = &slv_qhs_qupv3_east0, 1702 [SLAVE_QUP_2] = &slv_qhs_qupv3_east1, 1703 [SLAVE_QUP_0] = &slv_qhs_qupv3_west, 1704 [SLAVE_SDCC_2] = &slv_qhs_sdc2, 1705 [SLAVE_SDCC_4] = &slv_qhs_sdc4, 1706 [SLAVE_SECURITY] = &slv_qhs_security, 1707 [SLAVE_SNOC_CFG] = &slv_qhs_snoc_cfg, 1708 [SLAVE_SPSS_CFG] = &slv_qhs_spss_cfg, 1709 [SLAVE_TCSR] = &slv_qhs_tcsr, 1710 [SLAVE_TLMM_EAST] = &slv_qhs_tlmm_east, 1711 [SLAVE_TLMM_SOUTH] = &slv_qhs_tlmm_south, 1712 [SLAVE_TLMM_WEST] = &slv_qhs_tlmm_west, 1713 [SLAVE_TSIF] = &slv_qhs_tsif, 1714 [SLAVE_UFS_CARD_CFG] = &slv_qhs_ufs_card_cfg, 1715 [SLAVE_UFS_MEM_0_CFG] = &slv_qhs_ufs_mem0_cfg, 1716 [SLAVE_UFS_MEM_1_CFG] = &slv_qhs_ufs_mem1_cfg, 1717 [SLAVE_USB3] = &slv_qhs_usb3_0, 1718 [SLAVE_USB3_1] = &slv_qhs_usb3_1, 1719 [SLAVE_USB3_2] = &slv_qhs_usb3_2, 1720 [SLAVE_VENUS_CFG] = &slv_qhs_venus_cfg, 1721 [SLAVE_VSENSE_CTRL_CFG] = &slv_qhs_vsense_ctrl_cfg, 1722 [SLAVE_SERVICE_CNOC] = &slv_srvc_cnoc, 1723 }; 1724 1725 static struct qcom_icc_node * const dc_noc_nodes[] = { 1726 [MASTER_CNOC_DC_NOC] = &mas_qhm_cnoc_dc_noc, 1727 [SLAVE_GEM_NOC_CFG] = &slv_qhs_gemnoc, 1728 [SLAVE_LLCC_CFG] = &slv_qhs_llcc, 1729 }; 1730 1731 static struct qcom_icc_node * const gem_noc_nodes[] = { 1732 [MASTER_AMPSS_M0] = &mas_acm_apps, 1733 [MASTER_GPU_TCU] = &mas_acm_gpu_tcu, 1734 [MASTER_SYS_TCU] = &mas_acm_sys_tcu, 1735 [MASTER_GEM_NOC_CFG] = &mas_qhm_gemnoc_cfg, 1736 [MASTER_COMPUTE_NOC] = &mas_qnm_cmpnoc, 1737 [MASTER_GRAPHICS_3D] = &mas_qnm_gpu, 1738 [MASTER_MNOC_HF_MEM_NOC] = &mas_qnm_mnoc_hf, 1739 [MASTER_MNOC_SF_MEM_NOC] = &mas_qnm_mnoc_sf, 1740 [MASTER_GEM_NOC_PCIE_SNOC] = &mas_qnm_pcie, 1741 [MASTER_SNOC_GC_MEM_NOC] = &mas_qnm_snoc_gc, 1742 [MASTER_SNOC_SF_MEM_NOC] = &mas_qnm_snoc_sf, 1743 [MASTER_ECC] = &mas_qxm_ecc, 1744 [SLAVE_MSS_PROC_MS_MPU_CFG] = &slv_qhs_mdsp_ms_mpu_cfg, 1745 [SLAVE_ECC] = &slv_qns_ecc, 1746 [SLAVE_GEM_NOC_SNOC] = &slv_qns_gem_noc_snoc, 1747 [SLAVE_LLCC] = &slv_qns_llcc, 1748 [SLAVE_SERVICE_GEM_NOC] = &slv_srvc_gemnoc, 1749 [SLAVE_SERVICE_GEM_NOC_1] = &slv_srvc_gemnoc1, 1750 }; 1751 1752 static struct qcom_icc_node * const mc_virt_nodes[] = { 1753 [MASTER_LLCC] = &mas_llcc_mc, 1754 [SLAVE_EBI_CH0] = &slv_ebi, 1755 }; 1756 1757 static struct qcom_icc_node * const mmss_noc_nodes[] = { 1758 [MASTER_CNOC_MNOC_CFG] = &mas_qhm_mnoc_cfg, 1759 [MASTER_CAMNOC_HF0] = &mas_qxm_camnoc_hf0, 1760 [MASTER_CAMNOC_HF1] = &mas_qxm_camnoc_hf1, 1761 [MASTER_CAMNOC_SF] = &mas_qxm_camnoc_sf, 1762 [MASTER_MDP_PORT0] = &mas_qxm_mdp0, 1763 [MASTER_MDP_PORT1] = &mas_qxm_mdp1, 1764 [MASTER_ROTATOR] = &mas_qxm_rot, 1765 [MASTER_VIDEO_P0] = &mas_qxm_venus0, 1766 [MASTER_VIDEO_P1] = &mas_qxm_venus1, 1767 [MASTER_VIDEO_PROC] = &mas_qxm_venus_arm9, 1768 [SLAVE_MNOC_SF_MEM_NOC] = &slv_qns2_mem_noc, 1769 [SLAVE_MNOC_HF_MEM_NOC] = &slv_qns_mem_noc_hf, 1770 [SLAVE_SERVICE_MNOC] = &slv_srvc_mnoc, 1771 }; 1772 1773 static struct qcom_icc_node * const system_noc_nodes[] = { 1774 [MASTER_SNOC_CFG] = &mas_qhm_snoc_cfg, 1775 [A1NOC_SNOC_MAS] = &mas_qnm_aggre1_noc, 1776 [A2NOC_SNOC_MAS] = &mas_qnm_aggre2_noc, 1777 [MASTER_GEM_NOC_SNOC] = &mas_qnm_gemnoc, 1778 [MASTER_PIMEM] = &mas_qxm_pimem, 1779 [MASTER_GIC] = &mas_xm_gic, 1780 [SLAVE_APPSS] = &slv_qhs_apss, 1781 [SNOC_CNOC_SLV] = &slv_qns_cnoc, 1782 [SLAVE_SNOC_GEM_NOC_GC] = &slv_qns_gemnoc_gc, 1783 [SLAVE_SNOC_GEM_NOC_SF] = &slv_qns_gemnoc_sf, 1784 [SLAVE_OCIMEM] = &slv_qxs_imem, 1785 [SLAVE_PIMEM] = &slv_qxs_pimem, 1786 [SLAVE_SERVICE_SNOC] = &slv_srvc_snoc, 1787 [SLAVE_QDSS_STM] = &slv_xs_qdss_stm, 1788 [SLAVE_TCU] = &slv_xs_sys_tcu_cfg, 1789 }; 1790 1791 static const struct qcom_icc_desc sc8180x_aggre1_noc = { 1792 .nodes = aggre1_noc_nodes, 1793 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 1794 .bcms = aggre1_noc_bcms, 1795 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 1796 }; 1797 1798 static const struct qcom_icc_desc sc8180x_aggre2_noc = { 1799 .nodes = aggre2_noc_nodes, 1800 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 1801 .bcms = aggre2_noc_bcms, 1802 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 1803 }; 1804 1805 static const struct qcom_icc_desc sc8180x_camnoc_virt = { 1806 .nodes = camnoc_virt_nodes, 1807 .num_nodes = ARRAY_SIZE(camnoc_virt_nodes), 1808 .bcms = camnoc_virt_bcms, 1809 .num_bcms = ARRAY_SIZE(camnoc_virt_bcms), 1810 }; 1811 1812 static const struct qcom_icc_desc sc8180x_compute_noc = { 1813 .nodes = compute_noc_nodes, 1814 .num_nodes = ARRAY_SIZE(compute_noc_nodes), 1815 .bcms = compute_noc_bcms, 1816 .num_bcms = ARRAY_SIZE(compute_noc_bcms), 1817 }; 1818 1819 static const struct qcom_icc_desc sc8180x_config_noc = { 1820 .nodes = config_noc_nodes, 1821 .num_nodes = ARRAY_SIZE(config_noc_nodes), 1822 .bcms = config_noc_bcms, 1823 .num_bcms = ARRAY_SIZE(config_noc_bcms), 1824 }; 1825 1826 static const struct qcom_icc_desc sc8180x_dc_noc = { 1827 .nodes = dc_noc_nodes, 1828 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 1829 }; 1830 1831 static const struct qcom_icc_desc sc8180x_gem_noc = { 1832 .nodes = gem_noc_nodes, 1833 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 1834 .bcms = gem_noc_bcms, 1835 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 1836 }; 1837 1838 static const struct qcom_icc_desc sc8180x_mc_virt = { 1839 .nodes = mc_virt_nodes, 1840 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 1841 .bcms = mc_virt_bcms, 1842 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 1843 }; 1844 1845 static const struct qcom_icc_desc sc8180x_mmss_noc = { 1846 .nodes = mmss_noc_nodes, 1847 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 1848 .bcms = mmss_noc_bcms, 1849 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 1850 }; 1851 1852 static const struct qcom_icc_desc sc8180x_system_noc = { 1853 .nodes = system_noc_nodes, 1854 .num_nodes = ARRAY_SIZE(system_noc_nodes), 1855 .bcms = system_noc_bcms, 1856 .num_bcms = ARRAY_SIZE(system_noc_bcms), 1857 }; 1858 1859 static struct qcom_icc_bcm * const qup_virt_bcms[] = { 1860 &bcm_qup0, 1861 }; 1862 1863 static struct qcom_icc_node * const qup_virt_nodes[] = { 1864 [MASTER_QUP_CORE_0] = &mas_qup_core_0, 1865 [MASTER_QUP_CORE_1] = &mas_qup_core_1, 1866 [MASTER_QUP_CORE_2] = &mas_qup_core_2, 1867 [SLAVE_QUP_CORE_0] = &slv_qup_core_0, 1868 [SLAVE_QUP_CORE_1] = &slv_qup_core_1, 1869 [SLAVE_QUP_CORE_2] = &slv_qup_core_2, 1870 }; 1871 1872 static const struct qcom_icc_desc sc8180x_qup_virt = { 1873 .nodes = qup_virt_nodes, 1874 .num_nodes = ARRAY_SIZE(qup_virt_nodes), 1875 .bcms = qup_virt_bcms, 1876 .num_bcms = ARRAY_SIZE(qup_virt_bcms), 1877 }; 1878 1879 static const struct of_device_id qnoc_of_match[] = { 1880 { .compatible = "qcom,sc8180x-aggre1-noc", .data = &sc8180x_aggre1_noc }, 1881 { .compatible = "qcom,sc8180x-aggre2-noc", .data = &sc8180x_aggre2_noc }, 1882 { .compatible = "qcom,sc8180x-camnoc-virt", .data = &sc8180x_camnoc_virt }, 1883 { .compatible = "qcom,sc8180x-compute-noc", .data = &sc8180x_compute_noc, }, 1884 { .compatible = "qcom,sc8180x-config-noc", .data = &sc8180x_config_noc }, 1885 { .compatible = "qcom,sc8180x-dc-noc", .data = &sc8180x_dc_noc }, 1886 { .compatible = "qcom,sc8180x-gem-noc", .data = &sc8180x_gem_noc }, 1887 { .compatible = "qcom,sc8180x-mc-virt", .data = &sc8180x_mc_virt }, 1888 { .compatible = "qcom,sc8180x-mmss-noc", .data = &sc8180x_mmss_noc }, 1889 { .compatible = "qcom,sc8180x-qup-virt", .data = &sc8180x_qup_virt }, 1890 { .compatible = "qcom,sc8180x-system-noc", .data = &sc8180x_system_noc }, 1891 { } 1892 }; 1893 MODULE_DEVICE_TABLE(of, qnoc_of_match); 1894 1895 static struct platform_driver qnoc_driver = { 1896 .probe = qcom_icc_rpmh_probe, 1897 .remove = qcom_icc_rpmh_remove, 1898 .driver = { 1899 .name = "qnoc-sc8180x", 1900 .of_match_table = qnoc_of_match, 1901 .sync_state = icc_sync_state, 1902 }, 1903 }; 1904 module_platform_driver(qnoc_driver); 1905 1906 MODULE_DESCRIPTION("Qualcomm sc8180x NoC driver"); 1907 MODULE_LICENSE("GPL v2"); 1908