1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021, Linaro Ltd. 5 */ 6 7 #include <linux/device.h> 8 #include <linux/interconnect-provider.h> 9 #include <linux/module.h> 10 #include <linux/of_device.h> 11 12 #include <dt-bindings/interconnect/qcom,sc8180x.h> 13 14 #include "bcm-voter.h" 15 #include "icc-rpmh.h" 16 #include "sc8180x.h" 17 18 DEFINE_QNODE(mas_qhm_a1noc_cfg, SC8180X_MASTER_A1NOC_CFG, 1, 4, SC8180X_SLAVE_SERVICE_A1NOC); 19 DEFINE_QNODE(mas_xm_ufs_card, SC8180X_MASTER_UFS_CARD, 1, 8, SC8180X_A1NOC_SNOC_SLV); 20 DEFINE_QNODE(mas_xm_ufs_g4, SC8180X_MASTER_UFS_GEN4, 1, 8, SC8180X_A1NOC_SNOC_SLV); 21 DEFINE_QNODE(mas_xm_ufs_mem, SC8180X_MASTER_UFS_MEM, 1, 8, SC8180X_A1NOC_SNOC_SLV); 22 DEFINE_QNODE(mas_xm_usb3_0, SC8180X_MASTER_USB3, 1, 8, SC8180X_A1NOC_SNOC_SLV); 23 DEFINE_QNODE(mas_xm_usb3_1, SC8180X_MASTER_USB3_1, 1, 8, SC8180X_A1NOC_SNOC_SLV); 24 DEFINE_QNODE(mas_xm_usb3_2, SC8180X_MASTER_USB3_2, 1, 16, SC8180X_A1NOC_SNOC_SLV); 25 DEFINE_QNODE(mas_qhm_a2noc_cfg, SC8180X_MASTER_A2NOC_CFG, 1, 4, SC8180X_SLAVE_SERVICE_A2NOC); 26 DEFINE_QNODE(mas_qhm_qdss_bam, SC8180X_MASTER_QDSS_BAM, 1, 4, SC8180X_A2NOC_SNOC_SLV); 27 DEFINE_QNODE(mas_qhm_qspi, SC8180X_MASTER_QSPI_0, 1, 4, SC8180X_A2NOC_SNOC_SLV); 28 DEFINE_QNODE(mas_qhm_qspi1, SC8180X_MASTER_QSPI_1, 1, 4, SC8180X_A2NOC_SNOC_SLV); 29 DEFINE_QNODE(mas_qhm_qup0, SC8180X_MASTER_QUP_0, 1, 4, SC8180X_A2NOC_SNOC_SLV); 30 DEFINE_QNODE(mas_qhm_qup1, SC8180X_MASTER_QUP_1, 1, 4, SC8180X_A2NOC_SNOC_SLV); 31 DEFINE_QNODE(mas_qhm_qup2, SC8180X_MASTER_QUP_2, 1, 4, SC8180X_A2NOC_SNOC_SLV); 32 DEFINE_QNODE(mas_qhm_sensorss_ahb, SC8180X_MASTER_SENSORS_AHB, 1, 4, SC8180X_A2NOC_SNOC_SLV); 33 DEFINE_QNODE(mas_qxm_crypto, SC8180X_MASTER_CRYPTO_CORE_0, 1, 8, SC8180X_A2NOC_SNOC_SLV); 34 DEFINE_QNODE(mas_qxm_ipa, SC8180X_MASTER_IPA, 1, 8, SC8180X_A2NOC_SNOC_SLV); 35 DEFINE_QNODE(mas_xm_emac, SC8180X_MASTER_EMAC, 1, 8, SC8180X_A2NOC_SNOC_SLV); 36 DEFINE_QNODE(mas_xm_pcie3_0, SC8180X_MASTER_PCIE, 1, 8, SC8180X_SLAVE_ANOC_PCIE_GEM_NOC); 37 DEFINE_QNODE(mas_xm_pcie3_1, SC8180X_MASTER_PCIE_1, 1, 16, SC8180X_SLAVE_ANOC_PCIE_GEM_NOC); 38 DEFINE_QNODE(mas_xm_pcie3_2, SC8180X_MASTER_PCIE_2, 1, 8, SC8180X_SLAVE_ANOC_PCIE_GEM_NOC); 39 DEFINE_QNODE(mas_xm_pcie3_3, SC8180X_MASTER_PCIE_3, 1, 16, SC8180X_SLAVE_ANOC_PCIE_GEM_NOC); 40 DEFINE_QNODE(mas_xm_qdss_etr, SC8180X_MASTER_QDSS_ETR, 1, 8, SC8180X_A2NOC_SNOC_SLV); 41 DEFINE_QNODE(mas_xm_sdc2, SC8180X_MASTER_SDCC_2, 1, 8, SC8180X_A2NOC_SNOC_SLV); 42 DEFINE_QNODE(mas_xm_sdc4, SC8180X_MASTER_SDCC_4, 1, 8, SC8180X_A2NOC_SNOC_SLV); 43 DEFINE_QNODE(mas_qxm_camnoc_hf0_uncomp, SC8180X_MASTER_CAMNOC_HF0_UNCOMP, 1, 32, SC8180X_SLAVE_CAMNOC_UNCOMP); 44 DEFINE_QNODE(mas_qxm_camnoc_hf1_uncomp, SC8180X_MASTER_CAMNOC_HF1_UNCOMP, 1, 32, SC8180X_SLAVE_CAMNOC_UNCOMP); 45 DEFINE_QNODE(mas_qxm_camnoc_sf_uncomp, SC8180X_MASTER_CAMNOC_SF_UNCOMP, 1, 32, SC8180X_SLAVE_CAMNOC_UNCOMP); 46 DEFINE_QNODE(mas_qnm_npu, SC8180X_MASTER_NPU, 1, 32, SC8180X_SLAVE_CDSP_MEM_NOC); 47 DEFINE_QNODE(mas_qnm_snoc, SC8180X_SNOC_CNOC_MAS, 1, 8, SC8180X_SLAVE_TLMM_SOUTH, SC8180X_SLAVE_CDSP_CFG, SC8180X_SLAVE_SPSS_CFG, SC8180X_SLAVE_CAMERA_CFG, SC8180X_SLAVE_SDCC_4, SC8180X_SLAVE_AHB2PHY_CENTER, SC8180X_SLAVE_SDCC_2, SC8180X_SLAVE_PCIE_2_CFG, SC8180X_SLAVE_CNOC_MNOC_CFG, SC8180X_SLAVE_EMAC_CFG, SC8180X_SLAVE_QSPI_0, SC8180X_SLAVE_QSPI_1, SC8180X_SLAVE_TLMM_EAST, SC8180X_SLAVE_SNOC_CFG, SC8180X_SLAVE_AHB2PHY_EAST, SC8180X_SLAVE_GLM, SC8180X_SLAVE_PDM, SC8180X_SLAVE_PCIE_1_CFG, SC8180X_SLAVE_A2NOC_CFG, SC8180X_SLAVE_QDSS_CFG, SC8180X_SLAVE_DISPLAY_CFG, SC8180X_SLAVE_TCSR, SC8180X_SLAVE_UFS_MEM_0_CFG, SC8180X_SLAVE_CNOC_DDRSS, SC8180X_SLAVE_PCIE_0_CFG, SC8180X_SLAVE_QUP_1, SC8180X_SLAVE_QUP_2, SC8180X_SLAVE_NPU_CFG, SC8180X_SLAVE_CRYPTO_0_CFG, SC8180X_SLAVE_GRAPHICS_3D_CFG, SC8180X_SLAVE_VENUS_CFG, SC8180X_SLAVE_TSIF, SC8180X_SLAVE_IPA_CFG, SC8180X_SLAVE_CLK_CTL, SC8180X_SLAVE_SECURITY, SC8180X_SLAVE_AOP, SC8180X_SLAVE_AHB2PHY_WEST, SC8180X_SLAVE_AHB2PHY_SOUTH, SC8180X_SLAVE_SERVICE_CNOC, SC8180X_SLAVE_UFS_CARD_CFG, SC8180X_SLAVE_USB3_1, SC8180X_SLAVE_USB3_2, SC8180X_SLAVE_PCIE_3_CFG, SC8180X_SLAVE_RBCPR_CX_CFG, SC8180X_SLAVE_TLMM_WEST, SC8180X_SLAVE_A1NOC_CFG, SC8180X_SLAVE_AOSS, SC8180X_SLAVE_PRNG, SC8180X_SLAVE_VSENSE_CTRL_CFG, SC8180X_SLAVE_QUP_0, SC8180X_SLAVE_USB3, SC8180X_SLAVE_RBCPR_MMCX_CFG, SC8180X_SLAVE_PIMEM_CFG, SC8180X_SLAVE_UFS_MEM_1_CFG, SC8180X_SLAVE_RBCPR_MX_CFG, SC8180X_SLAVE_IMEM_CFG); 48 DEFINE_QNODE(mas_qhm_cnoc_dc_noc, SC8180X_MASTER_CNOC_DC_NOC, 1, 4, SC8180X_SLAVE_LLCC_CFG, SC8180X_SLAVE_GEM_NOC_CFG); 49 DEFINE_QNODE(mas_acm_apps, SC8180X_MASTER_AMPSS_M0, 4, 64, SC8180X_SLAVE_ECC, SC8180X_SLAVE_LLCC, SC8180X_SLAVE_GEM_NOC_SNOC); 50 DEFINE_QNODE(mas_acm_gpu_tcu, SC8180X_MASTER_GPU_TCU, 1, 8, SC8180X_SLAVE_LLCC, SC8180X_SLAVE_GEM_NOC_SNOC); 51 DEFINE_QNODE(mas_acm_sys_tcu, SC8180X_MASTER_SYS_TCU, 1, 8, SC8180X_SLAVE_LLCC, SC8180X_SLAVE_GEM_NOC_SNOC); 52 DEFINE_QNODE(mas_qhm_gemnoc_cfg, SC8180X_MASTER_GEM_NOC_CFG, 1, 4, SC8180X_SLAVE_SERVICE_GEM_NOC_1, SC8180X_SLAVE_SERVICE_GEM_NOC, SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG); 53 DEFINE_QNODE(mas_qnm_cmpnoc, SC8180X_MASTER_COMPUTE_NOC, 2, 32, SC8180X_SLAVE_ECC, SC8180X_SLAVE_LLCC, SC8180X_SLAVE_GEM_NOC_SNOC); 54 DEFINE_QNODE(mas_qnm_gpu, SC8180X_MASTER_GRAPHICS_3D, 4, 32, SC8180X_SLAVE_LLCC, SC8180X_SLAVE_GEM_NOC_SNOC); 55 DEFINE_QNODE(mas_qnm_mnoc_hf, SC8180X_MASTER_MNOC_HF_MEM_NOC, 2, 32, SC8180X_SLAVE_LLCC); 56 DEFINE_QNODE(mas_qnm_mnoc_sf, SC8180X_MASTER_MNOC_SF_MEM_NOC, 1, 32, SC8180X_SLAVE_LLCC, SC8180X_SLAVE_GEM_NOC_SNOC); 57 DEFINE_QNODE(mas_qnm_pcie, SC8180X_MASTER_GEM_NOC_PCIE_SNOC, 1, 32, SC8180X_SLAVE_LLCC, SC8180X_SLAVE_GEM_NOC_SNOC); 58 DEFINE_QNODE(mas_qnm_snoc_gc, SC8180X_MASTER_SNOC_GC_MEM_NOC, 1, 8, SC8180X_SLAVE_LLCC); 59 DEFINE_QNODE(mas_qnm_snoc_sf, SC8180X_MASTER_SNOC_SF_MEM_NOC, 1, 32, SC8180X_SLAVE_LLCC); 60 DEFINE_QNODE(mas_qxm_ecc, SC8180X_MASTER_ECC, 2, 32, SC8180X_SLAVE_LLCC); 61 DEFINE_QNODE(mas_ipa_core_master, SC8180X_MASTER_IPA_CORE, 1, 8, SC8180X_SLAVE_IPA_CORE); 62 DEFINE_QNODE(mas_llcc_mc, SC8180X_MASTER_LLCC, 8, 4, SC8180X_SLAVE_EBI_CH0); 63 DEFINE_QNODE(mas_qhm_mnoc_cfg, SC8180X_MASTER_CNOC_MNOC_CFG, 1, 4, SC8180X_SLAVE_SERVICE_MNOC); 64 DEFINE_QNODE(mas_qxm_camnoc_hf0, SC8180X_MASTER_CAMNOC_HF0, 1, 32, SC8180X_SLAVE_MNOC_HF_MEM_NOC); 65 DEFINE_QNODE(mas_qxm_camnoc_hf1, SC8180X_MASTER_CAMNOC_HF1, 1, 32, SC8180X_SLAVE_MNOC_HF_MEM_NOC); 66 DEFINE_QNODE(mas_qxm_camnoc_sf, SC8180X_MASTER_CAMNOC_SF, 1, 32, SC8180X_SLAVE_MNOC_SF_MEM_NOC); 67 DEFINE_QNODE(mas_qxm_mdp0, SC8180X_MASTER_MDP_PORT0, 1, 32, SC8180X_SLAVE_MNOC_HF_MEM_NOC); 68 DEFINE_QNODE(mas_qxm_mdp1, SC8180X_MASTER_MDP_PORT1, 1, 32, SC8180X_SLAVE_MNOC_HF_MEM_NOC); 69 DEFINE_QNODE(mas_qxm_rot, SC8180X_MASTER_ROTATOR, 1, 32, SC8180X_SLAVE_MNOC_SF_MEM_NOC); 70 DEFINE_QNODE(mas_qxm_venus0, SC8180X_MASTER_VIDEO_P0, 1, 32, SC8180X_SLAVE_MNOC_SF_MEM_NOC); 71 DEFINE_QNODE(mas_qxm_venus1, SC8180X_MASTER_VIDEO_P1, 1, 32, SC8180X_SLAVE_MNOC_SF_MEM_NOC); 72 DEFINE_QNODE(mas_qxm_venus_arm9, SC8180X_MASTER_VIDEO_PROC, 1, 8, SC8180X_SLAVE_MNOC_SF_MEM_NOC); 73 DEFINE_QNODE(mas_qhm_snoc_cfg, SC8180X_MASTER_SNOC_CFG, 1, 4, SC8180X_SLAVE_SERVICE_SNOC); 74 DEFINE_QNODE(mas_qnm_aggre1_noc, SC8180X_A1NOC_SNOC_MAS, 1, 32, SC8180X_SLAVE_SNOC_GEM_NOC_SF, SC8180X_SLAVE_PIMEM, SC8180X_SLAVE_OCIMEM, SC8180X_SLAVE_APPSS, SC8180X_SNOC_CNOC_SLV, SC8180X_SLAVE_QDSS_STM); 75 DEFINE_QNODE(mas_qnm_aggre2_noc, SC8180X_A2NOC_SNOC_MAS, 1, 16, SC8180X_SLAVE_SNOC_GEM_NOC_SF, SC8180X_SLAVE_PIMEM, SC8180X_SLAVE_PCIE_3, SC8180X_SLAVE_OCIMEM, SC8180X_SLAVE_APPSS, SC8180X_SLAVE_PCIE_2, SC8180X_SNOC_CNOC_SLV, SC8180X_SLAVE_PCIE_0, SC8180X_SLAVE_PCIE_1, SC8180X_SLAVE_TCU, SC8180X_SLAVE_QDSS_STM); 76 DEFINE_QNODE(mas_qnm_gemnoc, SC8180X_MASTER_GEM_NOC_SNOC, 1, 8, SC8180X_SLAVE_PIMEM, SC8180X_SLAVE_OCIMEM, SC8180X_SLAVE_APPSS, SC8180X_SNOC_CNOC_SLV, SC8180X_SLAVE_TCU, SC8180X_SLAVE_QDSS_STM); 77 DEFINE_QNODE(mas_qxm_pimem, SC8180X_MASTER_PIMEM, 1, 8, SC8180X_SLAVE_SNOC_GEM_NOC_GC, SC8180X_SLAVE_OCIMEM); 78 DEFINE_QNODE(mas_xm_gic, SC8180X_MASTER_GIC, 1, 8, SC8180X_SLAVE_SNOC_GEM_NOC_GC, SC8180X_SLAVE_OCIMEM); 79 DEFINE_QNODE(slv_qns_a1noc_snoc, SC8180X_A1NOC_SNOC_SLV, 1, 32, SC8180X_A1NOC_SNOC_MAS); 80 DEFINE_QNODE(slv_srvc_aggre1_noc, SC8180X_SLAVE_SERVICE_A1NOC, 1, 4); 81 DEFINE_QNODE(slv_qns_a2noc_snoc, SC8180X_A2NOC_SNOC_SLV, 1, 16, SC8180X_A2NOC_SNOC_MAS); 82 DEFINE_QNODE(slv_qns_pcie_mem_noc, SC8180X_SLAVE_ANOC_PCIE_GEM_NOC, 1, 32, SC8180X_MASTER_GEM_NOC_PCIE_SNOC); 83 DEFINE_QNODE(slv_srvc_aggre2_noc, SC8180X_SLAVE_SERVICE_A2NOC, 1, 4); 84 DEFINE_QNODE(slv_qns_camnoc_uncomp, SC8180X_SLAVE_CAMNOC_UNCOMP, 1, 32); 85 DEFINE_QNODE(slv_qns_cdsp_mem_noc, SC8180X_SLAVE_CDSP_MEM_NOC, 2, 32, SC8180X_MASTER_COMPUTE_NOC); 86 DEFINE_QNODE(slv_qhs_a1_noc_cfg, SC8180X_SLAVE_A1NOC_CFG, 1, 4, SC8180X_MASTER_A1NOC_CFG); 87 DEFINE_QNODE(slv_qhs_a2_noc_cfg, SC8180X_SLAVE_A2NOC_CFG, 1, 4, SC8180X_MASTER_A2NOC_CFG); 88 DEFINE_QNODE(slv_qhs_ahb2phy_refgen_center, SC8180X_SLAVE_AHB2PHY_CENTER, 1, 4); 89 DEFINE_QNODE(slv_qhs_ahb2phy_refgen_east, SC8180X_SLAVE_AHB2PHY_EAST, 1, 4); 90 DEFINE_QNODE(slv_qhs_ahb2phy_refgen_west, SC8180X_SLAVE_AHB2PHY_WEST, 1, 4); 91 DEFINE_QNODE(slv_qhs_ahb2phy_south, SC8180X_SLAVE_AHB2PHY_SOUTH, 1, 4); 92 DEFINE_QNODE(slv_qhs_aop, SC8180X_SLAVE_AOP, 1, 4); 93 DEFINE_QNODE(slv_qhs_aoss, SC8180X_SLAVE_AOSS, 1, 4); 94 DEFINE_QNODE(slv_qhs_camera_cfg, SC8180X_SLAVE_CAMERA_CFG, 1, 4); 95 DEFINE_QNODE(slv_qhs_clk_ctl, SC8180X_SLAVE_CLK_CTL, 1, 4); 96 DEFINE_QNODE(slv_qhs_compute_dsp, SC8180X_SLAVE_CDSP_CFG, 1, 4); 97 DEFINE_QNODE(slv_qhs_cpr_cx, SC8180X_SLAVE_RBCPR_CX_CFG, 1, 4); 98 DEFINE_QNODE(slv_qhs_cpr_mmcx, SC8180X_SLAVE_RBCPR_MMCX_CFG, 1, 4); 99 DEFINE_QNODE(slv_qhs_cpr_mx, SC8180X_SLAVE_RBCPR_MX_CFG, 1, 4); 100 DEFINE_QNODE(slv_qhs_crypto0_cfg, SC8180X_SLAVE_CRYPTO_0_CFG, 1, 4); 101 DEFINE_QNODE(slv_qhs_ddrss_cfg, SC8180X_SLAVE_CNOC_DDRSS, 1, 4, SC8180X_MASTER_CNOC_DC_NOC); 102 DEFINE_QNODE(slv_qhs_display_cfg, SC8180X_SLAVE_DISPLAY_CFG, 1, 4); 103 DEFINE_QNODE(slv_qhs_emac_cfg, SC8180X_SLAVE_EMAC_CFG, 1, 4); 104 DEFINE_QNODE(slv_qhs_glm, SC8180X_SLAVE_GLM, 1, 4); 105 DEFINE_QNODE(slv_qhs_gpuss_cfg, SC8180X_SLAVE_GRAPHICS_3D_CFG, 1, 8); 106 DEFINE_QNODE(slv_qhs_imem_cfg, SC8180X_SLAVE_IMEM_CFG, 1, 4); 107 DEFINE_QNODE(slv_qhs_ipa, SC8180X_SLAVE_IPA_CFG, 1, 4); 108 DEFINE_QNODE(slv_qhs_mnoc_cfg, SC8180X_SLAVE_CNOC_MNOC_CFG, 1, 4, SC8180X_MASTER_CNOC_MNOC_CFG); 109 DEFINE_QNODE(slv_qhs_npu_cfg, SC8180X_SLAVE_NPU_CFG, 1, 4); 110 DEFINE_QNODE(slv_qhs_pcie0_cfg, SC8180X_SLAVE_PCIE_0_CFG, 1, 4); 111 DEFINE_QNODE(slv_qhs_pcie1_cfg, SC8180X_SLAVE_PCIE_1_CFG, 1, 4); 112 DEFINE_QNODE(slv_qhs_pcie2_cfg, SC8180X_SLAVE_PCIE_2_CFG, 1, 4); 113 DEFINE_QNODE(slv_qhs_pcie3_cfg, SC8180X_SLAVE_PCIE_3_CFG, 1, 4); 114 DEFINE_QNODE(slv_qhs_pdm, SC8180X_SLAVE_PDM, 1, 4); 115 DEFINE_QNODE(slv_qhs_pimem_cfg, SC8180X_SLAVE_PIMEM_CFG, 1, 4); 116 DEFINE_QNODE(slv_qhs_prng, SC8180X_SLAVE_PRNG, 1, 4); 117 DEFINE_QNODE(slv_qhs_qdss_cfg, SC8180X_SLAVE_QDSS_CFG, 1, 4); 118 DEFINE_QNODE(slv_qhs_qspi_0, SC8180X_SLAVE_QSPI_0, 1, 4); 119 DEFINE_QNODE(slv_qhs_qspi_1, SC8180X_SLAVE_QSPI_1, 1, 4); 120 DEFINE_QNODE(slv_qhs_qupv3_east0, SC8180X_SLAVE_QUP_1, 1, 4); 121 DEFINE_QNODE(slv_qhs_qupv3_east1, SC8180X_SLAVE_QUP_2, 1, 4); 122 DEFINE_QNODE(slv_qhs_qupv3_west, SC8180X_SLAVE_QUP_0, 1, 4); 123 DEFINE_QNODE(slv_qhs_sdc2, SC8180X_SLAVE_SDCC_2, 1, 4); 124 DEFINE_QNODE(slv_qhs_sdc4, SC8180X_SLAVE_SDCC_4, 1, 4); 125 DEFINE_QNODE(slv_qhs_security, SC8180X_SLAVE_SECURITY, 1, 4); 126 DEFINE_QNODE(slv_qhs_snoc_cfg, SC8180X_SLAVE_SNOC_CFG, 1, 4, SC8180X_MASTER_SNOC_CFG); 127 DEFINE_QNODE(slv_qhs_spss_cfg, SC8180X_SLAVE_SPSS_CFG, 1, 4); 128 DEFINE_QNODE(slv_qhs_tcsr, SC8180X_SLAVE_TCSR, 1, 4); 129 DEFINE_QNODE(slv_qhs_tlmm_east, SC8180X_SLAVE_TLMM_EAST, 1, 4); 130 DEFINE_QNODE(slv_qhs_tlmm_south, SC8180X_SLAVE_TLMM_SOUTH, 1, 4); 131 DEFINE_QNODE(slv_qhs_tlmm_west, SC8180X_SLAVE_TLMM_WEST, 1, 4); 132 DEFINE_QNODE(slv_qhs_tsif, SC8180X_SLAVE_TSIF, 1, 4); 133 DEFINE_QNODE(slv_qhs_ufs_card_cfg, SC8180X_SLAVE_UFS_CARD_CFG, 1, 4); 134 DEFINE_QNODE(slv_qhs_ufs_mem0_cfg, SC8180X_SLAVE_UFS_MEM_0_CFG, 1, 4); 135 DEFINE_QNODE(slv_qhs_ufs_mem1_cfg, SC8180X_SLAVE_UFS_MEM_1_CFG, 1, 4); 136 DEFINE_QNODE(slv_qhs_usb3_0, SC8180X_SLAVE_USB3, 1, 4); 137 DEFINE_QNODE(slv_qhs_usb3_1, SC8180X_SLAVE_USB3_1, 1, 4); 138 DEFINE_QNODE(slv_qhs_usb3_2, SC8180X_SLAVE_USB3_2, 1, 4); 139 DEFINE_QNODE(slv_qhs_venus_cfg, SC8180X_SLAVE_VENUS_CFG, 1, 4); 140 DEFINE_QNODE(slv_qhs_vsense_ctrl_cfg, SC8180X_SLAVE_VSENSE_CTRL_CFG, 1, 4); 141 DEFINE_QNODE(slv_srvc_cnoc, SC8180X_SLAVE_SERVICE_CNOC, 1, 4); 142 DEFINE_QNODE(slv_qhs_gemnoc, SC8180X_SLAVE_GEM_NOC_CFG, 1, 4, SC8180X_MASTER_GEM_NOC_CFG); 143 DEFINE_QNODE(slv_qhs_llcc, SC8180X_SLAVE_LLCC_CFG, 1, 4); 144 DEFINE_QNODE(slv_qhs_mdsp_ms_mpu_cfg, SC8180X_SLAVE_MSS_PROC_MS_MPU_CFG, 1, 4); 145 DEFINE_QNODE(slv_qns_ecc, SC8180X_SLAVE_ECC, 1, 32); 146 DEFINE_QNODE(slv_qns_gem_noc_snoc, SC8180X_SLAVE_GEM_NOC_SNOC, 1, 8, SC8180X_MASTER_GEM_NOC_SNOC); 147 DEFINE_QNODE(slv_qns_llcc, SC8180X_SLAVE_LLCC, 8, 16, SC8180X_MASTER_LLCC); 148 DEFINE_QNODE(slv_srvc_gemnoc, SC8180X_SLAVE_SERVICE_GEM_NOC, 1, 4); 149 DEFINE_QNODE(slv_srvc_gemnoc1, SC8180X_SLAVE_SERVICE_GEM_NOC_1, 1, 4); 150 DEFINE_QNODE(slv_ipa_core_slave, SC8180X_SLAVE_IPA_CORE, 1, 8); 151 DEFINE_QNODE(slv_ebi, SC8180X_SLAVE_EBI_CH0, 8, 4); 152 DEFINE_QNODE(slv_qns2_mem_noc, SC8180X_SLAVE_MNOC_SF_MEM_NOC, 1, 32, SC8180X_MASTER_MNOC_SF_MEM_NOC); 153 DEFINE_QNODE(slv_qns_mem_noc_hf, SC8180X_SLAVE_MNOC_HF_MEM_NOC, 2, 32, SC8180X_MASTER_MNOC_HF_MEM_NOC); 154 DEFINE_QNODE(slv_srvc_mnoc, SC8180X_SLAVE_SERVICE_MNOC, 1, 4); 155 DEFINE_QNODE(slv_qhs_apss, SC8180X_SLAVE_APPSS, 1, 8); 156 DEFINE_QNODE(slv_qns_cnoc, SC8180X_SNOC_CNOC_SLV, 1, 8, SC8180X_SNOC_CNOC_MAS); 157 DEFINE_QNODE(slv_qns_gemnoc_gc, SC8180X_SLAVE_SNOC_GEM_NOC_GC, 1, 8, SC8180X_MASTER_SNOC_GC_MEM_NOC); 158 DEFINE_QNODE(slv_qns_gemnoc_sf, SC8180X_SLAVE_SNOC_GEM_NOC_SF, 1, 32, SC8180X_MASTER_SNOC_SF_MEM_NOC); 159 DEFINE_QNODE(slv_qxs_imem, SC8180X_SLAVE_OCIMEM, 1, 8); 160 DEFINE_QNODE(slv_qxs_pimem, SC8180X_SLAVE_PIMEM, 1, 8); 161 DEFINE_QNODE(slv_srvc_snoc, SC8180X_SLAVE_SERVICE_SNOC, 1, 4); 162 DEFINE_QNODE(slv_xs_pcie_0, SC8180X_SLAVE_PCIE_0, 1, 8); 163 DEFINE_QNODE(slv_xs_pcie_1, SC8180X_SLAVE_PCIE_1, 1, 8); 164 DEFINE_QNODE(slv_xs_pcie_2, SC8180X_SLAVE_PCIE_2, 1, 8); 165 DEFINE_QNODE(slv_xs_pcie_3, SC8180X_SLAVE_PCIE_3, 1, 8); 166 DEFINE_QNODE(slv_xs_qdss_stm, SC8180X_SLAVE_QDSS_STM, 1, 4); 167 DEFINE_QNODE(slv_xs_sys_tcu_cfg, SC8180X_SLAVE_TCU, 1, 8); 168 169 DEFINE_QBCM(bcm_acv, "ACV", false, &slv_ebi); 170 DEFINE_QBCM(bcm_mc0, "MC0", false, &slv_ebi); 171 DEFINE_QBCM(bcm_sh0, "SH0", false, &slv_qns_llcc); 172 DEFINE_QBCM(bcm_mm0, "MM0", false, &slv_qns_mem_noc_hf); 173 DEFINE_QBCM(bcm_co0, "CO0", false, &slv_qns_cdsp_mem_noc); 174 DEFINE_QBCM(bcm_ce0, "CE0", false, &mas_qxm_crypto); 175 DEFINE_QBCM(bcm_cn0, "CN0", false, &mas_qnm_snoc, &slv_qhs_a1_noc_cfg, &slv_qhs_a2_noc_cfg, &slv_qhs_ahb2phy_refgen_center, &slv_qhs_ahb2phy_refgen_east, &slv_qhs_ahb2phy_refgen_west, &slv_qhs_ahb2phy_south, &slv_qhs_aop, &slv_qhs_aoss, &slv_qhs_camera_cfg, &slv_qhs_clk_ctl, &slv_qhs_compute_dsp, &slv_qhs_cpr_cx, &slv_qhs_cpr_mmcx, &slv_qhs_cpr_mx, &slv_qhs_crypto0_cfg, &slv_qhs_ddrss_cfg, &slv_qhs_display_cfg, &slv_qhs_emac_cfg, &slv_qhs_glm, &slv_qhs_gpuss_cfg, &slv_qhs_imem_cfg, &slv_qhs_ipa, &slv_qhs_mnoc_cfg, &slv_qhs_npu_cfg, &slv_qhs_pcie0_cfg, &slv_qhs_pcie1_cfg, &slv_qhs_pcie2_cfg, &slv_qhs_pcie3_cfg, &slv_qhs_pdm, &slv_qhs_pimem_cfg, &slv_qhs_prng, &slv_qhs_qdss_cfg, &slv_qhs_qspi_0, &slv_qhs_qspi_1, &slv_qhs_qupv3_east0, &slv_qhs_qupv3_east1, &slv_qhs_qupv3_west, &slv_qhs_sdc2, &slv_qhs_sdc4, &slv_qhs_security, &slv_qhs_snoc_cfg, &slv_qhs_spss_cfg, &slv_qhs_tcsr, &slv_qhs_tlmm_east, &slv_qhs_tlmm_south, &slv_qhs_tlmm_west, &slv_qhs_tsif, &slv_qhs_ufs_card_cfg, &slv_qhs_ufs_mem0_cfg, &slv_qhs_ufs_mem1_cfg, &slv_qhs_usb3_0, &slv_qhs_usb3_1, &slv_qhs_usb3_2, &slv_qhs_venus_cfg, &slv_qhs_vsense_ctrl_cfg, &slv_srvc_cnoc); 176 DEFINE_QBCM(bcm_mm1, "MM1", false, &mas_qxm_camnoc_hf0_uncomp, &mas_qxm_camnoc_hf1_uncomp, &mas_qxm_camnoc_sf_uncomp, &mas_qxm_camnoc_hf0, &mas_qxm_camnoc_hf1, &mas_qxm_mdp0, &mas_qxm_mdp1); 177 DEFINE_QBCM(bcm_qup0, "QUP0", false, &mas_qhm_qup0, &mas_qhm_qup1, &mas_qhm_qup2); 178 DEFINE_QBCM(bcm_sh2, "SH2", false, &slv_qns_gem_noc_snoc); 179 DEFINE_QBCM(bcm_mm2, "MM2", false, &mas_qxm_camnoc_sf, &mas_qxm_rot, &mas_qxm_venus0, &mas_qxm_venus1, &mas_qxm_venus_arm9, &slv_qns2_mem_noc); 180 DEFINE_QBCM(bcm_sh3, "SH3", false, &mas_acm_apps); 181 DEFINE_QBCM(bcm_sn0, "SN0", false, &slv_qns_gemnoc_sf); 182 DEFINE_QBCM(bcm_sn1, "SN1", false, &slv_qxs_imem); 183 DEFINE_QBCM(bcm_sn2, "SN2", false, &slv_qns_gemnoc_gc); 184 DEFINE_QBCM(bcm_co2, "CO2", false, &mas_qnm_npu); 185 DEFINE_QBCM(bcm_ip0, "IP0", false, &slv_ipa_core_slave); 186 DEFINE_QBCM(bcm_sn3, "SN3", false, &slv_srvc_aggre1_noc, &slv_qns_cnoc); 187 DEFINE_QBCM(bcm_sn4, "SN4", false, &slv_qxs_pimem); 188 DEFINE_QBCM(bcm_sn8, "SN8", false, &slv_xs_pcie_0, &slv_xs_pcie_1, &slv_xs_pcie_2, &slv_xs_pcie_3); 189 DEFINE_QBCM(bcm_sn9, "SN9", false, &mas_qnm_aggre1_noc); 190 DEFINE_QBCM(bcm_sn11, "SN11", false, &mas_qnm_aggre2_noc); 191 DEFINE_QBCM(bcm_sn14, "SN14", false, &slv_qns_pcie_mem_noc); 192 DEFINE_QBCM(bcm_sn15, "SN15", false, &mas_qnm_gemnoc); 193 194 static struct qcom_icc_bcm *aggre1_noc_bcms[] = { 195 &bcm_sn3, 196 &bcm_ce0, 197 &bcm_qup0, 198 }; 199 200 static struct qcom_icc_bcm *aggre2_noc_bcms[] = { 201 &bcm_sn14, 202 &bcm_ce0, 203 &bcm_qup0, 204 }; 205 206 static struct qcom_icc_bcm *camnoc_virt_bcms[] = { 207 &bcm_mm1, 208 }; 209 210 static struct qcom_icc_bcm *compute_noc_bcms[] = { 211 &bcm_co0, 212 &bcm_co2, 213 }; 214 215 static struct qcom_icc_bcm *config_noc_bcms[] = { 216 &bcm_cn0, 217 }; 218 219 static struct qcom_icc_bcm *gem_noc_bcms[] = { 220 &bcm_sh0, 221 &bcm_sh2, 222 &bcm_sh3, 223 }; 224 225 static struct qcom_icc_bcm *ipa_virt_bcms[] = { 226 &bcm_ip0, 227 }; 228 229 static struct qcom_icc_bcm *mc_virt_bcms[] = { 230 &bcm_mc0, 231 &bcm_acv, 232 }; 233 234 static struct qcom_icc_bcm *mmss_noc_bcms[] = { 235 &bcm_mm0, 236 &bcm_mm1, 237 &bcm_mm2, 238 }; 239 240 static struct qcom_icc_bcm *system_noc_bcms[] = { 241 &bcm_sn0, 242 &bcm_sn1, 243 &bcm_sn2, 244 &bcm_sn3, 245 &bcm_sn4, 246 &bcm_sn8, 247 &bcm_sn9, 248 &bcm_sn11, 249 &bcm_sn15, 250 }; 251 252 static struct qcom_icc_node *aggre1_noc_nodes[] = { 253 [MASTER_A1NOC_CFG] = &mas_qhm_a1noc_cfg, 254 [MASTER_UFS_CARD] = &mas_xm_ufs_card, 255 [MASTER_UFS_GEN4] = &mas_xm_ufs_g4, 256 [MASTER_UFS_MEM] = &mas_xm_ufs_mem, 257 [MASTER_USB3] = &mas_xm_usb3_0, 258 [MASTER_USB3_1] = &mas_xm_usb3_1, 259 [MASTER_USB3_2] = &mas_xm_usb3_2, 260 [A1NOC_SNOC_SLV] = &slv_qns_a1noc_snoc, 261 [SLAVE_SERVICE_A1NOC] = &slv_srvc_aggre1_noc, 262 }; 263 264 static struct qcom_icc_node *aggre2_noc_nodes[] = { 265 [MASTER_A2NOC_CFG] = &mas_qhm_a2noc_cfg, 266 [MASTER_QDSS_BAM] = &mas_qhm_qdss_bam, 267 [MASTER_QSPI_0] = &mas_qhm_qspi, 268 [MASTER_QSPI_1] = &mas_qhm_qspi1, 269 [MASTER_QUP_0] = &mas_qhm_qup0, 270 [MASTER_QUP_1] = &mas_qhm_qup1, 271 [MASTER_QUP_2] = &mas_qhm_qup2, 272 [MASTER_SENSORS_AHB] = &mas_qhm_sensorss_ahb, 273 [MASTER_CRYPTO_CORE_0] = &mas_qxm_crypto, 274 [MASTER_IPA] = &mas_qxm_ipa, 275 [MASTER_EMAC] = &mas_xm_emac, 276 [MASTER_PCIE] = &mas_xm_pcie3_0, 277 [MASTER_PCIE_1] = &mas_xm_pcie3_1, 278 [MASTER_PCIE_2] = &mas_xm_pcie3_2, 279 [MASTER_PCIE_3] = &mas_xm_pcie3_3, 280 [MASTER_QDSS_ETR] = &mas_xm_qdss_etr, 281 [MASTER_SDCC_2] = &mas_xm_sdc2, 282 [MASTER_SDCC_4] = &mas_xm_sdc4, 283 [A2NOC_SNOC_SLV] = &slv_qns_a2noc_snoc, 284 [SLAVE_ANOC_PCIE_GEM_NOC] = &slv_qns_pcie_mem_noc, 285 [SLAVE_SERVICE_A2NOC] = &slv_srvc_aggre2_noc, 286 }; 287 288 static struct qcom_icc_node *camnoc_virt_nodes[] = { 289 [MASTER_CAMNOC_HF0_UNCOMP] = &mas_qxm_camnoc_hf0_uncomp, 290 [MASTER_CAMNOC_HF1_UNCOMP] = &mas_qxm_camnoc_hf1_uncomp, 291 [MASTER_CAMNOC_SF_UNCOMP] = &mas_qxm_camnoc_sf_uncomp, 292 [SLAVE_CAMNOC_UNCOMP] = &slv_qns_camnoc_uncomp, 293 }; 294 295 static struct qcom_icc_node *compute_noc_nodes[] = { 296 [MASTER_NPU] = &mas_qnm_npu, 297 [SLAVE_CDSP_MEM_NOC] = &slv_qns_cdsp_mem_noc, 298 }; 299 300 static struct qcom_icc_node *config_noc_nodes[] = { 301 [SNOC_CNOC_MAS] = &mas_qnm_snoc, 302 [SLAVE_A1NOC_CFG] = &slv_qhs_a1_noc_cfg, 303 [SLAVE_A2NOC_CFG] = &slv_qhs_a2_noc_cfg, 304 [SLAVE_AHB2PHY_CENTER] = &slv_qhs_ahb2phy_refgen_center, 305 [SLAVE_AHB2PHY_EAST] = &slv_qhs_ahb2phy_refgen_east, 306 [SLAVE_AHB2PHY_WEST] = &slv_qhs_ahb2phy_refgen_west, 307 [SLAVE_AHB2PHY_SOUTH] = &slv_qhs_ahb2phy_south, 308 [SLAVE_AOP] = &slv_qhs_aop, 309 [SLAVE_AOSS] = &slv_qhs_aoss, 310 [SLAVE_CAMERA_CFG] = &slv_qhs_camera_cfg, 311 [SLAVE_CLK_CTL] = &slv_qhs_clk_ctl, 312 [SLAVE_CDSP_CFG] = &slv_qhs_compute_dsp, 313 [SLAVE_RBCPR_CX_CFG] = &slv_qhs_cpr_cx, 314 [SLAVE_RBCPR_MMCX_CFG] = &slv_qhs_cpr_mmcx, 315 [SLAVE_RBCPR_MX_CFG] = &slv_qhs_cpr_mx, 316 [SLAVE_CRYPTO_0_CFG] = &slv_qhs_crypto0_cfg, 317 [SLAVE_CNOC_DDRSS] = &slv_qhs_ddrss_cfg, 318 [SLAVE_DISPLAY_CFG] = &slv_qhs_display_cfg, 319 [SLAVE_EMAC_CFG] = &slv_qhs_emac_cfg, 320 [SLAVE_GLM] = &slv_qhs_glm, 321 [SLAVE_GRAPHICS_3D_CFG] = &slv_qhs_gpuss_cfg, 322 [SLAVE_IMEM_CFG] = &slv_qhs_imem_cfg, 323 [SLAVE_IPA_CFG] = &slv_qhs_ipa, 324 [SLAVE_CNOC_MNOC_CFG] = &slv_qhs_mnoc_cfg, 325 [SLAVE_NPU_CFG] = &slv_qhs_npu_cfg, 326 [SLAVE_PCIE_0_CFG] = &slv_qhs_pcie0_cfg, 327 [SLAVE_PCIE_1_CFG] = &slv_qhs_pcie1_cfg, 328 [SLAVE_PCIE_2_CFG] = &slv_qhs_pcie2_cfg, 329 [SLAVE_PCIE_3_CFG] = &slv_qhs_pcie3_cfg, 330 [SLAVE_PDM] = &slv_qhs_pdm, 331 [SLAVE_PIMEM_CFG] = &slv_qhs_pimem_cfg, 332 [SLAVE_PRNG] = &slv_qhs_prng, 333 [SLAVE_QDSS_CFG] = &slv_qhs_qdss_cfg, 334 [SLAVE_QSPI_0] = &slv_qhs_qspi_0, 335 [SLAVE_QSPI_1] = &slv_qhs_qspi_1, 336 [SLAVE_QUP_1] = &slv_qhs_qupv3_east0, 337 [SLAVE_QUP_2] = &slv_qhs_qupv3_east1, 338 [SLAVE_QUP_0] = &slv_qhs_qupv3_west, 339 [SLAVE_SDCC_2] = &slv_qhs_sdc2, 340 [SLAVE_SDCC_4] = &slv_qhs_sdc4, 341 [SLAVE_SECURITY] = &slv_qhs_security, 342 [SLAVE_SNOC_CFG] = &slv_qhs_snoc_cfg, 343 [SLAVE_SPSS_CFG] = &slv_qhs_spss_cfg, 344 [SLAVE_TCSR] = &slv_qhs_tcsr, 345 [SLAVE_TLMM_EAST] = &slv_qhs_tlmm_east, 346 [SLAVE_TLMM_SOUTH] = &slv_qhs_tlmm_south, 347 [SLAVE_TLMM_WEST] = &slv_qhs_tlmm_west, 348 [SLAVE_TSIF] = &slv_qhs_tsif, 349 [SLAVE_UFS_CARD_CFG] = &slv_qhs_ufs_card_cfg, 350 [SLAVE_UFS_MEM_0_CFG] = &slv_qhs_ufs_mem0_cfg, 351 [SLAVE_UFS_MEM_1_CFG] = &slv_qhs_ufs_mem1_cfg, 352 [SLAVE_USB3] = &slv_qhs_usb3_0, 353 [SLAVE_USB3_1] = &slv_qhs_usb3_1, 354 [SLAVE_USB3_2] = &slv_qhs_usb3_2, 355 [SLAVE_VENUS_CFG] = &slv_qhs_venus_cfg, 356 [SLAVE_VSENSE_CTRL_CFG] = &slv_qhs_vsense_ctrl_cfg, 357 [SLAVE_SERVICE_CNOC] = &slv_srvc_cnoc, 358 }; 359 360 static struct qcom_icc_node *dc_noc_nodes[] = { 361 [MASTER_CNOC_DC_NOC] = &mas_qhm_cnoc_dc_noc, 362 [SLAVE_GEM_NOC_CFG] = &slv_qhs_gemnoc, 363 [SLAVE_LLCC_CFG] = &slv_qhs_llcc, 364 }; 365 366 static struct qcom_icc_node *gem_noc_nodes[] = { 367 [MASTER_AMPSS_M0] = &mas_acm_apps, 368 [MASTER_GPU_TCU] = &mas_acm_gpu_tcu, 369 [MASTER_SYS_TCU] = &mas_acm_sys_tcu, 370 [MASTER_GEM_NOC_CFG] = &mas_qhm_gemnoc_cfg, 371 [MASTER_COMPUTE_NOC] = &mas_qnm_cmpnoc, 372 [MASTER_GRAPHICS_3D] = &mas_qnm_gpu, 373 [MASTER_MNOC_HF_MEM_NOC] = &mas_qnm_mnoc_hf, 374 [MASTER_MNOC_SF_MEM_NOC] = &mas_qnm_mnoc_sf, 375 [MASTER_GEM_NOC_PCIE_SNOC] = &mas_qnm_pcie, 376 [MASTER_SNOC_GC_MEM_NOC] = &mas_qnm_snoc_gc, 377 [MASTER_SNOC_SF_MEM_NOC] = &mas_qnm_snoc_sf, 378 [MASTER_ECC] = &mas_qxm_ecc, 379 [SLAVE_MSS_PROC_MS_MPU_CFG] = &slv_qhs_mdsp_ms_mpu_cfg, 380 [SLAVE_ECC] = &slv_qns_ecc, 381 [SLAVE_GEM_NOC_SNOC] = &slv_qns_gem_noc_snoc, 382 [SLAVE_LLCC] = &slv_qns_llcc, 383 [SLAVE_SERVICE_GEM_NOC] = &slv_srvc_gemnoc, 384 [SLAVE_SERVICE_GEM_NOC_1] = &slv_srvc_gemnoc1, 385 }; 386 387 static struct qcom_icc_node *ipa_virt_nodes[] = { 388 [MASTER_IPA_CORE] = &mas_ipa_core_master, 389 [SLAVE_IPA_CORE] = &slv_ipa_core_slave, 390 }; 391 392 static struct qcom_icc_node *mc_virt_nodes[] = { 393 [MASTER_LLCC] = &mas_llcc_mc, 394 [SLAVE_EBI_CH0] = &slv_ebi, 395 }; 396 397 static struct qcom_icc_node *mmss_noc_nodes[] = { 398 [MASTER_CNOC_MNOC_CFG] = &mas_qhm_mnoc_cfg, 399 [MASTER_CAMNOC_HF0] = &mas_qxm_camnoc_hf0, 400 [MASTER_CAMNOC_HF1] = &mas_qxm_camnoc_hf1, 401 [MASTER_CAMNOC_SF] = &mas_qxm_camnoc_sf, 402 [MASTER_MDP_PORT0] = &mas_qxm_mdp0, 403 [MASTER_MDP_PORT1] = &mas_qxm_mdp1, 404 [MASTER_ROTATOR] = &mas_qxm_rot, 405 [MASTER_VIDEO_P0] = &mas_qxm_venus0, 406 [MASTER_VIDEO_P1] = &mas_qxm_venus1, 407 [MASTER_VIDEO_PROC] = &mas_qxm_venus_arm9, 408 [SLAVE_MNOC_SF_MEM_NOC] = &slv_qns2_mem_noc, 409 [SLAVE_MNOC_HF_MEM_NOC] = &slv_qns_mem_noc_hf, 410 [SLAVE_SERVICE_MNOC] = &slv_srvc_mnoc, 411 }; 412 413 static struct qcom_icc_node *system_noc_nodes[] = { 414 [MASTER_SNOC_CFG] = &mas_qhm_snoc_cfg, 415 [A1NOC_SNOC_MAS] = &mas_qnm_aggre1_noc, 416 [A2NOC_SNOC_MAS] = &mas_qnm_aggre2_noc, 417 [MASTER_GEM_NOC_SNOC] = &mas_qnm_gemnoc, 418 [MASTER_PIMEM] = &mas_qxm_pimem, 419 [MASTER_GIC] = &mas_xm_gic, 420 [SLAVE_APPSS] = &slv_qhs_apss, 421 [SNOC_CNOC_SLV] = &slv_qns_cnoc, 422 [SLAVE_SNOC_GEM_NOC_GC] = &slv_qns_gemnoc_gc, 423 [SLAVE_SNOC_GEM_NOC_SF] = &slv_qns_gemnoc_sf, 424 [SLAVE_OCIMEM] = &slv_qxs_imem, 425 [SLAVE_PIMEM] = &slv_qxs_pimem, 426 [SLAVE_SERVICE_SNOC] = &slv_srvc_snoc, 427 [SLAVE_QDSS_STM] = &slv_xs_qdss_stm, 428 [SLAVE_TCU] = &slv_xs_sys_tcu_cfg, 429 }; 430 431 static const struct qcom_icc_desc sc8180x_aggre1_noc = { 432 .nodes = aggre1_noc_nodes, 433 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 434 .bcms = aggre1_noc_bcms, 435 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 436 }; 437 438 static const struct qcom_icc_desc sc8180x_aggre2_noc = { 439 .nodes = aggre2_noc_nodes, 440 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 441 .bcms = aggre2_noc_bcms, 442 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 443 }; 444 445 static const struct qcom_icc_desc sc8180x_camnoc_virt = { 446 .nodes = camnoc_virt_nodes, 447 .num_nodes = ARRAY_SIZE(camnoc_virt_nodes), 448 .bcms = camnoc_virt_bcms, 449 .num_bcms = ARRAY_SIZE(camnoc_virt_bcms), 450 }; 451 452 static const struct qcom_icc_desc sc8180x_compute_noc = { 453 .nodes = compute_noc_nodes, 454 .num_nodes = ARRAY_SIZE(compute_noc_nodes), 455 .bcms = compute_noc_bcms, 456 .num_bcms = ARRAY_SIZE(compute_noc_bcms), 457 }; 458 459 static const struct qcom_icc_desc sc8180x_config_noc = { 460 .nodes = config_noc_nodes, 461 .num_nodes = ARRAY_SIZE(config_noc_nodes), 462 .bcms = config_noc_bcms, 463 .num_bcms = ARRAY_SIZE(config_noc_bcms), 464 }; 465 466 static const struct qcom_icc_desc sc8180x_dc_noc = { 467 .nodes = dc_noc_nodes, 468 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 469 }; 470 471 static const struct qcom_icc_desc sc8180x_gem_noc = { 472 .nodes = gem_noc_nodes, 473 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 474 .bcms = gem_noc_bcms, 475 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 476 }; 477 478 static const struct qcom_icc_desc sc8180x_ipa_virt = { 479 .nodes = ipa_virt_nodes, 480 .num_nodes = ARRAY_SIZE(ipa_virt_nodes), 481 .bcms = ipa_virt_bcms, 482 .num_bcms = ARRAY_SIZE(ipa_virt_bcms), 483 }; 484 485 static const struct qcom_icc_desc sc8180x_mc_virt = { 486 .nodes = mc_virt_nodes, 487 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 488 .bcms = mc_virt_bcms, 489 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 490 }; 491 492 static const struct qcom_icc_desc sc8180x_mmss_noc = { 493 .nodes = mmss_noc_nodes, 494 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 495 .bcms = mmss_noc_bcms, 496 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 497 }; 498 499 static const struct qcom_icc_desc sc8180x_system_noc = { 500 .nodes = system_noc_nodes, 501 .num_nodes = ARRAY_SIZE(system_noc_nodes), 502 .bcms = system_noc_bcms, 503 .num_bcms = ARRAY_SIZE(system_noc_bcms), 504 }; 505 506 static int qnoc_probe(struct platform_device *pdev) 507 { 508 const struct qcom_icc_desc *desc; 509 struct icc_onecell_data *data; 510 struct icc_provider *provider; 511 struct qcom_icc_node **qnodes; 512 struct qcom_icc_provider *qp; 513 struct icc_node *node; 514 size_t num_nodes, i; 515 int ret; 516 517 desc = device_get_match_data(&pdev->dev); 518 if (!desc) 519 return -EINVAL; 520 521 qnodes = desc->nodes; 522 num_nodes = desc->num_nodes; 523 524 qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL); 525 if (!qp) 526 return -ENOMEM; 527 528 data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL); 529 if (!data) 530 return -ENOMEM; 531 532 provider = &qp->provider; 533 provider->dev = &pdev->dev; 534 provider->set = qcom_icc_set; 535 provider->pre_aggregate = qcom_icc_pre_aggregate; 536 provider->aggregate = qcom_icc_aggregate; 537 provider->xlate = of_icc_xlate_onecell; 538 INIT_LIST_HEAD(&provider->nodes); 539 provider->data = data; 540 541 qp->dev = &pdev->dev; 542 qp->bcms = desc->bcms; 543 qp->num_bcms = desc->num_bcms; 544 545 qp->voter = of_bcm_voter_get(qp->dev, NULL); 546 if (IS_ERR(qp->voter)) 547 return PTR_ERR(qp->voter); 548 549 ret = icc_provider_add(provider); 550 if (ret) { 551 dev_err(&pdev->dev, "error adding interconnect provider\n"); 552 return ret; 553 } 554 555 for (i = 0; i < qp->num_bcms; i++) 556 qcom_icc_bcm_init(qp->bcms[i], &pdev->dev); 557 558 for (i = 0; i < num_nodes; i++) { 559 size_t j; 560 561 if (!qnodes[i]) 562 continue; 563 564 node = icc_node_create(qnodes[i]->id); 565 if (IS_ERR(node)) { 566 ret = PTR_ERR(node); 567 goto err; 568 } 569 570 node->name = qnodes[i]->name; 571 node->data = qnodes[i]; 572 icc_node_add(node, provider); 573 574 for (j = 0; j < qnodes[i]->num_links; j++) 575 icc_link_create(node, qnodes[i]->links[j]); 576 577 data->nodes[i] = node; 578 } 579 data->num_nodes = num_nodes; 580 581 platform_set_drvdata(pdev, qp); 582 583 return 0; 584 err: 585 icc_nodes_remove(provider); 586 icc_provider_del(provider); 587 return ret; 588 } 589 590 static int qnoc_remove(struct platform_device *pdev) 591 { 592 struct qcom_icc_provider *qp = platform_get_drvdata(pdev); 593 594 icc_nodes_remove(&qp->provider); 595 return icc_provider_del(&qp->provider); 596 } 597 598 static const struct of_device_id qnoc_of_match[] = { 599 { .compatible = "qcom,sc8180x-aggre1-noc", .data = &sc8180x_aggre1_noc }, 600 { .compatible = "qcom,sc8180x-aggre2-noc", .data = &sc8180x_aggre2_noc }, 601 { .compatible = "qcom,sc8180x-camnoc-virt", .data = &sc8180x_camnoc_virt }, 602 { .compatible = "qcom,sc8180x-compute-noc", .data = &sc8180x_compute_noc, }, 603 { .compatible = "qcom,sc8180x-config-noc", .data = &sc8180x_config_noc }, 604 { .compatible = "qcom,sc8180x-dc-noc", .data = &sc8180x_dc_noc }, 605 { .compatible = "qcom,sc8180x-gem-noc", .data = &sc8180x_gem_noc }, 606 { .compatible = "qcom,sc8180x-ipa-virt", .data = &sc8180x_ipa_virt }, 607 { .compatible = "qcom,sc8180x-mc-virt", .data = &sc8180x_mc_virt }, 608 { .compatible = "qcom,sc8180x-mmss-noc", .data = &sc8180x_mmss_noc }, 609 { .compatible = "qcom,sc8180x-system-noc", .data = &sc8180x_system_noc }, 610 { } 611 }; 612 MODULE_DEVICE_TABLE(of, qnoc_of_match); 613 614 static struct platform_driver qnoc_driver = { 615 .probe = qnoc_probe, 616 .remove = qnoc_remove, 617 .driver = { 618 .name = "qnoc-sc8180x", 619 .of_match_table = qnoc_of_match, 620 .sync_state = icc_sync_state, 621 }, 622 }; 623 module_platform_driver(qnoc_driver); 624 625 MODULE_DESCRIPTION("Qualcomm sc8180x NoC driver"); 626 MODULE_LICENSE("GPL v2"); 627