1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 5 * 6 */ 7 8 #include <linux/device.h> 9 #include <linux/interconnect.h> 10 #include <linux/interconnect-provider.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <dt-bindings/interconnect/qcom,sc7280.h> 14 15 #include "bcm-voter.h" 16 #include "icc-rpmh.h" 17 18 static struct qcom_icc_node qhm_qspi; 19 static struct qcom_icc_node qhm_qup0; 20 static struct qcom_icc_node qhm_qup1; 21 static struct qcom_icc_node qnm_a1noc_cfg; 22 static struct qcom_icc_node xm_sdc1; 23 static struct qcom_icc_node xm_sdc2; 24 static struct qcom_icc_node xm_sdc4; 25 static struct qcom_icc_node xm_ufs_mem; 26 static struct qcom_icc_node xm_usb2; 27 static struct qcom_icc_node xm_usb3_0; 28 static struct qcom_icc_node qhm_qdss_bam; 29 static struct qcom_icc_node qnm_a2noc_cfg; 30 static struct qcom_icc_node qnm_cnoc_datapath; 31 static struct qcom_icc_node qxm_crypto; 32 static struct qcom_icc_node qxm_ipa; 33 static struct qcom_icc_node xm_pcie3_0; 34 static struct qcom_icc_node xm_pcie3_1; 35 static struct qcom_icc_node xm_qdss_etr; 36 static struct qcom_icc_node qup0_core_master; 37 static struct qcom_icc_node qup1_core_master; 38 static struct qcom_icc_node qnm_cnoc3_cnoc2; 39 static struct qcom_icc_node xm_qdss_dap; 40 static struct qcom_icc_node qnm_cnoc2_cnoc3; 41 static struct qcom_icc_node qnm_gemnoc_cnoc; 42 static struct qcom_icc_node qnm_gemnoc_pcie; 43 static struct qcom_icc_node qnm_cnoc_dc_noc; 44 static struct qcom_icc_node alm_gpu_tcu; 45 static struct qcom_icc_node alm_sys_tcu; 46 static struct qcom_icc_node chm_apps; 47 static struct qcom_icc_node qnm_cmpnoc; 48 static struct qcom_icc_node qnm_gemnoc_cfg; 49 static struct qcom_icc_node qnm_gpu; 50 static struct qcom_icc_node qnm_mnoc_hf; 51 static struct qcom_icc_node qnm_mnoc_sf; 52 static struct qcom_icc_node qnm_pcie; 53 static struct qcom_icc_node qnm_snoc_gc; 54 static struct qcom_icc_node qnm_snoc_sf; 55 static struct qcom_icc_node qhm_config_noc; 56 static struct qcom_icc_node llcc_mc; 57 static struct qcom_icc_node qnm_mnoc_cfg; 58 static struct qcom_icc_node qnm_video0; 59 static struct qcom_icc_node qnm_video_cpu; 60 static struct qcom_icc_node qxm_camnoc_hf; 61 static struct qcom_icc_node qxm_camnoc_icp; 62 static struct qcom_icc_node qxm_camnoc_sf; 63 static struct qcom_icc_node qxm_mdp0; 64 static struct qcom_icc_node qhm_nsp_noc_config; 65 static struct qcom_icc_node qxm_nsp; 66 static struct qcom_icc_node qnm_aggre1_noc; 67 static struct qcom_icc_node qnm_aggre2_noc; 68 static struct qcom_icc_node qnm_snoc_cfg; 69 static struct qcom_icc_node qxm_pimem; 70 static struct qcom_icc_node xm_gic; 71 static struct qcom_icc_node qns_a1noc_snoc; 72 static struct qcom_icc_node srvc_aggre1_noc; 73 static struct qcom_icc_node qns_a2noc_snoc; 74 static struct qcom_icc_node qns_pcie_mem_noc; 75 static struct qcom_icc_node srvc_aggre2_noc; 76 static struct qcom_icc_node qup0_core_slave; 77 static struct qcom_icc_node qup1_core_slave; 78 static struct qcom_icc_node qhs_ahb2phy0; 79 static struct qcom_icc_node qhs_ahb2phy1; 80 static struct qcom_icc_node qhs_camera_cfg; 81 static struct qcom_icc_node qhs_clk_ctl; 82 static struct qcom_icc_node qhs_compute_cfg; 83 static struct qcom_icc_node qhs_cpr_cx; 84 static struct qcom_icc_node qhs_cpr_mx; 85 static struct qcom_icc_node qhs_crypto0_cfg; 86 static struct qcom_icc_node qhs_cx_rdpm; 87 static struct qcom_icc_node qhs_dcc_cfg; 88 static struct qcom_icc_node qhs_display_cfg; 89 static struct qcom_icc_node qhs_gpuss_cfg; 90 static struct qcom_icc_node qhs_hwkm; 91 static struct qcom_icc_node qhs_imem_cfg; 92 static struct qcom_icc_node qhs_ipa; 93 static struct qcom_icc_node qhs_ipc_router; 94 static struct qcom_icc_node qhs_lpass_cfg; 95 static struct qcom_icc_node qhs_mss_cfg; 96 static struct qcom_icc_node qhs_mx_rdpm; 97 static struct qcom_icc_node qhs_pcie0_cfg; 98 static struct qcom_icc_node qhs_pcie1_cfg; 99 static struct qcom_icc_node qhs_pdm; 100 static struct qcom_icc_node qhs_pimem_cfg; 101 static struct qcom_icc_node qhs_pka_wrapper_cfg; 102 static struct qcom_icc_node qhs_pmu_wrapper_cfg; 103 static struct qcom_icc_node qhs_qdss_cfg; 104 static struct qcom_icc_node qhs_qspi; 105 static struct qcom_icc_node qhs_qup0; 106 static struct qcom_icc_node qhs_qup1; 107 static struct qcom_icc_node qhs_sdc1; 108 static struct qcom_icc_node qhs_sdc2; 109 static struct qcom_icc_node qhs_sdc4; 110 static struct qcom_icc_node qhs_security; 111 static struct qcom_icc_node qhs_tcsr; 112 static struct qcom_icc_node qhs_tlmm; 113 static struct qcom_icc_node qhs_ufs_mem_cfg; 114 static struct qcom_icc_node qhs_usb2; 115 static struct qcom_icc_node qhs_usb3_0; 116 static struct qcom_icc_node qhs_venus_cfg; 117 static struct qcom_icc_node qhs_vsense_ctrl_cfg; 118 static struct qcom_icc_node qns_a1_noc_cfg; 119 static struct qcom_icc_node qns_a2_noc_cfg; 120 static struct qcom_icc_node qns_cnoc2_cnoc3; 121 static struct qcom_icc_node qns_mnoc_cfg; 122 static struct qcom_icc_node qns_snoc_cfg; 123 static struct qcom_icc_node qhs_aoss; 124 static struct qcom_icc_node qhs_apss; 125 static struct qcom_icc_node qns_cnoc3_cnoc2; 126 static struct qcom_icc_node qns_cnoc_a2noc; 127 static struct qcom_icc_node qns_ddrss_cfg; 128 static struct qcom_icc_node qxs_boot_imem; 129 static struct qcom_icc_node qxs_imem; 130 static struct qcom_icc_node qxs_pimem; 131 static struct qcom_icc_node xs_pcie_0; 132 static struct qcom_icc_node xs_pcie_1; 133 static struct qcom_icc_node xs_qdss_stm; 134 static struct qcom_icc_node xs_sys_tcu_cfg; 135 static struct qcom_icc_node qhs_llcc; 136 static struct qcom_icc_node qns_gemnoc; 137 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; 138 static struct qcom_icc_node qhs_modem_ms_mpu_cfg; 139 static struct qcom_icc_node qns_gem_noc_cnoc; 140 static struct qcom_icc_node qns_llcc; 141 static struct qcom_icc_node qns_pcie; 142 static struct qcom_icc_node srvc_even_gemnoc; 143 static struct qcom_icc_node srvc_odd_gemnoc; 144 static struct qcom_icc_node srvc_sys_gemnoc; 145 static struct qcom_icc_node qhs_lpass_core; 146 static struct qcom_icc_node qhs_lpass_lpi; 147 static struct qcom_icc_node qhs_lpass_mpu; 148 static struct qcom_icc_node qhs_lpass_top; 149 static struct qcom_icc_node srvc_niu_aml_noc; 150 static struct qcom_icc_node srvc_niu_lpass_agnoc; 151 static struct qcom_icc_node ebi; 152 static struct qcom_icc_node qns_mem_noc_hf; 153 static struct qcom_icc_node qns_mem_noc_sf; 154 static struct qcom_icc_node srvc_mnoc; 155 static struct qcom_icc_node qns_nsp_gemnoc; 156 static struct qcom_icc_node service_nsp_noc; 157 static struct qcom_icc_node qns_gemnoc_gc; 158 static struct qcom_icc_node qns_gemnoc_sf; 159 static struct qcom_icc_node srvc_snoc; 160 161 static struct qcom_icc_node qhm_qspi = { 162 .name = "qhm_qspi", 163 .channels = 1, 164 .buswidth = 4, 165 .qosbox = &(const struct qcom_icc_qosbox) { 166 .num_ports = 1, 167 .port_offsets = { 0x7000 }, 168 .prio = 2, 169 .urg_fwd = 0, 170 }, 171 .num_links = 1, 172 .link_nodes = { &qns_a1noc_snoc }, 173 }; 174 175 static struct qcom_icc_node qhm_qup0 = { 176 .name = "qhm_qup0", 177 .channels = 1, 178 .buswidth = 4, 179 .qosbox = &(const struct qcom_icc_qosbox) { 180 .num_ports = 1, 181 .port_offsets = { 0x11000 }, 182 .prio = 2, 183 .urg_fwd = 0, 184 }, 185 .num_links = 1, 186 .link_nodes = { &qns_a1noc_snoc }, 187 }; 188 189 static struct qcom_icc_node qhm_qup1 = { 190 .name = "qhm_qup1", 191 .channels = 1, 192 .buswidth = 4, 193 .qosbox = &(const struct qcom_icc_qosbox) { 194 .num_ports = 1, 195 .port_offsets = { 0x8000 }, 196 .prio = 2, 197 .urg_fwd = 0, 198 }, 199 .num_links = 1, 200 .link_nodes = { &qns_a1noc_snoc }, 201 }; 202 203 static struct qcom_icc_node qnm_a1noc_cfg = { 204 .name = "qnm_a1noc_cfg", 205 .channels = 1, 206 .buswidth = 4, 207 .num_links = 1, 208 .link_nodes = { &srvc_aggre1_noc }, 209 }; 210 211 static struct qcom_icc_node xm_sdc1 = { 212 .name = "xm_sdc1", 213 .channels = 1, 214 .buswidth = 8, 215 .qosbox = &(const struct qcom_icc_qosbox) { 216 .num_ports = 1, 217 .port_offsets = { 0xc000 }, 218 .prio = 2, 219 .urg_fwd = 0, 220 }, 221 .num_links = 1, 222 .link_nodes = { &qns_a1noc_snoc }, 223 }; 224 225 static struct qcom_icc_node xm_sdc2 = { 226 .name = "xm_sdc2", 227 .channels = 1, 228 .buswidth = 8, 229 .qosbox = &(const struct qcom_icc_qosbox) { 230 .num_ports = 1, 231 .port_offsets = { 0xe000 }, 232 .prio = 2, 233 .urg_fwd = 0, 234 }, 235 .num_links = 1, 236 .link_nodes = { &qns_a1noc_snoc }, 237 }; 238 239 static struct qcom_icc_node xm_sdc4 = { 240 .name = "xm_sdc4", 241 .channels = 1, 242 .buswidth = 8, 243 .qosbox = &(const struct qcom_icc_qosbox) { 244 .num_ports = 1, 245 .port_offsets = { 0x9000 }, 246 .prio = 2, 247 .urg_fwd = 0, 248 }, 249 .num_links = 1, 250 .link_nodes = { &qns_a1noc_snoc }, 251 }; 252 253 static struct qcom_icc_node xm_ufs_mem = { 254 .name = "xm_ufs_mem", 255 .channels = 1, 256 .buswidth = 8, 257 .qosbox = &(const struct qcom_icc_qosbox) { 258 .num_ports = 1, 259 .port_offsets = { 0xa000 }, 260 .prio = 2, 261 .urg_fwd = 0, 262 }, 263 .num_links = 1, 264 .link_nodes = { &qns_a1noc_snoc }, 265 }; 266 267 static struct qcom_icc_node xm_usb2 = { 268 .name = "xm_usb2", 269 .channels = 1, 270 .buswidth = 8, 271 .num_links = 1, 272 .link_nodes = { &qns_a1noc_snoc }, 273 }; 274 275 static struct qcom_icc_node xm_usb3_0 = { 276 .name = "xm_usb3_0", 277 .channels = 1, 278 .buswidth = 8, 279 .qosbox = &(const struct qcom_icc_qosbox) { 280 .num_ports = 1, 281 .port_offsets = { 0xb000 }, 282 .prio = 2, 283 .urg_fwd = 0, 284 }, 285 .num_links = 1, 286 .link_nodes = { &qns_a1noc_snoc }, 287 }; 288 289 static struct qcom_icc_node qhm_qdss_bam = { 290 .name = "qhm_qdss_bam", 291 .channels = 1, 292 .buswidth = 4, 293 .qosbox = &(const struct qcom_icc_qosbox) { 294 .num_ports = 1, 295 .port_offsets = { 0x18000 }, 296 .prio = 2, 297 .urg_fwd = 0, 298 }, 299 .num_links = 1, 300 .link_nodes = { &qns_a2noc_snoc }, 301 }; 302 303 static struct qcom_icc_node qnm_a2noc_cfg = { 304 .name = "qnm_a2noc_cfg", 305 .channels = 1, 306 .buswidth = 4, 307 .num_links = 1, 308 .link_nodes = { &srvc_aggre2_noc }, 309 }; 310 311 static struct qcom_icc_node qnm_cnoc_datapath = { 312 .name = "qnm_cnoc_datapath", 313 .channels = 1, 314 .buswidth = 8, 315 .qosbox = &(const struct qcom_icc_qosbox) { 316 .num_ports = 1, 317 .port_offsets = { 0x1c000 }, 318 .prio = 2, 319 .urg_fwd = 0, 320 }, 321 .num_links = 1, 322 .link_nodes = { &qns_a2noc_snoc }, 323 }; 324 325 static struct qcom_icc_node qxm_crypto = { 326 .name = "qxm_crypto", 327 .channels = 1, 328 .buswidth = 8, 329 .qosbox = &(const struct qcom_icc_qosbox) { 330 .num_ports = 1, 331 .port_offsets = { 0x1d000 }, 332 .prio = 2, 333 .urg_fwd = 0, 334 }, 335 .num_links = 1, 336 .link_nodes = { &qns_a2noc_snoc }, 337 }; 338 339 static struct qcom_icc_node qxm_ipa = { 340 .name = "qxm_ipa", 341 .channels = 1, 342 .buswidth = 8, 343 .qosbox = &(const struct qcom_icc_qosbox) { 344 .num_ports = 1, 345 .port_offsets = { 0x10000 }, 346 .prio = 2, 347 .urg_fwd = 0, 348 }, 349 .num_links = 1, 350 .link_nodes = { &qns_a2noc_snoc }, 351 }; 352 353 static struct qcom_icc_node xm_pcie3_0 = { 354 .name = "xm_pcie3_0", 355 .channels = 1, 356 .buswidth = 8, 357 .num_links = 1, 358 .link_nodes = { &qns_pcie_mem_noc }, 359 }; 360 361 static struct qcom_icc_node xm_pcie3_1 = { 362 .name = "xm_pcie3_1", 363 .channels = 1, 364 .buswidth = 8, 365 .num_links = 1, 366 .link_nodes = { &qns_pcie_mem_noc }, 367 }; 368 369 static struct qcom_icc_node xm_qdss_etr = { 370 .name = "xm_qdss_etr", 371 .channels = 1, 372 .buswidth = 8, 373 .qosbox = &(const struct qcom_icc_qosbox) { 374 .num_ports = 1, 375 .port_offsets = { 0x15000 }, 376 .prio = 2, 377 .urg_fwd = 0, 378 }, 379 .num_links = 1, 380 .link_nodes = { &qns_a2noc_snoc }, 381 }; 382 383 static struct qcom_icc_node qup0_core_master = { 384 .name = "qup0_core_master", 385 .channels = 1, 386 .buswidth = 4, 387 .num_links = 1, 388 .link_nodes = { &qup0_core_slave }, 389 }; 390 391 static struct qcom_icc_node qup1_core_master = { 392 .name = "qup1_core_master", 393 .channels = 1, 394 .buswidth = 4, 395 .num_links = 1, 396 .link_nodes = { &qup1_core_slave }, 397 }; 398 399 static struct qcom_icc_node qnm_cnoc3_cnoc2 = { 400 .name = "qnm_cnoc3_cnoc2", 401 .channels = 1, 402 .buswidth = 8, 403 .num_links = 44, 404 .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, 405 &qhs_camera_cfg, &qhs_clk_ctl, 406 &qhs_compute_cfg, &qhs_cpr_cx, 407 &qhs_cpr_mx, &qhs_crypto0_cfg, 408 &qhs_cx_rdpm, &qhs_dcc_cfg, 409 &qhs_display_cfg, &qhs_gpuss_cfg, 410 &qhs_hwkm, &qhs_imem_cfg, 411 &qhs_ipa, &qhs_ipc_router, 412 &qhs_lpass_cfg, &qhs_mss_cfg, 413 &qhs_mx_rdpm, &qhs_pcie0_cfg, 414 &qhs_pcie1_cfg, &qhs_pdm, 415 &qhs_pimem_cfg, &qhs_pka_wrapper_cfg, 416 &qhs_pmu_wrapper_cfg, &qhs_qdss_cfg, 417 &qhs_qspi, &qhs_qup0, 418 &qhs_qup1, &qhs_sdc1, 419 &qhs_sdc2, &qhs_sdc4, 420 &qhs_security, &qhs_tcsr, 421 &qhs_tlmm, &qhs_ufs_mem_cfg, 422 &qhs_usb2, &qhs_usb3_0, 423 &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, 424 &qns_a1_noc_cfg, &qns_a2_noc_cfg, 425 &qns_mnoc_cfg, &qns_snoc_cfg }, 426 }; 427 428 static struct qcom_icc_node xm_qdss_dap = { 429 .name = "xm_qdss_dap", 430 .channels = 1, 431 .buswidth = 8, 432 .num_links = 45, 433 .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, 434 &qhs_camera_cfg, &qhs_clk_ctl, 435 &qhs_compute_cfg, &qhs_cpr_cx, 436 &qhs_cpr_mx, &qhs_crypto0_cfg, 437 &qhs_cx_rdpm, &qhs_dcc_cfg, 438 &qhs_display_cfg, &qhs_gpuss_cfg, 439 &qhs_hwkm, &qhs_imem_cfg, 440 &qhs_ipa, &qhs_ipc_router, 441 &qhs_lpass_cfg, &qhs_mss_cfg, 442 &qhs_mx_rdpm, &qhs_pcie0_cfg, 443 &qhs_pcie1_cfg, &qhs_pdm, 444 &qhs_pimem_cfg, &qhs_pka_wrapper_cfg, 445 &qhs_pmu_wrapper_cfg, &qhs_qdss_cfg, 446 &qhs_qspi, &qhs_qup0, 447 &qhs_qup1, &qhs_sdc1, 448 &qhs_sdc2, &qhs_sdc4, 449 &qhs_security, &qhs_tcsr, 450 &qhs_tlmm, &qhs_ufs_mem_cfg, 451 &qhs_usb2, &qhs_usb3_0, 452 &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, 453 &qns_a1_noc_cfg, &qns_a2_noc_cfg, 454 &qns_cnoc2_cnoc3, &qns_mnoc_cfg, 455 &qns_snoc_cfg }, 456 }; 457 458 static struct qcom_icc_node qnm_cnoc2_cnoc3 = { 459 .name = "qnm_cnoc2_cnoc3", 460 .channels = 1, 461 .buswidth = 8, 462 .num_links = 9, 463 .link_nodes = { &qhs_aoss, &qhs_apss, 464 &qns_cnoc_a2noc, &qns_ddrss_cfg, 465 &qxs_boot_imem, &qxs_imem, 466 &qxs_pimem, &xs_qdss_stm, 467 &xs_sys_tcu_cfg }, 468 }; 469 470 static struct qcom_icc_node qnm_gemnoc_cnoc = { 471 .name = "qnm_gemnoc_cnoc", 472 .channels = 1, 473 .buswidth = 16, 474 .num_links = 9, 475 .link_nodes = { &qhs_aoss, &qhs_apss, 476 &qns_cnoc3_cnoc2, &qns_ddrss_cfg, 477 &qxs_boot_imem, &qxs_imem, 478 &qxs_pimem, &xs_qdss_stm, 479 &xs_sys_tcu_cfg }, 480 }; 481 482 static struct qcom_icc_node qnm_gemnoc_pcie = { 483 .name = "qnm_gemnoc_pcie", 484 .channels = 1, 485 .buswidth = 8, 486 .num_links = 2, 487 .link_nodes = { &xs_pcie_0, &xs_pcie_1 }, 488 }; 489 490 static struct qcom_icc_node qnm_cnoc_dc_noc = { 491 .name = "qnm_cnoc_dc_noc", 492 .channels = 1, 493 .buswidth = 4, 494 .num_links = 2, 495 .link_nodes = { &qhs_llcc, &qns_gemnoc }, 496 }; 497 498 static struct qcom_icc_node alm_gpu_tcu = { 499 .name = "alm_gpu_tcu", 500 .channels = 1, 501 .buswidth = 8, 502 .qosbox = &(const struct qcom_icc_qosbox) { 503 .num_ports = 1, 504 .port_offsets = { 0xd7000 }, 505 .prio = 2, 506 .urg_fwd = 0, 507 }, 508 .num_links = 2, 509 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 510 }; 511 512 static struct qcom_icc_node alm_sys_tcu = { 513 .name = "alm_sys_tcu", 514 .channels = 1, 515 .buswidth = 8, 516 .qosbox = &(const struct qcom_icc_qosbox) { 517 .num_ports = 1, 518 .port_offsets = { 0xd6000 }, 519 .prio = 6, 520 .urg_fwd = 0, 521 }, 522 .num_links = 2, 523 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 524 }; 525 526 static struct qcom_icc_node chm_apps = { 527 .name = "chm_apps", 528 .channels = 1, 529 .buswidth = 32, 530 .num_links = 3, 531 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 532 &qns_pcie }, 533 }; 534 535 static struct qcom_icc_node qnm_cmpnoc = { 536 .name = "qnm_cmpnoc", 537 .channels = 2, 538 .buswidth = 32, 539 .qosbox = &(const struct qcom_icc_qosbox) { 540 .num_ports = 2, 541 .port_offsets = { 0x21000, 0x61000 }, 542 .prio = 0, 543 .urg_fwd = 1, 544 }, 545 .num_links = 2, 546 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 547 }; 548 549 static struct qcom_icc_node qnm_gemnoc_cfg = { 550 .name = "qnm_gemnoc_cfg", 551 .channels = 1, 552 .buswidth = 4, 553 .num_links = 5, 554 .link_nodes = { &qhs_mdsp_ms_mpu_cfg, &qhs_modem_ms_mpu_cfg, 555 &srvc_even_gemnoc, &srvc_odd_gemnoc, 556 &srvc_sys_gemnoc }, 557 }; 558 559 static struct qcom_icc_node qnm_gpu = { 560 .name = "qnm_gpu", 561 .channels = 2, 562 .buswidth = 32, 563 .qosbox = &(const struct qcom_icc_qosbox) { 564 .num_ports = 2, 565 .port_offsets = { 0x22000, 0x62000 }, 566 .prio = 0, 567 .urg_fwd = 0, 568 }, 569 .num_links = 2, 570 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 571 }; 572 573 static struct qcom_icc_node qnm_mnoc_hf = { 574 .name = "qnm_mnoc_hf", 575 .channels = 2, 576 .buswidth = 32, 577 .qosbox = &(const struct qcom_icc_qosbox) { 578 .num_ports = 2, 579 .port_offsets = { 0x23000, 0x63000 }, 580 .prio = 0, 581 .urg_fwd = 1, 582 }, 583 .num_links = 1, 584 .link_nodes = { &qns_llcc }, 585 }; 586 587 static struct qcom_icc_node qnm_mnoc_sf = { 588 .name = "qnm_mnoc_sf", 589 .channels = 1, 590 .buswidth = 32, 591 .qosbox = &(const struct qcom_icc_qosbox) { 592 .num_ports = 1, 593 .port_offsets = { 0xcf000 }, 594 .prio = 0, 595 .urg_fwd = 1, 596 }, 597 .num_links = 2, 598 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 599 }; 600 601 static struct qcom_icc_node qnm_pcie = { 602 .name = "qnm_pcie", 603 .channels = 1, 604 .buswidth = 16, 605 .num_links = 2, 606 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 607 }; 608 609 static struct qcom_icc_node qnm_snoc_gc = { 610 .name = "qnm_snoc_gc", 611 .channels = 1, 612 .buswidth = 8, 613 .qosbox = &(const struct qcom_icc_qosbox) { 614 .num_ports = 1, 615 .port_offsets = { 0xd3000 }, 616 .prio = 0, 617 .urg_fwd = 1, 618 }, 619 .num_links = 1, 620 .link_nodes = { &qns_llcc }, 621 }; 622 623 static struct qcom_icc_node qnm_snoc_sf = { 624 .name = "qnm_snoc_sf", 625 .channels = 1, 626 .buswidth = 16, 627 .qosbox = &(const struct qcom_icc_qosbox) { 628 .num_ports = 1, 629 .port_offsets = { 0xd4000 }, 630 .prio = 0, 631 .urg_fwd = 1, 632 }, 633 .num_links = 3, 634 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 635 &qns_pcie }, 636 }; 637 638 static struct qcom_icc_node qhm_config_noc = { 639 .name = "qhm_config_noc", 640 .channels = 1, 641 .buswidth = 4, 642 .num_links = 6, 643 .link_nodes = { &qhs_lpass_core, &qhs_lpass_lpi, 644 &qhs_lpass_mpu, &qhs_lpass_top, 645 &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, 646 }; 647 648 static struct qcom_icc_node llcc_mc = { 649 .name = "llcc_mc", 650 .channels = 2, 651 .buswidth = 4, 652 .num_links = 1, 653 .link_nodes = { &ebi }, 654 }; 655 656 static struct qcom_icc_node qnm_mnoc_cfg = { 657 .name = "qnm_mnoc_cfg", 658 .channels = 1, 659 .buswidth = 4, 660 .num_links = 1, 661 .link_nodes = { &srvc_mnoc }, 662 }; 663 664 static struct qcom_icc_node qnm_video0 = { 665 .name = "qnm_video0", 666 .channels = 1, 667 .buswidth = 32, 668 .qosbox = &(const struct qcom_icc_qosbox) { 669 .num_ports = 1, 670 .port_offsets = { 0x14000 }, 671 .prio = 0, 672 .urg_fwd = 1, 673 }, 674 .num_links = 1, 675 .link_nodes = { &qns_mem_noc_sf }, 676 }; 677 678 static struct qcom_icc_node qnm_video_cpu = { 679 .name = "qnm_video_cpu", 680 .channels = 1, 681 .buswidth = 8, 682 .qosbox = &(const struct qcom_icc_qosbox) { 683 .num_ports = 1, 684 .port_offsets = { 0x15000 }, 685 .prio = 0, 686 .urg_fwd = 1, 687 }, 688 .num_links = 1, 689 .link_nodes = { &qns_mem_noc_sf }, 690 }; 691 692 static struct qcom_icc_node qxm_camnoc_hf = { 693 .name = "qxm_camnoc_hf", 694 .channels = 2, 695 .buswidth = 32, 696 .qosbox = &(const struct qcom_icc_qosbox) { 697 .num_ports = 2, 698 .port_offsets = { 0x10000, 0x10180 }, 699 .prio = 0, 700 .urg_fwd = 1, 701 }, 702 .num_links = 1, 703 .link_nodes = { &qns_mem_noc_hf }, 704 }; 705 706 static struct qcom_icc_node qxm_camnoc_icp = { 707 .name = "qxm_camnoc_icp", 708 .channels = 1, 709 .buswidth = 8, 710 .qosbox = &(const struct qcom_icc_qosbox) { 711 .num_ports = 1, 712 .port_offsets = { 0x11000 }, 713 .prio = 0, 714 .urg_fwd = 1, 715 }, 716 .num_links = 1, 717 .link_nodes = { &qns_mem_noc_sf }, 718 }; 719 720 static struct qcom_icc_node qxm_camnoc_sf = { 721 .name = "qxm_camnoc_sf", 722 .channels = 1, 723 .buswidth = 32, 724 .qosbox = &(const struct qcom_icc_qosbox) { 725 .num_ports = 1, 726 .port_offsets = { 0x12000 }, 727 .prio = 0, 728 .urg_fwd = 1, 729 }, 730 .num_links = 1, 731 .link_nodes = { &qns_mem_noc_sf }, 732 }; 733 734 static struct qcom_icc_node qxm_mdp0 = { 735 .name = "qxm_mdp0", 736 .channels = 1, 737 .buswidth = 32, 738 .qosbox = &(const struct qcom_icc_qosbox) { 739 .num_ports = 1, 740 .port_offsets = { 0x16000 }, 741 .prio = 0, 742 .urg_fwd = 1, 743 }, 744 .num_links = 1, 745 .link_nodes = { &qns_mem_noc_hf }, 746 }; 747 748 static struct qcom_icc_node qhm_nsp_noc_config = { 749 .name = "qhm_nsp_noc_config", 750 .channels = 1, 751 .buswidth = 4, 752 .num_links = 1, 753 .link_nodes = { &service_nsp_noc }, 754 }; 755 756 static struct qcom_icc_node qxm_nsp = { 757 .name = "qxm_nsp", 758 .channels = 2, 759 .buswidth = 32, 760 .num_links = 1, 761 .link_nodes = { &qns_nsp_gemnoc }, 762 }; 763 764 static struct qcom_icc_node qnm_aggre1_noc = { 765 .name = "qnm_aggre1_noc", 766 .channels = 1, 767 .buswidth = 16, 768 .num_links = 1, 769 .link_nodes = { &qns_gemnoc_sf }, 770 }; 771 772 static struct qcom_icc_node qnm_aggre2_noc = { 773 .name = "qnm_aggre2_noc", 774 .channels = 1, 775 .buswidth = 16, 776 .num_links = 1, 777 .link_nodes = { &qns_gemnoc_sf }, 778 }; 779 780 static struct qcom_icc_node qnm_snoc_cfg = { 781 .name = "qnm_snoc_cfg", 782 .channels = 1, 783 .buswidth = 4, 784 .num_links = 1, 785 .link_nodes = { &srvc_snoc }, 786 }; 787 788 static struct qcom_icc_node qxm_pimem = { 789 .name = "qxm_pimem", 790 .channels = 1, 791 .buswidth = 8, 792 .qosbox = &(const struct qcom_icc_qosbox) { 793 .num_ports = 1, 794 .port_offsets = { 0x8000 }, 795 .prio = 2, 796 .urg_fwd = 0, 797 }, 798 .num_links = 1, 799 .link_nodes = { &qns_gemnoc_gc }, 800 }; 801 802 static struct qcom_icc_node xm_gic = { 803 .name = "xm_gic", 804 .channels = 1, 805 .buswidth = 8, 806 .qosbox = &(const struct qcom_icc_qosbox) { 807 .num_ports = 1, 808 .port_offsets = { 0xa000 }, 809 .prio = 2, 810 .urg_fwd = 0, 811 }, 812 .num_links = 1, 813 .link_nodes = { &qns_gemnoc_gc }, 814 }; 815 816 static struct qcom_icc_node qns_a1noc_snoc = { 817 .name = "qns_a1noc_snoc", 818 .channels = 1, 819 .buswidth = 16, 820 .num_links = 1, 821 .link_nodes = { &qnm_aggre1_noc }, 822 }; 823 824 static struct qcom_icc_node srvc_aggre1_noc = { 825 .name = "srvc_aggre1_noc", 826 .channels = 1, 827 .buswidth = 4, 828 }; 829 830 static struct qcom_icc_node qns_a2noc_snoc = { 831 .name = "qns_a2noc_snoc", 832 .channels = 1, 833 .buswidth = 16, 834 .num_links = 1, 835 .link_nodes = { &qnm_aggre2_noc }, 836 }; 837 838 static struct qcom_icc_node qns_pcie_mem_noc = { 839 .name = "qns_pcie_mem_noc", 840 .channels = 1, 841 .buswidth = 16, 842 .num_links = 1, 843 .link_nodes = { &qnm_pcie }, 844 }; 845 846 static struct qcom_icc_node srvc_aggre2_noc = { 847 .name = "srvc_aggre2_noc", 848 .channels = 1, 849 .buswidth = 4, 850 }; 851 852 static struct qcom_icc_node qup0_core_slave = { 853 .name = "qup0_core_slave", 854 .channels = 1, 855 .buswidth = 4, 856 }; 857 858 static struct qcom_icc_node qup1_core_slave = { 859 .name = "qup1_core_slave", 860 .channels = 1, 861 .buswidth = 4, 862 }; 863 864 static struct qcom_icc_node qhs_ahb2phy0 = { 865 .name = "qhs_ahb2phy0", 866 .channels = 1, 867 .buswidth = 4, 868 }; 869 870 static struct qcom_icc_node qhs_ahb2phy1 = { 871 .name = "qhs_ahb2phy1", 872 .channels = 1, 873 .buswidth = 4, 874 }; 875 876 static struct qcom_icc_node qhs_camera_cfg = { 877 .name = "qhs_camera_cfg", 878 .channels = 1, 879 .buswidth = 4, 880 }; 881 882 static struct qcom_icc_node qhs_clk_ctl = { 883 .name = "qhs_clk_ctl", 884 .channels = 1, 885 .buswidth = 4, 886 }; 887 888 static struct qcom_icc_node qhs_compute_cfg = { 889 .name = "qhs_compute_cfg", 890 .channels = 1, 891 .buswidth = 4, 892 .num_links = 1, 893 .link_nodes = { &qhm_nsp_noc_config }, 894 }; 895 896 static struct qcom_icc_node qhs_cpr_cx = { 897 .name = "qhs_cpr_cx", 898 .channels = 1, 899 .buswidth = 4, 900 }; 901 902 static struct qcom_icc_node qhs_cpr_mx = { 903 .name = "qhs_cpr_mx", 904 .channels = 1, 905 .buswidth = 4, 906 }; 907 908 static struct qcom_icc_node qhs_crypto0_cfg = { 909 .name = "qhs_crypto0_cfg", 910 .channels = 1, 911 .buswidth = 4, 912 }; 913 914 static struct qcom_icc_node qhs_cx_rdpm = { 915 .name = "qhs_cx_rdpm", 916 .channels = 1, 917 .buswidth = 4, 918 }; 919 920 static struct qcom_icc_node qhs_dcc_cfg = { 921 .name = "qhs_dcc_cfg", 922 .channels = 1, 923 .buswidth = 4, 924 }; 925 926 static struct qcom_icc_node qhs_display_cfg = { 927 .name = "qhs_display_cfg", 928 .channels = 1, 929 .buswidth = 4, 930 }; 931 932 static struct qcom_icc_node qhs_gpuss_cfg = { 933 .name = "qhs_gpuss_cfg", 934 .channels = 1, 935 .buswidth = 8, 936 }; 937 938 static struct qcom_icc_node qhs_hwkm = { 939 .name = "qhs_hwkm", 940 .channels = 1, 941 .buswidth = 4, 942 }; 943 944 static struct qcom_icc_node qhs_imem_cfg = { 945 .name = "qhs_imem_cfg", 946 .channels = 1, 947 .buswidth = 4, 948 }; 949 950 static struct qcom_icc_node qhs_ipa = { 951 .name = "qhs_ipa", 952 .channels = 1, 953 .buswidth = 4, 954 }; 955 956 static struct qcom_icc_node qhs_ipc_router = { 957 .name = "qhs_ipc_router", 958 .channels = 1, 959 .buswidth = 4, 960 }; 961 962 static struct qcom_icc_node qhs_lpass_cfg = { 963 .name = "qhs_lpass_cfg", 964 .channels = 1, 965 .buswidth = 4, 966 .num_links = 1, 967 .link_nodes = { &qhm_config_noc }, 968 }; 969 970 static struct qcom_icc_node qhs_mss_cfg = { 971 .name = "qhs_mss_cfg", 972 .channels = 1, 973 .buswidth = 4, 974 }; 975 976 static struct qcom_icc_node qhs_mx_rdpm = { 977 .name = "qhs_mx_rdpm", 978 .channels = 1, 979 .buswidth = 4, 980 }; 981 982 static struct qcom_icc_node qhs_pcie0_cfg = { 983 .name = "qhs_pcie0_cfg", 984 .channels = 1, 985 .buswidth = 4, 986 }; 987 988 static struct qcom_icc_node qhs_pcie1_cfg = { 989 .name = "qhs_pcie1_cfg", 990 .channels = 1, 991 .buswidth = 4, 992 }; 993 994 static struct qcom_icc_node qhs_pdm = { 995 .name = "qhs_pdm", 996 .channels = 1, 997 .buswidth = 4, 998 }; 999 1000 static struct qcom_icc_node qhs_pimem_cfg = { 1001 .name = "qhs_pimem_cfg", 1002 .channels = 1, 1003 .buswidth = 4, 1004 }; 1005 1006 static struct qcom_icc_node qhs_pka_wrapper_cfg = { 1007 .name = "qhs_pka_wrapper_cfg", 1008 .channels = 1, 1009 .buswidth = 4, 1010 }; 1011 1012 static struct qcom_icc_node qhs_pmu_wrapper_cfg = { 1013 .name = "qhs_pmu_wrapper_cfg", 1014 .channels = 1, 1015 .buswidth = 4, 1016 }; 1017 1018 static struct qcom_icc_node qhs_qdss_cfg = { 1019 .name = "qhs_qdss_cfg", 1020 .channels = 1, 1021 .buswidth = 4, 1022 }; 1023 1024 static struct qcom_icc_node qhs_qspi = { 1025 .name = "qhs_qspi", 1026 .channels = 1, 1027 .buswidth = 4, 1028 }; 1029 1030 static struct qcom_icc_node qhs_qup0 = { 1031 .name = "qhs_qup0", 1032 .channels = 1, 1033 .buswidth = 4, 1034 }; 1035 1036 static struct qcom_icc_node qhs_qup1 = { 1037 .name = "qhs_qup1", 1038 .channels = 1, 1039 .buswidth = 4, 1040 }; 1041 1042 static struct qcom_icc_node qhs_sdc1 = { 1043 .name = "qhs_sdc1", 1044 .channels = 1, 1045 .buswidth = 4, 1046 }; 1047 1048 static struct qcom_icc_node qhs_sdc2 = { 1049 .name = "qhs_sdc2", 1050 .channels = 1, 1051 .buswidth = 4, 1052 }; 1053 1054 static struct qcom_icc_node qhs_sdc4 = { 1055 .name = "qhs_sdc4", 1056 .channels = 1, 1057 .buswidth = 4, 1058 }; 1059 1060 static struct qcom_icc_node qhs_security = { 1061 .name = "qhs_security", 1062 .channels = 1, 1063 .buswidth = 4, 1064 }; 1065 1066 static struct qcom_icc_node qhs_tcsr = { 1067 .name = "qhs_tcsr", 1068 .channels = 1, 1069 .buswidth = 4, 1070 }; 1071 1072 static struct qcom_icc_node qhs_tlmm = { 1073 .name = "qhs_tlmm", 1074 .channels = 1, 1075 .buswidth = 4, 1076 }; 1077 1078 static struct qcom_icc_node qhs_ufs_mem_cfg = { 1079 .name = "qhs_ufs_mem_cfg", 1080 .channels = 1, 1081 .buswidth = 4, 1082 }; 1083 1084 static struct qcom_icc_node qhs_usb2 = { 1085 .name = "qhs_usb2", 1086 .channels = 1, 1087 .buswidth = 4, 1088 }; 1089 1090 static struct qcom_icc_node qhs_usb3_0 = { 1091 .name = "qhs_usb3_0", 1092 .channels = 1, 1093 .buswidth = 4, 1094 }; 1095 1096 static struct qcom_icc_node qhs_venus_cfg = { 1097 .name = "qhs_venus_cfg", 1098 .channels = 1, 1099 .buswidth = 4, 1100 }; 1101 1102 static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 1103 .name = "qhs_vsense_ctrl_cfg", 1104 .channels = 1, 1105 .buswidth = 4, 1106 }; 1107 1108 static struct qcom_icc_node qns_a1_noc_cfg = { 1109 .name = "qns_a1_noc_cfg", 1110 .channels = 1, 1111 .buswidth = 4, 1112 .num_links = 1, 1113 .link_nodes = { &qnm_a1noc_cfg }, 1114 }; 1115 1116 static struct qcom_icc_node qns_a2_noc_cfg = { 1117 .name = "qns_a2_noc_cfg", 1118 .channels = 1, 1119 .buswidth = 4, 1120 .num_links = 1, 1121 .link_nodes = { &qnm_a2noc_cfg }, 1122 }; 1123 1124 static struct qcom_icc_node qns_cnoc2_cnoc3 = { 1125 .name = "qns_cnoc2_cnoc3", 1126 .channels = 1, 1127 .buswidth = 8, 1128 .num_links = 1, 1129 .link_nodes = { &qnm_cnoc2_cnoc3 }, 1130 }; 1131 1132 static struct qcom_icc_node qns_mnoc_cfg = { 1133 .name = "qns_mnoc_cfg", 1134 .channels = 1, 1135 .buswidth = 4, 1136 .num_links = 1, 1137 .link_nodes = { &qnm_mnoc_cfg }, 1138 }; 1139 1140 static struct qcom_icc_node qns_snoc_cfg = { 1141 .name = "qns_snoc_cfg", 1142 .channels = 1, 1143 .buswidth = 4, 1144 .num_links = 1, 1145 .link_nodes = { &qnm_snoc_cfg }, 1146 }; 1147 1148 static struct qcom_icc_node qhs_aoss = { 1149 .name = "qhs_aoss", 1150 .channels = 1, 1151 .buswidth = 4, 1152 }; 1153 1154 static struct qcom_icc_node qhs_apss = { 1155 .name = "qhs_apss", 1156 .channels = 1, 1157 .buswidth = 8, 1158 }; 1159 1160 static struct qcom_icc_node qns_cnoc3_cnoc2 = { 1161 .name = "qns_cnoc3_cnoc2", 1162 .channels = 1, 1163 .buswidth = 8, 1164 .num_links = 1, 1165 .link_nodes = { &qnm_cnoc3_cnoc2 }, 1166 }; 1167 1168 static struct qcom_icc_node qns_cnoc_a2noc = { 1169 .name = "qns_cnoc_a2noc", 1170 .channels = 1, 1171 .buswidth = 8, 1172 .num_links = 1, 1173 .link_nodes = { &qnm_cnoc_datapath }, 1174 }; 1175 1176 static struct qcom_icc_node qns_ddrss_cfg = { 1177 .name = "qns_ddrss_cfg", 1178 .channels = 1, 1179 .buswidth = 4, 1180 .num_links = 1, 1181 .link_nodes = { &qnm_cnoc_dc_noc }, 1182 }; 1183 1184 static struct qcom_icc_node qxs_boot_imem = { 1185 .name = "qxs_boot_imem", 1186 .channels = 1, 1187 .buswidth = 8, 1188 }; 1189 1190 static struct qcom_icc_node qxs_imem = { 1191 .name = "qxs_imem", 1192 .channels = 1, 1193 .buswidth = 8, 1194 }; 1195 1196 static struct qcom_icc_node qxs_pimem = { 1197 .name = "qxs_pimem", 1198 .channels = 1, 1199 .buswidth = 8, 1200 }; 1201 1202 static struct qcom_icc_node xs_pcie_0 = { 1203 .name = "xs_pcie_0", 1204 .channels = 1, 1205 .buswidth = 8, 1206 }; 1207 1208 static struct qcom_icc_node xs_pcie_1 = { 1209 .name = "xs_pcie_1", 1210 .channels = 1, 1211 .buswidth = 8, 1212 }; 1213 1214 static struct qcom_icc_node xs_qdss_stm = { 1215 .name = "xs_qdss_stm", 1216 .channels = 1, 1217 .buswidth = 4, 1218 }; 1219 1220 static struct qcom_icc_node xs_sys_tcu_cfg = { 1221 .name = "xs_sys_tcu_cfg", 1222 .channels = 1, 1223 .buswidth = 8, 1224 }; 1225 1226 static struct qcom_icc_node qhs_llcc = { 1227 .name = "qhs_llcc", 1228 .channels = 1, 1229 .buswidth = 4, 1230 }; 1231 1232 static struct qcom_icc_node qns_gemnoc = { 1233 .name = "qns_gemnoc", 1234 .channels = 1, 1235 .buswidth = 4, 1236 .num_links = 1, 1237 .link_nodes = { &qnm_gemnoc_cfg }, 1238 }; 1239 1240 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { 1241 .name = "qhs_mdsp_ms_mpu_cfg", 1242 .channels = 1, 1243 .buswidth = 4, 1244 }; 1245 1246 static struct qcom_icc_node qhs_modem_ms_mpu_cfg = { 1247 .name = "qhs_modem_ms_mpu_cfg", 1248 .channels = 1, 1249 .buswidth = 4, 1250 }; 1251 1252 static struct qcom_icc_node qns_gem_noc_cnoc = { 1253 .name = "qns_gem_noc_cnoc", 1254 .channels = 1, 1255 .buswidth = 16, 1256 .num_links = 1, 1257 .link_nodes = { &qnm_gemnoc_cnoc }, 1258 }; 1259 1260 static struct qcom_icc_node qns_llcc = { 1261 .name = "qns_llcc", 1262 .channels = 2, 1263 .buswidth = 16, 1264 .num_links = 1, 1265 .link_nodes = { &llcc_mc }, 1266 }; 1267 1268 static struct qcom_icc_node qns_pcie = { 1269 .name = "qns_pcie", 1270 .channels = 1, 1271 .buswidth = 8, 1272 .num_links = 1, 1273 .link_nodes = { &qnm_gemnoc_pcie }, 1274 }; 1275 1276 static struct qcom_icc_node srvc_even_gemnoc = { 1277 .name = "srvc_even_gemnoc", 1278 .channels = 1, 1279 .buswidth = 4, 1280 }; 1281 1282 static struct qcom_icc_node srvc_odd_gemnoc = { 1283 .name = "srvc_odd_gemnoc", 1284 .channels = 1, 1285 .buswidth = 4, 1286 }; 1287 1288 static struct qcom_icc_node srvc_sys_gemnoc = { 1289 .name = "srvc_sys_gemnoc", 1290 .channels = 1, 1291 .buswidth = 4, 1292 }; 1293 1294 static struct qcom_icc_node qhs_lpass_core = { 1295 .name = "qhs_lpass_core", 1296 .channels = 1, 1297 .buswidth = 4, 1298 }; 1299 1300 static struct qcom_icc_node qhs_lpass_lpi = { 1301 .name = "qhs_lpass_lpi", 1302 .channels = 1, 1303 .buswidth = 4, 1304 }; 1305 1306 static struct qcom_icc_node qhs_lpass_mpu = { 1307 .name = "qhs_lpass_mpu", 1308 .channels = 1, 1309 .buswidth = 4, 1310 }; 1311 1312 static struct qcom_icc_node qhs_lpass_top = { 1313 .name = "qhs_lpass_top", 1314 .channels = 1, 1315 .buswidth = 4, 1316 }; 1317 1318 static struct qcom_icc_node srvc_niu_aml_noc = { 1319 .name = "srvc_niu_aml_noc", 1320 .channels = 1, 1321 .buswidth = 4, 1322 }; 1323 1324 static struct qcom_icc_node srvc_niu_lpass_agnoc = { 1325 .name = "srvc_niu_lpass_agnoc", 1326 .channels = 1, 1327 .buswidth = 4, 1328 }; 1329 1330 static struct qcom_icc_node ebi = { 1331 .name = "ebi", 1332 .channels = 2, 1333 .buswidth = 4, 1334 }; 1335 1336 static struct qcom_icc_node qns_mem_noc_hf = { 1337 .name = "qns_mem_noc_hf", 1338 .channels = 2, 1339 .buswidth = 32, 1340 .num_links = 1, 1341 .link_nodes = { &qnm_mnoc_hf }, 1342 }; 1343 1344 static struct qcom_icc_node qns_mem_noc_sf = { 1345 .name = "qns_mem_noc_sf", 1346 .channels = 1, 1347 .buswidth = 32, 1348 .num_links = 1, 1349 .link_nodes = { &qnm_mnoc_sf }, 1350 }; 1351 1352 static struct qcom_icc_node srvc_mnoc = { 1353 .name = "srvc_mnoc", 1354 .channels = 1, 1355 .buswidth = 4, 1356 }; 1357 1358 static struct qcom_icc_node qns_nsp_gemnoc = { 1359 .name = "qns_nsp_gemnoc", 1360 .channels = 2, 1361 .buswidth = 32, 1362 .num_links = 1, 1363 .link_nodes = { &qnm_cmpnoc }, 1364 }; 1365 1366 static struct qcom_icc_node service_nsp_noc = { 1367 .name = "service_nsp_noc", 1368 .channels = 1, 1369 .buswidth = 4, 1370 }; 1371 1372 static struct qcom_icc_node qns_gemnoc_gc = { 1373 .name = "qns_gemnoc_gc", 1374 .channels = 1, 1375 .buswidth = 8, 1376 .num_links = 1, 1377 .link_nodes = { &qnm_snoc_gc }, 1378 }; 1379 1380 static struct qcom_icc_node qns_gemnoc_sf = { 1381 .name = "qns_gemnoc_sf", 1382 .channels = 1, 1383 .buswidth = 16, 1384 .num_links = 1, 1385 .link_nodes = { &qnm_snoc_sf }, 1386 }; 1387 1388 static struct qcom_icc_node srvc_snoc = { 1389 .name = "srvc_snoc", 1390 .channels = 1, 1391 .buswidth = 4, 1392 }; 1393 1394 static struct qcom_icc_bcm bcm_acv = { 1395 .name = "ACV", 1396 .enable_mask = BIT(3), 1397 .num_nodes = 1, 1398 .nodes = { &ebi }, 1399 }; 1400 1401 static struct qcom_icc_bcm bcm_ce0 = { 1402 .name = "CE0", 1403 .num_nodes = 1, 1404 .nodes = { &qxm_crypto }, 1405 }; 1406 1407 static struct qcom_icc_bcm bcm_cn0 = { 1408 .name = "CN0", 1409 .keepalive = true, 1410 .num_nodes = 2, 1411 .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie }, 1412 }; 1413 1414 static struct qcom_icc_bcm bcm_cn1 = { 1415 .name = "CN1", 1416 .num_nodes = 47, 1417 .nodes = { &qnm_cnoc3_cnoc2, &xm_qdss_dap, 1418 &qhs_ahb2phy0, &qhs_ahb2phy1, 1419 &qhs_camera_cfg, &qhs_clk_ctl, 1420 &qhs_compute_cfg, &qhs_cpr_cx, 1421 &qhs_cpr_mx, &qhs_crypto0_cfg, 1422 &qhs_cx_rdpm, &qhs_dcc_cfg, 1423 &qhs_display_cfg, &qhs_gpuss_cfg, 1424 &qhs_hwkm, &qhs_imem_cfg, 1425 &qhs_ipa, &qhs_ipc_router, 1426 &qhs_mss_cfg, &qhs_mx_rdpm, 1427 &qhs_pcie0_cfg, &qhs_pcie1_cfg, 1428 &qhs_pimem_cfg, &qhs_pka_wrapper_cfg, 1429 &qhs_pmu_wrapper_cfg, &qhs_qdss_cfg, 1430 &qhs_qup0, &qhs_qup1, 1431 &qhs_security, &qhs_tcsr, 1432 &qhs_tlmm, &qhs_ufs_mem_cfg, &qhs_usb2, 1433 &qhs_usb3_0, &qhs_venus_cfg, 1434 &qhs_vsense_ctrl_cfg, &qns_a1_noc_cfg, 1435 &qns_a2_noc_cfg, &qns_cnoc2_cnoc3, 1436 &qns_mnoc_cfg, &qns_snoc_cfg, 1437 &qnm_cnoc2_cnoc3, &qhs_aoss, 1438 &qhs_apss, &qns_cnoc3_cnoc2, 1439 &qns_cnoc_a2noc, &qns_ddrss_cfg }, 1440 }; 1441 1442 static struct qcom_icc_bcm bcm_cn2 = { 1443 .name = "CN2", 1444 .num_nodes = 6, 1445 .nodes = { &qhs_lpass_cfg, &qhs_pdm, 1446 &qhs_qspi, &qhs_sdc1, 1447 &qhs_sdc2, &qhs_sdc4 }, 1448 }; 1449 1450 static struct qcom_icc_bcm bcm_co0 = { 1451 .name = "CO0", 1452 .num_nodes = 1, 1453 .nodes = { &qns_nsp_gemnoc }, 1454 }; 1455 1456 static struct qcom_icc_bcm bcm_co3 = { 1457 .name = "CO3", 1458 .num_nodes = 1, 1459 .nodes = { &qxm_nsp }, 1460 }; 1461 1462 static struct qcom_icc_bcm bcm_mc0 = { 1463 .name = "MC0", 1464 .keepalive = true, 1465 .num_nodes = 1, 1466 .nodes = { &ebi }, 1467 }; 1468 1469 static struct qcom_icc_bcm bcm_mm0 = { 1470 .name = "MM0", 1471 .keepalive = true, 1472 .num_nodes = 1, 1473 .nodes = { &qns_mem_noc_hf }, 1474 }; 1475 1476 static struct qcom_icc_bcm bcm_mm1 = { 1477 .name = "MM1", 1478 .num_nodes = 2, 1479 .nodes = { &qxm_camnoc_hf, &qxm_mdp0 }, 1480 }; 1481 1482 static struct qcom_icc_bcm bcm_mm4 = { 1483 .name = "MM4", 1484 .num_nodes = 1, 1485 .nodes = { &qns_mem_noc_sf }, 1486 }; 1487 1488 static struct qcom_icc_bcm bcm_mm5 = { 1489 .name = "MM5", 1490 .num_nodes = 3, 1491 .nodes = { &qnm_video0, &qxm_camnoc_icp, 1492 &qxm_camnoc_sf }, 1493 }; 1494 1495 static struct qcom_icc_bcm bcm_qup0 = { 1496 .name = "QUP0", 1497 .vote_scale = 1, 1498 .num_nodes = 1, 1499 .nodes = { &qup0_core_slave }, 1500 }; 1501 1502 static struct qcom_icc_bcm bcm_qup1 = { 1503 .name = "QUP1", 1504 .vote_scale = 1, 1505 .num_nodes = 1, 1506 .nodes = { &qup1_core_slave }, 1507 }; 1508 1509 static struct qcom_icc_bcm bcm_sh0 = { 1510 .name = "SH0", 1511 .keepalive = true, 1512 .num_nodes = 1, 1513 .nodes = { &qns_llcc }, 1514 }; 1515 1516 static struct qcom_icc_bcm bcm_sh2 = { 1517 .name = "SH2", 1518 .num_nodes = 2, 1519 .nodes = { &alm_gpu_tcu, &alm_sys_tcu }, 1520 }; 1521 1522 static struct qcom_icc_bcm bcm_sh3 = { 1523 .name = "SH3", 1524 .num_nodes = 1, 1525 .nodes = { &qnm_cmpnoc }, 1526 }; 1527 1528 static struct qcom_icc_bcm bcm_sh4 = { 1529 .name = "SH4", 1530 .num_nodes = 1, 1531 .nodes = { &chm_apps }, 1532 }; 1533 1534 static struct qcom_icc_bcm bcm_sn0 = { 1535 .name = "SN0", 1536 .keepalive = true, 1537 .num_nodes = 1, 1538 .nodes = { &qns_gemnoc_sf }, 1539 }; 1540 1541 static struct qcom_icc_bcm bcm_sn2 = { 1542 .name = "SN2", 1543 .num_nodes = 1, 1544 .nodes = { &qns_gemnoc_gc }, 1545 }; 1546 1547 static struct qcom_icc_bcm bcm_sn3 = { 1548 .name = "SN3", 1549 .num_nodes = 1, 1550 .nodes = { &qxs_pimem }, 1551 }; 1552 1553 static struct qcom_icc_bcm bcm_sn4 = { 1554 .name = "SN4", 1555 .num_nodes = 1, 1556 .nodes = { &xs_qdss_stm }, 1557 }; 1558 1559 static struct qcom_icc_bcm bcm_sn5 = { 1560 .name = "SN5", 1561 .num_nodes = 1, 1562 .nodes = { &xm_pcie3_0 }, 1563 }; 1564 1565 static struct qcom_icc_bcm bcm_sn6 = { 1566 .name = "SN6", 1567 .num_nodes = 1, 1568 .nodes = { &xm_pcie3_1 }, 1569 }; 1570 1571 static struct qcom_icc_bcm bcm_sn7 = { 1572 .name = "SN7", 1573 .num_nodes = 1, 1574 .nodes = { &qnm_aggre1_noc }, 1575 }; 1576 1577 static struct qcom_icc_bcm bcm_sn8 = { 1578 .name = "SN8", 1579 .num_nodes = 1, 1580 .nodes = { &qnm_aggre2_noc }, 1581 }; 1582 1583 static struct qcom_icc_bcm bcm_sn14 = { 1584 .name = "SN14", 1585 .num_nodes = 1, 1586 .nodes = { &qns_pcie_mem_noc }, 1587 }; 1588 1589 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 1590 &bcm_sn5, 1591 &bcm_sn6, 1592 &bcm_sn14, 1593 }; 1594 1595 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1596 [MASTER_QSPI_0] = &qhm_qspi, 1597 [MASTER_QUP_0] = &qhm_qup0, 1598 [MASTER_QUP_1] = &qhm_qup1, 1599 [MASTER_A1NOC_CFG] = &qnm_a1noc_cfg, 1600 [MASTER_PCIE_0] = &xm_pcie3_0, 1601 [MASTER_PCIE_1] = &xm_pcie3_1, 1602 [MASTER_SDCC_1] = &xm_sdc1, 1603 [MASTER_SDCC_2] = &xm_sdc2, 1604 [MASTER_SDCC_4] = &xm_sdc4, 1605 [MASTER_UFS_MEM] = &xm_ufs_mem, 1606 [MASTER_USB2] = &xm_usb2, 1607 [MASTER_USB3_0] = &xm_usb3_0, 1608 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, 1609 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, 1610 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, 1611 }; 1612 1613 static const struct regmap_config sc7280_aggre1_noc_regmap_config = { 1614 .reg_bits = 32, 1615 .reg_stride = 4, 1616 .val_bits = 32, 1617 .max_register = 0x1c080, 1618 .fast_io = true, 1619 }; 1620 1621 static const struct qcom_icc_desc sc7280_aggre1_noc = { 1622 .config = &sc7280_aggre1_noc_regmap_config, 1623 .nodes = aggre1_noc_nodes, 1624 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 1625 .bcms = aggre1_noc_bcms, 1626 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 1627 .qos_requires_clocks = true, 1628 }; 1629 1630 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 1631 &bcm_ce0, 1632 }; 1633 1634 static const struct regmap_config sc7280_aggre2_noc_regmap_config = { 1635 .reg_bits = 32, 1636 .reg_stride = 4, 1637 .val_bits = 32, 1638 .max_register = 0x2b080, 1639 .fast_io = true, 1640 }; 1641 1642 static struct qcom_icc_node * const aggre2_noc_nodes[] = { 1643 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 1644 [MASTER_A2NOC_CFG] = &qnm_a2noc_cfg, 1645 [MASTER_CNOC_A2NOC] = &qnm_cnoc_datapath, 1646 [MASTER_CRYPTO] = &qxm_crypto, 1647 [MASTER_IPA] = &qxm_ipa, 1648 [MASTER_QDSS_ETR] = &xm_qdss_etr, 1649 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, 1650 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, 1651 }; 1652 1653 static const struct qcom_icc_desc sc7280_aggre2_noc = { 1654 .config = &sc7280_aggre2_noc_regmap_config, 1655 .nodes = aggre2_noc_nodes, 1656 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 1657 .bcms = aggre2_noc_bcms, 1658 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 1659 .qos_requires_clocks = true, 1660 }; 1661 1662 static struct qcom_icc_bcm * const clk_virt_bcms[] = { 1663 &bcm_qup0, 1664 &bcm_qup1, 1665 }; 1666 1667 static struct qcom_icc_node * const clk_virt_nodes[] = { 1668 [MASTER_QUP_CORE_0] = &qup0_core_master, 1669 [MASTER_QUP_CORE_1] = &qup1_core_master, 1670 [SLAVE_QUP_CORE_0] = &qup0_core_slave, 1671 [SLAVE_QUP_CORE_1] = &qup1_core_slave, 1672 }; 1673 1674 static const struct qcom_icc_desc sc7280_clk_virt = { 1675 .nodes = clk_virt_nodes, 1676 .num_nodes = ARRAY_SIZE(clk_virt_nodes), 1677 .bcms = clk_virt_bcms, 1678 .num_bcms = ARRAY_SIZE(clk_virt_bcms), 1679 }; 1680 1681 static struct qcom_icc_bcm * const cnoc2_bcms[] = { 1682 &bcm_cn1, 1683 &bcm_cn2, 1684 }; 1685 1686 static struct qcom_icc_node * const cnoc2_nodes[] = { 1687 [MASTER_CNOC3_CNOC2] = &qnm_cnoc3_cnoc2, 1688 [MASTER_QDSS_DAP] = &xm_qdss_dap, 1689 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, 1690 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1, 1691 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 1692 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1693 [SLAVE_CDSP_CFG] = &qhs_compute_cfg, 1694 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 1695 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, 1696 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1697 [SLAVE_CX_RDPM] = &qhs_cx_rdpm, 1698 [SLAVE_DCC_CFG] = &qhs_dcc_cfg, 1699 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 1700 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, 1701 [SLAVE_HWKM] = &qhs_hwkm, 1702 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1703 [SLAVE_IPA_CFG] = &qhs_ipa, 1704 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, 1705 [SLAVE_LPASS] = &qhs_lpass_cfg, 1706 [SLAVE_CNOC_MSS] = &qhs_mss_cfg, 1707 [SLAVE_MX_RDPM] = &qhs_mx_rdpm, 1708 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, 1709 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, 1710 [SLAVE_PDM] = &qhs_pdm, 1711 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 1712 [SLAVE_PKA_WRAPPER_CFG] = &qhs_pka_wrapper_cfg, 1713 [SLAVE_PMU_WRAPPER_CFG] = &qhs_pmu_wrapper_cfg, 1714 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1715 [SLAVE_QSPI_0] = &qhs_qspi, 1716 [SLAVE_QUP_0] = &qhs_qup0, 1717 [SLAVE_QUP_1] = &qhs_qup1, 1718 [SLAVE_SDCC_1] = &qhs_sdc1, 1719 [SLAVE_SDCC_2] = &qhs_sdc2, 1720 [SLAVE_SDCC_4] = &qhs_sdc4, 1721 [SLAVE_SECURITY] = &qhs_security, 1722 [SLAVE_TCSR] = &qhs_tcsr, 1723 [SLAVE_TLMM] = &qhs_tlmm, 1724 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 1725 [SLAVE_USB2] = &qhs_usb2, 1726 [SLAVE_USB3_0] = &qhs_usb3_0, 1727 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1728 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 1729 [SLAVE_A1NOC_CFG] = &qns_a1_noc_cfg, 1730 [SLAVE_A2NOC_CFG] = &qns_a2_noc_cfg, 1731 [SLAVE_CNOC2_CNOC3] = &qns_cnoc2_cnoc3, 1732 [SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg, 1733 [SLAVE_SNOC_CFG] = &qns_snoc_cfg, 1734 }; 1735 1736 static const struct regmap_config sc7280_cnoc2_regmap_config = { 1737 .reg_bits = 32, 1738 .reg_stride = 4, 1739 .val_bits = 32, 1740 .max_register = 0x1000, 1741 .fast_io = true, 1742 }; 1743 1744 static const struct qcom_icc_desc sc7280_cnoc2 = { 1745 .config = &sc7280_cnoc2_regmap_config, 1746 .nodes = cnoc2_nodes, 1747 .num_nodes = ARRAY_SIZE(cnoc2_nodes), 1748 .bcms = cnoc2_bcms, 1749 .num_bcms = ARRAY_SIZE(cnoc2_bcms), 1750 }; 1751 1752 static struct qcom_icc_bcm * const cnoc3_bcms[] = { 1753 &bcm_cn0, 1754 &bcm_cn1, 1755 &bcm_sn3, 1756 &bcm_sn4, 1757 }; 1758 1759 static struct qcom_icc_node * const cnoc3_nodes[] = { 1760 [MASTER_CNOC2_CNOC3] = &qnm_cnoc2_cnoc3, 1761 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, 1762 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, 1763 [SLAVE_AOSS] = &qhs_aoss, 1764 [SLAVE_APPSS] = &qhs_apss, 1765 [SLAVE_CNOC3_CNOC2] = &qns_cnoc3_cnoc2, 1766 [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc, 1767 [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg, 1768 [SLAVE_BOOT_IMEM] = &qxs_boot_imem, 1769 [SLAVE_IMEM] = &qxs_imem, 1770 [SLAVE_PIMEM] = &qxs_pimem, 1771 [SLAVE_PCIE_0] = &xs_pcie_0, 1772 [SLAVE_PCIE_1] = &xs_pcie_1, 1773 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1774 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1775 }; 1776 1777 static const struct regmap_config sc7280_cnoc3_regmap_config = { 1778 .reg_bits = 32, 1779 .reg_stride = 4, 1780 .val_bits = 32, 1781 .max_register = 0x1000, 1782 .fast_io = true, 1783 }; 1784 1785 static const struct qcom_icc_desc sc7280_cnoc3 = { 1786 .config = &sc7280_cnoc3_regmap_config, 1787 .nodes = cnoc3_nodes, 1788 .num_nodes = ARRAY_SIZE(cnoc3_nodes), 1789 .bcms = cnoc3_bcms, 1790 .num_bcms = ARRAY_SIZE(cnoc3_bcms), 1791 }; 1792 1793 static struct qcom_icc_bcm * const dc_noc_bcms[] = { 1794 }; 1795 1796 static struct qcom_icc_node * const dc_noc_nodes[] = { 1797 [MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc, 1798 [SLAVE_LLCC_CFG] = &qhs_llcc, 1799 [SLAVE_GEM_NOC_CFG] = &qns_gemnoc, 1800 }; 1801 1802 static const struct regmap_config sc7280_dc_noc_regmap_config = { 1803 .reg_bits = 32, 1804 .reg_stride = 4, 1805 .val_bits = 32, 1806 .max_register = 0x5080, 1807 .fast_io = true, 1808 }; 1809 1810 static const struct qcom_icc_desc sc7280_dc_noc = { 1811 .config = &sc7280_dc_noc_regmap_config, 1812 .nodes = dc_noc_nodes, 1813 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 1814 .bcms = dc_noc_bcms, 1815 .num_bcms = ARRAY_SIZE(dc_noc_bcms), 1816 }; 1817 1818 static struct qcom_icc_bcm * const gem_noc_bcms[] = { 1819 &bcm_sh0, 1820 &bcm_sh2, 1821 &bcm_sh3, 1822 &bcm_sh4, 1823 }; 1824 1825 static struct qcom_icc_node * const gem_noc_nodes[] = { 1826 [MASTER_GPU_TCU] = &alm_gpu_tcu, 1827 [MASTER_SYS_TCU] = &alm_sys_tcu, 1828 [MASTER_APPSS_PROC] = &chm_apps, 1829 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc, 1830 [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg, 1831 [MASTER_GFX3D] = &qnm_gpu, 1832 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 1833 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 1834 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, 1835 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 1836 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 1837 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg, 1838 [SLAVE_MCDMA_MS_MPU_CFG] = &qhs_modem_ms_mpu_cfg, 1839 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, 1840 [SLAVE_LLCC] = &qns_llcc, 1841 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, 1842 [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc, 1843 [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc, 1844 [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc, 1845 }; 1846 1847 static const struct regmap_config sc7280_gem_noc_regmap_config = { 1848 .reg_bits = 32, 1849 .reg_stride = 4, 1850 .val_bits = 32, 1851 .max_register = 0xe2200, 1852 .fast_io = true, 1853 }; 1854 1855 static const struct qcom_icc_desc sc7280_gem_noc = { 1856 .config = &sc7280_gem_noc_regmap_config, 1857 .nodes = gem_noc_nodes, 1858 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 1859 .bcms = gem_noc_bcms, 1860 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 1861 }; 1862 1863 static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = { 1864 }; 1865 1866 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { 1867 [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc, 1868 [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core, 1869 [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi, 1870 [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu, 1871 [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top, 1872 [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc, 1873 [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, 1874 }; 1875 1876 static const struct regmap_config sc7280_lpass_ag_noc_regmap_config = { 1877 .reg_bits = 32, 1878 .reg_stride = 4, 1879 .val_bits = 32, 1880 .max_register = 0xf080, 1881 .fast_io = true, 1882 }; 1883 1884 static const struct qcom_icc_desc sc7280_lpass_ag_noc = { 1885 .config = &sc7280_lpass_ag_noc_regmap_config, 1886 .nodes = lpass_ag_noc_nodes, 1887 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), 1888 .bcms = lpass_ag_noc_bcms, 1889 .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms), 1890 }; 1891 1892 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 1893 &bcm_acv, 1894 &bcm_mc0, 1895 }; 1896 1897 static struct qcom_icc_node * const mc_virt_nodes[] = { 1898 [MASTER_LLCC] = &llcc_mc, 1899 [SLAVE_EBI1] = &ebi, 1900 }; 1901 1902 static const struct regmap_config sc7280_mc_virt_regmap_config = { 1903 .reg_bits = 32, 1904 .reg_stride = 4, 1905 .val_bits = 32, 1906 .max_register = 0x4, 1907 .fast_io = true, 1908 }; 1909 1910 static const struct qcom_icc_desc sc7280_mc_virt = { 1911 .config = &sc7280_mc_virt_regmap_config, 1912 .nodes = mc_virt_nodes, 1913 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 1914 .bcms = mc_virt_bcms, 1915 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 1916 }; 1917 1918 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 1919 &bcm_mm0, 1920 &bcm_mm1, 1921 &bcm_mm4, 1922 &bcm_mm5, 1923 }; 1924 1925 static struct qcom_icc_node * const mmss_noc_nodes[] = { 1926 [MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg, 1927 [MASTER_VIDEO_P0] = &qnm_video0, 1928 [MASTER_VIDEO_PROC] = &qnm_video_cpu, 1929 [MASTER_CAMNOC_HF] = &qxm_camnoc_hf, 1930 [MASTER_CAMNOC_ICP] = &qxm_camnoc_icp, 1931 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf, 1932 [MASTER_MDP0] = &qxm_mdp0, 1933 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 1934 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, 1935 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 1936 }; 1937 1938 static const struct regmap_config sc7280_mmss_noc_regmap_config = { 1939 .reg_bits = 32, 1940 .reg_stride = 4, 1941 .val_bits = 32, 1942 .max_register = 0x1e080, 1943 .fast_io = true, 1944 }; 1945 1946 static const struct qcom_icc_desc sc7280_mmss_noc = { 1947 .config = &sc7280_mmss_noc_regmap_config, 1948 .nodes = mmss_noc_nodes, 1949 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 1950 .bcms = mmss_noc_bcms, 1951 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 1952 }; 1953 1954 static struct qcom_icc_bcm * const nsp_noc_bcms[] = { 1955 &bcm_co0, 1956 &bcm_co3, 1957 }; 1958 1959 static struct qcom_icc_node * const nsp_noc_nodes[] = { 1960 [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config, 1961 [MASTER_CDSP_PROC] = &qxm_nsp, 1962 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, 1963 [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, 1964 }; 1965 1966 static const struct regmap_config sc7280_nsp_noc_regmap_config = { 1967 .reg_bits = 32, 1968 .reg_stride = 4, 1969 .val_bits = 32, 1970 .max_register = 0x10000, 1971 .fast_io = true, 1972 }; 1973 1974 static const struct qcom_icc_desc sc7280_nsp_noc = { 1975 .config = &sc7280_nsp_noc_regmap_config, 1976 .nodes = nsp_noc_nodes, 1977 .num_nodes = ARRAY_SIZE(nsp_noc_nodes), 1978 .bcms = nsp_noc_bcms, 1979 .num_bcms = ARRAY_SIZE(nsp_noc_bcms), 1980 }; 1981 1982 static struct qcom_icc_bcm * const system_noc_bcms[] = { 1983 &bcm_sn0, 1984 &bcm_sn2, 1985 &bcm_sn7, 1986 &bcm_sn8, 1987 }; 1988 1989 static struct qcom_icc_node * const system_noc_nodes[] = { 1990 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, 1991 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, 1992 [MASTER_SNOC_CFG] = &qnm_snoc_cfg, 1993 [MASTER_PIMEM] = &qxm_pimem, 1994 [MASTER_GIC] = &xm_gic, 1995 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, 1996 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 1997 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 1998 }; 1999 2000 static const struct regmap_config sc7280_system_noc_regmap_config = { 2001 .reg_bits = 32, 2002 .reg_stride = 4, 2003 .val_bits = 32, 2004 .max_register = 0x15480, 2005 .fast_io = true, 2006 }; 2007 2008 static const struct qcom_icc_desc sc7280_system_noc = { 2009 .config = &sc7280_system_noc_regmap_config, 2010 .nodes = system_noc_nodes, 2011 .num_nodes = ARRAY_SIZE(system_noc_nodes), 2012 .bcms = system_noc_bcms, 2013 .num_bcms = ARRAY_SIZE(system_noc_bcms), 2014 }; 2015 2016 static const struct of_device_id qnoc_of_match[] = { 2017 { .compatible = "qcom,sc7280-aggre1-noc", 2018 .data = &sc7280_aggre1_noc}, 2019 { .compatible = "qcom,sc7280-aggre2-noc", 2020 .data = &sc7280_aggre2_noc}, 2021 { .compatible = "qcom,sc7280-clk-virt", 2022 .data = &sc7280_clk_virt}, 2023 { .compatible = "qcom,sc7280-cnoc2", 2024 .data = &sc7280_cnoc2}, 2025 { .compatible = "qcom,sc7280-cnoc3", 2026 .data = &sc7280_cnoc3}, 2027 { .compatible = "qcom,sc7280-dc-noc", 2028 .data = &sc7280_dc_noc}, 2029 { .compatible = "qcom,sc7280-gem-noc", 2030 .data = &sc7280_gem_noc}, 2031 { .compatible = "qcom,sc7280-lpass-ag-noc", 2032 .data = &sc7280_lpass_ag_noc}, 2033 { .compatible = "qcom,sc7280-mc-virt", 2034 .data = &sc7280_mc_virt}, 2035 { .compatible = "qcom,sc7280-mmss-noc", 2036 .data = &sc7280_mmss_noc}, 2037 { .compatible = "qcom,sc7280-nsp-noc", 2038 .data = &sc7280_nsp_noc}, 2039 { .compatible = "qcom,sc7280-system-noc", 2040 .data = &sc7280_system_noc}, 2041 { } 2042 }; 2043 MODULE_DEVICE_TABLE(of, qnoc_of_match); 2044 2045 static struct platform_driver qnoc_driver = { 2046 .probe = qcom_icc_rpmh_probe, 2047 .remove = qcom_icc_rpmh_remove, 2048 .driver = { 2049 .name = "qnoc-sc7280", 2050 .of_match_table = qnoc_of_match, 2051 .sync_state = icc_sync_state, 2052 }, 2053 }; 2054 module_platform_driver(qnoc_driver); 2055 2056 MODULE_DESCRIPTION("SC7280 NoC driver"); 2057 MODULE_LICENSE("GPL v2"); 2058