1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * 5 */ 6 7 #include <linux/device.h> 8 #include <linux/interconnect.h> 9 #include <linux/interconnect-provider.h> 10 #include <linux/module.h> 11 #include <linux/of_platform.h> 12 #include <dt-bindings/interconnect/qcom,sc7280.h> 13 14 #include "bcm-voter.h" 15 #include "icc-rpmh.h" 16 #include "sc7280.h" 17 18 static struct qcom_icc_node qhm_qspi = { 19 .name = "qhm_qspi", 20 .id = SC7280_MASTER_QSPI_0, 21 .channels = 1, 22 .buswidth = 4, 23 .num_links = 1, 24 .links = { SC7280_SLAVE_A1NOC_SNOC }, 25 }; 26 27 static struct qcom_icc_node qhm_qup0 = { 28 .name = "qhm_qup0", 29 .id = SC7280_MASTER_QUP_0, 30 .channels = 1, 31 .buswidth = 4, 32 .num_links = 1, 33 .links = { SC7280_SLAVE_A1NOC_SNOC }, 34 }; 35 36 static struct qcom_icc_node qhm_qup1 = { 37 .name = "qhm_qup1", 38 .id = SC7280_MASTER_QUP_1, 39 .channels = 1, 40 .buswidth = 4, 41 .num_links = 1, 42 .links = { SC7280_SLAVE_A1NOC_SNOC }, 43 }; 44 45 static struct qcom_icc_node qnm_a1noc_cfg = { 46 .name = "qnm_a1noc_cfg", 47 .id = SC7280_MASTER_A1NOC_CFG, 48 .channels = 1, 49 .buswidth = 4, 50 .num_links = 1, 51 .links = { SC7280_SLAVE_SERVICE_A1NOC }, 52 }; 53 54 static struct qcom_icc_node xm_sdc1 = { 55 .name = "xm_sdc1", 56 .id = SC7280_MASTER_SDCC_1, 57 .channels = 1, 58 .buswidth = 8, 59 .num_links = 1, 60 .links = { SC7280_SLAVE_A1NOC_SNOC }, 61 }; 62 63 static struct qcom_icc_node xm_sdc2 = { 64 .name = "xm_sdc2", 65 .id = SC7280_MASTER_SDCC_2, 66 .channels = 1, 67 .buswidth = 8, 68 .num_links = 1, 69 .links = { SC7280_SLAVE_A1NOC_SNOC }, 70 }; 71 72 static struct qcom_icc_node xm_sdc4 = { 73 .name = "xm_sdc4", 74 .id = SC7280_MASTER_SDCC_4, 75 .channels = 1, 76 .buswidth = 8, 77 .num_links = 1, 78 .links = { SC7280_SLAVE_A1NOC_SNOC }, 79 }; 80 81 static struct qcom_icc_node xm_ufs_mem = { 82 .name = "xm_ufs_mem", 83 .id = SC7280_MASTER_UFS_MEM, 84 .channels = 1, 85 .buswidth = 8, 86 .num_links = 1, 87 .links = { SC7280_SLAVE_A1NOC_SNOC }, 88 }; 89 90 static struct qcom_icc_node xm_usb2 = { 91 .name = "xm_usb2", 92 .id = SC7280_MASTER_USB2, 93 .channels = 1, 94 .buswidth = 8, 95 .num_links = 1, 96 .links = { SC7280_SLAVE_A1NOC_SNOC }, 97 }; 98 99 static struct qcom_icc_node xm_usb3_0 = { 100 .name = "xm_usb3_0", 101 .id = SC7280_MASTER_USB3_0, 102 .channels = 1, 103 .buswidth = 8, 104 .num_links = 1, 105 .links = { SC7280_SLAVE_A1NOC_SNOC }, 106 }; 107 108 static struct qcom_icc_node qhm_qdss_bam = { 109 .name = "qhm_qdss_bam", 110 .id = SC7280_MASTER_QDSS_BAM, 111 .channels = 1, 112 .buswidth = 4, 113 .num_links = 1, 114 .links = { SC7280_SLAVE_A2NOC_SNOC }, 115 }; 116 117 static struct qcom_icc_node qnm_a2noc_cfg = { 118 .name = "qnm_a2noc_cfg", 119 .id = SC7280_MASTER_A2NOC_CFG, 120 .channels = 1, 121 .buswidth = 4, 122 .num_links = 1, 123 .links = { SC7280_SLAVE_SERVICE_A2NOC }, 124 }; 125 126 static struct qcom_icc_node qnm_cnoc_datapath = { 127 .name = "qnm_cnoc_datapath", 128 .id = SC7280_MASTER_CNOC_A2NOC, 129 .channels = 1, 130 .buswidth = 8, 131 .num_links = 1, 132 .links = { SC7280_SLAVE_A2NOC_SNOC }, 133 }; 134 135 static struct qcom_icc_node qxm_crypto = { 136 .name = "qxm_crypto", 137 .id = SC7280_MASTER_CRYPTO, 138 .channels = 1, 139 .buswidth = 8, 140 .num_links = 1, 141 .links = { SC7280_SLAVE_A2NOC_SNOC }, 142 }; 143 144 static struct qcom_icc_node qxm_ipa = { 145 .name = "qxm_ipa", 146 .id = SC7280_MASTER_IPA, 147 .channels = 1, 148 .buswidth = 8, 149 .num_links = 1, 150 .links = { SC7280_SLAVE_A2NOC_SNOC }, 151 }; 152 153 static struct qcom_icc_node xm_pcie3_0 = { 154 .name = "xm_pcie3_0", 155 .id = SC7280_MASTER_PCIE_0, 156 .channels = 1, 157 .buswidth = 8, 158 .num_links = 1, 159 .links = { SC7280_SLAVE_ANOC_PCIE_GEM_NOC }, 160 }; 161 162 static struct qcom_icc_node xm_pcie3_1 = { 163 .name = "xm_pcie3_1", 164 .id = SC7280_MASTER_PCIE_1, 165 .channels = 1, 166 .buswidth = 8, 167 .links = { SC7280_SLAVE_ANOC_PCIE_GEM_NOC }, 168 }; 169 170 static struct qcom_icc_node xm_qdss_etr = { 171 .name = "xm_qdss_etr", 172 .id = SC7280_MASTER_QDSS_ETR, 173 .channels = 1, 174 .buswidth = 8, 175 .num_links = 1, 176 .links = { SC7280_SLAVE_A2NOC_SNOC }, 177 }; 178 179 static struct qcom_icc_node qup0_core_master = { 180 .name = "qup0_core_master", 181 .id = SC7280_MASTER_QUP_CORE_0, 182 .channels = 1, 183 .buswidth = 4, 184 .num_links = 1, 185 .links = { SC7280_SLAVE_QUP_CORE_0 }, 186 }; 187 188 static struct qcom_icc_node qup1_core_master = { 189 .name = "qup1_core_master", 190 .id = SC7280_MASTER_QUP_CORE_1, 191 .channels = 1, 192 .buswidth = 4, 193 .num_links = 1, 194 .links = { SC7280_SLAVE_QUP_CORE_1 }, 195 }; 196 197 static struct qcom_icc_node qnm_cnoc3_cnoc2 = { 198 .name = "qnm_cnoc3_cnoc2", 199 .id = SC7280_MASTER_CNOC3_CNOC2, 200 .channels = 1, 201 .buswidth = 8, 202 .num_links = 44, 203 .links = { SC7280_SLAVE_AHB2PHY_SOUTH, SC7280_SLAVE_AHB2PHY_NORTH, 204 SC7280_SLAVE_CAMERA_CFG, SC7280_SLAVE_CLK_CTL, 205 SC7280_SLAVE_CDSP_CFG, SC7280_SLAVE_RBCPR_CX_CFG, 206 SC7280_SLAVE_RBCPR_MX_CFG, SC7280_SLAVE_CRYPTO_0_CFG, 207 SC7280_SLAVE_CX_RDPM, SC7280_SLAVE_DCC_CFG, 208 SC7280_SLAVE_DISPLAY_CFG, SC7280_SLAVE_GFX3D_CFG, 209 SC7280_SLAVE_HWKM, SC7280_SLAVE_IMEM_CFG, 210 SC7280_SLAVE_IPA_CFG, SC7280_SLAVE_IPC_ROUTER_CFG, 211 SC7280_SLAVE_LPASS, SC7280_SLAVE_CNOC_MSS, 212 SC7280_SLAVE_MX_RDPM, SC7280_SLAVE_PCIE_0_CFG, 213 SC7280_SLAVE_PCIE_1_CFG, SC7280_SLAVE_PDM, 214 SC7280_SLAVE_PIMEM_CFG, SC7280_SLAVE_PKA_WRAPPER_CFG, 215 SC7280_SLAVE_PMU_WRAPPER_CFG, SC7280_SLAVE_QDSS_CFG, 216 SC7280_SLAVE_QSPI_0, SC7280_SLAVE_QUP_0, 217 SC7280_SLAVE_QUP_1, SC7280_SLAVE_SDCC_1, 218 SC7280_SLAVE_SDCC_2, SC7280_SLAVE_SDCC_4, 219 SC7280_SLAVE_SECURITY, SC7280_SLAVE_TCSR, 220 SC7280_SLAVE_TLMM, SC7280_SLAVE_UFS_MEM_CFG, 221 SC7280_SLAVE_USB2, SC7280_SLAVE_USB3_0, 222 SC7280_SLAVE_VENUS_CFG, SC7280_SLAVE_VSENSE_CTRL_CFG, 223 SC7280_SLAVE_A1NOC_CFG, SC7280_SLAVE_A2NOC_CFG, 224 SC7280_SLAVE_CNOC_MNOC_CFG, SC7280_SLAVE_SNOC_CFG }, 225 }; 226 227 static struct qcom_icc_node xm_qdss_dap = { 228 .name = "xm_qdss_dap", 229 .id = SC7280_MASTER_QDSS_DAP, 230 .channels = 1, 231 .buswidth = 8, 232 .num_links = 45, 233 .links = { SC7280_SLAVE_AHB2PHY_SOUTH, SC7280_SLAVE_AHB2PHY_NORTH, 234 SC7280_SLAVE_CAMERA_CFG, SC7280_SLAVE_CLK_CTL, 235 SC7280_SLAVE_CDSP_CFG, SC7280_SLAVE_RBCPR_CX_CFG, 236 SC7280_SLAVE_RBCPR_MX_CFG, SC7280_SLAVE_CRYPTO_0_CFG, 237 SC7280_SLAVE_CX_RDPM, SC7280_SLAVE_DCC_CFG, 238 SC7280_SLAVE_DISPLAY_CFG, SC7280_SLAVE_GFX3D_CFG, 239 SC7280_SLAVE_HWKM, SC7280_SLAVE_IMEM_CFG, 240 SC7280_SLAVE_IPA_CFG, SC7280_SLAVE_IPC_ROUTER_CFG, 241 SC7280_SLAVE_LPASS, SC7280_SLAVE_CNOC_MSS, 242 SC7280_SLAVE_MX_RDPM, SC7280_SLAVE_PCIE_0_CFG, 243 SC7280_SLAVE_PCIE_1_CFG, SC7280_SLAVE_PDM, 244 SC7280_SLAVE_PIMEM_CFG, SC7280_SLAVE_PKA_WRAPPER_CFG, 245 SC7280_SLAVE_PMU_WRAPPER_CFG, SC7280_SLAVE_QDSS_CFG, 246 SC7280_SLAVE_QSPI_0, SC7280_SLAVE_QUP_0, 247 SC7280_SLAVE_QUP_1, SC7280_SLAVE_SDCC_1, 248 SC7280_SLAVE_SDCC_2, SC7280_SLAVE_SDCC_4, 249 SC7280_SLAVE_SECURITY, SC7280_SLAVE_TCSR, 250 SC7280_SLAVE_TLMM, SC7280_SLAVE_UFS_MEM_CFG, 251 SC7280_SLAVE_USB2, SC7280_SLAVE_USB3_0, 252 SC7280_SLAVE_VENUS_CFG, SC7280_SLAVE_VSENSE_CTRL_CFG, 253 SC7280_SLAVE_A1NOC_CFG, SC7280_SLAVE_A2NOC_CFG, 254 SC7280_SLAVE_CNOC2_CNOC3, SC7280_SLAVE_CNOC_MNOC_CFG, 255 SC7280_SLAVE_SNOC_CFG }, 256 }; 257 258 static struct qcom_icc_node qnm_cnoc2_cnoc3 = { 259 .name = "qnm_cnoc2_cnoc3", 260 .id = SC7280_MASTER_CNOC2_CNOC3, 261 .channels = 1, 262 .buswidth = 8, 263 .num_links = 9, 264 .links = { SC7280_SLAVE_AOSS, SC7280_SLAVE_APPSS, 265 SC7280_SLAVE_CNOC_A2NOC, SC7280_SLAVE_DDRSS_CFG, 266 SC7280_SLAVE_BOOT_IMEM, SC7280_SLAVE_IMEM, 267 SC7280_SLAVE_PIMEM, SC7280_SLAVE_QDSS_STM, 268 SC7280_SLAVE_TCU }, 269 }; 270 271 static struct qcom_icc_node qnm_gemnoc_cnoc = { 272 .name = "qnm_gemnoc_cnoc", 273 .id = SC7280_MASTER_GEM_NOC_CNOC, 274 .channels = 1, 275 .buswidth = 16, 276 .num_links = 9, 277 .links = { SC7280_SLAVE_AOSS, SC7280_SLAVE_APPSS, 278 SC7280_SLAVE_CNOC3_CNOC2, SC7280_SLAVE_DDRSS_CFG, 279 SC7280_SLAVE_BOOT_IMEM, SC7280_SLAVE_IMEM, 280 SC7280_SLAVE_PIMEM, SC7280_SLAVE_QDSS_STM, 281 SC7280_SLAVE_TCU }, 282 }; 283 284 static struct qcom_icc_node qnm_gemnoc_pcie = { 285 .name = "qnm_gemnoc_pcie", 286 .id = SC7280_MASTER_GEM_NOC_PCIE_SNOC, 287 .channels = 1, 288 .buswidth = 8, 289 .num_links = 2, 290 .links = { SC7280_SLAVE_PCIE_0, SC7280_SLAVE_PCIE_1 }, 291 }; 292 293 static struct qcom_icc_node qnm_cnoc_dc_noc = { 294 .name = "qnm_cnoc_dc_noc", 295 .id = SC7280_MASTER_CNOC_DC_NOC, 296 .channels = 1, 297 .buswidth = 4, 298 .num_links = 2, 299 .links = { SC7280_SLAVE_LLCC_CFG, SC7280_SLAVE_GEM_NOC_CFG }, 300 }; 301 302 static struct qcom_icc_node alm_gpu_tcu = { 303 .name = "alm_gpu_tcu", 304 .id = SC7280_MASTER_GPU_TCU, 305 .channels = 1, 306 .buswidth = 8, 307 .num_links = 2, 308 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, 309 }; 310 311 static struct qcom_icc_node alm_sys_tcu = { 312 .name = "alm_sys_tcu", 313 .id = SC7280_MASTER_SYS_TCU, 314 .channels = 1, 315 .buswidth = 8, 316 .num_links = 2, 317 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, 318 }; 319 320 static struct qcom_icc_node chm_apps = { 321 .name = "chm_apps", 322 .id = SC7280_MASTER_APPSS_PROC, 323 .channels = 1, 324 .buswidth = 32, 325 .num_links = 3, 326 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC, 327 SC7280_SLAVE_MEM_NOC_PCIE_SNOC }, 328 }; 329 330 static struct qcom_icc_node qnm_cmpnoc = { 331 .name = "qnm_cmpnoc", 332 .id = SC7280_MASTER_COMPUTE_NOC, 333 .channels = 2, 334 .buswidth = 32, 335 .num_links = 2, 336 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, 337 }; 338 339 static struct qcom_icc_node qnm_gemnoc_cfg = { 340 .name = "qnm_gemnoc_cfg", 341 .id = SC7280_MASTER_GEM_NOC_CFG, 342 .channels = 1, 343 .buswidth = 4, 344 .num_links = 5, 345 .links = { SC7280_SLAVE_MSS_PROC_MS_MPU_CFG, SC7280_SLAVE_MCDMA_MS_MPU_CFG, 346 SC7280_SLAVE_SERVICE_GEM_NOC_1, SC7280_SLAVE_SERVICE_GEM_NOC_2, 347 SC7280_SLAVE_SERVICE_GEM_NOC }, 348 }; 349 350 static struct qcom_icc_node qnm_gpu = { 351 .name = "qnm_gpu", 352 .id = SC7280_MASTER_GFX3D, 353 .channels = 2, 354 .buswidth = 32, 355 .num_links = 2, 356 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, 357 }; 358 359 static struct qcom_icc_node qnm_mnoc_hf = { 360 .name = "qnm_mnoc_hf", 361 .id = SC7280_MASTER_MNOC_HF_MEM_NOC, 362 .channels = 2, 363 .buswidth = 32, 364 .num_links = 1, 365 .links = { SC7280_SLAVE_LLCC }, 366 }; 367 368 static struct qcom_icc_node qnm_mnoc_sf = { 369 .name = "qnm_mnoc_sf", 370 .id = SC7280_MASTER_MNOC_SF_MEM_NOC, 371 .channels = 1, 372 .buswidth = 32, 373 .num_links = 2, 374 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, 375 }; 376 377 static struct qcom_icc_node qnm_pcie = { 378 .name = "qnm_pcie", 379 .id = SC7280_MASTER_ANOC_PCIE_GEM_NOC, 380 .channels = 1, 381 .buswidth = 16, 382 .num_links = 2, 383 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC }, 384 }; 385 386 static struct qcom_icc_node qnm_snoc_gc = { 387 .name = "qnm_snoc_gc", 388 .id = SC7280_MASTER_SNOC_GC_MEM_NOC, 389 .channels = 1, 390 .buswidth = 8, 391 .num_links = 1, 392 .links = { SC7280_SLAVE_LLCC }, 393 }; 394 395 static struct qcom_icc_node qnm_snoc_sf = { 396 .name = "qnm_snoc_sf", 397 .id = SC7280_MASTER_SNOC_SF_MEM_NOC, 398 .channels = 1, 399 .buswidth = 16, 400 .num_links = 3, 401 .links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC, 402 SC7280_SLAVE_MEM_NOC_PCIE_SNOC }, 403 }; 404 405 static struct qcom_icc_node qhm_config_noc = { 406 .name = "qhm_config_noc", 407 .id = SC7280_MASTER_CNOC_LPASS_AG_NOC, 408 .channels = 1, 409 .buswidth = 4, 410 .num_links = 6, 411 .links = { SC7280_SLAVE_LPASS_CORE_CFG, SC7280_SLAVE_LPASS_LPI_CFG, 412 SC7280_SLAVE_LPASS_MPU_CFG, SC7280_SLAVE_LPASS_TOP_CFG, 413 SC7280_SLAVE_SERVICES_LPASS_AML_NOC, SC7280_SLAVE_SERVICE_LPASS_AG_NOC }, 414 }; 415 416 static struct qcom_icc_node llcc_mc = { 417 .name = "llcc_mc", 418 .id = SC7280_MASTER_LLCC, 419 .channels = 2, 420 .buswidth = 4, 421 .num_links = 1, 422 .links = { SC7280_SLAVE_EBI1 }, 423 }; 424 425 static struct qcom_icc_node qnm_mnoc_cfg = { 426 .name = "qnm_mnoc_cfg", 427 .id = SC7280_MASTER_CNOC_MNOC_CFG, 428 .channels = 1, 429 .buswidth = 4, 430 .num_links = 1, 431 .links = { SC7280_SLAVE_SERVICE_MNOC }, 432 }; 433 434 static struct qcom_icc_node qnm_video0 = { 435 .name = "qnm_video0", 436 .id = SC7280_MASTER_VIDEO_P0, 437 .channels = 1, 438 .buswidth = 32, 439 .num_links = 1, 440 .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC }, 441 }; 442 443 static struct qcom_icc_node qnm_video_cpu = { 444 .name = "qnm_video_cpu", 445 .id = SC7280_MASTER_VIDEO_PROC, 446 .channels = 1, 447 .buswidth = 8, 448 .num_links = 1, 449 .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC }, 450 }; 451 452 static struct qcom_icc_node qxm_camnoc_hf = { 453 .name = "qxm_camnoc_hf", 454 .id = SC7280_MASTER_CAMNOC_HF, 455 .channels = 2, 456 .buswidth = 32, 457 .num_links = 1, 458 .links = { SC7280_SLAVE_MNOC_HF_MEM_NOC }, 459 }; 460 461 static struct qcom_icc_node qxm_camnoc_icp = { 462 .name = "qxm_camnoc_icp", 463 .id = SC7280_MASTER_CAMNOC_ICP, 464 .channels = 1, 465 .buswidth = 8, 466 .num_links = 1, 467 .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC }, 468 }; 469 470 static struct qcom_icc_node qxm_camnoc_sf = { 471 .name = "qxm_camnoc_sf", 472 .id = SC7280_MASTER_CAMNOC_SF, 473 .channels = 1, 474 .buswidth = 32, 475 .num_links = 1, 476 .links = { SC7280_SLAVE_MNOC_SF_MEM_NOC }, 477 }; 478 479 static struct qcom_icc_node qxm_mdp0 = { 480 .name = "qxm_mdp0", 481 .id = SC7280_MASTER_MDP0, 482 .channels = 1, 483 .buswidth = 32, 484 .num_links = 1, 485 .links = { SC7280_SLAVE_MNOC_HF_MEM_NOC }, 486 }; 487 488 static struct qcom_icc_node qhm_nsp_noc_config = { 489 .name = "qhm_nsp_noc_config", 490 .id = SC7280_MASTER_CDSP_NOC_CFG, 491 .channels = 1, 492 .buswidth = 4, 493 .num_links = 1, 494 .links = { SC7280_SLAVE_SERVICE_NSP_NOC }, 495 }; 496 497 static struct qcom_icc_node qxm_nsp = { 498 .name = "qxm_nsp", 499 .id = SC7280_MASTER_CDSP_PROC, 500 .channels = 2, 501 .buswidth = 32, 502 .num_links = 1, 503 .links = { SC7280_SLAVE_CDSP_MEM_NOC }, 504 }; 505 506 static struct qcom_icc_node qnm_aggre1_noc = { 507 .name = "qnm_aggre1_noc", 508 .id = SC7280_MASTER_A1NOC_SNOC, 509 .channels = 1, 510 .buswidth = 16, 511 .num_links = 1, 512 .links = { SC7280_SLAVE_SNOC_GEM_NOC_SF }, 513 }; 514 515 static struct qcom_icc_node qnm_aggre2_noc = { 516 .name = "qnm_aggre2_noc", 517 .id = SC7280_MASTER_A2NOC_SNOC, 518 .channels = 1, 519 .buswidth = 16, 520 .num_links = 1, 521 .links = { SC7280_SLAVE_SNOC_GEM_NOC_SF }, 522 }; 523 524 static struct qcom_icc_node qnm_snoc_cfg = { 525 .name = "qnm_snoc_cfg", 526 .id = SC7280_MASTER_SNOC_CFG, 527 .channels = 1, 528 .buswidth = 4, 529 .num_links = 1, 530 .links = { SC7280_SLAVE_SERVICE_SNOC }, 531 }; 532 533 static struct qcom_icc_node qxm_pimem = { 534 .name = "qxm_pimem", 535 .id = SC7280_MASTER_PIMEM, 536 .channels = 1, 537 .buswidth = 8, 538 .num_links = 1, 539 .links = { SC7280_SLAVE_SNOC_GEM_NOC_GC }, 540 }; 541 542 static struct qcom_icc_node xm_gic = { 543 .name = "xm_gic", 544 .id = SC7280_MASTER_GIC, 545 .channels = 1, 546 .buswidth = 8, 547 .num_links = 1, 548 .links = { SC7280_SLAVE_SNOC_GEM_NOC_GC }, 549 }; 550 551 static struct qcom_icc_node qns_a1noc_snoc = { 552 .name = "qns_a1noc_snoc", 553 .id = SC7280_SLAVE_A1NOC_SNOC, 554 .channels = 1, 555 .buswidth = 16, 556 .num_links = 1, 557 .links = { SC7280_MASTER_A1NOC_SNOC }, 558 }; 559 560 static struct qcom_icc_node srvc_aggre1_noc = { 561 .name = "srvc_aggre1_noc", 562 .id = SC7280_SLAVE_SERVICE_A1NOC, 563 .channels = 1, 564 .buswidth = 4, 565 .num_links = 0, 566 }; 567 568 static struct qcom_icc_node qns_a2noc_snoc = { 569 .name = "qns_a2noc_snoc", 570 .id = SC7280_SLAVE_A2NOC_SNOC, 571 .channels = 1, 572 .buswidth = 16, 573 .num_links = 1, 574 .links = { SC7280_MASTER_A2NOC_SNOC }, 575 }; 576 577 static struct qcom_icc_node qns_pcie_mem_noc = { 578 .name = "qns_pcie_mem_noc", 579 .id = SC7280_SLAVE_ANOC_PCIE_GEM_NOC, 580 .channels = 1, 581 .buswidth = 16, 582 .num_links = 1, 583 .links = { SC7280_MASTER_ANOC_PCIE_GEM_NOC }, 584 }; 585 586 static struct qcom_icc_node srvc_aggre2_noc = { 587 .name = "srvc_aggre2_noc", 588 .id = SC7280_SLAVE_SERVICE_A2NOC, 589 .channels = 1, 590 .buswidth = 4, 591 .num_links = 0, 592 }; 593 594 static struct qcom_icc_node qup0_core_slave = { 595 .name = "qup0_core_slave", 596 .id = SC7280_SLAVE_QUP_CORE_0, 597 .channels = 1, 598 .buswidth = 4, 599 .num_links = 0, 600 }; 601 602 static struct qcom_icc_node qup1_core_slave = { 603 .name = "qup1_core_slave", 604 .id = SC7280_SLAVE_QUP_CORE_1, 605 .channels = 1, 606 .buswidth = 4, 607 .num_links = 0, 608 }; 609 610 static struct qcom_icc_node qhs_ahb2phy0 = { 611 .name = "qhs_ahb2phy0", 612 .id = SC7280_SLAVE_AHB2PHY_SOUTH, 613 .channels = 1, 614 .buswidth = 4, 615 .num_links = 0, 616 }; 617 618 static struct qcom_icc_node qhs_ahb2phy1 = { 619 .name = "qhs_ahb2phy1", 620 .id = SC7280_SLAVE_AHB2PHY_NORTH, 621 .channels = 1, 622 .buswidth = 4, 623 .num_links = 0, 624 }; 625 626 static struct qcom_icc_node qhs_camera_cfg = { 627 .name = "qhs_camera_cfg", 628 .id = SC7280_SLAVE_CAMERA_CFG, 629 .channels = 1, 630 .buswidth = 4, 631 .num_links = 0, 632 }; 633 634 static struct qcom_icc_node qhs_clk_ctl = { 635 .name = "qhs_clk_ctl", 636 .id = SC7280_SLAVE_CLK_CTL, 637 .channels = 1, 638 .buswidth = 4, 639 .num_links = 0, 640 }; 641 642 static struct qcom_icc_node qhs_compute_cfg = { 643 .name = "qhs_compute_cfg", 644 .id = SC7280_SLAVE_CDSP_CFG, 645 .channels = 1, 646 .buswidth = 4, 647 .num_links = 1, 648 .links = { SC7280_MASTER_CDSP_NOC_CFG }, 649 }; 650 651 static struct qcom_icc_node qhs_cpr_cx = { 652 .name = "qhs_cpr_cx", 653 .id = SC7280_SLAVE_RBCPR_CX_CFG, 654 .channels = 1, 655 .buswidth = 4, 656 .num_links = 0, 657 }; 658 659 static struct qcom_icc_node qhs_cpr_mx = { 660 .name = "qhs_cpr_mx", 661 .id = SC7280_SLAVE_RBCPR_MX_CFG, 662 .channels = 1, 663 .buswidth = 4, 664 .num_links = 0, 665 }; 666 667 static struct qcom_icc_node qhs_crypto0_cfg = { 668 .name = "qhs_crypto0_cfg", 669 .id = SC7280_SLAVE_CRYPTO_0_CFG, 670 .channels = 1, 671 .buswidth = 4, 672 .num_links = 0, 673 }; 674 675 static struct qcom_icc_node qhs_cx_rdpm = { 676 .name = "qhs_cx_rdpm", 677 .id = SC7280_SLAVE_CX_RDPM, 678 .channels = 1, 679 .buswidth = 4, 680 .num_links = 0, 681 }; 682 683 static struct qcom_icc_node qhs_dcc_cfg = { 684 .name = "qhs_dcc_cfg", 685 .id = SC7280_SLAVE_DCC_CFG, 686 .channels = 1, 687 .buswidth = 4, 688 .num_links = 0, 689 }; 690 691 static struct qcom_icc_node qhs_display_cfg = { 692 .name = "qhs_display_cfg", 693 .id = SC7280_SLAVE_DISPLAY_CFG, 694 .channels = 1, 695 .buswidth = 4, 696 .num_links = 0, 697 }; 698 699 static struct qcom_icc_node qhs_gpuss_cfg = { 700 .name = "qhs_gpuss_cfg", 701 .id = SC7280_SLAVE_GFX3D_CFG, 702 .channels = 1, 703 .buswidth = 8, 704 .num_links = 0, 705 }; 706 707 static struct qcom_icc_node qhs_hwkm = { 708 .name = "qhs_hwkm", 709 .id = SC7280_SLAVE_HWKM, 710 .channels = 1, 711 .buswidth = 4, 712 .num_links = 0, 713 }; 714 715 static struct qcom_icc_node qhs_imem_cfg = { 716 .name = "qhs_imem_cfg", 717 .id = SC7280_SLAVE_IMEM_CFG, 718 .channels = 1, 719 .buswidth = 4, 720 .num_links = 0, 721 }; 722 723 static struct qcom_icc_node qhs_ipa = { 724 .name = "qhs_ipa", 725 .id = SC7280_SLAVE_IPA_CFG, 726 .channels = 1, 727 .buswidth = 4, 728 .num_links = 0, 729 }; 730 731 static struct qcom_icc_node qhs_ipc_router = { 732 .name = "qhs_ipc_router", 733 .id = SC7280_SLAVE_IPC_ROUTER_CFG, 734 .channels = 1, 735 .buswidth = 4, 736 .num_links = 0, 737 }; 738 739 static struct qcom_icc_node qhs_lpass_cfg = { 740 .name = "qhs_lpass_cfg", 741 .id = SC7280_SLAVE_LPASS, 742 .channels = 1, 743 .buswidth = 4, 744 .num_links = 1, 745 .links = { SC7280_MASTER_CNOC_LPASS_AG_NOC }, 746 }; 747 748 static struct qcom_icc_node qhs_mss_cfg = { 749 .name = "qhs_mss_cfg", 750 .id = SC7280_SLAVE_CNOC_MSS, 751 .channels = 1, 752 .buswidth = 4, 753 .num_links = 0, 754 }; 755 756 static struct qcom_icc_node qhs_mx_rdpm = { 757 .name = "qhs_mx_rdpm", 758 .id = SC7280_SLAVE_MX_RDPM, 759 .channels = 1, 760 .buswidth = 4, 761 .num_links = 0, 762 }; 763 764 static struct qcom_icc_node qhs_pcie0_cfg = { 765 .name = "qhs_pcie0_cfg", 766 .id = SC7280_SLAVE_PCIE_0_CFG, 767 .channels = 1, 768 .buswidth = 4, 769 .num_links = 0, 770 }; 771 772 static struct qcom_icc_node qhs_pcie1_cfg = { 773 .name = "qhs_pcie1_cfg", 774 .id = SC7280_SLAVE_PCIE_1_CFG, 775 .channels = 1, 776 .buswidth = 4, 777 .num_links = 0, 778 }; 779 780 static struct qcom_icc_node qhs_pdm = { 781 .name = "qhs_pdm", 782 .id = SC7280_SLAVE_PDM, 783 .channels = 1, 784 .buswidth = 4, 785 .num_links = 0, 786 }; 787 788 static struct qcom_icc_node qhs_pimem_cfg = { 789 .name = "qhs_pimem_cfg", 790 .id = SC7280_SLAVE_PIMEM_CFG, 791 .channels = 1, 792 .buswidth = 4, 793 .num_links = 0, 794 }; 795 796 static struct qcom_icc_node qhs_pka_wrapper_cfg = { 797 .name = "qhs_pka_wrapper_cfg", 798 .id = SC7280_SLAVE_PKA_WRAPPER_CFG, 799 .channels = 1, 800 .buswidth = 4, 801 .num_links = 0, 802 }; 803 804 static struct qcom_icc_node qhs_pmu_wrapper_cfg = { 805 .name = "qhs_pmu_wrapper_cfg", 806 .id = SC7280_SLAVE_PMU_WRAPPER_CFG, 807 .channels = 1, 808 .buswidth = 4, 809 .num_links = 0, 810 }; 811 812 static struct qcom_icc_node qhs_qdss_cfg = { 813 .name = "qhs_qdss_cfg", 814 .id = SC7280_SLAVE_QDSS_CFG, 815 .channels = 1, 816 .buswidth = 4, 817 .num_links = 0, 818 }; 819 820 static struct qcom_icc_node qhs_qspi = { 821 .name = "qhs_qspi", 822 .id = SC7280_SLAVE_QSPI_0, 823 .channels = 1, 824 .buswidth = 4, 825 .num_links = 0, 826 }; 827 828 static struct qcom_icc_node qhs_qup0 = { 829 .name = "qhs_qup0", 830 .id = SC7280_SLAVE_QUP_0, 831 .channels = 1, 832 .buswidth = 4, 833 .num_links = 0, 834 }; 835 836 static struct qcom_icc_node qhs_qup1 = { 837 .name = "qhs_qup1", 838 .id = SC7280_SLAVE_QUP_1, 839 .channels = 1, 840 .buswidth = 4, 841 .num_links = 0, 842 }; 843 844 static struct qcom_icc_node qhs_sdc1 = { 845 .name = "qhs_sdc1", 846 .id = SC7280_SLAVE_SDCC_1, 847 .channels = 1, 848 .buswidth = 4, 849 .num_links = 0, 850 }; 851 852 static struct qcom_icc_node qhs_sdc2 = { 853 .name = "qhs_sdc2", 854 .id = SC7280_SLAVE_SDCC_2, 855 .channels = 1, 856 .buswidth = 4, 857 .num_links = 0, 858 }; 859 860 static struct qcom_icc_node qhs_sdc4 = { 861 .name = "qhs_sdc4", 862 .id = SC7280_SLAVE_SDCC_4, 863 .channels = 1, 864 .buswidth = 4, 865 .num_links = 0, 866 }; 867 868 static struct qcom_icc_node qhs_security = { 869 .name = "qhs_security", 870 .id = SC7280_SLAVE_SECURITY, 871 .channels = 1, 872 .buswidth = 4, 873 .num_links = 0, 874 }; 875 876 static struct qcom_icc_node qhs_tcsr = { 877 .name = "qhs_tcsr", 878 .id = SC7280_SLAVE_TCSR, 879 .channels = 1, 880 .buswidth = 4, 881 .num_links = 0, 882 }; 883 884 static struct qcom_icc_node qhs_tlmm = { 885 .name = "qhs_tlmm", 886 .id = SC7280_SLAVE_TLMM, 887 .channels = 1, 888 .buswidth = 4, 889 .num_links = 0, 890 }; 891 892 static struct qcom_icc_node qhs_ufs_mem_cfg = { 893 .name = "qhs_ufs_mem_cfg", 894 .id = SC7280_SLAVE_UFS_MEM_CFG, 895 .channels = 1, 896 .buswidth = 4, 897 .num_links = 0, 898 }; 899 900 static struct qcom_icc_node qhs_usb2 = { 901 .name = "qhs_usb2", 902 .id = SC7280_SLAVE_USB2, 903 .channels = 1, 904 .buswidth = 4, 905 .num_links = 0, 906 }; 907 908 static struct qcom_icc_node qhs_usb3_0 = { 909 .name = "qhs_usb3_0", 910 .id = SC7280_SLAVE_USB3_0, 911 .channels = 1, 912 .buswidth = 4, 913 .num_links = 0, 914 }; 915 916 static struct qcom_icc_node qhs_venus_cfg = { 917 .name = "qhs_venus_cfg", 918 .id = SC7280_SLAVE_VENUS_CFG, 919 .channels = 1, 920 .buswidth = 4, 921 .num_links = 0, 922 }; 923 924 static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 925 .name = "qhs_vsense_ctrl_cfg", 926 .id = SC7280_SLAVE_VSENSE_CTRL_CFG, 927 .channels = 1, 928 .buswidth = 4, 929 .num_links = 0, 930 }; 931 932 static struct qcom_icc_node qns_a1_noc_cfg = { 933 .name = "qns_a1_noc_cfg", 934 .id = SC7280_SLAVE_A1NOC_CFG, 935 .channels = 1, 936 .buswidth = 4, 937 .num_links = 1, 938 .links = { SC7280_MASTER_A1NOC_CFG }, 939 }; 940 941 static struct qcom_icc_node qns_a2_noc_cfg = { 942 .name = "qns_a2_noc_cfg", 943 .id = SC7280_SLAVE_A2NOC_CFG, 944 .channels = 1, 945 .buswidth = 4, 946 .num_links = 1, 947 .links = { SC7280_MASTER_A2NOC_CFG }, 948 }; 949 950 static struct qcom_icc_node qns_cnoc2_cnoc3 = { 951 .name = "qns_cnoc2_cnoc3", 952 .id = SC7280_SLAVE_CNOC2_CNOC3, 953 .channels = 1, 954 .buswidth = 8, 955 .num_links = 1, 956 .links = { SC7280_MASTER_CNOC2_CNOC3 }, 957 }; 958 959 static struct qcom_icc_node qns_mnoc_cfg = { 960 .name = "qns_mnoc_cfg", 961 .id = SC7280_SLAVE_CNOC_MNOC_CFG, 962 .channels = 1, 963 .buswidth = 4, 964 .num_links = 1, 965 .links = { SC7280_MASTER_CNOC_MNOC_CFG }, 966 }; 967 968 static struct qcom_icc_node qns_snoc_cfg = { 969 .name = "qns_snoc_cfg", 970 .id = SC7280_SLAVE_SNOC_CFG, 971 .channels = 1, 972 .buswidth = 4, 973 .num_links = 1, 974 .links = { SC7280_MASTER_SNOC_CFG }, 975 }; 976 977 static struct qcom_icc_node qhs_aoss = { 978 .name = "qhs_aoss", 979 .id = SC7280_SLAVE_AOSS, 980 .channels = 1, 981 .buswidth = 4, 982 .num_links = 0, 983 }; 984 985 static struct qcom_icc_node qhs_apss = { 986 .name = "qhs_apss", 987 .id = SC7280_SLAVE_APPSS, 988 .channels = 1, 989 .buswidth = 8, 990 .num_links = 0, 991 }; 992 993 static struct qcom_icc_node qns_cnoc3_cnoc2 = { 994 .name = "qns_cnoc3_cnoc2", 995 .id = SC7280_SLAVE_CNOC3_CNOC2, 996 .channels = 1, 997 .buswidth = 8, 998 .num_links = 1, 999 .links = { SC7280_MASTER_CNOC3_CNOC2 }, 1000 }; 1001 1002 static struct qcom_icc_node qns_cnoc_a2noc = { 1003 .name = "qns_cnoc_a2noc", 1004 .id = SC7280_SLAVE_CNOC_A2NOC, 1005 .channels = 1, 1006 .buswidth = 8, 1007 .num_links = 1, 1008 .links = { SC7280_MASTER_CNOC_A2NOC }, 1009 }; 1010 1011 static struct qcom_icc_node qns_ddrss_cfg = { 1012 .name = "qns_ddrss_cfg", 1013 .id = SC7280_SLAVE_DDRSS_CFG, 1014 .channels = 1, 1015 .buswidth = 4, 1016 .num_links = 1, 1017 .links = { SC7280_MASTER_CNOC_DC_NOC }, 1018 }; 1019 1020 static struct qcom_icc_node qxs_boot_imem = { 1021 .name = "qxs_boot_imem", 1022 .id = SC7280_SLAVE_BOOT_IMEM, 1023 .channels = 1, 1024 .buswidth = 8, 1025 .num_links = 0, 1026 }; 1027 1028 static struct qcom_icc_node qxs_imem = { 1029 .name = "qxs_imem", 1030 .id = SC7280_SLAVE_IMEM, 1031 .channels = 1, 1032 .buswidth = 8, 1033 .num_links = 0, 1034 }; 1035 1036 static struct qcom_icc_node qxs_pimem = { 1037 .name = "qxs_pimem", 1038 .id = SC7280_SLAVE_PIMEM, 1039 .channels = 1, 1040 .buswidth = 8, 1041 .num_links = 0, 1042 }; 1043 1044 static struct qcom_icc_node xs_pcie_0 = { 1045 .name = "xs_pcie_0", 1046 .id = SC7280_SLAVE_PCIE_0, 1047 .channels = 1, 1048 .buswidth = 8, 1049 .num_links = 0, 1050 }; 1051 1052 static struct qcom_icc_node xs_pcie_1 = { 1053 .name = "xs_pcie_1", 1054 .id = SC7280_SLAVE_PCIE_1, 1055 .channels = 1, 1056 .buswidth = 8, 1057 .num_links = 0, 1058 }; 1059 1060 static struct qcom_icc_node xs_qdss_stm = { 1061 .name = "xs_qdss_stm", 1062 .id = SC7280_SLAVE_QDSS_STM, 1063 .channels = 1, 1064 .buswidth = 4, 1065 .num_links = 0, 1066 }; 1067 1068 static struct qcom_icc_node xs_sys_tcu_cfg = { 1069 .name = "xs_sys_tcu_cfg", 1070 .id = SC7280_SLAVE_TCU, 1071 .channels = 1, 1072 .buswidth = 8, 1073 .num_links = 0, 1074 }; 1075 1076 static struct qcom_icc_node qhs_llcc = { 1077 .name = "qhs_llcc", 1078 .id = SC7280_SLAVE_LLCC_CFG, 1079 .channels = 1, 1080 .buswidth = 4, 1081 .num_links = 0, 1082 }; 1083 1084 static struct qcom_icc_node qns_gemnoc = { 1085 .name = "qns_gemnoc", 1086 .id = SC7280_SLAVE_GEM_NOC_CFG, 1087 .channels = 1, 1088 .buswidth = 4, 1089 .num_links = 1, 1090 .links = { SC7280_MASTER_GEM_NOC_CFG }, 1091 }; 1092 1093 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { 1094 .name = "qhs_mdsp_ms_mpu_cfg", 1095 .id = SC7280_SLAVE_MSS_PROC_MS_MPU_CFG, 1096 .channels = 1, 1097 .buswidth = 4, 1098 .num_links = 0, 1099 }; 1100 1101 static struct qcom_icc_node qhs_modem_ms_mpu_cfg = { 1102 .name = "qhs_modem_ms_mpu_cfg", 1103 .id = SC7280_SLAVE_MCDMA_MS_MPU_CFG, 1104 .channels = 1, 1105 .buswidth = 4, 1106 .num_links = 0, 1107 }; 1108 1109 static struct qcom_icc_node qns_gem_noc_cnoc = { 1110 .name = "qns_gem_noc_cnoc", 1111 .id = SC7280_SLAVE_GEM_NOC_CNOC, 1112 .channels = 1, 1113 .buswidth = 16, 1114 .num_links = 1, 1115 .links = { SC7280_MASTER_GEM_NOC_CNOC }, 1116 }; 1117 1118 static struct qcom_icc_node qns_llcc = { 1119 .name = "qns_llcc", 1120 .id = SC7280_SLAVE_LLCC, 1121 .channels = 2, 1122 .buswidth = 16, 1123 .num_links = 1, 1124 .links = { SC7280_MASTER_LLCC }, 1125 }; 1126 1127 static struct qcom_icc_node qns_pcie = { 1128 .name = "qns_pcie", 1129 .id = SC7280_SLAVE_MEM_NOC_PCIE_SNOC, 1130 .channels = 1, 1131 .buswidth = 8, 1132 .num_links = 1, 1133 .links = { SC7280_MASTER_GEM_NOC_PCIE_SNOC }, 1134 }; 1135 1136 static struct qcom_icc_node srvc_even_gemnoc = { 1137 .name = "srvc_even_gemnoc", 1138 .id = SC7280_SLAVE_SERVICE_GEM_NOC_1, 1139 .channels = 1, 1140 .buswidth = 4, 1141 .num_links = 0, 1142 }; 1143 1144 static struct qcom_icc_node srvc_odd_gemnoc = { 1145 .name = "srvc_odd_gemnoc", 1146 .id = SC7280_SLAVE_SERVICE_GEM_NOC_2, 1147 .channels = 1, 1148 .buswidth = 4, 1149 .num_links = 0, 1150 }; 1151 1152 static struct qcom_icc_node srvc_sys_gemnoc = { 1153 .name = "srvc_sys_gemnoc", 1154 .id = SC7280_SLAVE_SERVICE_GEM_NOC, 1155 .channels = 1, 1156 .buswidth = 4, 1157 .num_links = 0, 1158 }; 1159 1160 static struct qcom_icc_node qhs_lpass_core = { 1161 .name = "qhs_lpass_core", 1162 .id = SC7280_SLAVE_LPASS_CORE_CFG, 1163 .channels = 1, 1164 .buswidth = 4, 1165 .num_links = 0, 1166 }; 1167 1168 static struct qcom_icc_node qhs_lpass_lpi = { 1169 .name = "qhs_lpass_lpi", 1170 .id = SC7280_SLAVE_LPASS_LPI_CFG, 1171 .channels = 1, 1172 .buswidth = 4, 1173 .num_links = 0, 1174 }; 1175 1176 static struct qcom_icc_node qhs_lpass_mpu = { 1177 .name = "qhs_lpass_mpu", 1178 .id = SC7280_SLAVE_LPASS_MPU_CFG, 1179 .channels = 1, 1180 .buswidth = 4, 1181 .num_links = 0, 1182 }; 1183 1184 static struct qcom_icc_node qhs_lpass_top = { 1185 .name = "qhs_lpass_top", 1186 .id = SC7280_SLAVE_LPASS_TOP_CFG, 1187 .channels = 1, 1188 .buswidth = 4, 1189 .num_links = 0, 1190 }; 1191 1192 static struct qcom_icc_node srvc_niu_aml_noc = { 1193 .name = "srvc_niu_aml_noc", 1194 .id = SC7280_SLAVE_SERVICES_LPASS_AML_NOC, 1195 .channels = 1, 1196 .buswidth = 4, 1197 .num_links = 0, 1198 }; 1199 1200 static struct qcom_icc_node srvc_niu_lpass_agnoc = { 1201 .name = "srvc_niu_lpass_agnoc", 1202 .id = SC7280_SLAVE_SERVICE_LPASS_AG_NOC, 1203 .channels = 1, 1204 .buswidth = 4, 1205 .num_links = 0, 1206 }; 1207 1208 static struct qcom_icc_node ebi = { 1209 .name = "ebi", 1210 .id = SC7280_SLAVE_EBI1, 1211 .channels = 2, 1212 .buswidth = 4, 1213 .num_links = 0, 1214 }; 1215 1216 static struct qcom_icc_node qns_mem_noc_hf = { 1217 .name = "qns_mem_noc_hf", 1218 .id = SC7280_SLAVE_MNOC_HF_MEM_NOC, 1219 .channels = 2, 1220 .buswidth = 32, 1221 .num_links = 1, 1222 .links = { SC7280_MASTER_MNOC_HF_MEM_NOC }, 1223 }; 1224 1225 static struct qcom_icc_node qns_mem_noc_sf = { 1226 .name = "qns_mem_noc_sf", 1227 .id = SC7280_SLAVE_MNOC_SF_MEM_NOC, 1228 .channels = 1, 1229 .buswidth = 32, 1230 .num_links = 1, 1231 .links = { SC7280_MASTER_MNOC_SF_MEM_NOC }, 1232 }; 1233 1234 static struct qcom_icc_node srvc_mnoc = { 1235 .name = "srvc_mnoc", 1236 .id = SC7280_SLAVE_SERVICE_MNOC, 1237 .channels = 1, 1238 .buswidth = 4, 1239 .num_links = 0, 1240 }; 1241 1242 static struct qcom_icc_node qns_nsp_gemnoc = { 1243 .name = "qns_nsp_gemnoc", 1244 .id = SC7280_SLAVE_CDSP_MEM_NOC, 1245 .channels = 2, 1246 .buswidth = 32, 1247 .num_links = 1, 1248 .links = { SC7280_MASTER_COMPUTE_NOC }, 1249 }; 1250 1251 static struct qcom_icc_node service_nsp_noc = { 1252 .name = "service_nsp_noc", 1253 .id = SC7280_SLAVE_SERVICE_NSP_NOC, 1254 .channels = 1, 1255 .buswidth = 4, 1256 .num_links = 0, 1257 }; 1258 1259 static struct qcom_icc_node qns_gemnoc_gc = { 1260 .name = "qns_gemnoc_gc", 1261 .id = SC7280_SLAVE_SNOC_GEM_NOC_GC, 1262 .channels = 1, 1263 .buswidth = 8, 1264 .num_links = 1, 1265 .links = { SC7280_MASTER_SNOC_GC_MEM_NOC }, 1266 }; 1267 1268 static struct qcom_icc_node qns_gemnoc_sf = { 1269 .name = "qns_gemnoc_sf", 1270 .id = SC7280_SLAVE_SNOC_GEM_NOC_SF, 1271 .channels = 1, 1272 .buswidth = 16, 1273 .num_links = 1, 1274 .links = { SC7280_MASTER_SNOC_SF_MEM_NOC }, 1275 }; 1276 1277 static struct qcom_icc_node srvc_snoc = { 1278 .name = "srvc_snoc", 1279 .id = SC7280_SLAVE_SERVICE_SNOC, 1280 .channels = 1, 1281 .buswidth = 4, 1282 .num_links = 0, 1283 }; 1284 1285 static struct qcom_icc_bcm bcm_acv = { 1286 .name = "ACV", 1287 .num_nodes = 1, 1288 .nodes = { &ebi }, 1289 }; 1290 1291 static struct qcom_icc_bcm bcm_ce0 = { 1292 .name = "CE0", 1293 .num_nodes = 1, 1294 .nodes = { &qxm_crypto }, 1295 }; 1296 1297 static struct qcom_icc_bcm bcm_cn0 = { 1298 .name = "CN0", 1299 .keepalive = true, 1300 .num_nodes = 2, 1301 .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie }, 1302 }; 1303 1304 static struct qcom_icc_bcm bcm_cn1 = { 1305 .name = "CN1", 1306 .num_nodes = 47, 1307 .nodes = { &qnm_cnoc3_cnoc2, &xm_qdss_dap, 1308 &qhs_ahb2phy0, &qhs_ahb2phy1, 1309 &qhs_camera_cfg, &qhs_clk_ctl, 1310 &qhs_compute_cfg, &qhs_cpr_cx, 1311 &qhs_cpr_mx, &qhs_crypto0_cfg, 1312 &qhs_cx_rdpm, &qhs_dcc_cfg, 1313 &qhs_display_cfg, &qhs_gpuss_cfg, 1314 &qhs_hwkm, &qhs_imem_cfg, 1315 &qhs_ipa, &qhs_ipc_router, 1316 &qhs_mss_cfg, &qhs_mx_rdpm, 1317 &qhs_pcie0_cfg, &qhs_pcie1_cfg, 1318 &qhs_pimem_cfg, &qhs_pka_wrapper_cfg, 1319 &qhs_pmu_wrapper_cfg, &qhs_qdss_cfg, 1320 &qhs_qup0, &qhs_qup1, 1321 &qhs_security, &qhs_tcsr, 1322 &qhs_tlmm, &qhs_ufs_mem_cfg, &qhs_usb2, 1323 &qhs_usb3_0, &qhs_venus_cfg, 1324 &qhs_vsense_ctrl_cfg, &qns_a1_noc_cfg, 1325 &qns_a2_noc_cfg, &qns_cnoc2_cnoc3, 1326 &qns_mnoc_cfg, &qns_snoc_cfg, 1327 &qnm_cnoc2_cnoc3, &qhs_aoss, 1328 &qhs_apss, &qns_cnoc3_cnoc2, 1329 &qns_cnoc_a2noc, &qns_ddrss_cfg }, 1330 }; 1331 1332 static struct qcom_icc_bcm bcm_cn2 = { 1333 .name = "CN2", 1334 .num_nodes = 6, 1335 .nodes = { &qhs_lpass_cfg, &qhs_pdm, 1336 &qhs_qspi, &qhs_sdc1, 1337 &qhs_sdc2, &qhs_sdc4 }, 1338 }; 1339 1340 static struct qcom_icc_bcm bcm_co0 = { 1341 .name = "CO0", 1342 .num_nodes = 1, 1343 .nodes = { &qns_nsp_gemnoc }, 1344 }; 1345 1346 static struct qcom_icc_bcm bcm_co3 = { 1347 .name = "CO3", 1348 .num_nodes = 1, 1349 .nodes = { &qxm_nsp }, 1350 }; 1351 1352 static struct qcom_icc_bcm bcm_mc0 = { 1353 .name = "MC0", 1354 .keepalive = true, 1355 .num_nodes = 1, 1356 .nodes = { &ebi }, 1357 }; 1358 1359 static struct qcom_icc_bcm bcm_mm0 = { 1360 .name = "MM0", 1361 .keepalive = true, 1362 .num_nodes = 1, 1363 .nodes = { &qns_mem_noc_hf }, 1364 }; 1365 1366 static struct qcom_icc_bcm bcm_mm1 = { 1367 .name = "MM1", 1368 .num_nodes = 2, 1369 .nodes = { &qxm_camnoc_hf, &qxm_mdp0 }, 1370 }; 1371 1372 static struct qcom_icc_bcm bcm_mm4 = { 1373 .name = "MM4", 1374 .num_nodes = 1, 1375 .nodes = { &qns_mem_noc_sf }, 1376 }; 1377 1378 static struct qcom_icc_bcm bcm_mm5 = { 1379 .name = "MM5", 1380 .num_nodes = 3, 1381 .nodes = { &qnm_video0, &qxm_camnoc_icp, 1382 &qxm_camnoc_sf }, 1383 }; 1384 1385 static struct qcom_icc_bcm bcm_qup0 = { 1386 .name = "QUP0", 1387 .vote_scale = 1, 1388 .num_nodes = 1, 1389 .nodes = { &qup0_core_slave }, 1390 }; 1391 1392 static struct qcom_icc_bcm bcm_qup1 = { 1393 .name = "QUP1", 1394 .vote_scale = 1, 1395 .num_nodes = 1, 1396 .nodes = { &qup1_core_slave }, 1397 }; 1398 1399 static struct qcom_icc_bcm bcm_sh0 = { 1400 .name = "SH0", 1401 .keepalive = true, 1402 .num_nodes = 1, 1403 .nodes = { &qns_llcc }, 1404 }; 1405 1406 static struct qcom_icc_bcm bcm_sh2 = { 1407 .name = "SH2", 1408 .num_nodes = 2, 1409 .nodes = { &alm_gpu_tcu, &alm_sys_tcu }, 1410 }; 1411 1412 static struct qcom_icc_bcm bcm_sh3 = { 1413 .name = "SH3", 1414 .num_nodes = 1, 1415 .nodes = { &qnm_cmpnoc }, 1416 }; 1417 1418 static struct qcom_icc_bcm bcm_sh4 = { 1419 .name = "SH4", 1420 .num_nodes = 1, 1421 .nodes = { &chm_apps }, 1422 }; 1423 1424 static struct qcom_icc_bcm bcm_sn0 = { 1425 .name = "SN0", 1426 .keepalive = true, 1427 .num_nodes = 1, 1428 .nodes = { &qns_gemnoc_sf }, 1429 }; 1430 1431 static struct qcom_icc_bcm bcm_sn2 = { 1432 .name = "SN2", 1433 .num_nodes = 1, 1434 .nodes = { &qns_gemnoc_gc }, 1435 }; 1436 1437 static struct qcom_icc_bcm bcm_sn3 = { 1438 .name = "SN3", 1439 .num_nodes = 1, 1440 .nodes = { &qxs_pimem }, 1441 }; 1442 1443 static struct qcom_icc_bcm bcm_sn4 = { 1444 .name = "SN4", 1445 .num_nodes = 1, 1446 .nodes = { &xs_qdss_stm }, 1447 }; 1448 1449 static struct qcom_icc_bcm bcm_sn5 = { 1450 .name = "SN5", 1451 .num_nodes = 1, 1452 .nodes = { &xm_pcie3_0 }, 1453 }; 1454 1455 static struct qcom_icc_bcm bcm_sn6 = { 1456 .name = "SN6", 1457 .num_nodes = 1, 1458 .nodes = { &xm_pcie3_1 }, 1459 }; 1460 1461 static struct qcom_icc_bcm bcm_sn7 = { 1462 .name = "SN7", 1463 .num_nodes = 1, 1464 .nodes = { &qnm_aggre1_noc }, 1465 }; 1466 1467 static struct qcom_icc_bcm bcm_sn8 = { 1468 .name = "SN8", 1469 .num_nodes = 1, 1470 .nodes = { &qnm_aggre2_noc }, 1471 }; 1472 1473 static struct qcom_icc_bcm bcm_sn14 = { 1474 .name = "SN14", 1475 .num_nodes = 1, 1476 .nodes = { &qns_pcie_mem_noc }, 1477 }; 1478 1479 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 1480 &bcm_sn5, 1481 &bcm_sn6, 1482 &bcm_sn14, 1483 }; 1484 1485 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1486 [MASTER_QSPI_0] = &qhm_qspi, 1487 [MASTER_QUP_0] = &qhm_qup0, 1488 [MASTER_QUP_1] = &qhm_qup1, 1489 [MASTER_A1NOC_CFG] = &qnm_a1noc_cfg, 1490 [MASTER_PCIE_0] = &xm_pcie3_0, 1491 [MASTER_PCIE_1] = &xm_pcie3_1, 1492 [MASTER_SDCC_1] = &xm_sdc1, 1493 [MASTER_SDCC_2] = &xm_sdc2, 1494 [MASTER_SDCC_4] = &xm_sdc4, 1495 [MASTER_UFS_MEM] = &xm_ufs_mem, 1496 [MASTER_USB2] = &xm_usb2, 1497 [MASTER_USB3_0] = &xm_usb3_0, 1498 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, 1499 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, 1500 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, 1501 }; 1502 1503 static const struct qcom_icc_desc sc7280_aggre1_noc = { 1504 .nodes = aggre1_noc_nodes, 1505 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 1506 .bcms = aggre1_noc_bcms, 1507 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 1508 }; 1509 1510 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 1511 &bcm_ce0, 1512 }; 1513 1514 static struct qcom_icc_node * const aggre2_noc_nodes[] = { 1515 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 1516 [MASTER_A2NOC_CFG] = &qnm_a2noc_cfg, 1517 [MASTER_CNOC_A2NOC] = &qnm_cnoc_datapath, 1518 [MASTER_CRYPTO] = &qxm_crypto, 1519 [MASTER_IPA] = &qxm_ipa, 1520 [MASTER_QDSS_ETR] = &xm_qdss_etr, 1521 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, 1522 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, 1523 }; 1524 1525 static const struct qcom_icc_desc sc7280_aggre2_noc = { 1526 .nodes = aggre2_noc_nodes, 1527 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 1528 .bcms = aggre2_noc_bcms, 1529 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 1530 }; 1531 1532 static struct qcom_icc_bcm * const clk_virt_bcms[] = { 1533 &bcm_qup0, 1534 &bcm_qup1, 1535 }; 1536 1537 static struct qcom_icc_node * const clk_virt_nodes[] = { 1538 [MASTER_QUP_CORE_0] = &qup0_core_master, 1539 [MASTER_QUP_CORE_1] = &qup1_core_master, 1540 [SLAVE_QUP_CORE_0] = &qup0_core_slave, 1541 [SLAVE_QUP_CORE_1] = &qup1_core_slave, 1542 }; 1543 1544 static const struct qcom_icc_desc sc7280_clk_virt = { 1545 .nodes = clk_virt_nodes, 1546 .num_nodes = ARRAY_SIZE(clk_virt_nodes), 1547 .bcms = clk_virt_bcms, 1548 .num_bcms = ARRAY_SIZE(clk_virt_bcms), 1549 }; 1550 1551 static struct qcom_icc_bcm * const cnoc2_bcms[] = { 1552 &bcm_cn1, 1553 &bcm_cn2, 1554 }; 1555 1556 static struct qcom_icc_node * const cnoc2_nodes[] = { 1557 [MASTER_CNOC3_CNOC2] = &qnm_cnoc3_cnoc2, 1558 [MASTER_QDSS_DAP] = &xm_qdss_dap, 1559 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, 1560 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1, 1561 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 1562 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1563 [SLAVE_CDSP_CFG] = &qhs_compute_cfg, 1564 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 1565 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, 1566 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1567 [SLAVE_CX_RDPM] = &qhs_cx_rdpm, 1568 [SLAVE_DCC_CFG] = &qhs_dcc_cfg, 1569 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 1570 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, 1571 [SLAVE_HWKM] = &qhs_hwkm, 1572 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1573 [SLAVE_IPA_CFG] = &qhs_ipa, 1574 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, 1575 [SLAVE_LPASS] = &qhs_lpass_cfg, 1576 [SLAVE_CNOC_MSS] = &qhs_mss_cfg, 1577 [SLAVE_MX_RDPM] = &qhs_mx_rdpm, 1578 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, 1579 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, 1580 [SLAVE_PDM] = &qhs_pdm, 1581 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 1582 [SLAVE_PKA_WRAPPER_CFG] = &qhs_pka_wrapper_cfg, 1583 [SLAVE_PMU_WRAPPER_CFG] = &qhs_pmu_wrapper_cfg, 1584 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1585 [SLAVE_QSPI_0] = &qhs_qspi, 1586 [SLAVE_QUP_0] = &qhs_qup0, 1587 [SLAVE_QUP_1] = &qhs_qup1, 1588 [SLAVE_SDCC_1] = &qhs_sdc1, 1589 [SLAVE_SDCC_2] = &qhs_sdc2, 1590 [SLAVE_SDCC_4] = &qhs_sdc4, 1591 [SLAVE_SECURITY] = &qhs_security, 1592 [SLAVE_TCSR] = &qhs_tcsr, 1593 [SLAVE_TLMM] = &qhs_tlmm, 1594 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 1595 [SLAVE_USB2] = &qhs_usb2, 1596 [SLAVE_USB3_0] = &qhs_usb3_0, 1597 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1598 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 1599 [SLAVE_A1NOC_CFG] = &qns_a1_noc_cfg, 1600 [SLAVE_A2NOC_CFG] = &qns_a2_noc_cfg, 1601 [SLAVE_CNOC2_CNOC3] = &qns_cnoc2_cnoc3, 1602 [SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg, 1603 [SLAVE_SNOC_CFG] = &qns_snoc_cfg, 1604 }; 1605 1606 static const struct qcom_icc_desc sc7280_cnoc2 = { 1607 .nodes = cnoc2_nodes, 1608 .num_nodes = ARRAY_SIZE(cnoc2_nodes), 1609 .bcms = cnoc2_bcms, 1610 .num_bcms = ARRAY_SIZE(cnoc2_bcms), 1611 }; 1612 1613 static struct qcom_icc_bcm * const cnoc3_bcms[] = { 1614 &bcm_cn0, 1615 &bcm_cn1, 1616 &bcm_sn3, 1617 &bcm_sn4, 1618 }; 1619 1620 static struct qcom_icc_node * const cnoc3_nodes[] = { 1621 [MASTER_CNOC2_CNOC3] = &qnm_cnoc2_cnoc3, 1622 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, 1623 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, 1624 [SLAVE_AOSS] = &qhs_aoss, 1625 [SLAVE_APPSS] = &qhs_apss, 1626 [SLAVE_CNOC3_CNOC2] = &qns_cnoc3_cnoc2, 1627 [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc, 1628 [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg, 1629 [SLAVE_BOOT_IMEM] = &qxs_boot_imem, 1630 [SLAVE_IMEM] = &qxs_imem, 1631 [SLAVE_PIMEM] = &qxs_pimem, 1632 [SLAVE_PCIE_0] = &xs_pcie_0, 1633 [SLAVE_PCIE_1] = &xs_pcie_1, 1634 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1635 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1636 }; 1637 1638 static const struct qcom_icc_desc sc7280_cnoc3 = { 1639 .nodes = cnoc3_nodes, 1640 .num_nodes = ARRAY_SIZE(cnoc3_nodes), 1641 .bcms = cnoc3_bcms, 1642 .num_bcms = ARRAY_SIZE(cnoc3_bcms), 1643 }; 1644 1645 static struct qcom_icc_bcm * const dc_noc_bcms[] = { 1646 }; 1647 1648 static struct qcom_icc_node * const dc_noc_nodes[] = { 1649 [MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc, 1650 [SLAVE_LLCC_CFG] = &qhs_llcc, 1651 [SLAVE_GEM_NOC_CFG] = &qns_gemnoc, 1652 }; 1653 1654 static const struct qcom_icc_desc sc7280_dc_noc = { 1655 .nodes = dc_noc_nodes, 1656 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 1657 .bcms = dc_noc_bcms, 1658 .num_bcms = ARRAY_SIZE(dc_noc_bcms), 1659 }; 1660 1661 static struct qcom_icc_bcm * const gem_noc_bcms[] = { 1662 &bcm_sh0, 1663 &bcm_sh2, 1664 &bcm_sh3, 1665 &bcm_sh4, 1666 }; 1667 1668 static struct qcom_icc_node * const gem_noc_nodes[] = { 1669 [MASTER_GPU_TCU] = &alm_gpu_tcu, 1670 [MASTER_SYS_TCU] = &alm_sys_tcu, 1671 [MASTER_APPSS_PROC] = &chm_apps, 1672 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc, 1673 [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg, 1674 [MASTER_GFX3D] = &qnm_gpu, 1675 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 1676 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 1677 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, 1678 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 1679 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 1680 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg, 1681 [SLAVE_MCDMA_MS_MPU_CFG] = &qhs_modem_ms_mpu_cfg, 1682 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, 1683 [SLAVE_LLCC] = &qns_llcc, 1684 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, 1685 [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc, 1686 [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc, 1687 [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc, 1688 }; 1689 1690 static const struct qcom_icc_desc sc7280_gem_noc = { 1691 .nodes = gem_noc_nodes, 1692 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 1693 .bcms = gem_noc_bcms, 1694 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 1695 }; 1696 1697 static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = { 1698 }; 1699 1700 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { 1701 [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc, 1702 [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core, 1703 [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi, 1704 [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu, 1705 [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top, 1706 [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc, 1707 [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, 1708 }; 1709 1710 static const struct qcom_icc_desc sc7280_lpass_ag_noc = { 1711 .nodes = lpass_ag_noc_nodes, 1712 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), 1713 .bcms = lpass_ag_noc_bcms, 1714 .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms), 1715 }; 1716 1717 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 1718 &bcm_acv, 1719 &bcm_mc0, 1720 }; 1721 1722 static struct qcom_icc_node * const mc_virt_nodes[] = { 1723 [MASTER_LLCC] = &llcc_mc, 1724 [SLAVE_EBI1] = &ebi, 1725 }; 1726 1727 static const struct qcom_icc_desc sc7280_mc_virt = { 1728 .nodes = mc_virt_nodes, 1729 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 1730 .bcms = mc_virt_bcms, 1731 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 1732 }; 1733 1734 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 1735 &bcm_mm0, 1736 &bcm_mm1, 1737 &bcm_mm4, 1738 &bcm_mm5, 1739 }; 1740 1741 static struct qcom_icc_node * const mmss_noc_nodes[] = { 1742 [MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg, 1743 [MASTER_VIDEO_P0] = &qnm_video0, 1744 [MASTER_VIDEO_PROC] = &qnm_video_cpu, 1745 [MASTER_CAMNOC_HF] = &qxm_camnoc_hf, 1746 [MASTER_CAMNOC_ICP] = &qxm_camnoc_icp, 1747 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf, 1748 [MASTER_MDP0] = &qxm_mdp0, 1749 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 1750 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, 1751 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 1752 }; 1753 1754 static const struct qcom_icc_desc sc7280_mmss_noc = { 1755 .nodes = mmss_noc_nodes, 1756 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 1757 .bcms = mmss_noc_bcms, 1758 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 1759 }; 1760 1761 static struct qcom_icc_bcm * const nsp_noc_bcms[] = { 1762 &bcm_co0, 1763 &bcm_co3, 1764 }; 1765 1766 static struct qcom_icc_node * const nsp_noc_nodes[] = { 1767 [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config, 1768 [MASTER_CDSP_PROC] = &qxm_nsp, 1769 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, 1770 [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, 1771 }; 1772 1773 static const struct qcom_icc_desc sc7280_nsp_noc = { 1774 .nodes = nsp_noc_nodes, 1775 .num_nodes = ARRAY_SIZE(nsp_noc_nodes), 1776 .bcms = nsp_noc_bcms, 1777 .num_bcms = ARRAY_SIZE(nsp_noc_bcms), 1778 }; 1779 1780 static struct qcom_icc_bcm * const system_noc_bcms[] = { 1781 &bcm_sn0, 1782 &bcm_sn2, 1783 &bcm_sn7, 1784 &bcm_sn8, 1785 }; 1786 1787 static struct qcom_icc_node * const system_noc_nodes[] = { 1788 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, 1789 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, 1790 [MASTER_SNOC_CFG] = &qnm_snoc_cfg, 1791 [MASTER_PIMEM] = &qxm_pimem, 1792 [MASTER_GIC] = &xm_gic, 1793 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, 1794 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 1795 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 1796 }; 1797 1798 static const struct qcom_icc_desc sc7280_system_noc = { 1799 .nodes = system_noc_nodes, 1800 .num_nodes = ARRAY_SIZE(system_noc_nodes), 1801 .bcms = system_noc_bcms, 1802 .num_bcms = ARRAY_SIZE(system_noc_bcms), 1803 }; 1804 1805 static const struct of_device_id qnoc_of_match[] = { 1806 { .compatible = "qcom,sc7280-aggre1-noc", 1807 .data = &sc7280_aggre1_noc}, 1808 { .compatible = "qcom,sc7280-aggre2-noc", 1809 .data = &sc7280_aggre2_noc}, 1810 { .compatible = "qcom,sc7280-clk-virt", 1811 .data = &sc7280_clk_virt}, 1812 { .compatible = "qcom,sc7280-cnoc2", 1813 .data = &sc7280_cnoc2}, 1814 { .compatible = "qcom,sc7280-cnoc3", 1815 .data = &sc7280_cnoc3}, 1816 { .compatible = "qcom,sc7280-dc-noc", 1817 .data = &sc7280_dc_noc}, 1818 { .compatible = "qcom,sc7280-gem-noc", 1819 .data = &sc7280_gem_noc}, 1820 { .compatible = "qcom,sc7280-lpass-ag-noc", 1821 .data = &sc7280_lpass_ag_noc}, 1822 { .compatible = "qcom,sc7280-mc-virt", 1823 .data = &sc7280_mc_virt}, 1824 { .compatible = "qcom,sc7280-mmss-noc", 1825 .data = &sc7280_mmss_noc}, 1826 { .compatible = "qcom,sc7280-nsp-noc", 1827 .data = &sc7280_nsp_noc}, 1828 { .compatible = "qcom,sc7280-system-noc", 1829 .data = &sc7280_system_noc}, 1830 { } 1831 }; 1832 MODULE_DEVICE_TABLE(of, qnoc_of_match); 1833 1834 static struct platform_driver qnoc_driver = { 1835 .probe = qcom_icc_rpmh_probe, 1836 .remove = qcom_icc_rpmh_remove, 1837 .driver = { 1838 .name = "qnoc-sc7280", 1839 .of_match_table = qnoc_of_match, 1840 .sync_state = icc_sync_state, 1841 }, 1842 }; 1843 module_platform_driver(qnoc_driver); 1844 1845 MODULE_DESCRIPTION("SC7280 NoC driver"); 1846 MODULE_LICENSE("GPL v2"); 1847