1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 * 5 */ 6 7 #include <linux/device.h> 8 #include <linux/interconnect.h> 9 #include <linux/interconnect-provider.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include <dt-bindings/interconnect/qcom,sc7180.h> 13 14 #include "bcm-voter.h" 15 #include "icc-rpmh.h" 16 17 static struct qcom_icc_node qhm_a1noc_cfg; 18 static struct qcom_icc_node qhm_qspi; 19 static struct qcom_icc_node qhm_qup_0; 20 static struct qcom_icc_node xm_sdc2; 21 static struct qcom_icc_node xm_emmc; 22 static struct qcom_icc_node xm_ufs_mem; 23 static struct qcom_icc_node qhm_a2noc_cfg; 24 static struct qcom_icc_node qhm_qdss_bam; 25 static struct qcom_icc_node qhm_qup_1; 26 static struct qcom_icc_node qxm_crypto; 27 static struct qcom_icc_node qxm_ipa; 28 static struct qcom_icc_node xm_qdss_etr; 29 static struct qcom_icc_node qhm_usb3; 30 static struct qcom_icc_node qxm_camnoc_hf0_uncomp; 31 static struct qcom_icc_node qxm_camnoc_hf1_uncomp; 32 static struct qcom_icc_node qxm_camnoc_sf_uncomp; 33 static struct qcom_icc_node qnm_npu; 34 static struct qcom_icc_node qxm_npu_dsp; 35 static struct qcom_icc_node qnm_snoc; 36 static struct qcom_icc_node xm_qdss_dap; 37 static struct qcom_icc_node qhm_cnoc_dc_noc; 38 static struct qcom_icc_node acm_apps0; 39 static struct qcom_icc_node acm_sys_tcu; 40 static struct qcom_icc_node qhm_gemnoc_cfg; 41 static struct qcom_icc_node qnm_cmpnoc; 42 static struct qcom_icc_node qnm_mnoc_hf; 43 static struct qcom_icc_node qnm_mnoc_sf; 44 static struct qcom_icc_node qnm_snoc_gc; 45 static struct qcom_icc_node qnm_snoc_sf; 46 static struct qcom_icc_node qxm_gpu; 47 static struct qcom_icc_node llcc_mc; 48 static struct qcom_icc_node qhm_mnoc_cfg; 49 static struct qcom_icc_node qxm_camnoc_hf0; 50 static struct qcom_icc_node qxm_camnoc_hf1; 51 static struct qcom_icc_node qxm_camnoc_sf; 52 static struct qcom_icc_node qxm_mdp0; 53 static struct qcom_icc_node qxm_rot; 54 static struct qcom_icc_node qxm_venus0; 55 static struct qcom_icc_node qxm_venus_arm9; 56 static struct qcom_icc_node amm_npu_sys; 57 static struct qcom_icc_node qhm_npu_cfg; 58 static struct qcom_icc_node qup_core_master_1; 59 static struct qcom_icc_node qup_core_master_2; 60 static struct qcom_icc_node qhm_snoc_cfg; 61 static struct qcom_icc_node qnm_aggre1_noc; 62 static struct qcom_icc_node qnm_aggre2_noc; 63 static struct qcom_icc_node qnm_gemnoc; 64 static struct qcom_icc_node qxm_pimem; 65 static struct qcom_icc_node qns_a1noc_snoc; 66 static struct qcom_icc_node srvc_aggre1_noc; 67 static struct qcom_icc_node qns_a2noc_snoc; 68 static struct qcom_icc_node srvc_aggre2_noc; 69 static struct qcom_icc_node qns_camnoc_uncomp; 70 static struct qcom_icc_node qns_cdsp_gemnoc; 71 static struct qcom_icc_node qhs_a1_noc_cfg; 72 static struct qcom_icc_node qhs_a2_noc_cfg; 73 static struct qcom_icc_node qhs_ahb2phy0; 74 static struct qcom_icc_node qhs_ahb2phy2; 75 static struct qcom_icc_node qhs_aop; 76 static struct qcom_icc_node qhs_aoss; 77 static struct qcom_icc_node qhs_boot_rom; 78 static struct qcom_icc_node qhs_camera_cfg; 79 static struct qcom_icc_node qhs_camera_nrt_throttle_cfg; 80 static struct qcom_icc_node qhs_camera_rt_throttle_cfg; 81 static struct qcom_icc_node qhs_clk_ctl; 82 static struct qcom_icc_node qhs_cpr_cx; 83 static struct qcom_icc_node qhs_cpr_mx; 84 static struct qcom_icc_node qhs_crypto0_cfg; 85 static struct qcom_icc_node qhs_dcc_cfg; 86 static struct qcom_icc_node qhs_ddrss_cfg; 87 static struct qcom_icc_node qhs_display_cfg; 88 static struct qcom_icc_node qhs_display_rt_throttle_cfg; 89 static struct qcom_icc_node qhs_display_throttle_cfg; 90 static struct qcom_icc_node qhs_emmc_cfg; 91 static struct qcom_icc_node qhs_glm; 92 static struct qcom_icc_node qhs_gpuss_cfg; 93 static struct qcom_icc_node qhs_imem_cfg; 94 static struct qcom_icc_node qhs_ipa; 95 static struct qcom_icc_node qhs_mnoc_cfg; 96 static struct qcom_icc_node qhs_mss_cfg; 97 static struct qcom_icc_node qhs_npu_cfg; 98 static struct qcom_icc_node qhs_npu_dma_throttle_cfg; 99 static struct qcom_icc_node qhs_npu_dsp_throttle_cfg; 100 static struct qcom_icc_node qhs_pdm; 101 static struct qcom_icc_node qhs_pimem_cfg; 102 static struct qcom_icc_node qhs_prng; 103 static struct qcom_icc_node qhs_qdss_cfg; 104 static struct qcom_icc_node qhs_qm_cfg; 105 static struct qcom_icc_node qhs_qm_mpu_cfg; 106 static struct qcom_icc_node qhs_qspi; 107 static struct qcom_icc_node qhs_qup0; 108 static struct qcom_icc_node qhs_qup1; 109 static struct qcom_icc_node qhs_sdc2; 110 static struct qcom_icc_node qhs_security; 111 static struct qcom_icc_node qhs_snoc_cfg; 112 static struct qcom_icc_node qhs_tcsr; 113 static struct qcom_icc_node qhs_tlmm_1; 114 static struct qcom_icc_node qhs_tlmm_2; 115 static struct qcom_icc_node qhs_tlmm_3; 116 static struct qcom_icc_node qhs_ufs_mem_cfg; 117 static struct qcom_icc_node qhs_usb3; 118 static struct qcom_icc_node qhs_venus_cfg; 119 static struct qcom_icc_node qhs_venus_throttle_cfg; 120 static struct qcom_icc_node qhs_vsense_ctrl_cfg; 121 static struct qcom_icc_node srvc_cnoc; 122 static struct qcom_icc_node qhs_gemnoc; 123 static struct qcom_icc_node qhs_llcc; 124 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; 125 static struct qcom_icc_node qns_gem_noc_snoc; 126 static struct qcom_icc_node qns_llcc; 127 static struct qcom_icc_node srvc_gemnoc; 128 static struct qcom_icc_node ebi; 129 static struct qcom_icc_node qns_mem_noc_hf; 130 static struct qcom_icc_node qns_mem_noc_sf; 131 static struct qcom_icc_node srvc_mnoc; 132 static struct qcom_icc_node qhs_cal_dp0; 133 static struct qcom_icc_node qhs_cp; 134 static struct qcom_icc_node qhs_dma_bwmon; 135 static struct qcom_icc_node qhs_dpm; 136 static struct qcom_icc_node qhs_isense; 137 static struct qcom_icc_node qhs_llm; 138 static struct qcom_icc_node qhs_tcm; 139 static struct qcom_icc_node qns_npu_sys; 140 static struct qcom_icc_node srvc_noc; 141 static struct qcom_icc_node qup_core_slave_1; 142 static struct qcom_icc_node qup_core_slave_2; 143 static struct qcom_icc_node qhs_apss; 144 static struct qcom_icc_node qns_cnoc; 145 static struct qcom_icc_node qns_gemnoc_gc; 146 static struct qcom_icc_node qns_gemnoc_sf; 147 static struct qcom_icc_node qxs_imem; 148 static struct qcom_icc_node qxs_pimem; 149 static struct qcom_icc_node srvc_snoc; 150 static struct qcom_icc_node xs_qdss_stm; 151 static struct qcom_icc_node xs_sys_tcu_cfg; 152 153 static struct qcom_icc_node qhm_a1noc_cfg = { 154 .name = "qhm_a1noc_cfg", 155 .channels = 1, 156 .buswidth = 4, 157 .num_links = 1, 158 .link_nodes = { &srvc_aggre1_noc }, 159 }; 160 161 static struct qcom_icc_node qhm_qspi = { 162 .name = "qhm_qspi", 163 .channels = 1, 164 .buswidth = 4, 165 .num_links = 1, 166 .link_nodes = { &qns_a1noc_snoc }, 167 }; 168 169 static struct qcom_icc_node qhm_qup_0 = { 170 .name = "qhm_qup_0", 171 .channels = 1, 172 .buswidth = 4, 173 .num_links = 1, 174 .link_nodes = { &qns_a1noc_snoc }, 175 }; 176 177 static struct qcom_icc_node xm_sdc2 = { 178 .name = "xm_sdc2", 179 .channels = 1, 180 .buswidth = 8, 181 .num_links = 1, 182 .link_nodes = { &qns_a1noc_snoc }, 183 }; 184 185 static struct qcom_icc_node xm_emmc = { 186 .name = "xm_emmc", 187 .channels = 1, 188 .buswidth = 8, 189 .num_links = 1, 190 .link_nodes = { &qns_a1noc_snoc }, 191 }; 192 193 static struct qcom_icc_node xm_ufs_mem = { 194 .name = "xm_ufs_mem", 195 .channels = 1, 196 .buswidth = 8, 197 .num_links = 1, 198 .link_nodes = { &qns_a1noc_snoc }, 199 }; 200 201 static struct qcom_icc_node qhm_a2noc_cfg = { 202 .name = "qhm_a2noc_cfg", 203 .channels = 1, 204 .buswidth = 4, 205 .num_links = 1, 206 .link_nodes = { &srvc_aggre2_noc }, 207 }; 208 209 static struct qcom_icc_node qhm_qdss_bam = { 210 .name = "qhm_qdss_bam", 211 .channels = 1, 212 .buswidth = 4, 213 .num_links = 1, 214 .link_nodes = { &qns_a2noc_snoc }, 215 }; 216 217 static struct qcom_icc_node qhm_qup_1 = { 218 .name = "qhm_qup_1", 219 .channels = 1, 220 .buswidth = 4, 221 .num_links = 1, 222 .link_nodes = { &qns_a2noc_snoc }, 223 }; 224 225 static struct qcom_icc_node qxm_crypto = { 226 .name = "qxm_crypto", 227 .channels = 1, 228 .buswidth = 8, 229 .num_links = 1, 230 .link_nodes = { &qns_a2noc_snoc }, 231 }; 232 233 static struct qcom_icc_node qxm_ipa = { 234 .name = "qxm_ipa", 235 .channels = 1, 236 .buswidth = 8, 237 .num_links = 1, 238 .link_nodes = { &qns_a2noc_snoc }, 239 }; 240 241 static struct qcom_icc_node xm_qdss_etr = { 242 .name = "xm_qdss_etr", 243 .channels = 1, 244 .buswidth = 8, 245 .num_links = 1, 246 .link_nodes = { &qns_a2noc_snoc }, 247 }; 248 249 static struct qcom_icc_node qhm_usb3 = { 250 .name = "qhm_usb3", 251 .channels = 1, 252 .buswidth = 8, 253 .num_links = 1, 254 .link_nodes = { &qns_a2noc_snoc }, 255 }; 256 257 static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { 258 .name = "qxm_camnoc_hf0_uncomp", 259 .channels = 1, 260 .buswidth = 32, 261 .num_links = 1, 262 .link_nodes = { &qns_camnoc_uncomp }, 263 }; 264 265 static struct qcom_icc_node qxm_camnoc_hf1_uncomp = { 266 .name = "qxm_camnoc_hf1_uncomp", 267 .channels = 1, 268 .buswidth = 32, 269 .num_links = 1, 270 .link_nodes = { &qns_camnoc_uncomp }, 271 }; 272 273 static struct qcom_icc_node qxm_camnoc_sf_uncomp = { 274 .name = "qxm_camnoc_sf_uncomp", 275 .channels = 1, 276 .buswidth = 32, 277 .num_links = 1, 278 .link_nodes = { &qns_camnoc_uncomp }, 279 }; 280 281 static struct qcom_icc_node qnm_npu = { 282 .name = "qnm_npu", 283 .channels = 2, 284 .buswidth = 32, 285 .num_links = 1, 286 .link_nodes = { &qns_cdsp_gemnoc }, 287 }; 288 289 static struct qcom_icc_node qxm_npu_dsp = { 290 .name = "qxm_npu_dsp", 291 .channels = 1, 292 .buswidth = 8, 293 .num_links = 1, 294 .link_nodes = { &qns_cdsp_gemnoc }, 295 }; 296 297 static struct qcom_icc_node qnm_snoc = { 298 .name = "qnm_snoc", 299 .channels = 1, 300 .buswidth = 8, 301 .num_links = 51, 302 .link_nodes = { &qhs_a1_noc_cfg, 303 &qhs_a2_noc_cfg, 304 &qhs_ahb2phy0, 305 &qhs_ahb2phy2, 306 &qhs_aop, 307 &qhs_aoss, 308 &qhs_boot_rom, 309 &qhs_camera_cfg, 310 &qhs_camera_nrt_throttle_cfg, 311 &qhs_camera_rt_throttle_cfg, 312 &qhs_clk_ctl, 313 &qhs_cpr_cx, 314 &qhs_cpr_mx, 315 &qhs_crypto0_cfg, 316 &qhs_dcc_cfg, 317 &qhs_ddrss_cfg, 318 &qhs_display_cfg, 319 &qhs_display_rt_throttle_cfg, 320 &qhs_display_throttle_cfg, 321 &qhs_emmc_cfg, 322 &qhs_glm, 323 &qhs_gpuss_cfg, 324 &qhs_imem_cfg, 325 &qhs_ipa, 326 &qhs_mnoc_cfg, 327 &qhs_mss_cfg, 328 &qhs_npu_cfg, 329 &qhs_npu_dma_throttle_cfg, 330 &qhs_npu_dsp_throttle_cfg, 331 &qhs_pdm, 332 &qhs_pimem_cfg, 333 &qhs_prng, 334 &qhs_qdss_cfg, 335 &qhs_qm_cfg, 336 &qhs_qm_mpu_cfg, 337 &qhs_qspi, 338 &qhs_qup0, 339 &qhs_qup1, 340 &qhs_sdc2, 341 &qhs_security, 342 &qhs_snoc_cfg, 343 &qhs_tcsr, 344 &qhs_tlmm_1, 345 &qhs_tlmm_2, 346 &qhs_tlmm_3, 347 &qhs_ufs_mem_cfg, 348 &qhs_usb3, 349 &qhs_venus_cfg, 350 &qhs_venus_throttle_cfg, 351 &qhs_vsense_ctrl_cfg, 352 &srvc_cnoc }, 353 }; 354 355 static struct qcom_icc_node xm_qdss_dap = { 356 .name = "xm_qdss_dap", 357 .channels = 1, 358 .buswidth = 8, 359 .num_links = 51, 360 .link_nodes = { &qhs_a1_noc_cfg, 361 &qhs_a2_noc_cfg, 362 &qhs_ahb2phy0, 363 &qhs_ahb2phy2, 364 &qhs_aop, 365 &qhs_aoss, 366 &qhs_boot_rom, 367 &qhs_camera_cfg, 368 &qhs_camera_nrt_throttle_cfg, 369 &qhs_camera_rt_throttle_cfg, 370 &qhs_clk_ctl, 371 &qhs_cpr_cx, 372 &qhs_cpr_mx, 373 &qhs_crypto0_cfg, 374 &qhs_dcc_cfg, 375 &qhs_ddrss_cfg, 376 &qhs_display_cfg, 377 &qhs_display_rt_throttle_cfg, 378 &qhs_display_throttle_cfg, 379 &qhs_emmc_cfg, 380 &qhs_glm, 381 &qhs_gpuss_cfg, 382 &qhs_imem_cfg, 383 &qhs_ipa, 384 &qhs_mnoc_cfg, 385 &qhs_mss_cfg, 386 &qhs_npu_cfg, 387 &qhs_npu_dma_throttle_cfg, 388 &qhs_npu_dsp_throttle_cfg, 389 &qhs_pdm, 390 &qhs_pimem_cfg, 391 &qhs_prng, 392 &qhs_qdss_cfg, 393 &qhs_qm_cfg, 394 &qhs_qm_mpu_cfg, 395 &qhs_qspi, 396 &qhs_qup0, 397 &qhs_qup1, 398 &qhs_sdc2, 399 &qhs_security, 400 &qhs_snoc_cfg, 401 &qhs_tcsr, 402 &qhs_tlmm_1, 403 &qhs_tlmm_2, 404 &qhs_tlmm_3, 405 &qhs_ufs_mem_cfg, 406 &qhs_usb3, 407 &qhs_venus_cfg, 408 &qhs_venus_throttle_cfg, 409 &qhs_vsense_ctrl_cfg, 410 &srvc_cnoc }, 411 }; 412 413 static struct qcom_icc_node qhm_cnoc_dc_noc = { 414 .name = "qhm_cnoc_dc_noc", 415 .channels = 1, 416 .buswidth = 4, 417 .num_links = 2, 418 .link_nodes = { &qhs_gemnoc, 419 &qhs_llcc }, 420 }; 421 422 static struct qcom_icc_node acm_apps0 = { 423 .name = "acm_apps0", 424 .channels = 1, 425 .buswidth = 16, 426 .num_links = 2, 427 .link_nodes = { &qns_gem_noc_snoc, 428 &qns_llcc }, 429 }; 430 431 static struct qcom_icc_node acm_sys_tcu = { 432 .name = "acm_sys_tcu", 433 .channels = 1, 434 .buswidth = 8, 435 .num_links = 2, 436 .link_nodes = { &qns_gem_noc_snoc, 437 &qns_llcc }, 438 }; 439 440 static struct qcom_icc_node qhm_gemnoc_cfg = { 441 .name = "qhm_gemnoc_cfg", 442 .channels = 1, 443 .buswidth = 4, 444 .num_links = 2, 445 .link_nodes = { &qhs_mdsp_ms_mpu_cfg, 446 &srvc_gemnoc }, 447 }; 448 449 static struct qcom_icc_node qnm_cmpnoc = { 450 .name = "qnm_cmpnoc", 451 .channels = 1, 452 .buswidth = 32, 453 .num_links = 2, 454 .link_nodes = { &qns_gem_noc_snoc, 455 &qns_llcc }, 456 }; 457 458 static struct qcom_icc_node qnm_mnoc_hf = { 459 .name = "qnm_mnoc_hf", 460 .channels = 1, 461 .buswidth = 32, 462 .num_links = 1, 463 .link_nodes = { &qns_llcc }, 464 }; 465 466 static struct qcom_icc_node qnm_mnoc_sf = { 467 .name = "qnm_mnoc_sf", 468 .channels = 1, 469 .buswidth = 32, 470 .num_links = 2, 471 .link_nodes = { &qns_gem_noc_snoc, 472 &qns_llcc }, 473 }; 474 475 static struct qcom_icc_node qnm_snoc_gc = { 476 .name = "qnm_snoc_gc", 477 .channels = 1, 478 .buswidth = 8, 479 .num_links = 1, 480 .link_nodes = { &qns_llcc }, 481 }; 482 483 static struct qcom_icc_node qnm_snoc_sf = { 484 .name = "qnm_snoc_sf", 485 .channels = 1, 486 .buswidth = 16, 487 .num_links = 1, 488 .link_nodes = { &qns_llcc }, 489 }; 490 491 static struct qcom_icc_node qxm_gpu = { 492 .name = "qxm_gpu", 493 .channels = 2, 494 .buswidth = 32, 495 .num_links = 2, 496 .link_nodes = { &qns_gem_noc_snoc, 497 &qns_llcc }, 498 }; 499 500 static struct qcom_icc_node llcc_mc = { 501 .name = "llcc_mc", 502 .channels = 2, 503 .buswidth = 4, 504 .num_links = 1, 505 .link_nodes = { &ebi }, 506 }; 507 508 static struct qcom_icc_node qhm_mnoc_cfg = { 509 .name = "qhm_mnoc_cfg", 510 .channels = 1, 511 .buswidth = 4, 512 .num_links = 1, 513 .link_nodes = { &srvc_mnoc }, 514 }; 515 516 static struct qcom_icc_node qxm_camnoc_hf0 = { 517 .name = "qxm_camnoc_hf0", 518 .channels = 2, 519 .buswidth = 32, 520 .num_links = 1, 521 .link_nodes = { &qns_mem_noc_hf }, 522 }; 523 524 static struct qcom_icc_node qxm_camnoc_hf1 = { 525 .name = "qxm_camnoc_hf1", 526 .channels = 2, 527 .buswidth = 32, 528 .num_links = 1, 529 .link_nodes = { &qns_mem_noc_hf }, 530 }; 531 532 static struct qcom_icc_node qxm_camnoc_sf = { 533 .name = "qxm_camnoc_sf", 534 .channels = 1, 535 .buswidth = 32, 536 .num_links = 1, 537 .link_nodes = { &qns_mem_noc_sf }, 538 }; 539 540 static struct qcom_icc_node qxm_mdp0 = { 541 .name = "qxm_mdp0", 542 .channels = 1, 543 .buswidth = 32, 544 .num_links = 1, 545 .link_nodes = { &qns_mem_noc_hf }, 546 }; 547 548 static struct qcom_icc_node qxm_rot = { 549 .name = "qxm_rot", 550 .channels = 1, 551 .buswidth = 16, 552 .num_links = 1, 553 .link_nodes = { &qns_mem_noc_sf }, 554 }; 555 556 static struct qcom_icc_node qxm_venus0 = { 557 .name = "qxm_venus0", 558 .channels = 1, 559 .buswidth = 32, 560 .num_links = 1, 561 .link_nodes = { &qns_mem_noc_sf }, 562 }; 563 564 static struct qcom_icc_node qxm_venus_arm9 = { 565 .name = "qxm_venus_arm9", 566 .channels = 1, 567 .buswidth = 8, 568 .num_links = 1, 569 .link_nodes = { &qns_mem_noc_sf }, 570 }; 571 572 static struct qcom_icc_node amm_npu_sys = { 573 .name = "amm_npu_sys", 574 .channels = 2, 575 .buswidth = 32, 576 .num_links = 1, 577 .link_nodes = { &qns_npu_sys }, 578 }; 579 580 static struct qcom_icc_node qhm_npu_cfg = { 581 .name = "qhm_npu_cfg", 582 .channels = 1, 583 .buswidth = 4, 584 .num_links = 8, 585 .link_nodes = { &qhs_cal_dp0, 586 &qhs_cp, 587 &qhs_dma_bwmon, 588 &qhs_dpm, 589 &qhs_isense, 590 &qhs_llm, 591 &qhs_tcm, 592 &srvc_noc }, 593 }; 594 595 static struct qcom_icc_node qup_core_master_1 = { 596 .name = "qup_core_master_1", 597 .channels = 1, 598 .buswidth = 4, 599 .num_links = 1, 600 .link_nodes = { &qup_core_slave_1 }, 601 }; 602 603 static struct qcom_icc_node qup_core_master_2 = { 604 .name = "qup_core_master_2", 605 .channels = 1, 606 .buswidth = 4, 607 .num_links = 1, 608 .link_nodes = { &qup_core_slave_2 }, 609 }; 610 611 static struct qcom_icc_node qhm_snoc_cfg = { 612 .name = "qhm_snoc_cfg", 613 .channels = 1, 614 .buswidth = 4, 615 .num_links = 1, 616 .link_nodes = { &srvc_snoc }, 617 }; 618 619 static struct qcom_icc_node qnm_aggre1_noc = { 620 .name = "qnm_aggre1_noc", 621 .channels = 1, 622 .buswidth = 16, 623 .num_links = 6, 624 .link_nodes = { &qhs_apss, 625 &qns_cnoc, 626 &qns_gemnoc_sf, 627 &qxs_imem, 628 &qxs_pimem, 629 &xs_qdss_stm }, 630 }; 631 632 static struct qcom_icc_node qnm_aggre2_noc = { 633 .name = "qnm_aggre2_noc", 634 .channels = 1, 635 .buswidth = 16, 636 .num_links = 7, 637 .link_nodes = { &qhs_apss, 638 &qns_cnoc, 639 &qns_gemnoc_sf, 640 &qxs_imem, 641 &qxs_pimem, 642 &xs_qdss_stm, 643 &xs_sys_tcu_cfg }, 644 }; 645 646 static struct qcom_icc_node qnm_gemnoc = { 647 .name = "qnm_gemnoc", 648 .channels = 1, 649 .buswidth = 8, 650 .num_links = 6, 651 .link_nodes = { &qhs_apss, 652 &qns_cnoc, 653 &qxs_imem, 654 &qxs_pimem, 655 &xs_qdss_stm, 656 &xs_sys_tcu_cfg }, 657 }; 658 659 static struct qcom_icc_node qxm_pimem = { 660 .name = "qxm_pimem", 661 .channels = 1, 662 .buswidth = 8, 663 .num_links = 2, 664 .link_nodes = { &qns_gemnoc_gc, 665 &qxs_imem }, 666 }; 667 668 static struct qcom_icc_node qns_a1noc_snoc = { 669 .name = "qns_a1noc_snoc", 670 .channels = 1, 671 .buswidth = 16, 672 .num_links = 1, 673 .link_nodes = { &qnm_aggre1_noc }, 674 }; 675 676 static struct qcom_icc_node srvc_aggre1_noc = { 677 .name = "srvc_aggre1_noc", 678 .channels = 1, 679 .buswidth = 4, 680 }; 681 682 static struct qcom_icc_node qns_a2noc_snoc = { 683 .name = "qns_a2noc_snoc", 684 .channels = 1, 685 .buswidth = 16, 686 .num_links = 1, 687 .link_nodes = { &qnm_aggre2_noc }, 688 }; 689 690 static struct qcom_icc_node srvc_aggre2_noc = { 691 .name = "srvc_aggre2_noc", 692 .channels = 1, 693 .buswidth = 4, 694 }; 695 696 static struct qcom_icc_node qns_camnoc_uncomp = { 697 .name = "qns_camnoc_uncomp", 698 .channels = 1, 699 .buswidth = 32, 700 }; 701 702 static struct qcom_icc_node qns_cdsp_gemnoc = { 703 .name = "qns_cdsp_gemnoc", 704 .channels = 1, 705 .buswidth = 32, 706 .num_links = 1, 707 .link_nodes = { &qnm_cmpnoc }, 708 }; 709 710 static struct qcom_icc_node qhs_a1_noc_cfg = { 711 .name = "qhs_a1_noc_cfg", 712 .channels = 1, 713 .buswidth = 4, 714 .num_links = 1, 715 .link_nodes = { &qhm_a1noc_cfg }, 716 }; 717 718 static struct qcom_icc_node qhs_a2_noc_cfg = { 719 .name = "qhs_a2_noc_cfg", 720 .channels = 1, 721 .buswidth = 4, 722 .num_links = 1, 723 .link_nodes = { &qhm_a2noc_cfg }, 724 }; 725 726 static struct qcom_icc_node qhs_ahb2phy0 = { 727 .name = "qhs_ahb2phy0", 728 .channels = 1, 729 .buswidth = 4, 730 }; 731 732 static struct qcom_icc_node qhs_ahb2phy2 = { 733 .name = "qhs_ahb2phy2", 734 .channels = 1, 735 .buswidth = 4, 736 }; 737 738 static struct qcom_icc_node qhs_aop = { 739 .name = "qhs_aop", 740 .channels = 1, 741 .buswidth = 4, 742 }; 743 744 static struct qcom_icc_node qhs_aoss = { 745 .name = "qhs_aoss", 746 .channels = 1, 747 .buswidth = 4, 748 }; 749 750 static struct qcom_icc_node qhs_boot_rom = { 751 .name = "qhs_boot_rom", 752 .channels = 1, 753 .buswidth = 4, 754 }; 755 756 static struct qcom_icc_node qhs_camera_cfg = { 757 .name = "qhs_camera_cfg", 758 .channels = 1, 759 .buswidth = 4, 760 }; 761 762 static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = { 763 .name = "qhs_camera_nrt_throttle_cfg", 764 .channels = 1, 765 .buswidth = 4, 766 }; 767 768 static struct qcom_icc_node qhs_camera_rt_throttle_cfg = { 769 .name = "qhs_camera_rt_throttle_cfg", 770 .channels = 1, 771 .buswidth = 4, 772 }; 773 774 static struct qcom_icc_node qhs_clk_ctl = { 775 .name = "qhs_clk_ctl", 776 .channels = 1, 777 .buswidth = 4, 778 }; 779 780 static struct qcom_icc_node qhs_cpr_cx = { 781 .name = "qhs_cpr_cx", 782 .channels = 1, 783 .buswidth = 4, 784 }; 785 786 static struct qcom_icc_node qhs_cpr_mx = { 787 .name = "qhs_cpr_mx", 788 .channels = 1, 789 .buswidth = 4, 790 }; 791 792 static struct qcom_icc_node qhs_crypto0_cfg = { 793 .name = "qhs_crypto0_cfg", 794 .channels = 1, 795 .buswidth = 4, 796 }; 797 798 static struct qcom_icc_node qhs_dcc_cfg = { 799 .name = "qhs_dcc_cfg", 800 .channels = 1, 801 .buswidth = 4, 802 }; 803 804 static struct qcom_icc_node qhs_ddrss_cfg = { 805 .name = "qhs_ddrss_cfg", 806 .channels = 1, 807 .buswidth = 4, 808 .num_links = 1, 809 .link_nodes = { &qhm_cnoc_dc_noc }, 810 }; 811 812 static struct qcom_icc_node qhs_display_cfg = { 813 .name = "qhs_display_cfg", 814 .channels = 1, 815 .buswidth = 4, 816 }; 817 818 static struct qcom_icc_node qhs_display_rt_throttle_cfg = { 819 .name = "qhs_display_rt_throttle_cfg", 820 .channels = 1, 821 .buswidth = 4, 822 }; 823 824 static struct qcom_icc_node qhs_display_throttle_cfg = { 825 .name = "qhs_display_throttle_cfg", 826 .channels = 1, 827 .buswidth = 4, 828 }; 829 830 static struct qcom_icc_node qhs_emmc_cfg = { 831 .name = "qhs_emmc_cfg", 832 .channels = 1, 833 .buswidth = 4, 834 }; 835 836 static struct qcom_icc_node qhs_glm = { 837 .name = "qhs_glm", 838 .channels = 1, 839 .buswidth = 4, 840 }; 841 842 static struct qcom_icc_node qhs_gpuss_cfg = { 843 .name = "qhs_gpuss_cfg", 844 .channels = 1, 845 .buswidth = 8, 846 }; 847 848 static struct qcom_icc_node qhs_imem_cfg = { 849 .name = "qhs_imem_cfg", 850 .channels = 1, 851 .buswidth = 4, 852 }; 853 854 static struct qcom_icc_node qhs_ipa = { 855 .name = "qhs_ipa", 856 .channels = 1, 857 .buswidth = 4, 858 }; 859 860 static struct qcom_icc_node qhs_mnoc_cfg = { 861 .name = "qhs_mnoc_cfg", 862 .channels = 1, 863 .buswidth = 4, 864 .num_links = 1, 865 .link_nodes = { &qhm_mnoc_cfg }, 866 }; 867 868 static struct qcom_icc_node qhs_mss_cfg = { 869 .name = "qhs_mss_cfg", 870 .channels = 1, 871 .buswidth = 4, 872 }; 873 874 static struct qcom_icc_node qhs_npu_cfg = { 875 .name = "qhs_npu_cfg", 876 .channels = 1, 877 .buswidth = 4, 878 .num_links = 1, 879 .link_nodes = { &qhm_npu_cfg }, 880 }; 881 882 static struct qcom_icc_node qhs_npu_dma_throttle_cfg = { 883 .name = "qhs_npu_dma_throttle_cfg", 884 .channels = 1, 885 .buswidth = 4, 886 }; 887 888 static struct qcom_icc_node qhs_npu_dsp_throttle_cfg = { 889 .name = "qhs_npu_dsp_throttle_cfg", 890 .channels = 1, 891 .buswidth = 4, 892 }; 893 894 static struct qcom_icc_node qhs_pdm = { 895 .name = "qhs_pdm", 896 .channels = 1, 897 .buswidth = 4, 898 }; 899 900 static struct qcom_icc_node qhs_pimem_cfg = { 901 .name = "qhs_pimem_cfg", 902 .channels = 1, 903 .buswidth = 4, 904 }; 905 906 static struct qcom_icc_node qhs_prng = { 907 .name = "qhs_prng", 908 .channels = 1, 909 .buswidth = 4, 910 }; 911 912 static struct qcom_icc_node qhs_qdss_cfg = { 913 .name = "qhs_qdss_cfg", 914 .channels = 1, 915 .buswidth = 4, 916 }; 917 918 static struct qcom_icc_node qhs_qm_cfg = { 919 .name = "qhs_qm_cfg", 920 .channels = 1, 921 .buswidth = 4, 922 }; 923 924 static struct qcom_icc_node qhs_qm_mpu_cfg = { 925 .name = "qhs_qm_mpu_cfg", 926 .channels = 1, 927 .buswidth = 4, 928 }; 929 930 static struct qcom_icc_node qhs_qspi = { 931 .name = "qhs_qspi", 932 .channels = 1, 933 .buswidth = 4, 934 }; 935 936 static struct qcom_icc_node qhs_qup0 = { 937 .name = "qhs_qup0", 938 .channels = 1, 939 .buswidth = 4, 940 }; 941 942 static struct qcom_icc_node qhs_qup1 = { 943 .name = "qhs_qup1", 944 .channels = 1, 945 .buswidth = 4, 946 }; 947 948 static struct qcom_icc_node qhs_sdc2 = { 949 .name = "qhs_sdc2", 950 .channels = 1, 951 .buswidth = 4, 952 }; 953 954 static struct qcom_icc_node qhs_security = { 955 .name = "qhs_security", 956 .channels = 1, 957 .buswidth = 4, 958 }; 959 960 static struct qcom_icc_node qhs_snoc_cfg = { 961 .name = "qhs_snoc_cfg", 962 .channels = 1, 963 .buswidth = 4, 964 .num_links = 1, 965 .link_nodes = { &qhm_snoc_cfg }, 966 }; 967 968 static struct qcom_icc_node qhs_tcsr = { 969 .name = "qhs_tcsr", 970 .channels = 1, 971 .buswidth = 4, 972 }; 973 974 static struct qcom_icc_node qhs_tlmm_1 = { 975 .name = "qhs_tlmm_1", 976 .channels = 1, 977 .buswidth = 4, 978 }; 979 980 static struct qcom_icc_node qhs_tlmm_2 = { 981 .name = "qhs_tlmm_2", 982 .channels = 1, 983 .buswidth = 4, 984 }; 985 986 static struct qcom_icc_node qhs_tlmm_3 = { 987 .name = "qhs_tlmm_3", 988 .channels = 1, 989 .buswidth = 4, 990 }; 991 992 static struct qcom_icc_node qhs_ufs_mem_cfg = { 993 .name = "qhs_ufs_mem_cfg", 994 .channels = 1, 995 .buswidth = 4, 996 }; 997 998 static struct qcom_icc_node qhs_usb3 = { 999 .name = "qhs_usb3", 1000 .channels = 1, 1001 .buswidth = 4, 1002 }; 1003 1004 static struct qcom_icc_node qhs_venus_cfg = { 1005 .name = "qhs_venus_cfg", 1006 .channels = 1, 1007 .buswidth = 4, 1008 }; 1009 1010 static struct qcom_icc_node qhs_venus_throttle_cfg = { 1011 .name = "qhs_venus_throttle_cfg", 1012 .channels = 1, 1013 .buswidth = 4, 1014 }; 1015 1016 static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 1017 .name = "qhs_vsense_ctrl_cfg", 1018 .channels = 1, 1019 .buswidth = 4, 1020 }; 1021 1022 static struct qcom_icc_node srvc_cnoc = { 1023 .name = "srvc_cnoc", 1024 .channels = 1, 1025 .buswidth = 4, 1026 }; 1027 1028 static struct qcom_icc_node qhs_gemnoc = { 1029 .name = "qhs_gemnoc", 1030 .channels = 1, 1031 .buswidth = 4, 1032 .num_links = 1, 1033 .link_nodes = { &qhm_gemnoc_cfg }, 1034 }; 1035 1036 static struct qcom_icc_node qhs_llcc = { 1037 .name = "qhs_llcc", 1038 .channels = 1, 1039 .buswidth = 4, 1040 }; 1041 1042 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { 1043 .name = "qhs_mdsp_ms_mpu_cfg", 1044 .channels = 1, 1045 .buswidth = 4, 1046 }; 1047 1048 static struct qcom_icc_node qns_gem_noc_snoc = { 1049 .name = "qns_gem_noc_snoc", 1050 .channels = 1, 1051 .buswidth = 8, 1052 .num_links = 1, 1053 .link_nodes = { &qnm_gemnoc }, 1054 }; 1055 1056 static struct qcom_icc_node qns_llcc = { 1057 .name = "qns_llcc", 1058 .channels = 1, 1059 .buswidth = 16, 1060 .num_links = 1, 1061 .link_nodes = { &llcc_mc }, 1062 }; 1063 1064 static struct qcom_icc_node srvc_gemnoc = { 1065 .name = "srvc_gemnoc", 1066 .channels = 1, 1067 .buswidth = 4, 1068 }; 1069 1070 static struct qcom_icc_node ebi = { 1071 .name = "ebi", 1072 .channels = 2, 1073 .buswidth = 4, 1074 }; 1075 1076 static struct qcom_icc_node qns_mem_noc_hf = { 1077 .name = "qns_mem_noc_hf", 1078 .channels = 1, 1079 .buswidth = 32, 1080 .num_links = 1, 1081 .link_nodes = { &qnm_mnoc_hf }, 1082 }; 1083 1084 static struct qcom_icc_node qns_mem_noc_sf = { 1085 .name = "qns_mem_noc_sf", 1086 .channels = 1, 1087 .buswidth = 32, 1088 .num_links = 1, 1089 .link_nodes = { &qnm_mnoc_sf }, 1090 }; 1091 1092 static struct qcom_icc_node srvc_mnoc = { 1093 .name = "srvc_mnoc", 1094 .channels = 1, 1095 .buswidth = 4, 1096 }; 1097 1098 static struct qcom_icc_node qhs_cal_dp0 = { 1099 .name = "qhs_cal_dp0", 1100 .channels = 1, 1101 .buswidth = 4, 1102 }; 1103 1104 static struct qcom_icc_node qhs_cp = { 1105 .name = "qhs_cp", 1106 .channels = 1, 1107 .buswidth = 4, 1108 }; 1109 1110 static struct qcom_icc_node qhs_dma_bwmon = { 1111 .name = "qhs_dma_bwmon", 1112 .channels = 1, 1113 .buswidth = 4, 1114 }; 1115 1116 static struct qcom_icc_node qhs_dpm = { 1117 .name = "qhs_dpm", 1118 .channels = 1, 1119 .buswidth = 4, 1120 }; 1121 1122 static struct qcom_icc_node qhs_isense = { 1123 .name = "qhs_isense", 1124 .channels = 1, 1125 .buswidth = 4, 1126 }; 1127 1128 static struct qcom_icc_node qhs_llm = { 1129 .name = "qhs_llm", 1130 .channels = 1, 1131 .buswidth = 4, 1132 }; 1133 1134 static struct qcom_icc_node qhs_tcm = { 1135 .name = "qhs_tcm", 1136 .channels = 1, 1137 .buswidth = 4, 1138 }; 1139 1140 static struct qcom_icc_node qns_npu_sys = { 1141 .name = "qns_npu_sys", 1142 .channels = 2, 1143 .buswidth = 32, 1144 }; 1145 1146 static struct qcom_icc_node srvc_noc = { 1147 .name = "srvc_noc", 1148 .channels = 1, 1149 .buswidth = 4, 1150 }; 1151 1152 static struct qcom_icc_node qup_core_slave_1 = { 1153 .name = "qup_core_slave_1", 1154 .channels = 1, 1155 .buswidth = 4, 1156 }; 1157 1158 static struct qcom_icc_node qup_core_slave_2 = { 1159 .name = "qup_core_slave_2", 1160 .channels = 1, 1161 .buswidth = 4, 1162 }; 1163 1164 static struct qcom_icc_node qhs_apss = { 1165 .name = "qhs_apss", 1166 .channels = 1, 1167 .buswidth = 8, 1168 }; 1169 1170 static struct qcom_icc_node qns_cnoc = { 1171 .name = "qns_cnoc", 1172 .channels = 1, 1173 .buswidth = 8, 1174 .num_links = 1, 1175 .link_nodes = { &qnm_snoc }, 1176 }; 1177 1178 static struct qcom_icc_node qns_gemnoc_gc = { 1179 .name = "qns_gemnoc_gc", 1180 .channels = 1, 1181 .buswidth = 8, 1182 .num_links = 1, 1183 .link_nodes = { &qnm_snoc_gc }, 1184 }; 1185 1186 static struct qcom_icc_node qns_gemnoc_sf = { 1187 .name = "qns_gemnoc_sf", 1188 .channels = 1, 1189 .buswidth = 16, 1190 .num_links = 1, 1191 .link_nodes = { &qnm_snoc_sf }, 1192 }; 1193 1194 static struct qcom_icc_node qxs_imem = { 1195 .name = "qxs_imem", 1196 .channels = 1, 1197 .buswidth = 8, 1198 }; 1199 1200 static struct qcom_icc_node qxs_pimem = { 1201 .name = "qxs_pimem", 1202 .channels = 1, 1203 .buswidth = 8, 1204 }; 1205 1206 static struct qcom_icc_node srvc_snoc = { 1207 .name = "srvc_snoc", 1208 .channels = 1, 1209 .buswidth = 4, 1210 }; 1211 1212 static struct qcom_icc_node xs_qdss_stm = { 1213 .name = "xs_qdss_stm", 1214 .channels = 1, 1215 .buswidth = 4, 1216 }; 1217 1218 static struct qcom_icc_node xs_sys_tcu_cfg = { 1219 .name = "xs_sys_tcu_cfg", 1220 .channels = 1, 1221 .buswidth = 8, 1222 }; 1223 1224 static struct qcom_icc_bcm bcm_acv = { 1225 .name = "ACV", 1226 .enable_mask = BIT(3), 1227 .keepalive = false, 1228 .num_nodes = 1, 1229 .nodes = { &ebi }, 1230 }; 1231 1232 static struct qcom_icc_bcm bcm_mc0 = { 1233 .name = "MC0", 1234 .keepalive = true, 1235 .num_nodes = 1, 1236 .nodes = { &ebi }, 1237 }; 1238 1239 static struct qcom_icc_bcm bcm_sh0 = { 1240 .name = "SH0", 1241 .keepalive = true, 1242 .num_nodes = 1, 1243 .nodes = { &qns_llcc }, 1244 }; 1245 1246 static struct qcom_icc_bcm bcm_mm0 = { 1247 .name = "MM0", 1248 .keepalive = false, 1249 .num_nodes = 1, 1250 .nodes = { &qns_mem_noc_hf }, 1251 }; 1252 1253 static struct qcom_icc_bcm bcm_ce0 = { 1254 .name = "CE0", 1255 .keepalive = false, 1256 .num_nodes = 1, 1257 .nodes = { &qxm_crypto }, 1258 }; 1259 1260 static struct qcom_icc_bcm bcm_cn0 = { 1261 .name = "CN0", 1262 .keepalive = true, 1263 .num_nodes = 48, 1264 .nodes = { &qnm_snoc, 1265 &xm_qdss_dap, 1266 &qhs_a1_noc_cfg, 1267 &qhs_a2_noc_cfg, 1268 &qhs_ahb2phy0, 1269 &qhs_aop, 1270 &qhs_aoss, 1271 &qhs_boot_rom, 1272 &qhs_camera_cfg, 1273 &qhs_camera_nrt_throttle_cfg, 1274 &qhs_camera_rt_throttle_cfg, 1275 &qhs_clk_ctl, 1276 &qhs_cpr_cx, 1277 &qhs_cpr_mx, 1278 &qhs_crypto0_cfg, 1279 &qhs_dcc_cfg, 1280 &qhs_ddrss_cfg, 1281 &qhs_display_cfg, 1282 &qhs_display_rt_throttle_cfg, 1283 &qhs_display_throttle_cfg, 1284 &qhs_glm, 1285 &qhs_gpuss_cfg, 1286 &qhs_imem_cfg, 1287 &qhs_ipa, 1288 &qhs_mnoc_cfg, 1289 &qhs_mss_cfg, 1290 &qhs_npu_cfg, 1291 &qhs_npu_dma_throttle_cfg, 1292 &qhs_npu_dsp_throttle_cfg, 1293 &qhs_pimem_cfg, 1294 &qhs_prng, 1295 &qhs_qdss_cfg, 1296 &qhs_qm_cfg, 1297 &qhs_qm_mpu_cfg, 1298 &qhs_qup0, 1299 &qhs_qup1, 1300 &qhs_security, 1301 &qhs_snoc_cfg, 1302 &qhs_tcsr, 1303 &qhs_tlmm_1, 1304 &qhs_tlmm_2, 1305 &qhs_tlmm_3, 1306 &qhs_ufs_mem_cfg, 1307 &qhs_usb3, 1308 &qhs_venus_cfg, 1309 &qhs_venus_throttle_cfg, 1310 &qhs_vsense_ctrl_cfg, 1311 &srvc_cnoc 1312 }, 1313 }; 1314 1315 static struct qcom_icc_bcm bcm_mm1 = { 1316 .name = "MM1", 1317 .keepalive = false, 1318 .num_nodes = 8, 1319 .nodes = { &qxm_camnoc_hf0_uncomp, 1320 &qxm_camnoc_hf1_uncomp, 1321 &qxm_camnoc_sf_uncomp, 1322 &qhm_mnoc_cfg, 1323 &qxm_mdp0, 1324 &qxm_rot, 1325 &qxm_venus0, 1326 &qxm_venus_arm9 1327 }, 1328 }; 1329 1330 static struct qcom_icc_bcm bcm_sh2 = { 1331 .name = "SH2", 1332 .keepalive = false, 1333 .num_nodes = 1, 1334 .nodes = { &acm_sys_tcu }, 1335 }; 1336 1337 static struct qcom_icc_bcm bcm_mm2 = { 1338 .name = "MM2", 1339 .keepalive = false, 1340 .num_nodes = 1, 1341 .nodes = { &qns_mem_noc_sf }, 1342 }; 1343 1344 static struct qcom_icc_bcm bcm_qup0 = { 1345 .name = "QUP0", 1346 .keepalive = false, 1347 .num_nodes = 2, 1348 .nodes = { &qup_core_master_1, &qup_core_master_2 }, 1349 }; 1350 1351 static struct qcom_icc_bcm bcm_sh3 = { 1352 .name = "SH3", 1353 .keepalive = false, 1354 .num_nodes = 1, 1355 .nodes = { &qnm_cmpnoc }, 1356 }; 1357 1358 static struct qcom_icc_bcm bcm_sh4 = { 1359 .name = "SH4", 1360 .keepalive = false, 1361 .num_nodes = 1, 1362 .nodes = { &acm_apps0 }, 1363 }; 1364 1365 static struct qcom_icc_bcm bcm_sn0 = { 1366 .name = "SN0", 1367 .keepalive = true, 1368 .num_nodes = 1, 1369 .nodes = { &qns_gemnoc_sf }, 1370 }; 1371 1372 static struct qcom_icc_bcm bcm_co0 = { 1373 .name = "CO0", 1374 .keepalive = false, 1375 .num_nodes = 1, 1376 .nodes = { &qns_cdsp_gemnoc }, 1377 }; 1378 1379 static struct qcom_icc_bcm bcm_sn1 = { 1380 .name = "SN1", 1381 .keepalive = false, 1382 .num_nodes = 1, 1383 .nodes = { &qxs_imem }, 1384 }; 1385 1386 static struct qcom_icc_bcm bcm_cn1 = { 1387 .name = "CN1", 1388 .keepalive = false, 1389 .num_nodes = 8, 1390 .nodes = { &qhm_qspi, 1391 &xm_sdc2, 1392 &xm_emmc, 1393 &qhs_ahb2phy2, 1394 &qhs_emmc_cfg, 1395 &qhs_pdm, 1396 &qhs_qspi, 1397 &qhs_sdc2 1398 }, 1399 }; 1400 1401 static struct qcom_icc_bcm bcm_sn2 = { 1402 .name = "SN2", 1403 .keepalive = false, 1404 .num_nodes = 2, 1405 .nodes = { &qxm_pimem, &qns_gemnoc_gc }, 1406 }; 1407 1408 static struct qcom_icc_bcm bcm_co2 = { 1409 .name = "CO2", 1410 .keepalive = false, 1411 .num_nodes = 1, 1412 .nodes = { &qnm_npu }, 1413 }; 1414 1415 static struct qcom_icc_bcm bcm_sn3 = { 1416 .name = "SN3", 1417 .keepalive = false, 1418 .num_nodes = 1, 1419 .nodes = { &qxs_pimem }, 1420 }; 1421 1422 static struct qcom_icc_bcm bcm_co3 = { 1423 .name = "CO3", 1424 .keepalive = false, 1425 .num_nodes = 1, 1426 .nodes = { &qxm_npu_dsp }, 1427 }; 1428 1429 static struct qcom_icc_bcm bcm_sn4 = { 1430 .name = "SN4", 1431 .keepalive = false, 1432 .num_nodes = 1, 1433 .nodes = { &xs_qdss_stm }, 1434 }; 1435 1436 static struct qcom_icc_bcm bcm_sn7 = { 1437 .name = "SN7", 1438 .keepalive = false, 1439 .num_nodes = 1, 1440 .nodes = { &qnm_aggre1_noc }, 1441 }; 1442 1443 static struct qcom_icc_bcm bcm_sn9 = { 1444 .name = "SN9", 1445 .keepalive = false, 1446 .num_nodes = 1, 1447 .nodes = { &qnm_aggre2_noc }, 1448 }; 1449 1450 static struct qcom_icc_bcm bcm_sn12 = { 1451 .name = "SN12", 1452 .keepalive = false, 1453 .num_nodes = 1, 1454 .nodes = { &qnm_gemnoc }, 1455 }; 1456 1457 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 1458 &bcm_cn1, 1459 }; 1460 1461 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1462 [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg, 1463 [MASTER_QSPI] = &qhm_qspi, 1464 [MASTER_QUP_0] = &qhm_qup_0, 1465 [MASTER_SDCC_2] = &xm_sdc2, 1466 [MASTER_EMMC] = &xm_emmc, 1467 [MASTER_UFS_MEM] = &xm_ufs_mem, 1468 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, 1469 [SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc, 1470 }; 1471 1472 static const struct qcom_icc_desc sc7180_aggre1_noc = { 1473 .nodes = aggre1_noc_nodes, 1474 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 1475 .bcms = aggre1_noc_bcms, 1476 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 1477 }; 1478 1479 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 1480 &bcm_ce0, 1481 }; 1482 1483 static struct qcom_icc_node * const aggre2_noc_nodes[] = { 1484 [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg, 1485 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 1486 [MASTER_QUP_1] = &qhm_qup_1, 1487 [MASTER_USB3] = &qhm_usb3, 1488 [MASTER_CRYPTO] = &qxm_crypto, 1489 [MASTER_IPA] = &qxm_ipa, 1490 [MASTER_QDSS_ETR] = &xm_qdss_etr, 1491 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, 1492 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, 1493 }; 1494 1495 static const struct qcom_icc_desc sc7180_aggre2_noc = { 1496 .nodes = aggre2_noc_nodes, 1497 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 1498 .bcms = aggre2_noc_bcms, 1499 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 1500 }; 1501 1502 static struct qcom_icc_bcm * const camnoc_virt_bcms[] = { 1503 &bcm_mm1, 1504 }; 1505 1506 static struct qcom_icc_node * const camnoc_virt_nodes[] = { 1507 [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp, 1508 [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp, 1509 [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp, 1510 [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp, 1511 }; 1512 1513 static const struct qcom_icc_desc sc7180_camnoc_virt = { 1514 .nodes = camnoc_virt_nodes, 1515 .num_nodes = ARRAY_SIZE(camnoc_virt_nodes), 1516 .bcms = camnoc_virt_bcms, 1517 .num_bcms = ARRAY_SIZE(camnoc_virt_bcms), 1518 }; 1519 1520 static struct qcom_icc_bcm * const compute_noc_bcms[] = { 1521 &bcm_co0, 1522 &bcm_co2, 1523 &bcm_co3, 1524 }; 1525 1526 static struct qcom_icc_node * const compute_noc_nodes[] = { 1527 [MASTER_NPU] = &qnm_npu, 1528 [MASTER_NPU_PROC] = &qxm_npu_dsp, 1529 [SLAVE_CDSP_GEM_NOC] = &qns_cdsp_gemnoc, 1530 }; 1531 1532 static const struct qcom_icc_desc sc7180_compute_noc = { 1533 .nodes = compute_noc_nodes, 1534 .num_nodes = ARRAY_SIZE(compute_noc_nodes), 1535 .bcms = compute_noc_bcms, 1536 .num_bcms = ARRAY_SIZE(compute_noc_bcms), 1537 }; 1538 1539 static struct qcom_icc_bcm * const config_noc_bcms[] = { 1540 &bcm_cn0, 1541 &bcm_cn1, 1542 }; 1543 1544 static struct qcom_icc_node * const config_noc_nodes[] = { 1545 [MASTER_SNOC_CNOC] = &qnm_snoc, 1546 [MASTER_QDSS_DAP] = &xm_qdss_dap, 1547 [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg, 1548 [SLAVE_A2NOC_CFG] = &qhs_a2_noc_cfg, 1549 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, 1550 [SLAVE_AHB2PHY_CENTER] = &qhs_ahb2phy2, 1551 [SLAVE_AOP] = &qhs_aop, 1552 [SLAVE_AOSS] = &qhs_aoss, 1553 [SLAVE_BOOT_ROM] = &qhs_boot_rom, 1554 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 1555 [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_throttle_cfg, 1556 [SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg, 1557 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1558 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 1559 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, 1560 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1561 [SLAVE_DCC_CFG] = &qhs_dcc_cfg, 1562 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg, 1563 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 1564 [SLAVE_DISPLAY_RT_THROTTLE_CFG] = &qhs_display_rt_throttle_cfg, 1565 [SLAVE_DISPLAY_THROTTLE_CFG] = &qhs_display_throttle_cfg, 1566 [SLAVE_EMMC_CFG] = &qhs_emmc_cfg, 1567 [SLAVE_GLM] = &qhs_glm, 1568 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, 1569 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1570 [SLAVE_IPA_CFG] = &qhs_ipa, 1571 [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg, 1572 [SLAVE_CNOC_MSS] = &qhs_mss_cfg, 1573 [SLAVE_NPU_CFG] = &qhs_npu_cfg, 1574 [SLAVE_NPU_DMA_BWMON_CFG] = &qhs_npu_dma_throttle_cfg, 1575 [SLAVE_NPU_PROC_BWMON_CFG] = &qhs_npu_dsp_throttle_cfg, 1576 [SLAVE_PDM] = &qhs_pdm, 1577 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 1578 [SLAVE_PRNG] = &qhs_prng, 1579 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1580 [SLAVE_QM_CFG] = &qhs_qm_cfg, 1581 [SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg, 1582 [SLAVE_QSPI_0] = &qhs_qspi, 1583 [SLAVE_QUP_0] = &qhs_qup0, 1584 [SLAVE_QUP_1] = &qhs_qup1, 1585 [SLAVE_SDCC_2] = &qhs_sdc2, 1586 [SLAVE_SECURITY] = &qhs_security, 1587 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, 1588 [SLAVE_TCSR] = &qhs_tcsr, 1589 [SLAVE_TLMM_WEST] = &qhs_tlmm_1, 1590 [SLAVE_TLMM_NORTH] = &qhs_tlmm_2, 1591 [SLAVE_TLMM_SOUTH] = &qhs_tlmm_3, 1592 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 1593 [SLAVE_USB3] = &qhs_usb3, 1594 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1595 [SLAVE_VENUS_THROTTLE_CFG] = &qhs_venus_throttle_cfg, 1596 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 1597 [SLAVE_SERVICE_CNOC] = &srvc_cnoc, 1598 }; 1599 1600 static const struct qcom_icc_desc sc7180_config_noc = { 1601 .nodes = config_noc_nodes, 1602 .num_nodes = ARRAY_SIZE(config_noc_nodes), 1603 .bcms = config_noc_bcms, 1604 .num_bcms = ARRAY_SIZE(config_noc_bcms), 1605 }; 1606 1607 static struct qcom_icc_node * const dc_noc_nodes[] = { 1608 [MASTER_CNOC_DC_NOC] = &qhm_cnoc_dc_noc, 1609 [SLAVE_GEM_NOC_CFG] = &qhs_gemnoc, 1610 [SLAVE_LLCC_CFG] = &qhs_llcc, 1611 }; 1612 1613 static const struct qcom_icc_desc sc7180_dc_noc = { 1614 .nodes = dc_noc_nodes, 1615 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 1616 }; 1617 1618 static struct qcom_icc_bcm * const gem_noc_bcms[] = { 1619 &bcm_sh0, 1620 &bcm_sh2, 1621 &bcm_sh3, 1622 &bcm_sh4, 1623 }; 1624 1625 static struct qcom_icc_node * const gem_noc_nodes[] = { 1626 [MASTER_APPSS_PROC] = &acm_apps0, 1627 [MASTER_SYS_TCU] = &acm_sys_tcu, 1628 [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg, 1629 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc, 1630 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 1631 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 1632 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 1633 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 1634 [MASTER_GFX3D] = &qxm_gpu, 1635 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg, 1636 [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc, 1637 [SLAVE_LLCC] = &qns_llcc, 1638 [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc, 1639 }; 1640 1641 static const struct qcom_icc_desc sc7180_gem_noc = { 1642 .nodes = gem_noc_nodes, 1643 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 1644 .bcms = gem_noc_bcms, 1645 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 1646 }; 1647 1648 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 1649 &bcm_acv, 1650 &bcm_mc0, 1651 }; 1652 1653 static struct qcom_icc_node * const mc_virt_nodes[] = { 1654 [MASTER_LLCC] = &llcc_mc, 1655 [SLAVE_EBI1] = &ebi, 1656 }; 1657 1658 static const struct qcom_icc_desc sc7180_mc_virt = { 1659 .nodes = mc_virt_nodes, 1660 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 1661 .bcms = mc_virt_bcms, 1662 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 1663 }; 1664 1665 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 1666 &bcm_mm0, 1667 &bcm_mm1, 1668 &bcm_mm2, 1669 }; 1670 1671 static struct qcom_icc_node * const mmss_noc_nodes[] = { 1672 [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg, 1673 [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0, 1674 [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1, 1675 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf, 1676 [MASTER_MDP0] = &qxm_mdp0, 1677 [MASTER_ROTATOR] = &qxm_rot, 1678 [MASTER_VIDEO_P0] = &qxm_venus0, 1679 [MASTER_VIDEO_PROC] = &qxm_venus_arm9, 1680 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 1681 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, 1682 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 1683 }; 1684 1685 static const struct qcom_icc_desc sc7180_mmss_noc = { 1686 .nodes = mmss_noc_nodes, 1687 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 1688 .bcms = mmss_noc_bcms, 1689 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 1690 }; 1691 1692 static struct qcom_icc_node * const npu_noc_nodes[] = { 1693 [MASTER_NPU_SYS] = &amm_npu_sys, 1694 [MASTER_NPU_NOC_CFG] = &qhm_npu_cfg, 1695 [SLAVE_NPU_CAL_DP0] = &qhs_cal_dp0, 1696 [SLAVE_NPU_CP] = &qhs_cp, 1697 [SLAVE_NPU_INT_DMA_BWMON_CFG] = &qhs_dma_bwmon, 1698 [SLAVE_NPU_DPM] = &qhs_dpm, 1699 [SLAVE_ISENSE_CFG] = &qhs_isense, 1700 [SLAVE_NPU_LLM_CFG] = &qhs_llm, 1701 [SLAVE_NPU_TCM] = &qhs_tcm, 1702 [SLAVE_NPU_COMPUTE_NOC] = &qns_npu_sys, 1703 [SLAVE_SERVICE_NPU_NOC] = &srvc_noc, 1704 }; 1705 1706 static const struct qcom_icc_desc sc7180_npu_noc = { 1707 .nodes = npu_noc_nodes, 1708 .num_nodes = ARRAY_SIZE(npu_noc_nodes), 1709 }; 1710 1711 static struct qcom_icc_bcm * const qup_virt_bcms[] = { 1712 &bcm_qup0, 1713 }; 1714 1715 static struct qcom_icc_node * const qup_virt_nodes[] = { 1716 [MASTER_QUP_CORE_0] = &qup_core_master_1, 1717 [MASTER_QUP_CORE_1] = &qup_core_master_2, 1718 [SLAVE_QUP_CORE_0] = &qup_core_slave_1, 1719 [SLAVE_QUP_CORE_1] = &qup_core_slave_2, 1720 }; 1721 1722 static const struct qcom_icc_desc sc7180_qup_virt = { 1723 .nodes = qup_virt_nodes, 1724 .num_nodes = ARRAY_SIZE(qup_virt_nodes), 1725 .bcms = qup_virt_bcms, 1726 .num_bcms = ARRAY_SIZE(qup_virt_bcms), 1727 }; 1728 1729 static struct qcom_icc_bcm * const system_noc_bcms[] = { 1730 &bcm_sn0, 1731 &bcm_sn1, 1732 &bcm_sn2, 1733 &bcm_sn3, 1734 &bcm_sn4, 1735 &bcm_sn7, 1736 &bcm_sn9, 1737 &bcm_sn12, 1738 }; 1739 1740 static struct qcom_icc_node * const system_noc_nodes[] = { 1741 [MASTER_SNOC_CFG] = &qhm_snoc_cfg, 1742 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, 1743 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, 1744 [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc, 1745 [MASTER_PIMEM] = &qxm_pimem, 1746 [SLAVE_APPSS] = &qhs_apss, 1747 [SLAVE_SNOC_CNOC] = &qns_cnoc, 1748 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, 1749 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 1750 [SLAVE_IMEM] = &qxs_imem, 1751 [SLAVE_PIMEM] = &qxs_pimem, 1752 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 1753 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1754 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1755 }; 1756 1757 static const struct qcom_icc_desc sc7180_system_noc = { 1758 .nodes = system_noc_nodes, 1759 .num_nodes = ARRAY_SIZE(system_noc_nodes), 1760 .bcms = system_noc_bcms, 1761 .num_bcms = ARRAY_SIZE(system_noc_bcms), 1762 }; 1763 1764 static const struct of_device_id qnoc_of_match[] = { 1765 { .compatible = "qcom,sc7180-aggre1-noc", 1766 .data = &sc7180_aggre1_noc}, 1767 { .compatible = "qcom,sc7180-aggre2-noc", 1768 .data = &sc7180_aggre2_noc}, 1769 { .compatible = "qcom,sc7180-camnoc-virt", 1770 .data = &sc7180_camnoc_virt}, 1771 { .compatible = "qcom,sc7180-compute-noc", 1772 .data = &sc7180_compute_noc}, 1773 { .compatible = "qcom,sc7180-config-noc", 1774 .data = &sc7180_config_noc}, 1775 { .compatible = "qcom,sc7180-dc-noc", 1776 .data = &sc7180_dc_noc}, 1777 { .compatible = "qcom,sc7180-gem-noc", 1778 .data = &sc7180_gem_noc}, 1779 { .compatible = "qcom,sc7180-mc-virt", 1780 .data = &sc7180_mc_virt}, 1781 { .compatible = "qcom,sc7180-mmss-noc", 1782 .data = &sc7180_mmss_noc}, 1783 { .compatible = "qcom,sc7180-npu-noc", 1784 .data = &sc7180_npu_noc}, 1785 { .compatible = "qcom,sc7180-qup-virt", 1786 .data = &sc7180_qup_virt}, 1787 { .compatible = "qcom,sc7180-system-noc", 1788 .data = &sc7180_system_noc}, 1789 { } 1790 }; 1791 MODULE_DEVICE_TABLE(of, qnoc_of_match); 1792 1793 static struct platform_driver qnoc_driver = { 1794 .probe = qcom_icc_rpmh_probe, 1795 .remove = qcom_icc_rpmh_remove, 1796 .driver = { 1797 .name = "qnoc-sc7180", 1798 .of_match_table = qnoc_of_match, 1799 .sync_state = icc_sync_state, 1800 }, 1801 }; 1802 module_platform_driver(qnoc_driver); 1803 1804 MODULE_DESCRIPTION("Qualcomm SC7180 NoC driver"); 1805 MODULE_LICENSE("GPL v2"); 1806