1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. 5 * Copyright (c) 2024, Linaro Ltd. 6 */ 7 8 #include <linux/device.h> 9 #include <linux/interconnect.h> 10 #include <linux/interconnect-provider.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/of_device.h> 14 #include <linux/of_platform.h> 15 #include <linux/platform_device.h> 16 #include <linux/sort.h> 17 #include <dt-bindings/interconnect/qcom,sar2130p-rpmh.h> 18 19 #include "bcm-voter.h" 20 #include "icc-common.h" 21 #include "icc-rpmh.h" 22 23 static struct qcom_icc_node qup0_core_master; 24 static struct qcom_icc_node qup1_core_master; 25 static struct qcom_icc_node qnm_gemnoc_cnoc; 26 static struct qcom_icc_node qnm_gemnoc_pcie; 27 static struct qcom_icc_node xm_qdss_dap; 28 static struct qcom_icc_node alm_gpu_tcu; 29 static struct qcom_icc_node alm_sys_tcu; 30 static struct qcom_icc_node chm_apps; 31 static struct qcom_icc_node qnm_gpu; 32 static struct qcom_icc_node qnm_mnoc_hf; 33 static struct qcom_icc_node qnm_mnoc_sf; 34 static struct qcom_icc_node qnm_nsp_gemnoc; 35 static struct qcom_icc_node qnm_pcie; 36 static struct qcom_icc_node qnm_snoc_gc; 37 static struct qcom_icc_node qnm_snoc_sf; 38 static struct qcom_icc_node qxm_wlan_q6; 39 static struct qcom_icc_node qhm_config_noc; 40 static struct qcom_icc_node qxm_lpass_dsp; 41 static struct qcom_icc_node llcc_mc; 42 static struct qcom_icc_node qnm_camnoc_hf; 43 static struct qcom_icc_node qnm_camnoc_icp; 44 static struct qcom_icc_node qnm_camnoc_sf; 45 static struct qcom_icc_node qnm_lsr; 46 static struct qcom_icc_node qnm_mdp; 47 static struct qcom_icc_node qnm_mnoc_cfg; 48 static struct qcom_icc_node qnm_video; 49 static struct qcom_icc_node qnm_video_cv_cpu; 50 static struct qcom_icc_node qnm_video_cvp; 51 static struct qcom_icc_node qnm_video_v_cpu; 52 static struct qcom_icc_node qhm_nsp_noc_config; 53 static struct qcom_icc_node qxm_nsp; 54 static struct qcom_icc_node xm_pcie3_0; 55 static struct qcom_icc_node xm_pcie3_1; 56 static struct qcom_icc_node qhm_gic; 57 static struct qcom_icc_node qhm_qdss_bam; 58 static struct qcom_icc_node qhm_qspi; 59 static struct qcom_icc_node qhm_qup0; 60 static struct qcom_icc_node qhm_qup1; 61 static struct qcom_icc_node qnm_aggre2_noc; 62 static struct qcom_icc_node qnm_cnoc_datapath; 63 static struct qcom_icc_node qnm_lpass_noc; 64 static struct qcom_icc_node qnm_snoc_cfg; 65 static struct qcom_icc_node qxm_crypto; 66 static struct qcom_icc_node qxm_pimem; 67 static struct qcom_icc_node xm_gic; 68 static struct qcom_icc_node xm_qdss_etr_0; 69 static struct qcom_icc_node xm_qdss_etr_1; 70 static struct qcom_icc_node xm_sdc1; 71 static struct qcom_icc_node xm_usb3_0; 72 static struct qcom_icc_node qup0_core_slave; 73 static struct qcom_icc_node qup1_core_slave; 74 static struct qcom_icc_node qhs_ahb2phy0; 75 static struct qcom_icc_node qhs_aoss; 76 static struct qcom_icc_node qhs_camera_cfg; 77 static struct qcom_icc_node qhs_clk_ctl; 78 static struct qcom_icc_node qhs_compute_cfg; 79 static struct qcom_icc_node qhs_cpr_cx; 80 static struct qcom_icc_node qhs_cpr_mmcx; 81 static struct qcom_icc_node qhs_cpr_mxa; 82 static struct qcom_icc_node qhs_cpr_mxc; 83 static struct qcom_icc_node qhs_cpr_nspcx; 84 static struct qcom_icc_node qhs_crypto0_cfg; 85 static struct qcom_icc_node qhs_cx_rdpm; 86 static struct qcom_icc_node qhs_display_cfg; 87 static struct qcom_icc_node qhs_gpuss_cfg; 88 static struct qcom_icc_node qhs_imem_cfg; 89 static struct qcom_icc_node qhs_ipc_router; 90 static struct qcom_icc_node qhs_lpass_cfg; 91 static struct qcom_icc_node qhs_mx_rdpm; 92 static struct qcom_icc_node qhs_pcie0_cfg; 93 static struct qcom_icc_node qhs_pcie1_cfg; 94 static struct qcom_icc_node qhs_pdm; 95 static struct qcom_icc_node qhs_pimem_cfg; 96 static struct qcom_icc_node qhs_prng; 97 static struct qcom_icc_node qhs_qdss_cfg; 98 static struct qcom_icc_node qhs_qspi; 99 static struct qcom_icc_node qhs_qup0; 100 static struct qcom_icc_node qhs_qup1; 101 static struct qcom_icc_node qhs_sdc1; 102 static struct qcom_icc_node qhs_tcsr; 103 static struct qcom_icc_node qhs_tlmm; 104 static struct qcom_icc_node qhs_tme_cfg; 105 static struct qcom_icc_node qhs_usb3_0; 106 static struct qcom_icc_node qhs_venus_cfg; 107 static struct qcom_icc_node qhs_vsense_ctrl_cfg; 108 static struct qcom_icc_node qhs_wlan_q6; 109 static struct qcom_icc_node qns_ddrss_cfg; 110 static struct qcom_icc_node qns_mnoc_cfg; 111 static struct qcom_icc_node qns_snoc_cfg; 112 static struct qcom_icc_node qxs_imem; 113 static struct qcom_icc_node qxs_pimem; 114 static struct qcom_icc_node srvc_cnoc; 115 static struct qcom_icc_node xs_pcie_0; 116 static struct qcom_icc_node xs_pcie_1; 117 static struct qcom_icc_node xs_qdss_stm; 118 static struct qcom_icc_node xs_sys_tcu_cfg; 119 static struct qcom_icc_node qns_gem_noc_cnoc; 120 static struct qcom_icc_node qns_llcc; 121 static struct qcom_icc_node qns_pcie; 122 static struct qcom_icc_node qhs_lpass_core; 123 static struct qcom_icc_node qhs_lpass_lpi; 124 static struct qcom_icc_node qhs_lpass_mpu; 125 static struct qcom_icc_node qhs_lpass_top; 126 static struct qcom_icc_node qns_sysnoc; 127 static struct qcom_icc_node srvc_niu_aml_noc; 128 static struct qcom_icc_node srvc_niu_lpass_agnoc; 129 static struct qcom_icc_node ebi; 130 static struct qcom_icc_node qns_mem_noc_hf; 131 static struct qcom_icc_node qns_mem_noc_sf; 132 static struct qcom_icc_node srvc_mnoc; 133 static struct qcom_icc_node qns_nsp_gemnoc; 134 static struct qcom_icc_node service_nsp_noc; 135 static struct qcom_icc_node qns_pcie_mem_noc; 136 static struct qcom_icc_node qns_a2noc_snoc; 137 static struct qcom_icc_node qns_gemnoc_gc; 138 static struct qcom_icc_node qns_gemnoc_sf; 139 static struct qcom_icc_node srvc_snoc; 140 141 static const struct regmap_config icc_regmap_config = { 142 .reg_bits = 32, 143 .reg_stride = 4, 144 .val_bits = 32, 145 .fast_io = true, 146 }; 147 148 static struct qcom_icc_node qup0_core_master = { 149 .name = "qup0_core_master", 150 .channels = 1, 151 .buswidth = 4, 152 .num_links = 1, 153 .link_nodes = { &qup0_core_slave }, 154 }; 155 156 static struct qcom_icc_node qup1_core_master = { 157 .name = "qup1_core_master", 158 .channels = 1, 159 .buswidth = 4, 160 .num_links = 1, 161 .link_nodes = { &qup1_core_slave }, 162 }; 163 164 static struct qcom_icc_node qnm_gemnoc_cnoc = { 165 .name = "qnm_gemnoc_cnoc", 166 .channels = 1, 167 .buswidth = 16, 168 .num_links = 43, 169 .link_nodes = { &qhs_ahb2phy0, &qhs_aoss, 170 &qhs_camera_cfg, &qhs_clk_ctl, 171 &qhs_compute_cfg, &qhs_cpr_cx, 172 &qhs_cpr_mmcx, &qhs_cpr_mxa, 173 &qhs_cpr_mxc, &qhs_cpr_nspcx, 174 &qhs_crypto0_cfg, &qhs_cx_rdpm, 175 &qhs_display_cfg, &qhs_gpuss_cfg, 176 &qhs_imem_cfg, &qhs_ipc_router, 177 &qhs_lpass_cfg, &qhs_mx_rdpm, 178 &qhs_pcie0_cfg, &qhs_pcie1_cfg, 179 &qhs_pdm, &qhs_pimem_cfg, 180 &qhs_prng, &qhs_qdss_cfg, 181 &qhs_qspi, &qhs_qup0, 182 &qhs_qup1, &qhs_sdc1, 183 &qhs_tcsr, &qhs_tlmm, 184 &qhs_tme_cfg, &qhs_usb3_0, 185 &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, 186 &qhs_wlan_q6, &qns_ddrss_cfg, 187 &qns_mnoc_cfg, &qns_snoc_cfg, 188 &qxs_imem, &qxs_pimem, 189 &srvc_cnoc, &xs_qdss_stm, 190 &xs_sys_tcu_cfg }, 191 }; 192 193 static struct qcom_icc_node qnm_gemnoc_pcie = { 194 .name = "qnm_gemnoc_pcie", 195 .channels = 1, 196 .buswidth = 8, 197 .num_links = 2, 198 .link_nodes = { &xs_pcie_0, &xs_pcie_1 }, 199 }; 200 201 static struct qcom_icc_node xm_qdss_dap = { 202 .name = "xm_qdss_dap", 203 .channels = 1, 204 .buswidth = 8, 205 .num_links = 43, 206 .link_nodes = { &qhs_ahb2phy0, &qhs_aoss, 207 &qhs_camera_cfg, &qhs_clk_ctl, 208 &qhs_compute_cfg, &qhs_cpr_cx, 209 &qhs_cpr_mmcx, &qhs_cpr_mxa, 210 &qhs_cpr_mxc, &qhs_cpr_nspcx, 211 &qhs_crypto0_cfg, &qhs_cx_rdpm, 212 &qhs_display_cfg, &qhs_gpuss_cfg, 213 &qhs_imem_cfg, &qhs_ipc_router, 214 &qhs_lpass_cfg, &qhs_mx_rdpm, 215 &qhs_pcie0_cfg, &qhs_pcie1_cfg, 216 &qhs_pdm, &qhs_pimem_cfg, 217 &qhs_prng, &qhs_qdss_cfg, 218 &qhs_qspi, &qhs_qup0, 219 &qhs_qup1, &qhs_sdc1, 220 &qhs_tcsr, &qhs_tlmm, 221 &qhs_tme_cfg, &qhs_usb3_0, 222 &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, 223 &qhs_wlan_q6, &qns_ddrss_cfg, 224 &qns_mnoc_cfg, &qns_snoc_cfg, 225 &qxs_imem, &qxs_pimem, 226 &srvc_cnoc, &xs_qdss_stm, 227 &xs_sys_tcu_cfg }, 228 }; 229 230 static const struct qcom_icc_qosbox alm_gpu_tcu_qos = { 231 .num_ports = 1, 232 .port_offsets = { 0x9e000 }, 233 .prio = 1, 234 .urg_fwd = 0, 235 .prio_fwd_disable = 1, 236 }; 237 238 static struct qcom_icc_node alm_gpu_tcu = { 239 .name = "alm_gpu_tcu", 240 .channels = 1, 241 .buswidth = 8, 242 .qosbox = &alm_gpu_tcu_qos, 243 .num_links = 2, 244 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 245 }; 246 247 static const struct qcom_icc_qosbox alm_sys_tcu_qos = { 248 .num_ports = 1, 249 .port_offsets = { 0x9f000 }, 250 .prio = 6, 251 .urg_fwd = 0, 252 .prio_fwd_disable = 1, 253 }; 254 255 static struct qcom_icc_node alm_sys_tcu = { 256 .name = "alm_sys_tcu", 257 .channels = 1, 258 .buswidth = 8, 259 .qosbox = &alm_sys_tcu_qos, 260 .num_links = 2, 261 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 262 }; 263 264 static struct qcom_icc_node chm_apps = { 265 .name = "chm_apps", 266 .channels = 1, 267 .buswidth = 32, 268 .num_links = 3, 269 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 270 &qns_pcie }, 271 }; 272 273 static const struct qcom_icc_qosbox qnm_gpu_qos = { 274 .num_ports = 2, 275 .port_offsets = { 0xe000, 0x4e000 }, 276 .prio = 0, 277 .urg_fwd = 0, 278 .prio_fwd_disable = 1, 279 }; 280 281 static struct qcom_icc_node qnm_gpu = { 282 .name = "qnm_gpu", 283 .channels = 2, 284 .buswidth = 32, 285 .qosbox = &qnm_gpu_qos, 286 .num_links = 2, 287 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 288 }; 289 290 static const struct qcom_icc_qosbox qnm_mnoc_hf_qos = { 291 .num_ports = 2, 292 .port_offsets = { 0xf000, 0x4f000 }, 293 .prio = 0, 294 .urg_fwd = 1, 295 }; 296 297 static struct qcom_icc_node qnm_mnoc_hf = { 298 .name = "qnm_mnoc_hf", 299 .channels = 2, 300 .buswidth = 32, 301 .qosbox = &qnm_mnoc_hf_qos, 302 .num_links = 2, 303 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 304 }; 305 306 static const struct qcom_icc_qosbox qnm_mnoc_sf_qos = { 307 .num_ports = 1, 308 .port_offsets = { 0x9d000 }, 309 .prio = 0, 310 .urg_fwd = 1, 311 }; 312 313 static struct qcom_icc_node qnm_mnoc_sf = { 314 .name = "qnm_mnoc_sf", 315 .channels = 1, 316 .buswidth = 32, 317 .qosbox = &qnm_mnoc_sf_qos, 318 .num_links = 2, 319 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 320 }; 321 322 static const struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = { 323 .num_ports = 2, 324 .port_offsets = { 0x10000, 0x50000 }, 325 .prio = 0, 326 .urg_fwd = 0, 327 .prio_fwd_disable = 1, 328 }; 329 330 static struct qcom_icc_node qnm_nsp_gemnoc = { 331 .name = "qnm_nsp_gemnoc", 332 .channels = 2, 333 .buswidth = 32, 334 .qosbox = &qnm_nsp_gemnoc_qos, 335 .num_links = 2, 336 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 337 }; 338 339 static const struct qcom_icc_qosbox qnm_pcie_qos = { 340 .num_ports = 1, 341 .port_offsets = { 0xa2000 }, 342 .prio = 2, 343 .urg_fwd = 1, 344 }; 345 346 static struct qcom_icc_node qnm_pcie = { 347 .name = "qnm_pcie", 348 .channels = 1, 349 .buswidth = 16, 350 .qosbox = &qnm_pcie_qos, 351 .num_links = 2, 352 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 353 }; 354 355 static const struct qcom_icc_qosbox qnm_snoc_gc_qos = { 356 .num_ports = 1, 357 .port_offsets = { 0xa0000 }, 358 .prio = 0, 359 .urg_fwd = 1, 360 }; 361 362 static struct qcom_icc_node qnm_snoc_gc = { 363 .name = "qnm_snoc_gc", 364 .channels = 1, 365 .buswidth = 8, 366 .qosbox = &qnm_snoc_gc_qos, 367 .num_links = 1, 368 .link_nodes = { &qns_llcc }, 369 }; 370 371 static const struct qcom_icc_qosbox qnm_snoc_sf_qos = { 372 .num_ports = 1, 373 .port_offsets = { 0xa1000 }, 374 .prio = 0, 375 .urg_fwd = 1, 376 }; 377 378 static struct qcom_icc_node qnm_snoc_sf = { 379 .name = "qnm_snoc_sf", 380 .channels = 1, 381 .buswidth = 16, 382 .qosbox = &qnm_snoc_sf_qos, 383 .num_links = 3, 384 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 385 &qns_pcie }, 386 }; 387 388 static struct qcom_icc_node qxm_wlan_q6 = { 389 .name = "qxm_wlan_q6", 390 .channels = 1, 391 .buswidth = 8, 392 .num_links = 3, 393 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 394 &qns_pcie }, 395 }; 396 397 static struct qcom_icc_node qhm_config_noc = { 398 .name = "qhm_config_noc", 399 .channels = 1, 400 .buswidth = 4, 401 .num_links = 6, 402 .link_nodes = { &qhs_lpass_core, &qhs_lpass_lpi, 403 &qhs_lpass_mpu, &qhs_lpass_top, 404 &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, 405 }; 406 407 static struct qcom_icc_node qxm_lpass_dsp = { 408 .name = "qxm_lpass_dsp", 409 .channels = 1, 410 .buswidth = 8, 411 .num_links = 4, 412 .link_nodes = { &qhs_lpass_top, &qns_sysnoc, 413 &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, 414 }; 415 416 static struct qcom_icc_node llcc_mc = { 417 .name = "llcc_mc", 418 .channels = 1, 419 .buswidth = 4, 420 .num_links = 1, 421 .link_nodes = { &ebi }, 422 }; 423 424 static const struct qcom_icc_qosbox qnm_camnoc_hf_qos = { 425 .num_ports = 1, 426 .port_offsets = { 0x1c000 }, 427 .prio = 0, 428 .urg_fwd = 1, 429 }; 430 431 static struct qcom_icc_node qnm_camnoc_hf = { 432 .name = "qnm_camnoc_hf", 433 .channels = 1, 434 .buswidth = 32, 435 .qosbox = &qnm_camnoc_hf_qos, 436 .num_links = 1, 437 .link_nodes = { &qns_mem_noc_hf }, 438 }; 439 440 static const struct qcom_icc_qosbox qnm_camnoc_icp_qos = { 441 .num_ports = 1, 442 .port_offsets = { 0x1c080 }, 443 .prio = 4, 444 .urg_fwd = 1, 445 }; 446 447 static struct qcom_icc_node qnm_camnoc_icp = { 448 .name = "qnm_camnoc_icp", 449 .channels = 1, 450 .buswidth = 8, 451 .qosbox = &qnm_camnoc_icp_qos, 452 .num_links = 1, 453 .link_nodes = { &qns_mem_noc_sf }, 454 }; 455 456 static const struct qcom_icc_qosbox qnm_camnoc_sf_qos = { 457 .num_ports = 1, 458 .port_offsets = { 0x1c100 }, 459 .prio = 0, 460 .urg_fwd = 1, 461 }; 462 463 static struct qcom_icc_node qnm_camnoc_sf = { 464 .name = "qnm_camnoc_sf", 465 .channels = 1, 466 .buswidth = 32, 467 .qosbox = &qnm_camnoc_sf_qos, 468 .num_links = 1, 469 .link_nodes = { &qns_mem_noc_sf }, 470 }; 471 472 static const struct qcom_icc_qosbox qnm_lsr_qos = { 473 .num_ports = 2, 474 .port_offsets = { 0x1f000, 0x1f080 }, 475 .prio = 3, 476 .urg_fwd = 1, 477 }; 478 479 static struct qcom_icc_node qnm_lsr = { 480 .name = "qnm_lsr", 481 .channels = 2, 482 .buswidth = 32, 483 .qosbox = &qnm_lsr_qos, 484 .num_links = 1, 485 .link_nodes = { &qns_mem_noc_hf }, 486 }; 487 488 static const struct qcom_icc_qosbox qnm_mdp_qos = { 489 .num_ports = 2, 490 .port_offsets = { 0x1d000, 0x1d080 }, 491 .prio = 0, 492 .urg_fwd = 1, 493 }; 494 495 static struct qcom_icc_node qnm_mdp = { 496 .name = "qnm_mdp", 497 .channels = 2, 498 .buswidth = 32, 499 .qosbox = &qnm_mdp_qos, 500 .num_links = 1, 501 .link_nodes = { &qns_mem_noc_hf }, 502 }; 503 504 static struct qcom_icc_node qnm_mnoc_cfg = { 505 .name = "qnm_mnoc_cfg", 506 .channels = 1, 507 .buswidth = 4, 508 .num_links = 1, 509 .link_nodes = { &srvc_mnoc }, 510 }; 511 512 static const struct qcom_icc_qosbox qnm_video_qos = { 513 .num_ports = 2, 514 .port_offsets = { 0x1e000, 0x1e080 }, 515 .prio = 0, 516 .urg_fwd = 1, 517 }; 518 519 static struct qcom_icc_node qnm_video = { 520 .name = "qnm_video", 521 .channels = 2, 522 .buswidth = 32, 523 .qosbox = &qnm_video_qos, 524 .num_links = 1, 525 .link_nodes = { &qns_mem_noc_sf }, 526 }; 527 528 static const struct qcom_icc_qosbox qnm_video_cv_cpu_qos = { 529 .num_ports = 1, 530 .port_offsets = { 0x1e100 }, 531 .prio = 4, 532 .urg_fwd = 1, 533 }; 534 535 static struct qcom_icc_node qnm_video_cv_cpu = { 536 .name = "qnm_video_cv_cpu", 537 .channels = 1, 538 .buswidth = 8, 539 .qosbox = &qnm_video_cv_cpu_qos, 540 .num_links = 1, 541 .link_nodes = { &qns_mem_noc_sf }, 542 }; 543 544 static const struct qcom_icc_qosbox qnm_video_cvp_qos = { 545 .num_ports = 1, 546 .port_offsets = { 0x1e180 }, 547 .prio = 0, 548 .urg_fwd = 1, 549 }; 550 551 static struct qcom_icc_node qnm_video_cvp = { 552 .name = "qnm_video_cvp", 553 .channels = 1, 554 .buswidth = 32, 555 .qosbox = &qnm_video_cvp_qos, 556 .num_links = 1, 557 .link_nodes = { &qns_mem_noc_sf }, 558 }; 559 560 static const struct qcom_icc_qosbox qnm_video_v_cpu_qos = { 561 .num_ports = 1, 562 .port_offsets = { 0x1e200 }, 563 .prio = 4, 564 .urg_fwd = 1, 565 }; 566 567 static struct qcom_icc_node qnm_video_v_cpu = { 568 .name = "qnm_video_v_cpu", 569 .channels = 1, 570 .buswidth = 8, 571 .qosbox = &qnm_video_v_cpu_qos, 572 .num_links = 1, 573 .link_nodes = { &qns_mem_noc_sf }, 574 }; 575 576 static struct qcom_icc_node qhm_nsp_noc_config = { 577 .name = "qhm_nsp_noc_config", 578 .channels = 1, 579 .buswidth = 4, 580 .num_links = 1, 581 .link_nodes = { &service_nsp_noc }, 582 }; 583 584 static struct qcom_icc_node qxm_nsp = { 585 .name = "qxm_nsp", 586 .channels = 2, 587 .buswidth = 32, 588 .num_links = 1, 589 .link_nodes = { &qns_nsp_gemnoc }, 590 }; 591 592 static const struct qcom_icc_qosbox xm_pcie3_0_qos = { 593 .num_ports = 1, 594 .port_offsets = { 0x9000 }, 595 .prio = 3, 596 .urg_fwd = 0, 597 .prio_fwd_disable = 1, 598 }; 599 600 static struct qcom_icc_node xm_pcie3_0 = { 601 .name = "xm_pcie3_0", 602 .channels = 1, 603 .buswidth = 8, 604 .qosbox = &xm_pcie3_0_qos, 605 .num_links = 1, 606 .link_nodes = { &qns_pcie_mem_noc }, 607 }; 608 609 static const struct qcom_icc_qosbox xm_pcie3_1_qos = { 610 .num_ports = 1, 611 .port_offsets = { 0xa000 }, 612 .prio = 2, 613 .urg_fwd = 0, 614 .prio_fwd_disable = 1, 615 }; 616 617 static struct qcom_icc_node xm_pcie3_1 = { 618 .name = "xm_pcie3_1", 619 .channels = 1, 620 .buswidth = 8, 621 .qosbox = &xm_pcie3_1_qos, 622 .num_links = 1, 623 .link_nodes = { &qns_pcie_mem_noc }, 624 }; 625 626 static const struct qcom_icc_qosbox qhm_gic_qos = { 627 .num_ports = 1, 628 .port_offsets = { 0x1d000 }, 629 .prio = 2, 630 .urg_fwd = 0, 631 .prio_fwd_disable = 1, 632 }; 633 634 static struct qcom_icc_node qhm_gic = { 635 .name = "qhm_gic", 636 .channels = 1, 637 .buswidth = 4, 638 .qosbox = &qhm_gic_qos, 639 .num_links = 1, 640 .link_nodes = { &qns_gemnoc_sf }, 641 }; 642 643 static const struct qcom_icc_qosbox qhm_qdss_bam_qos = { 644 .num_ports = 1, 645 .port_offsets = { 0x22000 }, 646 .prio = 2, 647 .urg_fwd = 0, 648 .prio_fwd_disable = 1, 649 }; 650 651 static struct qcom_icc_node qhm_qdss_bam = { 652 .name = "qhm_qdss_bam", 653 .channels = 1, 654 .buswidth = 4, 655 .qosbox = &qhm_qdss_bam_qos, 656 .num_links = 1, 657 .link_nodes = { &qns_a2noc_snoc }, 658 }; 659 660 static const struct qcom_icc_qosbox qhm_qspi_qos = { 661 .num_ports = 1, 662 .port_offsets = { 0x23000 }, 663 .prio = 2, 664 .urg_fwd = 0, 665 .prio_fwd_disable = 1, 666 }; 667 668 static struct qcom_icc_node qhm_qspi = { 669 .name = "qhm_qspi", 670 .channels = 1, 671 .buswidth = 4, 672 .qosbox = &qhm_qspi_qos, 673 .num_links = 1, 674 .link_nodes = { &qns_a2noc_snoc }, 675 }; 676 677 static const struct qcom_icc_qosbox qhm_qup0_qos = { 678 .num_ports = 1, 679 .port_offsets = { 0x24000 }, 680 .prio = 2, 681 .urg_fwd = 0, 682 .prio_fwd_disable = 1, 683 }; 684 685 static struct qcom_icc_node qhm_qup0 = { 686 .name = "qhm_qup0", 687 .channels = 1, 688 .buswidth = 4, 689 .qosbox = &qhm_qup0_qos, 690 .num_links = 1, 691 .link_nodes = { &qns_a2noc_snoc }, 692 }; 693 694 static const struct qcom_icc_qosbox qhm_qup1_qos = { 695 .num_ports = 1, 696 .port_offsets = { 0x25000 }, 697 .prio = 2, 698 .urg_fwd = 0, 699 .prio_fwd_disable = 1, 700 }; 701 702 static struct qcom_icc_node qhm_qup1 = { 703 .name = "qhm_qup1", 704 .channels = 1, 705 .buswidth = 4, 706 .qosbox = &qhm_qup1_qos, 707 .num_links = 1, 708 .link_nodes = { &qns_a2noc_snoc }, 709 }; 710 711 static struct qcom_icc_node qnm_aggre2_noc = { 712 .name = "qnm_aggre2_noc", 713 .channels = 1, 714 .buswidth = 16, 715 .num_links = 1, 716 .link_nodes = { &qns_gemnoc_sf }, 717 }; 718 719 static const struct qcom_icc_qosbox qnm_cnoc_datapath_qos = { 720 .num_ports = 1, 721 .port_offsets = { 0x26000 }, 722 .prio = 2, 723 .urg_fwd = 0, 724 .prio_fwd_disable = 1, 725 }; 726 727 static struct qcom_icc_node qnm_cnoc_datapath = { 728 .name = "qnm_cnoc_datapath", 729 .channels = 1, 730 .buswidth = 8, 731 .qosbox = &qnm_cnoc_datapath_qos, 732 .num_links = 1, 733 .link_nodes = { &qns_a2noc_snoc }, 734 }; 735 736 static const struct qcom_icc_qosbox qnm_lpass_noc_qos = { 737 .num_ports = 1, 738 .port_offsets = { 0x1e000 }, 739 .prio = 0, 740 .urg_fwd = 0, 741 .prio_fwd_disable = 1, 742 }; 743 744 static struct qcom_icc_node qnm_lpass_noc = { 745 .name = "qnm_lpass_noc", 746 .channels = 1, 747 .buswidth = 16, 748 .qosbox = &qnm_lpass_noc_qos, 749 .num_links = 1, 750 .link_nodes = { &qns_gemnoc_sf }, 751 }; 752 753 static struct qcom_icc_node qnm_snoc_cfg = { 754 .name = "qnm_snoc_cfg", 755 .channels = 1, 756 .buswidth = 4, 757 .num_links = 1, 758 .link_nodes = { &srvc_snoc }, 759 }; 760 761 static const struct qcom_icc_qosbox qxm_crypto_qos = { 762 .num_ports = 1, 763 .port_offsets = { 0x27000 }, 764 .prio = 2, 765 .urg_fwd = 0, 766 .prio_fwd_disable = 1, 767 }; 768 769 static struct qcom_icc_node qxm_crypto = { 770 .name = "qxm_crypto", 771 .channels = 1, 772 .buswidth = 8, 773 .qosbox = &qxm_crypto_qos, 774 .num_links = 1, 775 .link_nodes = { &qns_a2noc_snoc }, 776 }; 777 778 static const struct qcom_icc_qosbox qxm_pimem_qos = { 779 .num_ports = 1, 780 .port_offsets = { 0x1f000 }, 781 .prio = 2, 782 .urg_fwd = 0, 783 .prio_fwd_disable = 1, 784 }; 785 786 static struct qcom_icc_node qxm_pimem = { 787 .name = "qxm_pimem", 788 .channels = 1, 789 .buswidth = 8, 790 .qosbox = &qxm_pimem_qos, 791 .num_links = 1, 792 .link_nodes = { &qns_gemnoc_gc }, 793 }; 794 795 static const struct qcom_icc_qosbox xm_gic_qos = { 796 .num_ports = 1, 797 .port_offsets = { 0x21000 }, 798 .prio = 2, 799 .urg_fwd = 0, 800 .prio_fwd_disable = 1, 801 }; 802 803 static struct qcom_icc_node xm_gic = { 804 .name = "xm_gic", 805 .channels = 1, 806 .buswidth = 8, 807 .qosbox = &xm_gic_qos, 808 .num_links = 1, 809 .link_nodes = { &qns_gemnoc_gc }, 810 }; 811 812 static const struct qcom_icc_qosbox xm_qdss_etr_0_qos = { 813 .num_ports = 1, 814 .port_offsets = { 0x1b000 }, 815 .prio = 2, 816 .urg_fwd = 0, 817 .prio_fwd_disable = 1, 818 }; 819 820 static struct qcom_icc_node xm_qdss_etr_0 = { 821 .name = "xm_qdss_etr_0", 822 .channels = 1, 823 .buswidth = 8, 824 .qosbox = &xm_qdss_etr_0_qos, 825 .num_links = 1, 826 .link_nodes = { &qns_a2noc_snoc }, 827 }; 828 829 static const struct qcom_icc_qosbox xm_qdss_etr_1_qos = { 830 .num_ports = 1, 831 .port_offsets = { 0x1c000 }, 832 .prio = 2, 833 .urg_fwd = 0, 834 .prio_fwd_disable = 1, 835 }; 836 837 static struct qcom_icc_node xm_qdss_etr_1 = { 838 .name = "xm_qdss_etr_1", 839 .channels = 1, 840 .buswidth = 8, 841 .qosbox = &xm_qdss_etr_1_qos, 842 .num_links = 1, 843 .link_nodes = { &qns_a2noc_snoc }, 844 }; 845 846 static const struct qcom_icc_qosbox xm_sdc1_qos = { 847 .num_ports = 1, 848 .port_offsets = { 0x29000 }, 849 .prio = 2, 850 .urg_fwd = 0, 851 .prio_fwd_disable = 1, 852 }; 853 854 static struct qcom_icc_node xm_sdc1 = { 855 .name = "xm_sdc1", 856 .channels = 1, 857 .buswidth = 8, 858 .qosbox = &xm_sdc1_qos, 859 .num_links = 1, 860 .link_nodes = { &qns_a2noc_snoc }, 861 }; 862 863 static const struct qcom_icc_qosbox xm_usb3_0_qos = { 864 .num_ports = 1, 865 .port_offsets = { 0x28000 }, 866 .prio = 2, 867 .urg_fwd = 0, 868 .prio_fwd_disable = 1, 869 }; 870 871 static struct qcom_icc_node xm_usb3_0 = { 872 .name = "xm_usb3_0", 873 .channels = 1, 874 .buswidth = 8, 875 .qosbox = &xm_usb3_0_qos, 876 .num_links = 1, 877 .link_nodes = { &qns_a2noc_snoc }, 878 }; 879 880 static struct qcom_icc_node qup0_core_slave = { 881 .name = "qup0_core_slave", 882 .channels = 1, 883 .buswidth = 4, 884 }; 885 886 static struct qcom_icc_node qup1_core_slave = { 887 .name = "qup1_core_slave", 888 .channels = 1, 889 .buswidth = 4, 890 }; 891 892 static struct qcom_icc_node qhs_ahb2phy0 = { 893 .name = "qhs_ahb2phy0", 894 .channels = 1, 895 .buswidth = 4, 896 }; 897 898 static struct qcom_icc_node qhs_aoss = { 899 .name = "qhs_aoss", 900 .channels = 1, 901 .buswidth = 4, 902 }; 903 904 static struct qcom_icc_node qhs_camera_cfg = { 905 .name = "qhs_camera_cfg", 906 .channels = 1, 907 .buswidth = 4, 908 }; 909 910 static struct qcom_icc_node qhs_clk_ctl = { 911 .name = "qhs_clk_ctl", 912 .channels = 1, 913 .buswidth = 4, 914 }; 915 916 static struct qcom_icc_node qhs_compute_cfg = { 917 .name = "qhs_compute_cfg", 918 .channels = 1, 919 .buswidth = 4, 920 .num_links = 1, 921 .link_nodes = { &qhm_nsp_noc_config }, 922 }; 923 924 static struct qcom_icc_node qhs_cpr_cx = { 925 .name = "qhs_cpr_cx", 926 .channels = 1, 927 .buswidth = 4, 928 }; 929 930 static struct qcom_icc_node qhs_cpr_mmcx = { 931 .name = "qhs_cpr_mmcx", 932 .channels = 1, 933 .buswidth = 4, 934 }; 935 936 static struct qcom_icc_node qhs_cpr_mxa = { 937 .name = "qhs_cpr_mxa", 938 .channels = 1, 939 .buswidth = 4, 940 }; 941 942 static struct qcom_icc_node qhs_cpr_mxc = { 943 .name = "qhs_cpr_mxc", 944 .channels = 1, 945 .buswidth = 4, 946 }; 947 948 static struct qcom_icc_node qhs_cpr_nspcx = { 949 .name = "qhs_cpr_nspcx", 950 .channels = 1, 951 .buswidth = 4, 952 }; 953 954 static struct qcom_icc_node qhs_crypto0_cfg = { 955 .name = "qhs_crypto0_cfg", 956 .channels = 1, 957 .buswidth = 4, 958 }; 959 960 static struct qcom_icc_node qhs_cx_rdpm = { 961 .name = "qhs_cx_rdpm", 962 .channels = 1, 963 .buswidth = 4, 964 }; 965 966 static struct qcom_icc_node qhs_display_cfg = { 967 .name = "qhs_display_cfg", 968 .channels = 1, 969 .buswidth = 4, 970 }; 971 972 static struct qcom_icc_node qhs_gpuss_cfg = { 973 .name = "qhs_gpuss_cfg", 974 .channels = 1, 975 .buswidth = 8, 976 }; 977 978 static struct qcom_icc_node qhs_imem_cfg = { 979 .name = "qhs_imem_cfg", 980 .channels = 1, 981 .buswidth = 4, 982 }; 983 984 static struct qcom_icc_node qhs_ipc_router = { 985 .name = "qhs_ipc_router", 986 .channels = 1, 987 .buswidth = 4, 988 }; 989 990 static struct qcom_icc_node qhs_lpass_cfg = { 991 .name = "qhs_lpass_cfg", 992 .channels = 1, 993 .buswidth = 4, 994 .num_links = 1, 995 .link_nodes = { &qhm_config_noc }, 996 }; 997 998 static struct qcom_icc_node qhs_mx_rdpm = { 999 .name = "qhs_mx_rdpm", 1000 .channels = 1, 1001 .buswidth = 4, 1002 }; 1003 1004 static struct qcom_icc_node qhs_pcie0_cfg = { 1005 .name = "qhs_pcie0_cfg", 1006 .channels = 1, 1007 .buswidth = 4, 1008 }; 1009 1010 static struct qcom_icc_node qhs_pcie1_cfg = { 1011 .name = "qhs_pcie1_cfg", 1012 .channels = 1, 1013 .buswidth = 4, 1014 }; 1015 1016 static struct qcom_icc_node qhs_pdm = { 1017 .name = "qhs_pdm", 1018 .channels = 1, 1019 .buswidth = 4, 1020 }; 1021 1022 static struct qcom_icc_node qhs_pimem_cfg = { 1023 .name = "qhs_pimem_cfg", 1024 .channels = 1, 1025 .buswidth = 4, 1026 }; 1027 1028 static struct qcom_icc_node qhs_prng = { 1029 .name = "qhs_prng", 1030 .channels = 1, 1031 .buswidth = 4, 1032 }; 1033 1034 static struct qcom_icc_node qhs_qdss_cfg = { 1035 .name = "qhs_qdss_cfg", 1036 .channels = 1, 1037 .buswidth = 4, 1038 }; 1039 1040 static struct qcom_icc_node qhs_qspi = { 1041 .name = "qhs_qspi", 1042 .channels = 1, 1043 .buswidth = 4, 1044 }; 1045 1046 static struct qcom_icc_node qhs_qup0 = { 1047 .name = "qhs_qup0", 1048 .channels = 1, 1049 .buswidth = 4, 1050 }; 1051 1052 static struct qcom_icc_node qhs_qup1 = { 1053 .name = "qhs_qup1", 1054 .channels = 1, 1055 .buswidth = 4, 1056 }; 1057 1058 static struct qcom_icc_node qhs_sdc1 = { 1059 .name = "qhs_sdc1", 1060 .channels = 1, 1061 .buswidth = 4, 1062 }; 1063 1064 static struct qcom_icc_node qhs_tcsr = { 1065 .name = "qhs_tcsr", 1066 .channels = 1, 1067 .buswidth = 4, 1068 }; 1069 1070 static struct qcom_icc_node qhs_tlmm = { 1071 .name = "qhs_tlmm", 1072 .channels = 1, 1073 .buswidth = 4, 1074 }; 1075 1076 static struct qcom_icc_node qhs_tme_cfg = { 1077 .name = "qhs_tme_cfg", 1078 .channels = 1, 1079 .buswidth = 4, 1080 }; 1081 1082 static struct qcom_icc_node qhs_usb3_0 = { 1083 .name = "qhs_usb3_0", 1084 .channels = 1, 1085 .buswidth = 4, 1086 }; 1087 1088 static struct qcom_icc_node qhs_venus_cfg = { 1089 .name = "qhs_venus_cfg", 1090 .channels = 1, 1091 .buswidth = 4, 1092 }; 1093 1094 static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 1095 .name = "qhs_vsense_ctrl_cfg", 1096 .channels = 1, 1097 .buswidth = 4, 1098 }; 1099 1100 static struct qcom_icc_node qhs_wlan_q6 = { 1101 .name = "qhs_wlan_q6", 1102 .channels = 1, 1103 .buswidth = 4, 1104 }; 1105 1106 static struct qcom_icc_node qns_ddrss_cfg = { 1107 .name = "qns_ddrss_cfg", 1108 .channels = 1, 1109 .buswidth = 4, 1110 }; 1111 1112 static struct qcom_icc_node qns_mnoc_cfg = { 1113 .name = "qns_mnoc_cfg", 1114 .channels = 1, 1115 .buswidth = 4, 1116 .num_links = 1, 1117 .link_nodes = { &qnm_mnoc_cfg }, 1118 }; 1119 1120 static struct qcom_icc_node qns_snoc_cfg = { 1121 .name = "qns_snoc_cfg", 1122 .channels = 1, 1123 .buswidth = 4, 1124 .num_links = 1, 1125 .link_nodes = { &qnm_snoc_cfg }, 1126 }; 1127 1128 static struct qcom_icc_node qxs_imem = { 1129 .name = "qxs_imem", 1130 .channels = 1, 1131 .buswidth = 8, 1132 }; 1133 1134 static struct qcom_icc_node qxs_pimem = { 1135 .name = "qxs_pimem", 1136 .channels = 1, 1137 .buswidth = 8, 1138 }; 1139 1140 static struct qcom_icc_node srvc_cnoc = { 1141 .name = "srvc_cnoc", 1142 .channels = 1, 1143 .buswidth = 4, 1144 }; 1145 1146 static struct qcom_icc_node xs_pcie_0 = { 1147 .name = "xs_pcie_0", 1148 .channels = 1, 1149 .buswidth = 8, 1150 }; 1151 1152 static struct qcom_icc_node xs_pcie_1 = { 1153 .name = "xs_pcie_1", 1154 .channels = 1, 1155 .buswidth = 8, 1156 }; 1157 1158 static struct qcom_icc_node xs_qdss_stm = { 1159 .name = "xs_qdss_stm", 1160 .channels = 1, 1161 .buswidth = 4, 1162 }; 1163 1164 static struct qcom_icc_node xs_sys_tcu_cfg = { 1165 .name = "xs_sys_tcu_cfg", 1166 .channels = 1, 1167 .buswidth = 8, 1168 }; 1169 1170 static struct qcom_icc_node qns_gem_noc_cnoc = { 1171 .name = "qns_gem_noc_cnoc", 1172 .channels = 1, 1173 .buswidth = 16, 1174 .num_links = 1, 1175 .link_nodes = { &qnm_gemnoc_cnoc }, 1176 }; 1177 1178 static struct qcom_icc_node qns_llcc = { 1179 .name = "qns_llcc", 1180 .channels = 2, 1181 .buswidth = 16, 1182 .num_links = 1, 1183 .link_nodes = { &llcc_mc }, 1184 }; 1185 1186 static struct qcom_icc_node qns_pcie = { 1187 .name = "qns_pcie", 1188 .channels = 1, 1189 .buswidth = 8, 1190 .num_links = 1, 1191 .link_nodes = { &qnm_gemnoc_pcie }, 1192 }; 1193 1194 static struct qcom_icc_node qhs_lpass_core = { 1195 .name = "qhs_lpass_core", 1196 .channels = 1, 1197 .buswidth = 4, 1198 }; 1199 1200 static struct qcom_icc_node qhs_lpass_lpi = { 1201 .name = "qhs_lpass_lpi", 1202 .channels = 1, 1203 .buswidth = 4, 1204 }; 1205 1206 static struct qcom_icc_node qhs_lpass_mpu = { 1207 .name = "qhs_lpass_mpu", 1208 .channels = 1, 1209 .buswidth = 4, 1210 }; 1211 1212 static struct qcom_icc_node qhs_lpass_top = { 1213 .name = "qhs_lpass_top", 1214 .channels = 1, 1215 .buswidth = 4, 1216 }; 1217 1218 static struct qcom_icc_node qns_sysnoc = { 1219 .name = "qns_sysnoc", 1220 .channels = 1, 1221 .buswidth = 16, 1222 .num_links = 1, 1223 .link_nodes = { &qnm_lpass_noc }, 1224 }; 1225 1226 static struct qcom_icc_node srvc_niu_aml_noc = { 1227 .name = "srvc_niu_aml_noc", 1228 .channels = 1, 1229 .buswidth = 4, 1230 }; 1231 1232 static struct qcom_icc_node srvc_niu_lpass_agnoc = { 1233 .name = "srvc_niu_lpass_agnoc", 1234 .channels = 1, 1235 .buswidth = 4, 1236 }; 1237 1238 static struct qcom_icc_node ebi = { 1239 .name = "ebi", 1240 .channels = 1, 1241 .buswidth = 4, 1242 }; 1243 1244 static struct qcom_icc_node qns_mem_noc_hf = { 1245 .name = "qns_mem_noc_hf", 1246 .channels = 2, 1247 .buswidth = 32, 1248 .num_links = 1, 1249 .link_nodes = { &qnm_mnoc_hf }, 1250 }; 1251 1252 static struct qcom_icc_node qns_mem_noc_sf = { 1253 .name = "qns_mem_noc_sf", 1254 .channels = 1, 1255 .buswidth = 32, 1256 .num_links = 1, 1257 .link_nodes = { &qnm_mnoc_sf }, 1258 }; 1259 1260 static struct qcom_icc_node srvc_mnoc = { 1261 .name = "srvc_mnoc", 1262 .channels = 1, 1263 .buswidth = 4, 1264 }; 1265 1266 static struct qcom_icc_node qns_nsp_gemnoc = { 1267 .name = "qns_nsp_gemnoc", 1268 .channels = 2, 1269 .buswidth = 32, 1270 .num_links = 1, 1271 .link_nodes = { &qnm_nsp_gemnoc }, 1272 }; 1273 1274 static struct qcom_icc_node service_nsp_noc = { 1275 .name = "service_nsp_noc", 1276 .channels = 1, 1277 .buswidth = 4, 1278 }; 1279 1280 static struct qcom_icc_node qns_pcie_mem_noc = { 1281 .name = "qns_pcie_mem_noc", 1282 .channels = 1, 1283 .buswidth = 16, 1284 .num_links = 1, 1285 .link_nodes = { &qnm_pcie }, 1286 }; 1287 1288 static struct qcom_icc_node qns_a2noc_snoc = { 1289 .name = "qns_a2noc_snoc", 1290 .channels = 1, 1291 .buswidth = 16, 1292 .num_links = 1, 1293 .link_nodes = { &qnm_aggre2_noc }, 1294 }; 1295 1296 static struct qcom_icc_node qns_gemnoc_gc = { 1297 .name = "qns_gemnoc_gc", 1298 .channels = 1, 1299 .buswidth = 8, 1300 .num_links = 1, 1301 .link_nodes = { &qnm_snoc_gc }, 1302 }; 1303 1304 static struct qcom_icc_node qns_gemnoc_sf = { 1305 .name = "qns_gemnoc_sf", 1306 .channels = 1, 1307 .buswidth = 16, 1308 .num_links = 1, 1309 .link_nodes = { &qnm_snoc_sf }, 1310 }; 1311 1312 static struct qcom_icc_node srvc_snoc = { 1313 .name = "srvc_snoc", 1314 .channels = 1, 1315 .buswidth = 4, 1316 }; 1317 1318 static struct qcom_icc_bcm bcm_acv = { 1319 .name = "ACV", 1320 .enable_mask = BIT(3), 1321 .num_nodes = 1, 1322 .nodes = { &ebi }, 1323 }; 1324 1325 static struct qcom_icc_bcm bcm_ce0 = { 1326 .name = "CE0", 1327 .num_nodes = 1, 1328 .nodes = { &qxm_crypto }, 1329 }; 1330 1331 static struct qcom_icc_bcm bcm_cn0 = { 1332 .name = "CN0", 1333 .enable_mask = BIT(0), 1334 .keepalive = true, 1335 .num_nodes = 48, 1336 .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie, 1337 &xm_qdss_dap, &qhs_ahb2phy0, 1338 &qhs_aoss, &qhs_camera_cfg, 1339 &qhs_clk_ctl, &qhs_compute_cfg, 1340 &qhs_cpr_cx, &qhs_cpr_mmcx, 1341 &qhs_cpr_mxa, &qhs_cpr_mxc, 1342 &qhs_cpr_nspcx, &qhs_crypto0_cfg, 1343 &qhs_cx_rdpm, &qhs_display_cfg, 1344 &qhs_gpuss_cfg, &qhs_imem_cfg, 1345 &qhs_ipc_router, &qhs_lpass_cfg, 1346 &qhs_mx_rdpm, &qhs_pcie0_cfg, 1347 &qhs_pcie1_cfg, &qhs_pdm, 1348 &qhs_pimem_cfg, &qhs_prng, 1349 &qhs_qdss_cfg, &qhs_qspi, 1350 &qhs_qup0, &qhs_qup1, 1351 &qhs_sdc1, &qhs_tcsr, 1352 &qhs_tlmm, &qhs_tme_cfg, 1353 &qhs_usb3_0, &qhs_venus_cfg, 1354 &qhs_vsense_ctrl_cfg, &qhs_wlan_q6, 1355 &qns_ddrss_cfg, &qns_mnoc_cfg, 1356 &qns_snoc_cfg, &qxs_imem, 1357 &qxs_pimem, &srvc_cnoc, 1358 &xs_pcie_0, &xs_pcie_1, 1359 &xs_qdss_stm, &xs_sys_tcu_cfg }, 1360 }; 1361 1362 static struct qcom_icc_bcm bcm_co0 = { 1363 .name = "CO0", 1364 .enable_mask = BIT(0), 1365 .num_nodes = 2, 1366 .nodes = { &qxm_nsp, &qns_nsp_gemnoc }, 1367 }; 1368 1369 static struct qcom_icc_bcm bcm_mc0 = { 1370 .name = "MC0", 1371 .keepalive = true, 1372 .num_nodes = 1, 1373 .nodes = { &ebi }, 1374 }; 1375 1376 static struct qcom_icc_bcm bcm_mm0 = { 1377 .name = "MM0", 1378 .keepalive = true, 1379 .num_nodes = 1, 1380 .nodes = { &qns_mem_noc_hf }, 1381 }; 1382 1383 static struct qcom_icc_bcm bcm_mm1 = { 1384 .name = "MM1", 1385 .enable_mask = BIT(0), 1386 .num_nodes = 11, 1387 .nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp, 1388 &qnm_camnoc_sf, &qnm_lsr, 1389 &qnm_mdp, &qnm_mnoc_cfg, 1390 &qnm_video, &qnm_video_cv_cpu, 1391 &qnm_video_cvp, &qnm_video_v_cpu, 1392 &qns_mem_noc_sf }, 1393 }; 1394 1395 static struct qcom_icc_bcm bcm_qup0 = { 1396 .name = "QUP0", 1397 .keepalive = true, 1398 .vote_scale = 1, 1399 .num_nodes = 1, 1400 .nodes = { &qup0_core_slave }, 1401 }; 1402 1403 static struct qcom_icc_bcm bcm_qup1 = { 1404 .name = "QUP1", 1405 .keepalive = true, 1406 .vote_scale = 1, 1407 .num_nodes = 1, 1408 .nodes = { &qup1_core_slave }, 1409 }; 1410 1411 static struct qcom_icc_bcm bcm_sh0 = { 1412 .name = "SH0", 1413 .keepalive = true, 1414 .num_nodes = 1, 1415 .nodes = { &qns_llcc }, 1416 }; 1417 1418 static struct qcom_icc_bcm bcm_sh1 = { 1419 .name = "SH1", 1420 .enable_mask = BIT(0), 1421 .num_nodes = 13, 1422 .nodes = { &alm_gpu_tcu, &alm_sys_tcu, 1423 &chm_apps, &qnm_gpu, 1424 &qnm_mnoc_hf, &qnm_mnoc_sf, 1425 &qnm_nsp_gemnoc, &qnm_pcie, 1426 &qnm_snoc_gc, &qnm_snoc_sf, 1427 &qxm_wlan_q6, &qns_gem_noc_cnoc, 1428 &qns_pcie }, 1429 }; 1430 1431 static struct qcom_icc_bcm bcm_sn0 = { 1432 .name = "SN0", 1433 .keepalive = true, 1434 .num_nodes = 1, 1435 .nodes = { &qns_gemnoc_sf }, 1436 }; 1437 1438 static struct qcom_icc_bcm bcm_sn1 = { 1439 .name = "SN1", 1440 .enable_mask = BIT(0), 1441 .num_nodes = 4, 1442 .nodes = { &qhm_gic, &qxm_pimem, 1443 &xm_gic, &qns_gemnoc_gc }, 1444 }; 1445 1446 static struct qcom_icc_bcm bcm_sn3 = { 1447 .name = "SN3", 1448 .num_nodes = 1, 1449 .nodes = { &qnm_aggre2_noc }, 1450 }; 1451 1452 static struct qcom_icc_bcm bcm_sn4 = { 1453 .name = "SN4", 1454 .num_nodes = 1, 1455 .nodes = { &qnm_lpass_noc }, 1456 }; 1457 1458 static struct qcom_icc_bcm bcm_sn7 = { 1459 .name = "SN7", 1460 .num_nodes = 1, 1461 .nodes = { &qns_pcie_mem_noc }, 1462 }; 1463 1464 static struct qcom_icc_bcm * const clk_virt_bcms[] = { 1465 &bcm_qup0, 1466 &bcm_qup1, 1467 }; 1468 1469 static struct qcom_icc_node * const clk_virt_nodes[] = { 1470 [MASTER_QUP_CORE_0] = &qup0_core_master, 1471 [MASTER_QUP_CORE_1] = &qup1_core_master, 1472 [SLAVE_QUP_CORE_0] = &qup0_core_slave, 1473 [SLAVE_QUP_CORE_1] = &qup1_core_slave, 1474 }; 1475 1476 static const struct qcom_icc_desc sar2130p_clk_virt = { 1477 .nodes = clk_virt_nodes, 1478 .num_nodes = ARRAY_SIZE(clk_virt_nodes), 1479 .bcms = clk_virt_bcms, 1480 .num_bcms = ARRAY_SIZE(clk_virt_bcms), 1481 }; 1482 1483 static struct qcom_icc_bcm * const config_noc_bcms[] = { 1484 &bcm_cn0, 1485 }; 1486 1487 static struct qcom_icc_node * const config_noc_nodes[] = { 1488 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, 1489 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, 1490 [MASTER_QDSS_DAP] = &xm_qdss_dap, 1491 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, 1492 [SLAVE_AOSS] = &qhs_aoss, 1493 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 1494 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1495 [SLAVE_CDSP_CFG] = &qhs_compute_cfg, 1496 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 1497 [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx, 1498 [SLAVE_RBCPR_MXA_CFG] = &qhs_cpr_mxa, 1499 [SLAVE_RBCPR_MXC_CFG] = &qhs_cpr_mxc, 1500 [SLAVE_CPR_NSPCX] = &qhs_cpr_nspcx, 1501 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1502 [SLAVE_CX_RDPM] = &qhs_cx_rdpm, 1503 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 1504 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, 1505 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1506 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, 1507 [SLAVE_LPASS] = &qhs_lpass_cfg, 1508 [SLAVE_MX_RDPM] = &qhs_mx_rdpm, 1509 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, 1510 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, 1511 [SLAVE_PDM] = &qhs_pdm, 1512 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 1513 [SLAVE_PRNG] = &qhs_prng, 1514 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1515 [SLAVE_QSPI_0] = &qhs_qspi, 1516 [SLAVE_QUP_0] = &qhs_qup0, 1517 [SLAVE_QUP_1] = &qhs_qup1, 1518 [SLAVE_SDCC_1] = &qhs_sdc1, 1519 [SLAVE_TCSR] = &qhs_tcsr, 1520 [SLAVE_TLMM] = &qhs_tlmm, 1521 [SLAVE_TME_CFG] = &qhs_tme_cfg, 1522 [SLAVE_USB3_0] = &qhs_usb3_0, 1523 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1524 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 1525 [SLAVE_WLAN_Q6_CFG] = &qhs_wlan_q6, 1526 [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg, 1527 [SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg, 1528 [SLAVE_SNOC_CFG] = &qns_snoc_cfg, 1529 [SLAVE_IMEM] = &qxs_imem, 1530 [SLAVE_PIMEM] = &qxs_pimem, 1531 [SLAVE_SERVICE_CNOC] = &srvc_cnoc, 1532 [SLAVE_PCIE_0] = &xs_pcie_0, 1533 [SLAVE_PCIE_1] = &xs_pcie_1, 1534 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1535 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1536 }; 1537 1538 static const struct qcom_icc_desc sar2130p_config_noc = { 1539 .config = &icc_regmap_config, 1540 .nodes = config_noc_nodes, 1541 .num_nodes = ARRAY_SIZE(config_noc_nodes), 1542 .bcms = config_noc_bcms, 1543 .num_bcms = ARRAY_SIZE(config_noc_bcms), 1544 }; 1545 1546 static struct qcom_icc_bcm * const gem_noc_bcms[] = { 1547 &bcm_sh0, 1548 &bcm_sh1, 1549 }; 1550 1551 static struct qcom_icc_node * const gem_noc_nodes[] = { 1552 [MASTER_GPU_TCU] = &alm_gpu_tcu, 1553 [MASTER_SYS_TCU] = &alm_sys_tcu, 1554 [MASTER_APPSS_PROC] = &chm_apps, 1555 [MASTER_GFX3D] = &qnm_gpu, 1556 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 1557 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 1558 [MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc, 1559 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, 1560 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 1561 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 1562 [MASTER_WLAN_Q6] = &qxm_wlan_q6, 1563 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, 1564 [SLAVE_LLCC] = &qns_llcc, 1565 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, 1566 }; 1567 1568 static const struct qcom_icc_desc sar2130p_gem_noc = { 1569 .config = &icc_regmap_config, 1570 .nodes = gem_noc_nodes, 1571 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 1572 .bcms = gem_noc_bcms, 1573 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 1574 }; 1575 1576 static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = { 1577 }; 1578 1579 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { 1580 [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc, 1581 [MASTER_LPASS_PROC] = &qxm_lpass_dsp, 1582 [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core, 1583 [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi, 1584 [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu, 1585 [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top, 1586 [SLAVE_LPASS_SNOC] = &qns_sysnoc, 1587 [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc, 1588 [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, 1589 }; 1590 1591 static const struct qcom_icc_desc sar2130p_lpass_ag_noc = { 1592 .config = &icc_regmap_config, 1593 .nodes = lpass_ag_noc_nodes, 1594 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), 1595 .bcms = lpass_ag_noc_bcms, 1596 .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms), 1597 }; 1598 1599 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 1600 &bcm_acv, 1601 &bcm_mc0, 1602 }; 1603 1604 static struct qcom_icc_node * const mc_virt_nodes[] = { 1605 [MASTER_LLCC] = &llcc_mc, 1606 [SLAVE_EBI1] = &ebi, 1607 }; 1608 1609 static const struct qcom_icc_desc sar2130p_mc_virt = { 1610 .nodes = mc_virt_nodes, 1611 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 1612 .bcms = mc_virt_bcms, 1613 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 1614 }; 1615 1616 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 1617 &bcm_mm0, 1618 &bcm_mm1, 1619 }; 1620 1621 static struct qcom_icc_node * const mmss_noc_nodes[] = { 1622 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, 1623 [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp, 1624 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, 1625 [MASTER_LSR] = &qnm_lsr, 1626 [MASTER_MDP] = &qnm_mdp, 1627 [MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg, 1628 [MASTER_VIDEO] = &qnm_video, 1629 [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu, 1630 [MASTER_VIDEO_PROC] = &qnm_video_cvp, 1631 [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu, 1632 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 1633 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, 1634 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 1635 }; 1636 1637 static const struct qcom_icc_desc sar2130p_mmss_noc = { 1638 .config = &icc_regmap_config, 1639 .nodes = mmss_noc_nodes, 1640 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 1641 .bcms = mmss_noc_bcms, 1642 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 1643 }; 1644 1645 static struct qcom_icc_bcm * const nsp_noc_bcms[] = { 1646 &bcm_co0, 1647 }; 1648 1649 static struct qcom_icc_node * const nsp_noc_nodes[] = { 1650 [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config, 1651 [MASTER_CDSP_PROC] = &qxm_nsp, 1652 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, 1653 [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, 1654 }; 1655 1656 static const struct qcom_icc_desc sar2130p_nsp_noc = { 1657 .config = &icc_regmap_config, 1658 .nodes = nsp_noc_nodes, 1659 .num_nodes = ARRAY_SIZE(nsp_noc_nodes), 1660 .bcms = nsp_noc_bcms, 1661 .num_bcms = ARRAY_SIZE(nsp_noc_bcms), 1662 }; 1663 1664 static struct qcom_icc_bcm * const pcie_anoc_bcms[] = { 1665 &bcm_sn7, 1666 }; 1667 1668 static struct qcom_icc_node * const pcie_anoc_nodes[] = { 1669 [MASTER_PCIE_0] = &xm_pcie3_0, 1670 [MASTER_PCIE_1] = &xm_pcie3_1, 1671 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, 1672 }; 1673 1674 static const struct qcom_icc_desc sar2130p_pcie_anoc = { 1675 .config = &icc_regmap_config, 1676 .nodes = pcie_anoc_nodes, 1677 .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), 1678 .bcms = pcie_anoc_bcms, 1679 .num_bcms = ARRAY_SIZE(pcie_anoc_bcms), 1680 }; 1681 1682 static struct qcom_icc_bcm * const system_noc_bcms[] = { 1683 &bcm_ce0, 1684 &bcm_sn0, 1685 &bcm_sn1, 1686 &bcm_sn3, 1687 &bcm_sn4, 1688 }; 1689 1690 static struct qcom_icc_node * const system_noc_nodes[] = { 1691 [MASTER_GIC_AHB] = &qhm_gic, 1692 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 1693 [MASTER_QSPI_0] = &qhm_qspi, 1694 [MASTER_QUP_0] = &qhm_qup0, 1695 [MASTER_QUP_1] = &qhm_qup1, 1696 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, 1697 [MASTER_CNOC_DATAPATH] = &qnm_cnoc_datapath, 1698 [MASTER_LPASS_ANOC] = &qnm_lpass_noc, 1699 [MASTER_SNOC_CFG] = &qnm_snoc_cfg, 1700 [MASTER_CRYPTO] = &qxm_crypto, 1701 [MASTER_PIMEM] = &qxm_pimem, 1702 [MASTER_GIC] = &xm_gic, 1703 [MASTER_QDSS_ETR] = &xm_qdss_etr_0, 1704 [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1, 1705 [MASTER_SDCC_1] = &xm_sdc1, 1706 [MASTER_USB3_0] = &xm_usb3_0, 1707 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, 1708 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, 1709 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 1710 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 1711 }; 1712 1713 static const struct qcom_icc_desc sar2130p_system_noc = { 1714 .config = &icc_regmap_config, 1715 .nodes = system_noc_nodes, 1716 .num_nodes = ARRAY_SIZE(system_noc_nodes), 1717 .bcms = system_noc_bcms, 1718 .num_bcms = ARRAY_SIZE(system_noc_bcms), 1719 }; 1720 1721 static const struct of_device_id qnoc_of_match[] = { 1722 { .compatible = "qcom,sar2130p-clk-virt", .data = &sar2130p_clk_virt}, 1723 { .compatible = "qcom,sar2130p-config-noc", .data = &sar2130p_config_noc}, 1724 { .compatible = "qcom,sar2130p-gem-noc", .data = &sar2130p_gem_noc}, 1725 { .compatible = "qcom,sar2130p-lpass-ag-noc", .data = &sar2130p_lpass_ag_noc}, 1726 { .compatible = "qcom,sar2130p-mc-virt", .data = &sar2130p_mc_virt}, 1727 { .compatible = "qcom,sar2130p-mmss-noc", .data = &sar2130p_mmss_noc}, 1728 { .compatible = "qcom,sar2130p-nsp-noc", .data = &sar2130p_nsp_noc}, 1729 { .compatible = "qcom,sar2130p-pcie-anoc", .data = &sar2130p_pcie_anoc}, 1730 { .compatible = "qcom,sar2130p-system-noc", .data = &sar2130p_system_noc}, 1731 { } 1732 }; 1733 MODULE_DEVICE_TABLE(of, qnoc_of_match); 1734 1735 static struct platform_driver qnoc_driver = { 1736 .probe = qcom_icc_rpmh_probe, 1737 .remove = qcom_icc_rpmh_remove, 1738 .driver = { 1739 .name = "qnoc-sar2130p", 1740 .of_match_table = qnoc_of_match, 1741 .sync_state = icc_sync_state, 1742 }, 1743 }; 1744 1745 static int __init qnoc_driver_init(void) 1746 { 1747 return platform_driver_register(&qnoc_driver); 1748 } 1749 core_initcall(qnoc_driver_init); 1750 1751 static void __exit qnoc_driver_exit(void) 1752 { 1753 platform_driver_unregister(&qnoc_driver); 1754 } 1755 1756 module_exit(qnoc_driver_exit); 1757 MODULE_DESCRIPTION("Qualcomm SAR2130P NoC driver"); 1758 MODULE_LICENSE("GPL"); 1759