1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. 5 * Copyright (c) 2024, Linaro Ltd. 6 */ 7 8 #include <linux/device.h> 9 #include <linux/interconnect.h> 10 #include <linux/interconnect-provider.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/of_device.h> 14 #include <linux/of_platform.h> 15 #include <linux/platform_device.h> 16 #include <linux/sort.h> 17 #include <dt-bindings/interconnect/qcom,sar2130p-rpmh.h> 18 19 #include "bcm-voter.h" 20 #include "icc-common.h" 21 #include "icc-rpmh.h" 22 23 enum { 24 SAR2130P_MASTER_QUP_CORE_0, 25 SAR2130P_MASTER_QUP_CORE_1, 26 SAR2130P_MASTER_GEM_NOC_CNOC, 27 SAR2130P_MASTER_GEM_NOC_PCIE_SNOC, 28 SAR2130P_MASTER_QDSS_DAP, 29 SAR2130P_MASTER_GPU_TCU, 30 SAR2130P_MASTER_SYS_TCU, 31 SAR2130P_MASTER_APPSS_PROC, 32 SAR2130P_MASTER_GFX3D, 33 SAR2130P_MASTER_MNOC_HF_MEM_NOC, 34 SAR2130P_MASTER_MNOC_SF_MEM_NOC, 35 SAR2130P_MASTER_COMPUTE_NOC, 36 SAR2130P_MASTER_ANOC_PCIE_GEM_NOC, 37 SAR2130P_MASTER_SNOC_GC_MEM_NOC, 38 SAR2130P_MASTER_SNOC_SF_MEM_NOC, 39 SAR2130P_MASTER_WLAN_Q6, 40 SAR2130P_MASTER_CNOC_LPASS_AG_NOC, 41 SAR2130P_MASTER_LPASS_PROC, 42 SAR2130P_MASTER_LLCC, 43 SAR2130P_MASTER_CAMNOC_HF, 44 SAR2130P_MASTER_CAMNOC_ICP, 45 SAR2130P_MASTER_CAMNOC_SF, 46 SAR2130P_MASTER_LSR, 47 SAR2130P_MASTER_MDP, 48 SAR2130P_MASTER_CNOC_MNOC_CFG, 49 SAR2130P_MASTER_VIDEO, 50 SAR2130P_MASTER_VIDEO_CV_PROC, 51 SAR2130P_MASTER_VIDEO_PROC, 52 SAR2130P_MASTER_VIDEO_V_PROC, 53 SAR2130P_MASTER_CDSP_NOC_CFG, 54 SAR2130P_MASTER_CDSP_PROC, 55 SAR2130P_MASTER_PCIE_0, 56 SAR2130P_MASTER_PCIE_1, 57 SAR2130P_MASTER_GIC_AHB, 58 SAR2130P_MASTER_QDSS_BAM, 59 SAR2130P_MASTER_QSPI_0, 60 SAR2130P_MASTER_QUP_0, 61 SAR2130P_MASTER_QUP_1, 62 SAR2130P_MASTER_A2NOC_SNOC, 63 SAR2130P_MASTER_CNOC_DATAPATH, 64 SAR2130P_MASTER_LPASS_ANOC, 65 SAR2130P_MASTER_SNOC_CFG, 66 SAR2130P_MASTER_CRYPTO, 67 SAR2130P_MASTER_PIMEM, 68 SAR2130P_MASTER_GIC, 69 SAR2130P_MASTER_QDSS_ETR, 70 SAR2130P_MASTER_QDSS_ETR_1, 71 SAR2130P_MASTER_SDCC_1, 72 SAR2130P_MASTER_USB3_0, 73 SAR2130P_SLAVE_QUP_CORE_0, 74 SAR2130P_SLAVE_QUP_CORE_1, 75 SAR2130P_SLAVE_AHB2PHY_SOUTH, 76 SAR2130P_SLAVE_AOSS, 77 SAR2130P_SLAVE_CAMERA_CFG, 78 SAR2130P_SLAVE_CLK_CTL, 79 SAR2130P_SLAVE_CDSP_CFG, 80 SAR2130P_SLAVE_RBCPR_CX_CFG, 81 SAR2130P_SLAVE_RBCPR_MMCX_CFG, 82 SAR2130P_SLAVE_RBCPR_MXA_CFG, 83 SAR2130P_SLAVE_RBCPR_MXC_CFG, 84 SAR2130P_SLAVE_CPR_NSPCX, 85 SAR2130P_SLAVE_CRYPTO_0_CFG, 86 SAR2130P_SLAVE_CX_RDPM, 87 SAR2130P_SLAVE_DISPLAY_CFG, 88 SAR2130P_SLAVE_GFX3D_CFG, 89 SAR2130P_SLAVE_IMEM_CFG, 90 SAR2130P_SLAVE_IPC_ROUTER_CFG, 91 SAR2130P_SLAVE_LPASS, 92 SAR2130P_SLAVE_MX_RDPM, 93 SAR2130P_SLAVE_PCIE_0_CFG, 94 SAR2130P_SLAVE_PCIE_1_CFG, 95 SAR2130P_SLAVE_PDM, 96 SAR2130P_SLAVE_PIMEM_CFG, 97 SAR2130P_SLAVE_PRNG, 98 SAR2130P_SLAVE_QDSS_CFG, 99 SAR2130P_SLAVE_QSPI_0, 100 SAR2130P_SLAVE_QUP_0, 101 SAR2130P_SLAVE_QUP_1, 102 SAR2130P_SLAVE_SDCC_1, 103 SAR2130P_SLAVE_TCSR, 104 SAR2130P_SLAVE_TLMM, 105 SAR2130P_SLAVE_TME_CFG, 106 SAR2130P_SLAVE_USB3_0, 107 SAR2130P_SLAVE_VENUS_CFG, 108 SAR2130P_SLAVE_VSENSE_CTRL_CFG, 109 SAR2130P_SLAVE_WLAN_Q6_CFG, 110 SAR2130P_SLAVE_DDRSS_CFG, 111 SAR2130P_SLAVE_CNOC_MNOC_CFG, 112 SAR2130P_SLAVE_SNOC_CFG, 113 SAR2130P_SLAVE_IMEM, 114 SAR2130P_SLAVE_PIMEM, 115 SAR2130P_SLAVE_SERVICE_CNOC, 116 SAR2130P_SLAVE_PCIE_0, 117 SAR2130P_SLAVE_PCIE_1, 118 SAR2130P_SLAVE_QDSS_STM, 119 SAR2130P_SLAVE_TCU, 120 SAR2130P_SLAVE_GEM_NOC_CNOC, 121 SAR2130P_SLAVE_LLCC, 122 SAR2130P_SLAVE_MEM_NOC_PCIE_SNOC, 123 SAR2130P_SLAVE_LPASS_CORE_CFG, 124 SAR2130P_SLAVE_LPASS_LPI_CFG, 125 SAR2130P_SLAVE_LPASS_MPU_CFG, 126 SAR2130P_SLAVE_LPASS_TOP_CFG, 127 SAR2130P_SLAVE_LPASS_SNOC, 128 SAR2130P_SLAVE_SERVICES_LPASS_AML_NOC, 129 SAR2130P_SLAVE_SERVICE_LPASS_AG_NOC, 130 SAR2130P_SLAVE_EBI1, 131 SAR2130P_SLAVE_MNOC_HF_MEM_NOC, 132 SAR2130P_SLAVE_MNOC_SF_MEM_NOC, 133 SAR2130P_SLAVE_SERVICE_MNOC, 134 SAR2130P_SLAVE_CDSP_MEM_NOC, 135 SAR2130P_SLAVE_SERVICE_NSP_NOC, 136 SAR2130P_SLAVE_ANOC_PCIE_GEM_NOC, 137 SAR2130P_SLAVE_A2NOC_SNOC, 138 SAR2130P_SLAVE_SNOC_GEM_NOC_GC, 139 SAR2130P_SLAVE_SNOC_GEM_NOC_SF, 140 SAR2130P_SLAVE_SERVICE_SNOC, 141 }; 142 143 static const struct regmap_config icc_regmap_config = { 144 .reg_bits = 32, 145 .reg_stride = 4, 146 .val_bits = 32, 147 .fast_io = true, 148 }; 149 150 static struct qcom_icc_node qup0_core_master = { 151 .name = "qup0_core_master", 152 .id = SAR2130P_MASTER_QUP_CORE_0, 153 .channels = 1, 154 .buswidth = 4, 155 .num_links = 1, 156 .links = { SAR2130P_SLAVE_QUP_CORE_0 }, 157 }; 158 159 static struct qcom_icc_node qup1_core_master = { 160 .name = "qup1_core_master", 161 .id = SAR2130P_MASTER_QUP_CORE_1, 162 .channels = 1, 163 .buswidth = 4, 164 .num_links = 1, 165 .links = { SAR2130P_SLAVE_QUP_CORE_1 }, 166 }; 167 168 static struct qcom_icc_node qnm_gemnoc_cnoc = { 169 .name = "qnm_gemnoc_cnoc", 170 .id = SAR2130P_MASTER_GEM_NOC_CNOC, 171 .channels = 1, 172 .buswidth = 16, 173 .num_links = 43, 174 .links = { SAR2130P_SLAVE_AHB2PHY_SOUTH, SAR2130P_SLAVE_AOSS, 175 SAR2130P_SLAVE_CAMERA_CFG, SAR2130P_SLAVE_CLK_CTL, 176 SAR2130P_SLAVE_CDSP_CFG, SAR2130P_SLAVE_RBCPR_CX_CFG, 177 SAR2130P_SLAVE_RBCPR_MMCX_CFG, SAR2130P_SLAVE_RBCPR_MXA_CFG, 178 SAR2130P_SLAVE_RBCPR_MXC_CFG, SAR2130P_SLAVE_CPR_NSPCX, 179 SAR2130P_SLAVE_CRYPTO_0_CFG, SAR2130P_SLAVE_CX_RDPM, 180 SAR2130P_SLAVE_DISPLAY_CFG, SAR2130P_SLAVE_GFX3D_CFG, 181 SAR2130P_SLAVE_IMEM_CFG, SAR2130P_SLAVE_IPC_ROUTER_CFG, 182 SAR2130P_SLAVE_LPASS, SAR2130P_SLAVE_MX_RDPM, 183 SAR2130P_SLAVE_PCIE_0_CFG, SAR2130P_SLAVE_PCIE_1_CFG, 184 SAR2130P_SLAVE_PDM, SAR2130P_SLAVE_PIMEM_CFG, 185 SAR2130P_SLAVE_PRNG, SAR2130P_SLAVE_QDSS_CFG, 186 SAR2130P_SLAVE_QSPI_0, SAR2130P_SLAVE_QUP_0, 187 SAR2130P_SLAVE_QUP_1, SAR2130P_SLAVE_SDCC_1, 188 SAR2130P_SLAVE_TCSR, SAR2130P_SLAVE_TLMM, 189 SAR2130P_SLAVE_TME_CFG, SAR2130P_SLAVE_USB3_0, 190 SAR2130P_SLAVE_VENUS_CFG, SAR2130P_SLAVE_VSENSE_CTRL_CFG, 191 SAR2130P_SLAVE_WLAN_Q6_CFG, SAR2130P_SLAVE_DDRSS_CFG, 192 SAR2130P_SLAVE_CNOC_MNOC_CFG, SAR2130P_SLAVE_SNOC_CFG, 193 SAR2130P_SLAVE_IMEM, SAR2130P_SLAVE_PIMEM, 194 SAR2130P_SLAVE_SERVICE_CNOC, SAR2130P_SLAVE_QDSS_STM, 195 SAR2130P_SLAVE_TCU }, 196 }; 197 198 static struct qcom_icc_node qnm_gemnoc_pcie = { 199 .name = "qnm_gemnoc_pcie", 200 .id = SAR2130P_MASTER_GEM_NOC_PCIE_SNOC, 201 .channels = 1, 202 .buswidth = 8, 203 .num_links = 2, 204 .links = { SAR2130P_SLAVE_PCIE_0, SAR2130P_SLAVE_PCIE_1 }, 205 }; 206 207 static struct qcom_icc_node xm_qdss_dap = { 208 .name = "xm_qdss_dap", 209 .id = SAR2130P_MASTER_QDSS_DAP, 210 .channels = 1, 211 .buswidth = 8, 212 .num_links = 43, 213 .links = { SAR2130P_SLAVE_AHB2PHY_SOUTH, SAR2130P_SLAVE_AOSS, 214 SAR2130P_SLAVE_CAMERA_CFG, SAR2130P_SLAVE_CLK_CTL, 215 SAR2130P_SLAVE_CDSP_CFG, SAR2130P_SLAVE_RBCPR_CX_CFG, 216 SAR2130P_SLAVE_RBCPR_MMCX_CFG, SAR2130P_SLAVE_RBCPR_MXA_CFG, 217 SAR2130P_SLAVE_RBCPR_MXC_CFG, SAR2130P_SLAVE_CPR_NSPCX, 218 SAR2130P_SLAVE_CRYPTO_0_CFG, SAR2130P_SLAVE_CX_RDPM, 219 SAR2130P_SLAVE_DISPLAY_CFG, SAR2130P_SLAVE_GFX3D_CFG, 220 SAR2130P_SLAVE_IMEM_CFG, SAR2130P_SLAVE_IPC_ROUTER_CFG, 221 SAR2130P_SLAVE_LPASS, SAR2130P_SLAVE_MX_RDPM, 222 SAR2130P_SLAVE_PCIE_0_CFG, SAR2130P_SLAVE_PCIE_1_CFG, 223 SAR2130P_SLAVE_PDM, SAR2130P_SLAVE_PIMEM_CFG, 224 SAR2130P_SLAVE_PRNG, SAR2130P_SLAVE_QDSS_CFG, 225 SAR2130P_SLAVE_QSPI_0, SAR2130P_SLAVE_QUP_0, 226 SAR2130P_SLAVE_QUP_1, SAR2130P_SLAVE_SDCC_1, 227 SAR2130P_SLAVE_TCSR, SAR2130P_SLAVE_TLMM, 228 SAR2130P_SLAVE_TME_CFG, SAR2130P_SLAVE_USB3_0, 229 SAR2130P_SLAVE_VENUS_CFG, SAR2130P_SLAVE_VSENSE_CTRL_CFG, 230 SAR2130P_SLAVE_WLAN_Q6_CFG, SAR2130P_SLAVE_DDRSS_CFG, 231 SAR2130P_SLAVE_CNOC_MNOC_CFG, SAR2130P_SLAVE_SNOC_CFG, 232 SAR2130P_SLAVE_IMEM, SAR2130P_SLAVE_PIMEM, 233 SAR2130P_SLAVE_SERVICE_CNOC, SAR2130P_SLAVE_QDSS_STM, 234 SAR2130P_SLAVE_TCU }, 235 }; 236 237 static const struct qcom_icc_qosbox alm_gpu_tcu_qos = { 238 .num_ports = 1, 239 .port_offsets = { 0x9e000 }, 240 .prio = 1, 241 .urg_fwd = 0, 242 .prio_fwd_disable = 1, 243 }; 244 245 static struct qcom_icc_node alm_gpu_tcu = { 246 .name = "alm_gpu_tcu", 247 .id = SAR2130P_MASTER_GPU_TCU, 248 .channels = 1, 249 .buswidth = 8, 250 .qosbox = &alm_gpu_tcu_qos, 251 .num_links = 2, 252 .links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC }, 253 }; 254 255 static const struct qcom_icc_qosbox alm_sys_tcu_qos = { 256 .num_ports = 1, 257 .port_offsets = { 0x9f000 }, 258 .prio = 6, 259 .urg_fwd = 0, 260 .prio_fwd_disable = 1, 261 }; 262 263 static struct qcom_icc_node alm_sys_tcu = { 264 .name = "alm_sys_tcu", 265 .id = SAR2130P_MASTER_SYS_TCU, 266 .channels = 1, 267 .buswidth = 8, 268 .qosbox = &alm_sys_tcu_qos, 269 .num_links = 2, 270 .links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC }, 271 }; 272 273 static struct qcom_icc_node chm_apps = { 274 .name = "chm_apps", 275 .id = SAR2130P_MASTER_APPSS_PROC, 276 .channels = 1, 277 .buswidth = 32, 278 .num_links = 3, 279 .links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC, 280 SAR2130P_SLAVE_MEM_NOC_PCIE_SNOC }, 281 }; 282 283 static const struct qcom_icc_qosbox qnm_gpu_qos = { 284 .num_ports = 2, 285 .port_offsets = { 0xe000, 0x4e000 }, 286 .prio = 0, 287 .urg_fwd = 0, 288 .prio_fwd_disable = 1, 289 }; 290 291 static struct qcom_icc_node qnm_gpu = { 292 .name = "qnm_gpu", 293 .id = SAR2130P_MASTER_GFX3D, 294 .channels = 2, 295 .buswidth = 32, 296 .qosbox = &qnm_gpu_qos, 297 .num_links = 2, 298 .links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC }, 299 }; 300 301 static const struct qcom_icc_qosbox qnm_mnoc_hf_qos = { 302 .num_ports = 2, 303 .port_offsets = { 0xf000, 0x4f000 }, 304 .prio = 0, 305 .urg_fwd = 1, 306 }; 307 308 static struct qcom_icc_node qnm_mnoc_hf = { 309 .name = "qnm_mnoc_hf", 310 .id = SAR2130P_MASTER_MNOC_HF_MEM_NOC, 311 .channels = 2, 312 .buswidth = 32, 313 .qosbox = &qnm_mnoc_hf_qos, 314 .num_links = 2, 315 .links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC }, 316 }; 317 318 static const struct qcom_icc_qosbox qnm_mnoc_sf_qos = { 319 .num_ports = 1, 320 .port_offsets = { 0x9d000 }, 321 .prio = 0, 322 .urg_fwd = 1, 323 }; 324 325 static struct qcom_icc_node qnm_mnoc_sf = { 326 .name = "qnm_mnoc_sf", 327 .id = SAR2130P_MASTER_MNOC_SF_MEM_NOC, 328 .channels = 1, 329 .buswidth = 32, 330 .qosbox = &qnm_mnoc_sf_qos, 331 .num_links = 2, 332 .links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC }, 333 }; 334 335 static const struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = { 336 .num_ports = 2, 337 .port_offsets = { 0x10000, 0x50000 }, 338 .prio = 0, 339 .urg_fwd = 0, 340 .prio_fwd_disable = 1, 341 }; 342 343 static struct qcom_icc_node qnm_nsp_gemnoc = { 344 .name = "qnm_nsp_gemnoc", 345 .id = SAR2130P_MASTER_COMPUTE_NOC, 346 .channels = 2, 347 .buswidth = 32, 348 .qosbox = &qnm_nsp_gemnoc_qos, 349 .num_links = 2, 350 .links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC }, 351 }; 352 353 static const struct qcom_icc_qosbox qnm_pcie_qos = { 354 .num_ports = 1, 355 .port_offsets = { 0xa2000 }, 356 .prio = 2, 357 .urg_fwd = 1, 358 }; 359 360 static struct qcom_icc_node qnm_pcie = { 361 .name = "qnm_pcie", 362 .id = SAR2130P_MASTER_ANOC_PCIE_GEM_NOC, 363 .channels = 1, 364 .buswidth = 16, 365 .qosbox = &qnm_pcie_qos, 366 .num_links = 2, 367 .links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC }, 368 }; 369 370 static const struct qcom_icc_qosbox qnm_snoc_gc_qos = { 371 .num_ports = 1, 372 .port_offsets = { 0xa0000 }, 373 .prio = 0, 374 .urg_fwd = 1, 375 }; 376 377 static struct qcom_icc_node qnm_snoc_gc = { 378 .name = "qnm_snoc_gc", 379 .id = SAR2130P_MASTER_SNOC_GC_MEM_NOC, 380 .channels = 1, 381 .buswidth = 8, 382 .qosbox = &qnm_snoc_gc_qos, 383 .num_links = 1, 384 .links = { SAR2130P_SLAVE_LLCC }, 385 }; 386 387 static const struct qcom_icc_qosbox qnm_snoc_sf_qos = { 388 .num_ports = 1, 389 .port_offsets = { 0xa1000 }, 390 .prio = 0, 391 .urg_fwd = 1, 392 }; 393 394 static struct qcom_icc_node qnm_snoc_sf = { 395 .name = "qnm_snoc_sf", 396 .id = SAR2130P_MASTER_SNOC_SF_MEM_NOC, 397 .channels = 1, 398 .buswidth = 16, 399 .qosbox = &qnm_snoc_sf_qos, 400 .num_links = 3, 401 .links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC, 402 SAR2130P_SLAVE_MEM_NOC_PCIE_SNOC }, 403 }; 404 405 static struct qcom_icc_node qxm_wlan_q6 = { 406 .name = "qxm_wlan_q6", 407 .id = SAR2130P_MASTER_WLAN_Q6, 408 .channels = 1, 409 .buswidth = 8, 410 .num_links = 3, 411 .links = { SAR2130P_SLAVE_GEM_NOC_CNOC, SAR2130P_SLAVE_LLCC, 412 SAR2130P_SLAVE_MEM_NOC_PCIE_SNOC }, 413 }; 414 415 static struct qcom_icc_node qhm_config_noc = { 416 .name = "qhm_config_noc", 417 .id = SAR2130P_MASTER_CNOC_LPASS_AG_NOC, 418 .channels = 1, 419 .buswidth = 4, 420 .num_links = 6, 421 .links = { SAR2130P_SLAVE_LPASS_CORE_CFG, SAR2130P_SLAVE_LPASS_LPI_CFG, 422 SAR2130P_SLAVE_LPASS_MPU_CFG, SAR2130P_SLAVE_LPASS_TOP_CFG, 423 SAR2130P_SLAVE_SERVICES_LPASS_AML_NOC, SAR2130P_SLAVE_SERVICE_LPASS_AG_NOC }, 424 }; 425 426 static struct qcom_icc_node qxm_lpass_dsp = { 427 .name = "qxm_lpass_dsp", 428 .id = SAR2130P_MASTER_LPASS_PROC, 429 .channels = 1, 430 .buswidth = 8, 431 .num_links = 4, 432 .links = { SAR2130P_SLAVE_LPASS_TOP_CFG, SAR2130P_SLAVE_LPASS_SNOC, 433 SAR2130P_SLAVE_SERVICES_LPASS_AML_NOC, SAR2130P_SLAVE_SERVICE_LPASS_AG_NOC }, 434 }; 435 436 static struct qcom_icc_node llcc_mc = { 437 .name = "llcc_mc", 438 .id = SAR2130P_MASTER_LLCC, 439 .channels = 1, 440 .buswidth = 4, 441 .num_links = 1, 442 .links = { SAR2130P_SLAVE_EBI1 }, 443 }; 444 445 static const struct qcom_icc_qosbox qnm_camnoc_hf_qos = { 446 .num_ports = 1, 447 .port_offsets = { 0x1c000 }, 448 .prio = 0, 449 .urg_fwd = 1, 450 }; 451 452 static struct qcom_icc_node qnm_camnoc_hf = { 453 .name = "qnm_camnoc_hf", 454 .id = SAR2130P_MASTER_CAMNOC_HF, 455 .channels = 1, 456 .buswidth = 32, 457 .qosbox = &qnm_camnoc_hf_qos, 458 .num_links = 1, 459 .links = { SAR2130P_SLAVE_MNOC_HF_MEM_NOC }, 460 }; 461 462 static const struct qcom_icc_qosbox qnm_camnoc_icp_qos = { 463 .num_ports = 1, 464 .port_offsets = { 0x1c080 }, 465 .prio = 4, 466 .urg_fwd = 1, 467 }; 468 469 static struct qcom_icc_node qnm_camnoc_icp = { 470 .name = "qnm_camnoc_icp", 471 .id = SAR2130P_MASTER_CAMNOC_ICP, 472 .channels = 1, 473 .buswidth = 8, 474 .qosbox = &qnm_camnoc_icp_qos, 475 .num_links = 1, 476 .links = { SAR2130P_SLAVE_MNOC_SF_MEM_NOC }, 477 }; 478 479 static const struct qcom_icc_qosbox qnm_camnoc_sf_qos = { 480 .num_ports = 1, 481 .port_offsets = { 0x1c100 }, 482 .prio = 0, 483 .urg_fwd = 1, 484 }; 485 486 static struct qcom_icc_node qnm_camnoc_sf = { 487 .name = "qnm_camnoc_sf", 488 .id = SAR2130P_MASTER_CAMNOC_SF, 489 .channels = 1, 490 .buswidth = 32, 491 .qosbox = &qnm_camnoc_sf_qos, 492 .num_links = 1, 493 .links = { SAR2130P_SLAVE_MNOC_SF_MEM_NOC }, 494 }; 495 496 static const struct qcom_icc_qosbox qnm_lsr_qos = { 497 .num_ports = 2, 498 .port_offsets = { 0x1f000, 0x1f080 }, 499 .prio = 3, 500 .urg_fwd = 1, 501 }; 502 503 static struct qcom_icc_node qnm_lsr = { 504 .name = "qnm_lsr", 505 .id = SAR2130P_MASTER_LSR, 506 .channels = 2, 507 .buswidth = 32, 508 .qosbox = &qnm_lsr_qos, 509 .num_links = 1, 510 .links = { SAR2130P_SLAVE_MNOC_HF_MEM_NOC }, 511 }; 512 513 static const struct qcom_icc_qosbox qnm_mdp_qos = { 514 .num_ports = 2, 515 .port_offsets = { 0x1d000, 0x1d080 }, 516 .prio = 0, 517 .urg_fwd = 1, 518 }; 519 520 static struct qcom_icc_node qnm_mdp = { 521 .name = "qnm_mdp", 522 .id = SAR2130P_MASTER_MDP, 523 .channels = 2, 524 .buswidth = 32, 525 .qosbox = &qnm_mdp_qos, 526 .num_links = 1, 527 .links = { SAR2130P_SLAVE_MNOC_HF_MEM_NOC }, 528 }; 529 530 static struct qcom_icc_node qnm_mnoc_cfg = { 531 .name = "qnm_mnoc_cfg", 532 .id = SAR2130P_MASTER_CNOC_MNOC_CFG, 533 .channels = 1, 534 .buswidth = 4, 535 .num_links = 1, 536 .links = { SAR2130P_SLAVE_SERVICE_MNOC }, 537 }; 538 539 static const struct qcom_icc_qosbox qnm_video_qos = { 540 .num_ports = 2, 541 .port_offsets = { 0x1e000, 0x1e080 }, 542 .prio = 0, 543 .urg_fwd = 1, 544 }; 545 546 static struct qcom_icc_node qnm_video = { 547 .name = "qnm_video", 548 .id = SAR2130P_MASTER_VIDEO, 549 .channels = 2, 550 .buswidth = 32, 551 .qosbox = &qnm_video_qos, 552 .num_links = 1, 553 .links = { SAR2130P_SLAVE_MNOC_SF_MEM_NOC }, 554 }; 555 556 static const struct qcom_icc_qosbox qnm_video_cv_cpu_qos = { 557 .num_ports = 1, 558 .port_offsets = { 0x1e100 }, 559 .prio = 4, 560 .urg_fwd = 1, 561 }; 562 563 static struct qcom_icc_node qnm_video_cv_cpu = { 564 .name = "qnm_video_cv_cpu", 565 .id = SAR2130P_MASTER_VIDEO_CV_PROC, 566 .channels = 1, 567 .buswidth = 8, 568 .qosbox = &qnm_video_cv_cpu_qos, 569 .num_links = 1, 570 .links = { SAR2130P_SLAVE_MNOC_SF_MEM_NOC }, 571 }; 572 573 static const struct qcom_icc_qosbox qnm_video_cvp_qos = { 574 .num_ports = 1, 575 .port_offsets = { 0x1e180 }, 576 .prio = 0, 577 .urg_fwd = 1, 578 }; 579 580 static struct qcom_icc_node qnm_video_cvp = { 581 .name = "qnm_video_cvp", 582 .id = SAR2130P_MASTER_VIDEO_PROC, 583 .channels = 1, 584 .buswidth = 32, 585 .qosbox = &qnm_video_cvp_qos, 586 .num_links = 1, 587 .links = { SAR2130P_SLAVE_MNOC_SF_MEM_NOC }, 588 }; 589 590 static const struct qcom_icc_qosbox qnm_video_v_cpu_qos = { 591 .num_ports = 1, 592 .port_offsets = { 0x1e200 }, 593 .prio = 4, 594 .urg_fwd = 1, 595 }; 596 597 static struct qcom_icc_node qnm_video_v_cpu = { 598 .name = "qnm_video_v_cpu", 599 .id = SAR2130P_MASTER_VIDEO_V_PROC, 600 .channels = 1, 601 .buswidth = 8, 602 .qosbox = &qnm_video_v_cpu_qos, 603 .num_links = 1, 604 .links = { SAR2130P_SLAVE_MNOC_SF_MEM_NOC }, 605 }; 606 607 static struct qcom_icc_node qhm_nsp_noc_config = { 608 .name = "qhm_nsp_noc_config", 609 .id = SAR2130P_MASTER_CDSP_NOC_CFG, 610 .channels = 1, 611 .buswidth = 4, 612 .num_links = 1, 613 .links = { SAR2130P_SLAVE_SERVICE_NSP_NOC }, 614 }; 615 616 static struct qcom_icc_node qxm_nsp = { 617 .name = "qxm_nsp", 618 .id = SAR2130P_MASTER_CDSP_PROC, 619 .channels = 2, 620 .buswidth = 32, 621 .num_links = 1, 622 .links = { SAR2130P_SLAVE_CDSP_MEM_NOC }, 623 }; 624 625 static const struct qcom_icc_qosbox xm_pcie3_0_qos = { 626 .num_ports = 1, 627 .port_offsets = { 0x9000 }, 628 .prio = 3, 629 .urg_fwd = 0, 630 .prio_fwd_disable = 1, 631 }; 632 633 static struct qcom_icc_node xm_pcie3_0 = { 634 .name = "xm_pcie3_0", 635 .id = SAR2130P_MASTER_PCIE_0, 636 .channels = 1, 637 .buswidth = 8, 638 .qosbox = &xm_pcie3_0_qos, 639 .num_links = 1, 640 .links = { SAR2130P_SLAVE_ANOC_PCIE_GEM_NOC }, 641 }; 642 643 static const struct qcom_icc_qosbox xm_pcie3_1_qos = { 644 .num_ports = 1, 645 .port_offsets = { 0xa000 }, 646 .prio = 2, 647 .urg_fwd = 0, 648 .prio_fwd_disable = 1, 649 }; 650 651 static struct qcom_icc_node xm_pcie3_1 = { 652 .name = "xm_pcie3_1", 653 .id = SAR2130P_MASTER_PCIE_1, 654 .channels = 1, 655 .buswidth = 8, 656 .qosbox = &xm_pcie3_1_qos, 657 .num_links = 1, 658 .links = { SAR2130P_SLAVE_ANOC_PCIE_GEM_NOC }, 659 }; 660 661 static const struct qcom_icc_qosbox qhm_gic_qos = { 662 .num_ports = 1, 663 .port_offsets = { 0x1d000 }, 664 .prio = 2, 665 .urg_fwd = 0, 666 .prio_fwd_disable = 1, 667 }; 668 669 static struct qcom_icc_node qhm_gic = { 670 .name = "qhm_gic", 671 .id = SAR2130P_MASTER_GIC_AHB, 672 .channels = 1, 673 .buswidth = 4, 674 .qosbox = &qhm_gic_qos, 675 .num_links = 1, 676 .links = { SAR2130P_SLAVE_SNOC_GEM_NOC_SF }, 677 }; 678 679 static const struct qcom_icc_qosbox qhm_qdss_bam_qos = { 680 .num_ports = 1, 681 .port_offsets = { 0x22000 }, 682 .prio = 2, 683 .urg_fwd = 0, 684 .prio_fwd_disable = 1, 685 }; 686 687 static struct qcom_icc_node qhm_qdss_bam = { 688 .name = "qhm_qdss_bam", 689 .id = SAR2130P_MASTER_QDSS_BAM, 690 .channels = 1, 691 .buswidth = 4, 692 .qosbox = &qhm_qdss_bam_qos, 693 .num_links = 1, 694 .links = { SAR2130P_SLAVE_A2NOC_SNOC }, 695 }; 696 697 static const struct qcom_icc_qosbox qhm_qspi_qos = { 698 .num_ports = 1, 699 .port_offsets = { 0x23000 }, 700 .prio = 2, 701 .urg_fwd = 0, 702 .prio_fwd_disable = 1, 703 }; 704 705 static struct qcom_icc_node qhm_qspi = { 706 .name = "qhm_qspi", 707 .id = SAR2130P_MASTER_QSPI_0, 708 .channels = 1, 709 .buswidth = 4, 710 .qosbox = &qhm_qspi_qos, 711 .num_links = 1, 712 .links = { SAR2130P_SLAVE_A2NOC_SNOC }, 713 }; 714 715 static const struct qcom_icc_qosbox qhm_qup0_qos = { 716 .num_ports = 1, 717 .port_offsets = { 0x24000 }, 718 .prio = 2, 719 .urg_fwd = 0, 720 .prio_fwd_disable = 1, 721 }; 722 723 static struct qcom_icc_node qhm_qup0 = { 724 .name = "qhm_qup0", 725 .id = SAR2130P_MASTER_QUP_0, 726 .channels = 1, 727 .buswidth = 4, 728 .qosbox = &qhm_qup0_qos, 729 .num_links = 1, 730 .links = { SAR2130P_SLAVE_A2NOC_SNOC }, 731 }; 732 733 static const struct qcom_icc_qosbox qhm_qup1_qos = { 734 .num_ports = 1, 735 .port_offsets = { 0x25000 }, 736 .prio = 2, 737 .urg_fwd = 0, 738 .prio_fwd_disable = 1, 739 }; 740 741 static struct qcom_icc_node qhm_qup1 = { 742 .name = "qhm_qup1", 743 .id = SAR2130P_MASTER_QUP_1, 744 .channels = 1, 745 .buswidth = 4, 746 .qosbox = &qhm_qup1_qos, 747 .num_links = 1, 748 .links = { SAR2130P_SLAVE_A2NOC_SNOC }, 749 }; 750 751 static struct qcom_icc_node qnm_aggre2_noc = { 752 .name = "qnm_aggre2_noc", 753 .id = SAR2130P_MASTER_A2NOC_SNOC, 754 .channels = 1, 755 .buswidth = 16, 756 .num_links = 1, 757 .links = { SAR2130P_SLAVE_SNOC_GEM_NOC_SF }, 758 }; 759 760 static const struct qcom_icc_qosbox qnm_cnoc_datapath_qos = { 761 .num_ports = 1, 762 .port_offsets = { 0x26000 }, 763 .prio = 2, 764 .urg_fwd = 0, 765 .prio_fwd_disable = 1, 766 }; 767 768 static struct qcom_icc_node qnm_cnoc_datapath = { 769 .name = "qnm_cnoc_datapath", 770 .id = SAR2130P_MASTER_CNOC_DATAPATH, 771 .channels = 1, 772 .buswidth = 8, 773 .qosbox = &qnm_cnoc_datapath_qos, 774 .num_links = 1, 775 .links = { SAR2130P_SLAVE_A2NOC_SNOC }, 776 }; 777 778 static const struct qcom_icc_qosbox qnm_lpass_noc_qos = { 779 .num_ports = 1, 780 .port_offsets = { 0x1e000 }, 781 .prio = 0, 782 .urg_fwd = 0, 783 .prio_fwd_disable = 1, 784 }; 785 786 static struct qcom_icc_node qnm_lpass_noc = { 787 .name = "qnm_lpass_noc", 788 .id = SAR2130P_MASTER_LPASS_ANOC, 789 .channels = 1, 790 .buswidth = 16, 791 .qosbox = &qnm_lpass_noc_qos, 792 .num_links = 1, 793 .links = { SAR2130P_SLAVE_SNOC_GEM_NOC_SF }, 794 }; 795 796 static struct qcom_icc_node qnm_snoc_cfg = { 797 .name = "qnm_snoc_cfg", 798 .id = SAR2130P_MASTER_SNOC_CFG, 799 .channels = 1, 800 .buswidth = 4, 801 .num_links = 1, 802 .links = { SAR2130P_SLAVE_SERVICE_SNOC }, 803 }; 804 805 static const struct qcom_icc_qosbox qxm_crypto_qos = { 806 .num_ports = 1, 807 .port_offsets = { 0x27000 }, 808 .prio = 2, 809 .urg_fwd = 0, 810 .prio_fwd_disable = 1, 811 }; 812 813 static struct qcom_icc_node qxm_crypto = { 814 .name = "qxm_crypto", 815 .id = SAR2130P_MASTER_CRYPTO, 816 .channels = 1, 817 .buswidth = 8, 818 .qosbox = &qxm_crypto_qos, 819 .num_links = 1, 820 .links = { SAR2130P_SLAVE_A2NOC_SNOC }, 821 }; 822 823 static const struct qcom_icc_qosbox qxm_pimem_qos = { 824 .num_ports = 1, 825 .port_offsets = { 0x1f000 }, 826 .prio = 2, 827 .urg_fwd = 0, 828 .prio_fwd_disable = 1, 829 }; 830 831 static struct qcom_icc_node qxm_pimem = { 832 .name = "qxm_pimem", 833 .id = SAR2130P_MASTER_PIMEM, 834 .channels = 1, 835 .buswidth = 8, 836 .qosbox = &qxm_pimem_qos, 837 .num_links = 1, 838 .links = { SAR2130P_SLAVE_SNOC_GEM_NOC_GC }, 839 }; 840 841 static const struct qcom_icc_qosbox xm_gic_qos = { 842 .num_ports = 1, 843 .port_offsets = { 0x21000 }, 844 .prio = 2, 845 .urg_fwd = 0, 846 .prio_fwd_disable = 1, 847 }; 848 849 static struct qcom_icc_node xm_gic = { 850 .name = "xm_gic", 851 .id = SAR2130P_MASTER_GIC, 852 .channels = 1, 853 .buswidth = 8, 854 .qosbox = &xm_gic_qos, 855 .num_links = 1, 856 .links = { SAR2130P_SLAVE_SNOC_GEM_NOC_GC }, 857 }; 858 859 static const struct qcom_icc_qosbox xm_qdss_etr_0_qos = { 860 .num_ports = 1, 861 .port_offsets = { 0x1b000 }, 862 .prio = 2, 863 .urg_fwd = 0, 864 .prio_fwd_disable = 1, 865 }; 866 867 static struct qcom_icc_node xm_qdss_etr_0 = { 868 .name = "xm_qdss_etr_0", 869 .id = SAR2130P_MASTER_QDSS_ETR, 870 .channels = 1, 871 .buswidth = 8, 872 .qosbox = &xm_qdss_etr_0_qos, 873 .num_links = 1, 874 .links = { SAR2130P_SLAVE_A2NOC_SNOC }, 875 }; 876 877 static const struct qcom_icc_qosbox xm_qdss_etr_1_qos = { 878 .num_ports = 1, 879 .port_offsets = { 0x1c000 }, 880 .prio = 2, 881 .urg_fwd = 0, 882 .prio_fwd_disable = 1, 883 }; 884 885 static struct qcom_icc_node xm_qdss_etr_1 = { 886 .name = "xm_qdss_etr_1", 887 .id = SAR2130P_MASTER_QDSS_ETR_1, 888 .channels = 1, 889 .buswidth = 8, 890 .qosbox = &xm_qdss_etr_1_qos, 891 .num_links = 1, 892 .links = { SAR2130P_SLAVE_A2NOC_SNOC }, 893 }; 894 895 static const struct qcom_icc_qosbox xm_sdc1_qos = { 896 .num_ports = 1, 897 .port_offsets = { 0x29000 }, 898 .prio = 2, 899 .urg_fwd = 0, 900 .prio_fwd_disable = 1, 901 }; 902 903 static struct qcom_icc_node xm_sdc1 = { 904 .name = "xm_sdc1", 905 .id = SAR2130P_MASTER_SDCC_1, 906 .channels = 1, 907 .buswidth = 8, 908 .qosbox = &xm_sdc1_qos, 909 .num_links = 1, 910 .links = { SAR2130P_SLAVE_A2NOC_SNOC }, 911 }; 912 913 static const struct qcom_icc_qosbox xm_usb3_0_qos = { 914 .num_ports = 1, 915 .port_offsets = { 0x28000 }, 916 .prio = 2, 917 .urg_fwd = 0, 918 .prio_fwd_disable = 1, 919 }; 920 921 static struct qcom_icc_node xm_usb3_0 = { 922 .name = "xm_usb3_0", 923 .id = SAR2130P_MASTER_USB3_0, 924 .channels = 1, 925 .buswidth = 8, 926 .qosbox = &xm_usb3_0_qos, 927 .num_links = 1, 928 .links = { SAR2130P_SLAVE_A2NOC_SNOC }, 929 }; 930 931 static struct qcom_icc_node qup0_core_slave = { 932 .name = "qup0_core_slave", 933 .id = SAR2130P_SLAVE_QUP_CORE_0, 934 .channels = 1, 935 .buswidth = 4, 936 .num_links = 0, 937 }; 938 939 static struct qcom_icc_node qup1_core_slave = { 940 .name = "qup1_core_slave", 941 .id = SAR2130P_SLAVE_QUP_CORE_1, 942 .channels = 1, 943 .buswidth = 4, 944 .num_links = 0, 945 }; 946 947 static struct qcom_icc_node qhs_ahb2phy0 = { 948 .name = "qhs_ahb2phy0", 949 .id = SAR2130P_SLAVE_AHB2PHY_SOUTH, 950 .channels = 1, 951 .buswidth = 4, 952 .num_links = 0, 953 }; 954 955 static struct qcom_icc_node qhs_aoss = { 956 .name = "qhs_aoss", 957 .id = SAR2130P_SLAVE_AOSS, 958 .channels = 1, 959 .buswidth = 4, 960 .num_links = 0, 961 }; 962 963 static struct qcom_icc_node qhs_camera_cfg = { 964 .name = "qhs_camera_cfg", 965 .id = SAR2130P_SLAVE_CAMERA_CFG, 966 .channels = 1, 967 .buswidth = 4, 968 .num_links = 0, 969 }; 970 971 static struct qcom_icc_node qhs_clk_ctl = { 972 .name = "qhs_clk_ctl", 973 .id = SAR2130P_SLAVE_CLK_CTL, 974 .channels = 1, 975 .buswidth = 4, 976 .num_links = 0, 977 }; 978 979 static struct qcom_icc_node qhs_compute_cfg = { 980 .name = "qhs_compute_cfg", 981 .id = SAR2130P_SLAVE_CDSP_CFG, 982 .channels = 1, 983 .buswidth = 4, 984 .num_links = 1, 985 .links = { SAR2130P_MASTER_CDSP_NOC_CFG }, 986 }; 987 988 static struct qcom_icc_node qhs_cpr_cx = { 989 .name = "qhs_cpr_cx", 990 .id = SAR2130P_SLAVE_RBCPR_CX_CFG, 991 .channels = 1, 992 .buswidth = 4, 993 .num_links = 0, 994 }; 995 996 static struct qcom_icc_node qhs_cpr_mmcx = { 997 .name = "qhs_cpr_mmcx", 998 .id = SAR2130P_SLAVE_RBCPR_MMCX_CFG, 999 .channels = 1, 1000 .buswidth = 4, 1001 .num_links = 0, 1002 }; 1003 1004 static struct qcom_icc_node qhs_cpr_mxa = { 1005 .name = "qhs_cpr_mxa", 1006 .id = SAR2130P_SLAVE_RBCPR_MXA_CFG, 1007 .channels = 1, 1008 .buswidth = 4, 1009 .num_links = 0, 1010 }; 1011 1012 static struct qcom_icc_node qhs_cpr_mxc = { 1013 .name = "qhs_cpr_mxc", 1014 .id = SAR2130P_SLAVE_RBCPR_MXC_CFG, 1015 .channels = 1, 1016 .buswidth = 4, 1017 .num_links = 0, 1018 }; 1019 1020 static struct qcom_icc_node qhs_cpr_nspcx = { 1021 .name = "qhs_cpr_nspcx", 1022 .id = SAR2130P_SLAVE_CPR_NSPCX, 1023 .channels = 1, 1024 .buswidth = 4, 1025 .num_links = 0, 1026 }; 1027 1028 static struct qcom_icc_node qhs_crypto0_cfg = { 1029 .name = "qhs_crypto0_cfg", 1030 .id = SAR2130P_SLAVE_CRYPTO_0_CFG, 1031 .channels = 1, 1032 .buswidth = 4, 1033 .num_links = 0, 1034 }; 1035 1036 static struct qcom_icc_node qhs_cx_rdpm = { 1037 .name = "qhs_cx_rdpm", 1038 .id = SAR2130P_SLAVE_CX_RDPM, 1039 .channels = 1, 1040 .buswidth = 4, 1041 .num_links = 0, 1042 }; 1043 1044 static struct qcom_icc_node qhs_display_cfg = { 1045 .name = "qhs_display_cfg", 1046 .id = SAR2130P_SLAVE_DISPLAY_CFG, 1047 .channels = 1, 1048 .buswidth = 4, 1049 .num_links = 0, 1050 }; 1051 1052 static struct qcom_icc_node qhs_gpuss_cfg = { 1053 .name = "qhs_gpuss_cfg", 1054 .id = SAR2130P_SLAVE_GFX3D_CFG, 1055 .channels = 1, 1056 .buswidth = 8, 1057 .num_links = 0, 1058 }; 1059 1060 static struct qcom_icc_node qhs_imem_cfg = { 1061 .name = "qhs_imem_cfg", 1062 .id = SAR2130P_SLAVE_IMEM_CFG, 1063 .channels = 1, 1064 .buswidth = 4, 1065 .num_links = 0, 1066 }; 1067 1068 static struct qcom_icc_node qhs_ipc_router = { 1069 .name = "qhs_ipc_router", 1070 .id = SAR2130P_SLAVE_IPC_ROUTER_CFG, 1071 .channels = 1, 1072 .buswidth = 4, 1073 .num_links = 0, 1074 }; 1075 1076 static struct qcom_icc_node qhs_lpass_cfg = { 1077 .name = "qhs_lpass_cfg", 1078 .id = SAR2130P_SLAVE_LPASS, 1079 .channels = 1, 1080 .buswidth = 4, 1081 .num_links = 1, 1082 .links = { SAR2130P_MASTER_CNOC_LPASS_AG_NOC }, 1083 }; 1084 1085 static struct qcom_icc_node qhs_mx_rdpm = { 1086 .name = "qhs_mx_rdpm", 1087 .id = SAR2130P_SLAVE_MX_RDPM, 1088 .channels = 1, 1089 .buswidth = 4, 1090 .num_links = 0, 1091 }; 1092 1093 static struct qcom_icc_node qhs_pcie0_cfg = { 1094 .name = "qhs_pcie0_cfg", 1095 .id = SAR2130P_SLAVE_PCIE_0_CFG, 1096 .channels = 1, 1097 .buswidth = 4, 1098 .num_links = 0, 1099 }; 1100 1101 static struct qcom_icc_node qhs_pcie1_cfg = { 1102 .name = "qhs_pcie1_cfg", 1103 .id = SAR2130P_SLAVE_PCIE_1_CFG, 1104 .channels = 1, 1105 .buswidth = 4, 1106 .num_links = 0, 1107 }; 1108 1109 static struct qcom_icc_node qhs_pdm = { 1110 .name = "qhs_pdm", 1111 .id = SAR2130P_SLAVE_PDM, 1112 .channels = 1, 1113 .buswidth = 4, 1114 .num_links = 0, 1115 }; 1116 1117 static struct qcom_icc_node qhs_pimem_cfg = { 1118 .name = "qhs_pimem_cfg", 1119 .id = SAR2130P_SLAVE_PIMEM_CFG, 1120 .channels = 1, 1121 .buswidth = 4, 1122 .num_links = 0, 1123 }; 1124 1125 static struct qcom_icc_node qhs_prng = { 1126 .name = "qhs_prng", 1127 .id = SAR2130P_SLAVE_PRNG, 1128 .channels = 1, 1129 .buswidth = 4, 1130 .num_links = 0, 1131 }; 1132 1133 static struct qcom_icc_node qhs_qdss_cfg = { 1134 .name = "qhs_qdss_cfg", 1135 .id = SAR2130P_SLAVE_QDSS_CFG, 1136 .channels = 1, 1137 .buswidth = 4, 1138 .num_links = 0, 1139 }; 1140 1141 static struct qcom_icc_node qhs_qspi = { 1142 .name = "qhs_qspi", 1143 .id = SAR2130P_SLAVE_QSPI_0, 1144 .channels = 1, 1145 .buswidth = 4, 1146 .num_links = 0, 1147 }; 1148 1149 static struct qcom_icc_node qhs_qup0 = { 1150 .name = "qhs_qup0", 1151 .id = SAR2130P_SLAVE_QUP_0, 1152 .channels = 1, 1153 .buswidth = 4, 1154 .num_links = 0, 1155 }; 1156 1157 static struct qcom_icc_node qhs_qup1 = { 1158 .name = "qhs_qup1", 1159 .id = SAR2130P_SLAVE_QUP_1, 1160 .channels = 1, 1161 .buswidth = 4, 1162 .num_links = 0, 1163 }; 1164 1165 static struct qcom_icc_node qhs_sdc1 = { 1166 .name = "qhs_sdc1", 1167 .id = SAR2130P_SLAVE_SDCC_1, 1168 .channels = 1, 1169 .buswidth = 4, 1170 .num_links = 0, 1171 }; 1172 1173 static struct qcom_icc_node qhs_tcsr = { 1174 .name = "qhs_tcsr", 1175 .id = SAR2130P_SLAVE_TCSR, 1176 .channels = 1, 1177 .buswidth = 4, 1178 .num_links = 0, 1179 }; 1180 1181 static struct qcom_icc_node qhs_tlmm = { 1182 .name = "qhs_tlmm", 1183 .id = SAR2130P_SLAVE_TLMM, 1184 .channels = 1, 1185 .buswidth = 4, 1186 .num_links = 0, 1187 }; 1188 1189 static struct qcom_icc_node qhs_tme_cfg = { 1190 .name = "qhs_tme_cfg", 1191 .id = SAR2130P_SLAVE_TME_CFG, 1192 .channels = 1, 1193 .buswidth = 4, 1194 .num_links = 0, 1195 }; 1196 1197 static struct qcom_icc_node qhs_usb3_0 = { 1198 .name = "qhs_usb3_0", 1199 .id = SAR2130P_SLAVE_USB3_0, 1200 .channels = 1, 1201 .buswidth = 4, 1202 .num_links = 0, 1203 }; 1204 1205 static struct qcom_icc_node qhs_venus_cfg = { 1206 .name = "qhs_venus_cfg", 1207 .id = SAR2130P_SLAVE_VENUS_CFG, 1208 .channels = 1, 1209 .buswidth = 4, 1210 .num_links = 0, 1211 }; 1212 1213 static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 1214 .name = "qhs_vsense_ctrl_cfg", 1215 .id = SAR2130P_SLAVE_VSENSE_CTRL_CFG, 1216 .channels = 1, 1217 .buswidth = 4, 1218 .num_links = 0, 1219 }; 1220 1221 static struct qcom_icc_node qhs_wlan_q6 = { 1222 .name = "qhs_wlan_q6", 1223 .id = SAR2130P_SLAVE_WLAN_Q6_CFG, 1224 .channels = 1, 1225 .buswidth = 4, 1226 .num_links = 0, 1227 }; 1228 1229 static struct qcom_icc_node qns_ddrss_cfg = { 1230 .name = "qns_ddrss_cfg", 1231 .id = SAR2130P_SLAVE_DDRSS_CFG, 1232 .channels = 1, 1233 .buswidth = 4, 1234 .num_links = 0, 1235 }; 1236 1237 static struct qcom_icc_node qns_mnoc_cfg = { 1238 .name = "qns_mnoc_cfg", 1239 .id = SAR2130P_SLAVE_CNOC_MNOC_CFG, 1240 .channels = 1, 1241 .buswidth = 4, 1242 .num_links = 1, 1243 .links = { SAR2130P_MASTER_CNOC_MNOC_CFG }, 1244 }; 1245 1246 static struct qcom_icc_node qns_snoc_cfg = { 1247 .name = "qns_snoc_cfg", 1248 .id = SAR2130P_SLAVE_SNOC_CFG, 1249 .channels = 1, 1250 .buswidth = 4, 1251 .num_links = 1, 1252 .links = { SAR2130P_MASTER_SNOC_CFG }, 1253 }; 1254 1255 static struct qcom_icc_node qxs_imem = { 1256 .name = "qxs_imem", 1257 .id = SAR2130P_SLAVE_IMEM, 1258 .channels = 1, 1259 .buswidth = 8, 1260 .num_links = 0, 1261 }; 1262 1263 static struct qcom_icc_node qxs_pimem = { 1264 .name = "qxs_pimem", 1265 .id = SAR2130P_SLAVE_PIMEM, 1266 .channels = 1, 1267 .buswidth = 8, 1268 .num_links = 0, 1269 }; 1270 1271 static struct qcom_icc_node srvc_cnoc = { 1272 .name = "srvc_cnoc", 1273 .id = SAR2130P_SLAVE_SERVICE_CNOC, 1274 .channels = 1, 1275 .buswidth = 4, 1276 .num_links = 0, 1277 }; 1278 1279 static struct qcom_icc_node xs_pcie_0 = { 1280 .name = "xs_pcie_0", 1281 .id = SAR2130P_SLAVE_PCIE_0, 1282 .channels = 1, 1283 .buswidth = 8, 1284 .num_links = 0, 1285 }; 1286 1287 static struct qcom_icc_node xs_pcie_1 = { 1288 .name = "xs_pcie_1", 1289 .id = SAR2130P_SLAVE_PCIE_1, 1290 .channels = 1, 1291 .buswidth = 8, 1292 .num_links = 0, 1293 }; 1294 1295 static struct qcom_icc_node xs_qdss_stm = { 1296 .name = "xs_qdss_stm", 1297 .id = SAR2130P_SLAVE_QDSS_STM, 1298 .channels = 1, 1299 .buswidth = 4, 1300 .num_links = 0, 1301 }; 1302 1303 static struct qcom_icc_node xs_sys_tcu_cfg = { 1304 .name = "xs_sys_tcu_cfg", 1305 .id = SAR2130P_SLAVE_TCU, 1306 .channels = 1, 1307 .buswidth = 8, 1308 .num_links = 0, 1309 }; 1310 1311 static struct qcom_icc_node qns_gem_noc_cnoc = { 1312 .name = "qns_gem_noc_cnoc", 1313 .id = SAR2130P_SLAVE_GEM_NOC_CNOC, 1314 .channels = 1, 1315 .buswidth = 16, 1316 .num_links = 1, 1317 .links = { SAR2130P_MASTER_GEM_NOC_CNOC }, 1318 }; 1319 1320 static struct qcom_icc_node qns_llcc = { 1321 .name = "qns_llcc", 1322 .id = SAR2130P_SLAVE_LLCC, 1323 .channels = 2, 1324 .buswidth = 16, 1325 .num_links = 1, 1326 .links = { SAR2130P_MASTER_LLCC }, 1327 }; 1328 1329 static struct qcom_icc_node qns_pcie = { 1330 .name = "qns_pcie", 1331 .id = SAR2130P_SLAVE_MEM_NOC_PCIE_SNOC, 1332 .channels = 1, 1333 .buswidth = 8, 1334 .num_links = 1, 1335 .links = { SAR2130P_MASTER_GEM_NOC_PCIE_SNOC }, 1336 }; 1337 1338 static struct qcom_icc_node qhs_lpass_core = { 1339 .name = "qhs_lpass_core", 1340 .id = SAR2130P_SLAVE_LPASS_CORE_CFG, 1341 .channels = 1, 1342 .buswidth = 4, 1343 .num_links = 0, 1344 }; 1345 1346 static struct qcom_icc_node qhs_lpass_lpi = { 1347 .name = "qhs_lpass_lpi", 1348 .id = SAR2130P_SLAVE_LPASS_LPI_CFG, 1349 .channels = 1, 1350 .buswidth = 4, 1351 .num_links = 0, 1352 }; 1353 1354 static struct qcom_icc_node qhs_lpass_mpu = { 1355 .name = "qhs_lpass_mpu", 1356 .id = SAR2130P_SLAVE_LPASS_MPU_CFG, 1357 .channels = 1, 1358 .buswidth = 4, 1359 .num_links = 0, 1360 }; 1361 1362 static struct qcom_icc_node qhs_lpass_top = { 1363 .name = "qhs_lpass_top", 1364 .id = SAR2130P_SLAVE_LPASS_TOP_CFG, 1365 .channels = 1, 1366 .buswidth = 4, 1367 .num_links = 0, 1368 }; 1369 1370 static struct qcom_icc_node qns_sysnoc = { 1371 .name = "qns_sysnoc", 1372 .id = SAR2130P_SLAVE_LPASS_SNOC, 1373 .channels = 1, 1374 .buswidth = 16, 1375 .num_links = 1, 1376 .links = { SAR2130P_MASTER_LPASS_ANOC }, 1377 }; 1378 1379 static struct qcom_icc_node srvc_niu_aml_noc = { 1380 .name = "srvc_niu_aml_noc", 1381 .id = SAR2130P_SLAVE_SERVICES_LPASS_AML_NOC, 1382 .channels = 1, 1383 .buswidth = 4, 1384 .num_links = 0, 1385 }; 1386 1387 static struct qcom_icc_node srvc_niu_lpass_agnoc = { 1388 .name = "srvc_niu_lpass_agnoc", 1389 .id = SAR2130P_SLAVE_SERVICE_LPASS_AG_NOC, 1390 .channels = 1, 1391 .buswidth = 4, 1392 .num_links = 0, 1393 }; 1394 1395 static struct qcom_icc_node ebi = { 1396 .name = "ebi", 1397 .id = SAR2130P_SLAVE_EBI1, 1398 .channels = 1, 1399 .buswidth = 4, 1400 .num_links = 0, 1401 }; 1402 1403 static struct qcom_icc_node qns_mem_noc_hf = { 1404 .name = "qns_mem_noc_hf", 1405 .id = SAR2130P_SLAVE_MNOC_HF_MEM_NOC, 1406 .channels = 2, 1407 .buswidth = 32, 1408 .num_links = 1, 1409 .links = { SAR2130P_MASTER_MNOC_HF_MEM_NOC }, 1410 }; 1411 1412 static struct qcom_icc_node qns_mem_noc_sf = { 1413 .name = "qns_mem_noc_sf", 1414 .id = SAR2130P_SLAVE_MNOC_SF_MEM_NOC, 1415 .channels = 1, 1416 .buswidth = 32, 1417 .num_links = 1, 1418 .links = { SAR2130P_MASTER_MNOC_SF_MEM_NOC }, 1419 }; 1420 1421 static struct qcom_icc_node srvc_mnoc = { 1422 .name = "srvc_mnoc", 1423 .id = SAR2130P_SLAVE_SERVICE_MNOC, 1424 .channels = 1, 1425 .buswidth = 4, 1426 .num_links = 0, 1427 }; 1428 1429 static struct qcom_icc_node qns_nsp_gemnoc = { 1430 .name = "qns_nsp_gemnoc", 1431 .id = SAR2130P_SLAVE_CDSP_MEM_NOC, 1432 .channels = 2, 1433 .buswidth = 32, 1434 .num_links = 1, 1435 .links = { SAR2130P_MASTER_COMPUTE_NOC }, 1436 }; 1437 1438 static struct qcom_icc_node service_nsp_noc = { 1439 .name = "service_nsp_noc", 1440 .id = SAR2130P_SLAVE_SERVICE_NSP_NOC, 1441 .channels = 1, 1442 .buswidth = 4, 1443 .num_links = 0, 1444 }; 1445 1446 static struct qcom_icc_node qns_pcie_mem_noc = { 1447 .name = "qns_pcie_mem_noc", 1448 .id = SAR2130P_SLAVE_ANOC_PCIE_GEM_NOC, 1449 .channels = 1, 1450 .buswidth = 16, 1451 .num_links = 1, 1452 .links = { SAR2130P_MASTER_ANOC_PCIE_GEM_NOC }, 1453 }; 1454 1455 static struct qcom_icc_node qns_a2noc_snoc = { 1456 .name = "qns_a2noc_snoc", 1457 .id = SAR2130P_SLAVE_A2NOC_SNOC, 1458 .channels = 1, 1459 .buswidth = 16, 1460 .num_links = 1, 1461 .links = { SAR2130P_MASTER_A2NOC_SNOC }, 1462 }; 1463 1464 static struct qcom_icc_node qns_gemnoc_gc = { 1465 .name = "qns_gemnoc_gc", 1466 .id = SAR2130P_SLAVE_SNOC_GEM_NOC_GC, 1467 .channels = 1, 1468 .buswidth = 8, 1469 .num_links = 1, 1470 .links = { SAR2130P_MASTER_SNOC_GC_MEM_NOC }, 1471 }; 1472 1473 static struct qcom_icc_node qns_gemnoc_sf = { 1474 .name = "qns_gemnoc_sf", 1475 .id = SAR2130P_SLAVE_SNOC_GEM_NOC_SF, 1476 .channels = 1, 1477 .buswidth = 16, 1478 .num_links = 1, 1479 .links = { SAR2130P_MASTER_SNOC_SF_MEM_NOC }, 1480 }; 1481 1482 static struct qcom_icc_node srvc_snoc = { 1483 .name = "srvc_snoc", 1484 .id = SAR2130P_SLAVE_SERVICE_SNOC, 1485 .channels = 1, 1486 .buswidth = 4, 1487 .num_links = 0, 1488 }; 1489 1490 static struct qcom_icc_bcm bcm_acv = { 1491 .name = "ACV", 1492 .enable_mask = BIT(3), 1493 .num_nodes = 1, 1494 .nodes = { &ebi }, 1495 }; 1496 1497 static struct qcom_icc_bcm bcm_ce0 = { 1498 .name = "CE0", 1499 .num_nodes = 1, 1500 .nodes = { &qxm_crypto }, 1501 }; 1502 1503 static struct qcom_icc_bcm bcm_cn0 = { 1504 .name = "CN0", 1505 .enable_mask = BIT(0), 1506 .keepalive = true, 1507 .num_nodes = 48, 1508 .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie, 1509 &xm_qdss_dap, &qhs_ahb2phy0, 1510 &qhs_aoss, &qhs_camera_cfg, 1511 &qhs_clk_ctl, &qhs_compute_cfg, 1512 &qhs_cpr_cx, &qhs_cpr_mmcx, 1513 &qhs_cpr_mxa, &qhs_cpr_mxc, 1514 &qhs_cpr_nspcx, &qhs_crypto0_cfg, 1515 &qhs_cx_rdpm, &qhs_display_cfg, 1516 &qhs_gpuss_cfg, &qhs_imem_cfg, 1517 &qhs_ipc_router, &qhs_lpass_cfg, 1518 &qhs_mx_rdpm, &qhs_pcie0_cfg, 1519 &qhs_pcie1_cfg, &qhs_pdm, 1520 &qhs_pimem_cfg, &qhs_prng, 1521 &qhs_qdss_cfg, &qhs_qspi, 1522 &qhs_qup0, &qhs_qup1, 1523 &qhs_sdc1, &qhs_tcsr, 1524 &qhs_tlmm, &qhs_tme_cfg, 1525 &qhs_usb3_0, &qhs_venus_cfg, 1526 &qhs_vsense_ctrl_cfg, &qhs_wlan_q6, 1527 &qns_ddrss_cfg, &qns_mnoc_cfg, 1528 &qns_snoc_cfg, &qxs_imem, 1529 &qxs_pimem, &srvc_cnoc, 1530 &xs_pcie_0, &xs_pcie_1, 1531 &xs_qdss_stm, &xs_sys_tcu_cfg }, 1532 }; 1533 1534 static struct qcom_icc_bcm bcm_co0 = { 1535 .name = "CO0", 1536 .enable_mask = BIT(0), 1537 .num_nodes = 2, 1538 .nodes = { &qxm_nsp, &qns_nsp_gemnoc }, 1539 }; 1540 1541 static struct qcom_icc_bcm bcm_mc0 = { 1542 .name = "MC0", 1543 .keepalive = true, 1544 .num_nodes = 1, 1545 .nodes = { &ebi }, 1546 }; 1547 1548 static struct qcom_icc_bcm bcm_mm0 = { 1549 .name = "MM0", 1550 .keepalive = true, 1551 .num_nodes = 1, 1552 .nodes = { &qns_mem_noc_hf }, 1553 }; 1554 1555 static struct qcom_icc_bcm bcm_mm1 = { 1556 .name = "MM1", 1557 .enable_mask = BIT(0), 1558 .num_nodes = 11, 1559 .nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp, 1560 &qnm_camnoc_sf, &qnm_lsr, 1561 &qnm_mdp, &qnm_mnoc_cfg, 1562 &qnm_video, &qnm_video_cv_cpu, 1563 &qnm_video_cvp, &qnm_video_v_cpu, 1564 &qns_mem_noc_sf }, 1565 }; 1566 1567 static struct qcom_icc_bcm bcm_qup0 = { 1568 .name = "QUP0", 1569 .keepalive = true, 1570 .vote_scale = 1, 1571 .num_nodes = 1, 1572 .nodes = { &qup0_core_slave }, 1573 }; 1574 1575 static struct qcom_icc_bcm bcm_qup1 = { 1576 .name = "QUP1", 1577 .keepalive = true, 1578 .vote_scale = 1, 1579 .num_nodes = 1, 1580 .nodes = { &qup1_core_slave }, 1581 }; 1582 1583 static struct qcom_icc_bcm bcm_sh0 = { 1584 .name = "SH0", 1585 .keepalive = true, 1586 .num_nodes = 1, 1587 .nodes = { &qns_llcc }, 1588 }; 1589 1590 static struct qcom_icc_bcm bcm_sh1 = { 1591 .name = "SH1", 1592 .enable_mask = BIT(0), 1593 .num_nodes = 13, 1594 .nodes = { &alm_gpu_tcu, &alm_sys_tcu, 1595 &chm_apps, &qnm_gpu, 1596 &qnm_mnoc_hf, &qnm_mnoc_sf, 1597 &qnm_nsp_gemnoc, &qnm_pcie, 1598 &qnm_snoc_gc, &qnm_snoc_sf, 1599 &qxm_wlan_q6, &qns_gem_noc_cnoc, 1600 &qns_pcie }, 1601 }; 1602 1603 static struct qcom_icc_bcm bcm_sn0 = { 1604 .name = "SN0", 1605 .keepalive = true, 1606 .num_nodes = 1, 1607 .nodes = { &qns_gemnoc_sf }, 1608 }; 1609 1610 static struct qcom_icc_bcm bcm_sn1 = { 1611 .name = "SN1", 1612 .enable_mask = BIT(0), 1613 .num_nodes = 4, 1614 .nodes = { &qhm_gic, &qxm_pimem, 1615 &xm_gic, &qns_gemnoc_gc }, 1616 }; 1617 1618 static struct qcom_icc_bcm bcm_sn3 = { 1619 .name = "SN3", 1620 .num_nodes = 1, 1621 .nodes = { &qnm_aggre2_noc }, 1622 }; 1623 1624 static struct qcom_icc_bcm bcm_sn4 = { 1625 .name = "SN4", 1626 .num_nodes = 1, 1627 .nodes = { &qnm_lpass_noc }, 1628 }; 1629 1630 static struct qcom_icc_bcm bcm_sn7 = { 1631 .name = "SN7", 1632 .num_nodes = 1, 1633 .nodes = { &qns_pcie_mem_noc }, 1634 }; 1635 1636 static struct qcom_icc_bcm * const clk_virt_bcms[] = { 1637 &bcm_qup0, 1638 &bcm_qup1, 1639 }; 1640 1641 static struct qcom_icc_node * const clk_virt_nodes[] = { 1642 [MASTER_QUP_CORE_0] = &qup0_core_master, 1643 [MASTER_QUP_CORE_1] = &qup1_core_master, 1644 [SLAVE_QUP_CORE_0] = &qup0_core_slave, 1645 [SLAVE_QUP_CORE_1] = &qup1_core_slave, 1646 }; 1647 1648 static const struct qcom_icc_desc sar2130p_clk_virt = { 1649 .nodes = clk_virt_nodes, 1650 .num_nodes = ARRAY_SIZE(clk_virt_nodes), 1651 .bcms = clk_virt_bcms, 1652 .num_bcms = ARRAY_SIZE(clk_virt_bcms), 1653 }; 1654 1655 static struct qcom_icc_bcm * const config_noc_bcms[] = { 1656 &bcm_cn0, 1657 }; 1658 1659 static struct qcom_icc_node * const config_noc_nodes[] = { 1660 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, 1661 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, 1662 [MASTER_QDSS_DAP] = &xm_qdss_dap, 1663 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, 1664 [SLAVE_AOSS] = &qhs_aoss, 1665 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 1666 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1667 [SLAVE_CDSP_CFG] = &qhs_compute_cfg, 1668 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 1669 [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx, 1670 [SLAVE_RBCPR_MXA_CFG] = &qhs_cpr_mxa, 1671 [SLAVE_RBCPR_MXC_CFG] = &qhs_cpr_mxc, 1672 [SLAVE_CPR_NSPCX] = &qhs_cpr_nspcx, 1673 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1674 [SLAVE_CX_RDPM] = &qhs_cx_rdpm, 1675 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 1676 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, 1677 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1678 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, 1679 [SLAVE_LPASS] = &qhs_lpass_cfg, 1680 [SLAVE_MX_RDPM] = &qhs_mx_rdpm, 1681 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, 1682 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, 1683 [SLAVE_PDM] = &qhs_pdm, 1684 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 1685 [SLAVE_PRNG] = &qhs_prng, 1686 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1687 [SLAVE_QSPI_0] = &qhs_qspi, 1688 [SLAVE_QUP_0] = &qhs_qup0, 1689 [SLAVE_QUP_1] = &qhs_qup1, 1690 [SLAVE_SDCC_1] = &qhs_sdc1, 1691 [SLAVE_TCSR] = &qhs_tcsr, 1692 [SLAVE_TLMM] = &qhs_tlmm, 1693 [SLAVE_TME_CFG] = &qhs_tme_cfg, 1694 [SLAVE_USB3_0] = &qhs_usb3_0, 1695 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1696 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 1697 [SLAVE_WLAN_Q6_CFG] = &qhs_wlan_q6, 1698 [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg, 1699 [SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg, 1700 [SLAVE_SNOC_CFG] = &qns_snoc_cfg, 1701 [SLAVE_IMEM] = &qxs_imem, 1702 [SLAVE_PIMEM] = &qxs_pimem, 1703 [SLAVE_SERVICE_CNOC] = &srvc_cnoc, 1704 [SLAVE_PCIE_0] = &xs_pcie_0, 1705 [SLAVE_PCIE_1] = &xs_pcie_1, 1706 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1707 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1708 }; 1709 1710 static const struct qcom_icc_desc sar2130p_config_noc = { 1711 .config = &icc_regmap_config, 1712 .nodes = config_noc_nodes, 1713 .num_nodes = ARRAY_SIZE(config_noc_nodes), 1714 .bcms = config_noc_bcms, 1715 .num_bcms = ARRAY_SIZE(config_noc_bcms), 1716 }; 1717 1718 static struct qcom_icc_bcm * const gem_noc_bcms[] = { 1719 &bcm_sh0, 1720 &bcm_sh1, 1721 }; 1722 1723 static struct qcom_icc_node * const gem_noc_nodes[] = { 1724 [MASTER_GPU_TCU] = &alm_gpu_tcu, 1725 [MASTER_SYS_TCU] = &alm_sys_tcu, 1726 [MASTER_APPSS_PROC] = &chm_apps, 1727 [MASTER_GFX3D] = &qnm_gpu, 1728 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 1729 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 1730 [MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc, 1731 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, 1732 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 1733 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 1734 [MASTER_WLAN_Q6] = &qxm_wlan_q6, 1735 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, 1736 [SLAVE_LLCC] = &qns_llcc, 1737 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, 1738 }; 1739 1740 static const struct qcom_icc_desc sar2130p_gem_noc = { 1741 .config = &icc_regmap_config, 1742 .nodes = gem_noc_nodes, 1743 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 1744 .bcms = gem_noc_bcms, 1745 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 1746 }; 1747 1748 static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = { 1749 }; 1750 1751 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { 1752 [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc, 1753 [MASTER_LPASS_PROC] = &qxm_lpass_dsp, 1754 [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core, 1755 [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi, 1756 [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu, 1757 [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top, 1758 [SLAVE_LPASS_SNOC] = &qns_sysnoc, 1759 [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc, 1760 [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, 1761 }; 1762 1763 static const struct qcom_icc_desc sar2130p_lpass_ag_noc = { 1764 .config = &icc_regmap_config, 1765 .nodes = lpass_ag_noc_nodes, 1766 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), 1767 .bcms = lpass_ag_noc_bcms, 1768 .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms), 1769 }; 1770 1771 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 1772 &bcm_acv, 1773 &bcm_mc0, 1774 }; 1775 1776 static struct qcom_icc_node * const mc_virt_nodes[] = { 1777 [MASTER_LLCC] = &llcc_mc, 1778 [SLAVE_EBI1] = &ebi, 1779 }; 1780 1781 static const struct qcom_icc_desc sar2130p_mc_virt = { 1782 .nodes = mc_virt_nodes, 1783 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 1784 .bcms = mc_virt_bcms, 1785 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 1786 }; 1787 1788 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 1789 &bcm_mm0, 1790 &bcm_mm1, 1791 }; 1792 1793 static struct qcom_icc_node * const mmss_noc_nodes[] = { 1794 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, 1795 [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp, 1796 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, 1797 [MASTER_LSR] = &qnm_lsr, 1798 [MASTER_MDP] = &qnm_mdp, 1799 [MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg, 1800 [MASTER_VIDEO] = &qnm_video, 1801 [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu, 1802 [MASTER_VIDEO_PROC] = &qnm_video_cvp, 1803 [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu, 1804 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 1805 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, 1806 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 1807 }; 1808 1809 static const struct qcom_icc_desc sar2130p_mmss_noc = { 1810 .config = &icc_regmap_config, 1811 .nodes = mmss_noc_nodes, 1812 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 1813 .bcms = mmss_noc_bcms, 1814 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 1815 }; 1816 1817 static struct qcom_icc_bcm * const nsp_noc_bcms[] = { 1818 &bcm_co0, 1819 }; 1820 1821 static struct qcom_icc_node * const nsp_noc_nodes[] = { 1822 [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config, 1823 [MASTER_CDSP_PROC] = &qxm_nsp, 1824 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, 1825 [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, 1826 }; 1827 1828 static const struct qcom_icc_desc sar2130p_nsp_noc = { 1829 .config = &icc_regmap_config, 1830 .nodes = nsp_noc_nodes, 1831 .num_nodes = ARRAY_SIZE(nsp_noc_nodes), 1832 .bcms = nsp_noc_bcms, 1833 .num_bcms = ARRAY_SIZE(nsp_noc_bcms), 1834 }; 1835 1836 static struct qcom_icc_bcm * const pcie_anoc_bcms[] = { 1837 &bcm_sn7, 1838 }; 1839 1840 static struct qcom_icc_node * const pcie_anoc_nodes[] = { 1841 [MASTER_PCIE_0] = &xm_pcie3_0, 1842 [MASTER_PCIE_1] = &xm_pcie3_1, 1843 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, 1844 }; 1845 1846 static const struct qcom_icc_desc sar2130p_pcie_anoc = { 1847 .config = &icc_regmap_config, 1848 .nodes = pcie_anoc_nodes, 1849 .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), 1850 .bcms = pcie_anoc_bcms, 1851 .num_bcms = ARRAY_SIZE(pcie_anoc_bcms), 1852 }; 1853 1854 static struct qcom_icc_bcm * const system_noc_bcms[] = { 1855 &bcm_ce0, 1856 &bcm_sn0, 1857 &bcm_sn1, 1858 &bcm_sn3, 1859 &bcm_sn4, 1860 }; 1861 1862 static struct qcom_icc_node * const system_noc_nodes[] = { 1863 [MASTER_GIC_AHB] = &qhm_gic, 1864 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 1865 [MASTER_QSPI_0] = &qhm_qspi, 1866 [MASTER_QUP_0] = &qhm_qup0, 1867 [MASTER_QUP_1] = &qhm_qup1, 1868 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, 1869 [MASTER_CNOC_DATAPATH] = &qnm_cnoc_datapath, 1870 [MASTER_LPASS_ANOC] = &qnm_lpass_noc, 1871 [MASTER_SNOC_CFG] = &qnm_snoc_cfg, 1872 [MASTER_CRYPTO] = &qxm_crypto, 1873 [MASTER_PIMEM] = &qxm_pimem, 1874 [MASTER_GIC] = &xm_gic, 1875 [MASTER_QDSS_ETR] = &xm_qdss_etr_0, 1876 [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1, 1877 [MASTER_SDCC_1] = &xm_sdc1, 1878 [MASTER_USB3_0] = &xm_usb3_0, 1879 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, 1880 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, 1881 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 1882 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 1883 }; 1884 1885 static const struct qcom_icc_desc sar2130p_system_noc = { 1886 .config = &icc_regmap_config, 1887 .nodes = system_noc_nodes, 1888 .num_nodes = ARRAY_SIZE(system_noc_nodes), 1889 .bcms = system_noc_bcms, 1890 .num_bcms = ARRAY_SIZE(system_noc_bcms), 1891 }; 1892 1893 static const struct of_device_id qnoc_of_match[] = { 1894 { .compatible = "qcom,sar2130p-clk-virt", .data = &sar2130p_clk_virt}, 1895 { .compatible = "qcom,sar2130p-config-noc", .data = &sar2130p_config_noc}, 1896 { .compatible = "qcom,sar2130p-gem-noc", .data = &sar2130p_gem_noc}, 1897 { .compatible = "qcom,sar2130p-lpass-ag-noc", .data = &sar2130p_lpass_ag_noc}, 1898 { .compatible = "qcom,sar2130p-mc-virt", .data = &sar2130p_mc_virt}, 1899 { .compatible = "qcom,sar2130p-mmss-noc", .data = &sar2130p_mmss_noc}, 1900 { .compatible = "qcom,sar2130p-nsp-noc", .data = &sar2130p_nsp_noc}, 1901 { .compatible = "qcom,sar2130p-pcie-anoc", .data = &sar2130p_pcie_anoc}, 1902 { .compatible = "qcom,sar2130p-system-noc", .data = &sar2130p_system_noc}, 1903 { } 1904 }; 1905 MODULE_DEVICE_TABLE(of, qnoc_of_match); 1906 1907 static struct platform_driver qnoc_driver = { 1908 .probe = qcom_icc_rpmh_probe, 1909 .remove = qcom_icc_rpmh_remove, 1910 .driver = { 1911 .name = "qnoc-sar2130p", 1912 .of_match_table = qnoc_of_match, 1913 .sync_state = icc_sync_state, 1914 }, 1915 }; 1916 1917 static int __init qnoc_driver_init(void) 1918 { 1919 return platform_driver_register(&qnoc_driver); 1920 } 1921 core_initcall(qnoc_driver_init); 1922 1923 static void __exit qnoc_driver_exit(void) 1924 { 1925 platform_driver_unregister(&qnoc_driver); 1926 } 1927 1928 module_exit(qnoc_driver_exit); 1929 MODULE_DESCRIPTION("Qualcomm SAR2130P NoC driver"); 1930 MODULE_LICENSE("GPL"); 1931