1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2023, Linaro Limited 5 */ 6 7 #include <linux/device.h> 8 #include <linux/interconnect.h> 9 #include <linux/interconnect-provider.h> 10 #include <linux/module.h> 11 #include <linux/of_platform.h> 12 #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> 13 14 #include "bcm-voter.h" 15 #include "icc-rpmh.h" 16 17 #define SA8775P_MASTER_GPU_TCU 0 18 #define SA8775P_MASTER_PCIE_TCU 1 19 #define SA8775P_MASTER_SYS_TCU 2 20 #define SA8775P_MASTER_APPSS_PROC 3 21 #define SA8775P_MASTER_LLCC 4 22 #define SA8775P_MASTER_CNOC_LPASS_AG_NOC 5 23 #define SA8775P_MASTER_GIC_AHB 6 24 #define SA8775P_MASTER_CDSP_NOC_CFG 7 25 #define SA8775P_MASTER_CDSPB_NOC_CFG 8 26 #define SA8775P_MASTER_QDSS_BAM 9 27 #define SA8775P_MASTER_QUP_0 10 28 #define SA8775P_MASTER_QUP_1 11 29 #define SA8775P_MASTER_QUP_2 12 30 #define SA8775P_MASTER_A1NOC_SNOC 13 31 #define SA8775P_MASTER_A2NOC_SNOC 14 32 #define SA8775P_MASTER_CAMNOC_HF 15 33 #define SA8775P_MASTER_CAMNOC_ICP 16 34 #define SA8775P_MASTER_CAMNOC_SF 17 35 #define SA8775P_MASTER_COMPUTE_NOC 18 36 #define SA8775P_MASTER_COMPUTE_NOC_1 19 37 #define SA8775P_MASTER_CNOC_A2NOC 20 38 #define SA8775P_MASTER_CNOC_DC_NOC 21 39 #define SA8775P_MASTER_GEM_NOC_CFG 22 40 #define SA8775P_MASTER_GEM_NOC_CNOC 23 41 #define SA8775P_MASTER_GEM_NOC_PCIE_SNOC 24 42 #define SA8775P_MASTER_GPDSP_SAIL 25 43 #define SA8775P_MASTER_GFX3D 26 44 #define SA8775P_MASTER_LPASS_ANOC 27 45 #define SA8775P_MASTER_MDP0 28 46 #define SA8775P_MASTER_MDP1 29 47 #define SA8775P_MASTER_MDP_CORE1_0 30 48 #define SA8775P_MASTER_MDP_CORE1_1 31 49 #define SA8775P_MASTER_MNOC_HF_MEM_NOC 32 50 #define SA8775P_MASTER_CNOC_MNOC_HF_CFG 33 51 #define SA8775P_MASTER_MNOC_SF_MEM_NOC 34 52 #define SA8775P_MASTER_CNOC_MNOC_SF_CFG 35 53 #define SA8775P_MASTER_ANOC_PCIE_GEM_NOC 36 54 #define SA8775P_MASTER_SNOC_CFG 37 55 #define SA8775P_MASTER_SNOC_GC_MEM_NOC 38 56 #define SA8775P_MASTER_SNOC_SF_MEM_NOC 39 57 #define SA8775P_MASTER_VIDEO_P0 40 58 #define SA8775P_MASTER_VIDEO_P1 41 59 #define SA8775P_MASTER_VIDEO_PROC 42 60 #define SA8775P_MASTER_VIDEO_V_PROC 43 61 #define SA8775P_MASTER_QUP_CORE_0 44 62 #define SA8775P_MASTER_QUP_CORE_1 45 63 #define SA8775P_MASTER_QUP_CORE_2 46 64 #define SA8775P_MASTER_QUP_CORE_3 47 65 #define SA8775P_MASTER_CRYPTO_CORE0 48 66 #define SA8775P_MASTER_CRYPTO_CORE1 49 67 #define SA8775P_MASTER_DSP0 50 68 #define SA8775P_MASTER_DSP1 51 69 #define SA8775P_MASTER_IPA 52 70 #define SA8775P_MASTER_LPASS_PROC 53 71 #define SA8775P_MASTER_CDSP_PROC 54 72 #define SA8775P_MASTER_CDSP_PROC_B 55 73 #define SA8775P_MASTER_PIMEM 56 74 #define SA8775P_MASTER_QUP_3 57 75 #define SA8775P_MASTER_EMAC 58 76 #define SA8775P_MASTER_EMAC_1 59 77 #define SA8775P_MASTER_GIC 60 78 #define SA8775P_MASTER_PCIE_0 61 79 #define SA8775P_MASTER_PCIE_1 62 80 #define SA8775P_MASTER_QDSS_ETR_0 63 81 #define SA8775P_MASTER_QDSS_ETR_1 64 82 #define SA8775P_MASTER_SDC 65 83 #define SA8775P_MASTER_UFS_CARD 66 84 #define SA8775P_MASTER_UFS_MEM 67 85 #define SA8775P_MASTER_USB2 68 86 #define SA8775P_MASTER_USB3_0 69 87 #define SA8775P_MASTER_USB3_1 70 88 #define SA8775P_SLAVE_EBI1 512 89 #define SA8775P_SLAVE_AHB2PHY_0 513 90 #define SA8775P_SLAVE_AHB2PHY_1 514 91 #define SA8775P_SLAVE_AHB2PHY_2 515 92 #define SA8775P_SLAVE_AHB2PHY_3 516 93 #define SA8775P_SLAVE_ANOC_THROTTLE_CFG 517 94 #define SA8775P_SLAVE_AOSS 518 95 #define SA8775P_SLAVE_APPSS 519 96 #define SA8775P_SLAVE_BOOT_ROM 520 97 #define SA8775P_SLAVE_CAMERA_CFG 521 98 #define SA8775P_SLAVE_CAMERA_NRT_THROTTLE_CFG 522 99 #define SA8775P_SLAVE_CAMERA_RT_THROTTLE_CFG 523 100 #define SA8775P_SLAVE_CLK_CTL 524 101 #define SA8775P_SLAVE_CDSP_CFG 525 102 #define SA8775P_SLAVE_CDSP1_CFG 526 103 #define SA8775P_SLAVE_RBCPR_CX_CFG 527 104 #define SA8775P_SLAVE_RBCPR_MMCX_CFG 528 105 #define SA8775P_SLAVE_RBCPR_MX_CFG 529 106 #define SA8775P_SLAVE_CPR_NSPCX 530 107 #define SA8775P_SLAVE_CRYPTO_0_CFG 531 108 #define SA8775P_SLAVE_CX_RDPM 532 109 #define SA8775P_SLAVE_DISPLAY_CFG 533 110 #define SA8775P_SLAVE_DISPLAY_RT_THROTTLE_CFG 534 111 #define SA8775P_SLAVE_DISPLAY1_CFG 535 112 #define SA8775P_SLAVE_DISPLAY1_RT_THROTTLE_CFG 536 113 #define SA8775P_SLAVE_EMAC_CFG 537 114 #define SA8775P_SLAVE_EMAC1_CFG 538 115 #define SA8775P_SLAVE_GP_DSP0_CFG 539 116 #define SA8775P_SLAVE_GP_DSP1_CFG 540 117 #define SA8775P_SLAVE_GPDSP0_THROTTLE_CFG 541 118 #define SA8775P_SLAVE_GPDSP1_THROTTLE_CFG 542 119 #define SA8775P_SLAVE_GPU_TCU_THROTTLE_CFG 543 120 #define SA8775P_SLAVE_GFX3D_CFG 544 121 #define SA8775P_SLAVE_HWKM 545 122 #define SA8775P_SLAVE_IMEM_CFG 546 123 #define SA8775P_SLAVE_IPA_CFG 547 124 #define SA8775P_SLAVE_IPC_ROUTER_CFG 548 125 #define SA8775P_SLAVE_LLCC_CFG 549 126 #define SA8775P_SLAVE_LPASS 550 127 #define SA8775P_SLAVE_LPASS_CORE_CFG 551 128 #define SA8775P_SLAVE_LPASS_LPI_CFG 552 129 #define SA8775P_SLAVE_LPASS_MPU_CFG 553 130 #define SA8775P_SLAVE_LPASS_THROTTLE_CFG 554 131 #define SA8775P_SLAVE_LPASS_TOP_CFG 555 132 #define SA8775P_SLAVE_MX_RDPM 556 133 #define SA8775P_SLAVE_MXC_RDPM 557 134 #define SA8775P_SLAVE_PCIE_0_CFG 558 135 #define SA8775P_SLAVE_PCIE_1_CFG 559 136 #define SA8775P_SLAVE_PCIE_RSC_CFG 560 137 #define SA8775P_SLAVE_PCIE_TCU_THROTTLE_CFG 561 138 #define SA8775P_SLAVE_PCIE_THROTTLE_CFG 562 139 #define SA8775P_SLAVE_PDM 563 140 #define SA8775P_SLAVE_PIMEM_CFG 564 141 #define SA8775P_SLAVE_PKA_WRAPPER_CFG 565 142 #define SA8775P_SLAVE_QDSS_CFG 566 143 #define SA8775P_SLAVE_QM_CFG 567 144 #define SA8775P_SLAVE_QM_MPU_CFG 568 145 #define SA8775P_SLAVE_QUP_0 569 146 #define SA8775P_SLAVE_QUP_1 570 147 #define SA8775P_SLAVE_QUP_2 571 148 #define SA8775P_SLAVE_QUP_3 572 149 #define SA8775P_SLAVE_SAIL_THROTTLE_CFG 573 150 #define SA8775P_SLAVE_SDC1 574 151 #define SA8775P_SLAVE_SECURITY 575 152 #define SA8775P_SLAVE_SNOC_THROTTLE_CFG 576 153 #define SA8775P_SLAVE_TCSR 577 154 #define SA8775P_SLAVE_TLMM 578 155 #define SA8775P_SLAVE_TSC_CFG 579 156 #define SA8775P_SLAVE_UFS_CARD_CFG 580 157 #define SA8775P_SLAVE_UFS_MEM_CFG 581 158 #define SA8775P_SLAVE_USB2 582 159 #define SA8775P_SLAVE_USB3_0 583 160 #define SA8775P_SLAVE_USB3_1 584 161 #define SA8775P_SLAVE_VENUS_CFG 585 162 #define SA8775P_SLAVE_VENUS_CVP_THROTTLE_CFG 586 163 #define SA8775P_SLAVE_VENUS_V_CPU_THROTTLE_CFG 587 164 #define SA8775P_SLAVE_VENUS_VCODEC_THROTTLE_CFG 588 165 #define SA8775P_SLAVE_A1NOC_SNOC 589 166 #define SA8775P_SLAVE_A2NOC_SNOC 590 167 #define SA8775P_SLAVE_DDRSS_CFG 591 168 #define SA8775P_SLAVE_GEM_NOC_CNOC 592 169 #define SA8775P_SLAVE_GEM_NOC_CFG 593 170 #define SA8775P_SLAVE_SNOC_GEM_NOC_GC 594 171 #define SA8775P_SLAVE_SNOC_GEM_NOC_SF 595 172 #define SA8775P_SLAVE_GP_DSP_SAIL_NOC 596 173 #define SA8775P_SLAVE_GPDSP_NOC_CFG 597 174 #define SA8775P_SLAVE_HCP_A 598 175 #define SA8775P_SLAVE_LLCC 599 176 #define SA8775P_SLAVE_MNOC_HF_MEM_NOC 600 177 #define SA8775P_SLAVE_MNOC_SF_MEM_NOC 601 178 #define SA8775P_SLAVE_CNOC_MNOC_HF_CFG 602 179 #define SA8775P_SLAVE_CNOC_MNOC_SF_CFG 603 180 #define SA8775P_SLAVE_CDSP_MEM_NOC 604 181 #define SA8775P_SLAVE_CDSPB_MEM_NOC 605 182 #define SA8775P_SLAVE_HCP_B 606 183 #define SA8775P_SLAVE_GEM_NOC_PCIE_CNOC 607 184 #define SA8775P_SLAVE_PCIE_ANOC_CFG 608 185 #define SA8775P_SLAVE_ANOC_PCIE_GEM_NOC 609 186 #define SA8775P_SLAVE_SNOC_CFG 610 187 #define SA8775P_SLAVE_LPASS_SNOC 611 188 #define SA8775P_SLAVE_QUP_CORE_0 612 189 #define SA8775P_SLAVE_QUP_CORE_1 613 190 #define SA8775P_SLAVE_QUP_CORE_2 614 191 #define SA8775P_SLAVE_QUP_CORE_3 615 192 #define SA8775P_SLAVE_BOOT_IMEM 616 193 #define SA8775P_SLAVE_IMEM 617 194 #define SA8775P_SLAVE_PIMEM 618 195 #define SA8775P_SLAVE_SERVICE_NSP_NOC 619 196 #define SA8775P_SLAVE_SERVICE_NSPB_NOC 620 197 #define SA8775P_SLAVE_SERVICE_GEM_NOC_1 621 198 #define SA8775P_SLAVE_SERVICE_MNOC_HF 622 199 #define SA8775P_SLAVE_SERVICE_MNOC_SF 623 200 #define SA8775P_SLAVE_SERVICES_LPASS_AML_NOC 624 201 #define SA8775P_SLAVE_SERVICE_LPASS_AG_NOC 625 202 #define SA8775P_SLAVE_SERVICE_GEM_NOC_2 626 203 #define SA8775P_SLAVE_SERVICE_SNOC 627 204 #define SA8775P_SLAVE_SERVICE_GEM_NOC 628 205 #define SA8775P_SLAVE_SERVICE_GEM_NOC2 629 206 #define SA8775P_SLAVE_PCIE_0 630 207 #define SA8775P_SLAVE_PCIE_1 631 208 #define SA8775P_SLAVE_QDSS_STM 632 209 #define SA8775P_SLAVE_TCU 633 210 211 static struct qcom_icc_node qxm_qup3 = { 212 .name = "qxm_qup3", 213 .id = SA8775P_MASTER_QUP_3, 214 .channels = 1, 215 .buswidth = 8, 216 .num_links = 1, 217 .links = { SA8775P_SLAVE_A1NOC_SNOC }, 218 }; 219 220 static struct qcom_icc_node xm_emac_0 = { 221 .name = "xm_emac_0", 222 .id = SA8775P_MASTER_EMAC, 223 .channels = 1, 224 .buswidth = 8, 225 .num_links = 1, 226 .links = { SA8775P_SLAVE_A1NOC_SNOC }, 227 }; 228 229 static struct qcom_icc_node xm_emac_1 = { 230 .name = "xm_emac_1", 231 .id = SA8775P_MASTER_EMAC_1, 232 .channels = 1, 233 .buswidth = 8, 234 .num_links = 1, 235 .links = { SA8775P_SLAVE_A1NOC_SNOC }, 236 }; 237 238 static struct qcom_icc_node xm_sdc1 = { 239 .name = "xm_sdc1", 240 .id = SA8775P_MASTER_SDC, 241 .channels = 1, 242 .buswidth = 8, 243 .num_links = 1, 244 .links = { SA8775P_SLAVE_A1NOC_SNOC }, 245 }; 246 247 static struct qcom_icc_node xm_ufs_mem = { 248 .name = "xm_ufs_mem", 249 .id = SA8775P_MASTER_UFS_MEM, 250 .channels = 1, 251 .buswidth = 8, 252 .num_links = 1, 253 .links = { SA8775P_SLAVE_A1NOC_SNOC }, 254 }; 255 256 static struct qcom_icc_node xm_usb2_2 = { 257 .name = "xm_usb2_2", 258 .id = SA8775P_MASTER_USB2, 259 .channels = 1, 260 .buswidth = 8, 261 .num_links = 1, 262 .links = { SA8775P_SLAVE_A1NOC_SNOC }, 263 }; 264 265 static struct qcom_icc_node xm_usb3_0 = { 266 .name = "xm_usb3_0", 267 .id = SA8775P_MASTER_USB3_0, 268 .channels = 1, 269 .buswidth = 8, 270 .num_links = 1, 271 .links = { SA8775P_SLAVE_A1NOC_SNOC }, 272 }; 273 274 static struct qcom_icc_node xm_usb3_1 = { 275 .name = "xm_usb3_1", 276 .id = SA8775P_MASTER_USB3_1, 277 .channels = 1, 278 .buswidth = 8, 279 .num_links = 1, 280 .links = { SA8775P_SLAVE_A1NOC_SNOC }, 281 }; 282 283 static struct qcom_icc_node qhm_qdss_bam = { 284 .name = "qhm_qdss_bam", 285 .id = SA8775P_MASTER_QDSS_BAM, 286 .channels = 1, 287 .buswidth = 4, 288 .num_links = 1, 289 .links = { SA8775P_SLAVE_A2NOC_SNOC }, 290 }; 291 292 static struct qcom_icc_node qhm_qup0 = { 293 .name = "qhm_qup0", 294 .id = SA8775P_MASTER_QUP_0, 295 .channels = 1, 296 .buswidth = 4, 297 .num_links = 1, 298 .links = { SA8775P_SLAVE_A2NOC_SNOC }, 299 }; 300 301 static struct qcom_icc_node qhm_qup1 = { 302 .name = "qhm_qup1", 303 .id = SA8775P_MASTER_QUP_1, 304 .channels = 1, 305 .buswidth = 4, 306 .num_links = 1, 307 .links = { SA8775P_SLAVE_A2NOC_SNOC }, 308 }; 309 310 static struct qcom_icc_node qhm_qup2 = { 311 .name = "qhm_qup2", 312 .id = SA8775P_MASTER_QUP_2, 313 .channels = 1, 314 .buswidth = 4, 315 .num_links = 1, 316 .links = { SA8775P_SLAVE_A2NOC_SNOC }, 317 }; 318 319 static struct qcom_icc_node qnm_cnoc_datapath = { 320 .name = "qnm_cnoc_datapath", 321 .id = SA8775P_MASTER_CNOC_A2NOC, 322 .channels = 1, 323 .buswidth = 8, 324 .num_links = 1, 325 .links = { SA8775P_SLAVE_A2NOC_SNOC }, 326 }; 327 328 static struct qcom_icc_node qxm_crypto_0 = { 329 .name = "qxm_crypto_0", 330 .id = SA8775P_MASTER_CRYPTO_CORE0, 331 .channels = 1, 332 .buswidth = 8, 333 .num_links = 1, 334 .links = { SA8775P_SLAVE_A2NOC_SNOC }, 335 }; 336 337 static struct qcom_icc_node qxm_crypto_1 = { 338 .name = "qxm_crypto_1", 339 .id = SA8775P_MASTER_CRYPTO_CORE1, 340 .channels = 1, 341 .buswidth = 8, 342 .num_links = 1, 343 .links = { SA8775P_SLAVE_A2NOC_SNOC }, 344 }; 345 346 static struct qcom_icc_node qxm_ipa = { 347 .name = "qxm_ipa", 348 .id = SA8775P_MASTER_IPA, 349 .channels = 1, 350 .buswidth = 8, 351 .num_links = 1, 352 .links = { SA8775P_SLAVE_A2NOC_SNOC }, 353 }; 354 355 static struct qcom_icc_node xm_qdss_etr_0 = { 356 .name = "xm_qdss_etr_0", 357 .id = SA8775P_MASTER_QDSS_ETR_0, 358 .channels = 1, 359 .buswidth = 8, 360 .num_links = 1, 361 .links = { SA8775P_SLAVE_A2NOC_SNOC }, 362 }; 363 364 static struct qcom_icc_node xm_qdss_etr_1 = { 365 .name = "xm_qdss_etr_1", 366 .id = SA8775P_MASTER_QDSS_ETR_1, 367 .channels = 1, 368 .buswidth = 8, 369 .num_links = 1, 370 .links = { SA8775P_SLAVE_A2NOC_SNOC }, 371 }; 372 373 static struct qcom_icc_node xm_ufs_card = { 374 .name = "xm_ufs_card", 375 .id = SA8775P_MASTER_UFS_CARD, 376 .channels = 1, 377 .buswidth = 8, 378 .num_links = 1, 379 .links = { SA8775P_SLAVE_A2NOC_SNOC }, 380 }; 381 382 static struct qcom_icc_node qup0_core_master = { 383 .name = "qup0_core_master", 384 .id = SA8775P_MASTER_QUP_CORE_0, 385 .channels = 1, 386 .buswidth = 4, 387 .num_links = 1, 388 .links = { SA8775P_SLAVE_QUP_CORE_0 }, 389 }; 390 391 static struct qcom_icc_node qup1_core_master = { 392 .name = "qup1_core_master", 393 .id = SA8775P_MASTER_QUP_CORE_1, 394 .channels = 1, 395 .buswidth = 4, 396 .num_links = 1, 397 .links = { SA8775P_SLAVE_QUP_CORE_1 }, 398 }; 399 400 static struct qcom_icc_node qup2_core_master = { 401 .name = "qup2_core_master", 402 .id = SA8775P_MASTER_QUP_CORE_2, 403 .channels = 1, 404 .buswidth = 4, 405 .num_links = 1, 406 .links = { SA8775P_SLAVE_QUP_CORE_2 }, 407 }; 408 409 static struct qcom_icc_node qup3_core_master = { 410 .name = "qup3_core_master", 411 .id = SA8775P_MASTER_QUP_CORE_3, 412 .channels = 1, 413 .buswidth = 4, 414 .num_links = 1, 415 .links = { SA8775P_SLAVE_QUP_CORE_3 }, 416 }; 417 418 static struct qcom_icc_node qnm_gemnoc_cnoc = { 419 .name = "qnm_gemnoc_cnoc", 420 .id = SA8775P_MASTER_GEM_NOC_CNOC, 421 .channels = 1, 422 .buswidth = 16, 423 .num_links = 82, 424 .links = { SA8775P_SLAVE_AHB2PHY_0, 425 SA8775P_SLAVE_AHB2PHY_1, 426 SA8775P_SLAVE_AHB2PHY_2, 427 SA8775P_SLAVE_AHB2PHY_3, 428 SA8775P_SLAVE_ANOC_THROTTLE_CFG, 429 SA8775P_SLAVE_AOSS, 430 SA8775P_SLAVE_APPSS, 431 SA8775P_SLAVE_BOOT_ROM, 432 SA8775P_SLAVE_CAMERA_CFG, 433 SA8775P_SLAVE_CAMERA_NRT_THROTTLE_CFG, 434 SA8775P_SLAVE_CAMERA_RT_THROTTLE_CFG, 435 SA8775P_SLAVE_CLK_CTL, 436 SA8775P_SLAVE_CDSP_CFG, 437 SA8775P_SLAVE_CDSP1_CFG, 438 SA8775P_SLAVE_RBCPR_CX_CFG, 439 SA8775P_SLAVE_RBCPR_MMCX_CFG, 440 SA8775P_SLAVE_RBCPR_MX_CFG, 441 SA8775P_SLAVE_CPR_NSPCX, 442 SA8775P_SLAVE_CRYPTO_0_CFG, 443 SA8775P_SLAVE_CX_RDPM, 444 SA8775P_SLAVE_DISPLAY_CFG, 445 SA8775P_SLAVE_DISPLAY_RT_THROTTLE_CFG, 446 SA8775P_SLAVE_DISPLAY1_CFG, 447 SA8775P_SLAVE_DISPLAY1_RT_THROTTLE_CFG, 448 SA8775P_SLAVE_EMAC_CFG, 449 SA8775P_SLAVE_EMAC1_CFG, 450 SA8775P_SLAVE_GP_DSP0_CFG, 451 SA8775P_SLAVE_GP_DSP1_CFG, 452 SA8775P_SLAVE_GPDSP0_THROTTLE_CFG, 453 SA8775P_SLAVE_GPDSP1_THROTTLE_CFG, 454 SA8775P_SLAVE_GPU_TCU_THROTTLE_CFG, 455 SA8775P_SLAVE_GFX3D_CFG, 456 SA8775P_SLAVE_HWKM, 457 SA8775P_SLAVE_IMEM_CFG, 458 SA8775P_SLAVE_IPA_CFG, 459 SA8775P_SLAVE_IPC_ROUTER_CFG, 460 SA8775P_SLAVE_LPASS, 461 SA8775P_SLAVE_LPASS_THROTTLE_CFG, 462 SA8775P_SLAVE_MX_RDPM, 463 SA8775P_SLAVE_MXC_RDPM, 464 SA8775P_SLAVE_PCIE_0_CFG, 465 SA8775P_SLAVE_PCIE_1_CFG, 466 SA8775P_SLAVE_PCIE_RSC_CFG, 467 SA8775P_SLAVE_PCIE_TCU_THROTTLE_CFG, 468 SA8775P_SLAVE_PCIE_THROTTLE_CFG, 469 SA8775P_SLAVE_PDM, 470 SA8775P_SLAVE_PIMEM_CFG, 471 SA8775P_SLAVE_PKA_WRAPPER_CFG, 472 SA8775P_SLAVE_QDSS_CFG, 473 SA8775P_SLAVE_QM_CFG, 474 SA8775P_SLAVE_QM_MPU_CFG, 475 SA8775P_SLAVE_QUP_0, 476 SA8775P_SLAVE_QUP_1, 477 SA8775P_SLAVE_QUP_2, 478 SA8775P_SLAVE_QUP_3, 479 SA8775P_SLAVE_SAIL_THROTTLE_CFG, 480 SA8775P_SLAVE_SDC1, 481 SA8775P_SLAVE_SECURITY, 482 SA8775P_SLAVE_SNOC_THROTTLE_CFG, 483 SA8775P_SLAVE_TCSR, 484 SA8775P_SLAVE_TLMM, 485 SA8775P_SLAVE_TSC_CFG, 486 SA8775P_SLAVE_UFS_CARD_CFG, 487 SA8775P_SLAVE_UFS_MEM_CFG, 488 SA8775P_SLAVE_USB2, 489 SA8775P_SLAVE_USB3_0, 490 SA8775P_SLAVE_USB3_1, 491 SA8775P_SLAVE_VENUS_CFG, 492 SA8775P_SLAVE_VENUS_CVP_THROTTLE_CFG, 493 SA8775P_SLAVE_VENUS_V_CPU_THROTTLE_CFG, 494 SA8775P_SLAVE_VENUS_VCODEC_THROTTLE_CFG, 495 SA8775P_SLAVE_DDRSS_CFG, 496 SA8775P_SLAVE_GPDSP_NOC_CFG, 497 SA8775P_SLAVE_CNOC_MNOC_HF_CFG, 498 SA8775P_SLAVE_CNOC_MNOC_SF_CFG, 499 SA8775P_SLAVE_PCIE_ANOC_CFG, 500 SA8775P_SLAVE_SNOC_CFG, 501 SA8775P_SLAVE_BOOT_IMEM, 502 SA8775P_SLAVE_IMEM, 503 SA8775P_SLAVE_PIMEM, 504 SA8775P_SLAVE_QDSS_STM, 505 SA8775P_SLAVE_TCU 506 }, 507 }; 508 509 static struct qcom_icc_node qnm_gemnoc_pcie = { 510 .name = "qnm_gemnoc_pcie", 511 .id = SA8775P_MASTER_GEM_NOC_PCIE_SNOC, 512 .channels = 1, 513 .buswidth = 16, 514 .num_links = 2, 515 .links = { SA8775P_SLAVE_PCIE_0, 516 SA8775P_SLAVE_PCIE_1 517 }, 518 }; 519 520 static struct qcom_icc_node qnm_cnoc_dc_noc = { 521 .name = "qnm_cnoc_dc_noc", 522 .id = SA8775P_MASTER_CNOC_DC_NOC, 523 .channels = 1, 524 .buswidth = 4, 525 .num_links = 2, 526 .links = { SA8775P_SLAVE_LLCC_CFG, 527 SA8775P_SLAVE_GEM_NOC_CFG 528 }, 529 }; 530 531 static struct qcom_icc_node alm_gpu_tcu = { 532 .name = "alm_gpu_tcu", 533 .id = SA8775P_MASTER_GPU_TCU, 534 .channels = 1, 535 .buswidth = 8, 536 .num_links = 2, 537 .links = { SA8775P_SLAVE_GEM_NOC_CNOC, 538 SA8775P_SLAVE_LLCC 539 }, 540 }; 541 542 static struct qcom_icc_node alm_pcie_tcu = { 543 .name = "alm_pcie_tcu", 544 .id = SA8775P_MASTER_PCIE_TCU, 545 .channels = 1, 546 .buswidth = 8, 547 .num_links = 2, 548 .links = { SA8775P_SLAVE_GEM_NOC_CNOC, 549 SA8775P_SLAVE_LLCC 550 }, 551 }; 552 553 static struct qcom_icc_node alm_sys_tcu = { 554 .name = "alm_sys_tcu", 555 .id = SA8775P_MASTER_SYS_TCU, 556 .channels = 1, 557 .buswidth = 8, 558 .num_links = 2, 559 .links = { SA8775P_SLAVE_GEM_NOC_CNOC, 560 SA8775P_SLAVE_LLCC 561 }, 562 }; 563 564 static struct qcom_icc_node chm_apps = { 565 .name = "chm_apps", 566 .id = SA8775P_MASTER_APPSS_PROC, 567 .channels = 4, 568 .buswidth = 32, 569 .num_links = 3, 570 .links = { SA8775P_SLAVE_GEM_NOC_CNOC, 571 SA8775P_SLAVE_LLCC, 572 SA8775P_SLAVE_GEM_NOC_PCIE_CNOC 573 }, 574 }; 575 576 static struct qcom_icc_node qnm_cmpnoc0 = { 577 .name = "qnm_cmpnoc0", 578 .id = SA8775P_MASTER_COMPUTE_NOC, 579 .channels = 2, 580 .buswidth = 32, 581 .num_links = 2, 582 .links = { SA8775P_SLAVE_GEM_NOC_CNOC, 583 SA8775P_SLAVE_LLCC 584 }, 585 }; 586 587 static struct qcom_icc_node qnm_cmpnoc1 = { 588 .name = "qnm_cmpnoc1", 589 .id = SA8775P_MASTER_COMPUTE_NOC_1, 590 .channels = 2, 591 .buswidth = 32, 592 .num_links = 2, 593 .links = { SA8775P_SLAVE_GEM_NOC_CNOC, 594 SA8775P_SLAVE_LLCC 595 }, 596 }; 597 598 static struct qcom_icc_node qnm_gemnoc_cfg = { 599 .name = "qnm_gemnoc_cfg", 600 .id = SA8775P_MASTER_GEM_NOC_CFG, 601 .channels = 1, 602 .buswidth = 4, 603 .num_links = 4, 604 .links = { SA8775P_SLAVE_SERVICE_GEM_NOC_1, 605 SA8775P_SLAVE_SERVICE_GEM_NOC_2, 606 SA8775P_SLAVE_SERVICE_GEM_NOC, 607 SA8775P_SLAVE_SERVICE_GEM_NOC2 608 }, 609 }; 610 611 static struct qcom_icc_node qnm_gpdsp_sail = { 612 .name = "qnm_gpdsp_sail", 613 .id = SA8775P_MASTER_GPDSP_SAIL, 614 .channels = 1, 615 .buswidth = 16, 616 .num_links = 2, 617 .links = { SA8775P_SLAVE_GEM_NOC_CNOC, 618 SA8775P_SLAVE_LLCC 619 }, 620 }; 621 622 static struct qcom_icc_node qnm_gpu = { 623 .name = "qnm_gpu", 624 .id = SA8775P_MASTER_GFX3D, 625 .channels = 2, 626 .buswidth = 32, 627 .num_links = 2, 628 .links = { SA8775P_SLAVE_GEM_NOC_CNOC, 629 SA8775P_SLAVE_LLCC 630 }, 631 }; 632 633 static struct qcom_icc_node qnm_mnoc_hf = { 634 .name = "qnm_mnoc_hf", 635 .id = SA8775P_MASTER_MNOC_HF_MEM_NOC, 636 .channels = 2, 637 .buswidth = 32, 638 .num_links = 2, 639 .links = { SA8775P_SLAVE_LLCC, 640 SA8775P_SLAVE_GEM_NOC_PCIE_CNOC 641 }, 642 }; 643 644 static struct qcom_icc_node qnm_mnoc_sf = { 645 .name = "qnm_mnoc_sf", 646 .id = SA8775P_MASTER_MNOC_SF_MEM_NOC, 647 .channels = 2, 648 .buswidth = 32, 649 .num_links = 3, 650 .links = { SA8775P_SLAVE_GEM_NOC_CNOC, 651 SA8775P_SLAVE_LLCC, 652 SA8775P_SLAVE_GEM_NOC_PCIE_CNOC 653 }, 654 }; 655 656 static struct qcom_icc_node qnm_pcie = { 657 .name = "qnm_pcie", 658 .id = SA8775P_MASTER_ANOC_PCIE_GEM_NOC, 659 .channels = 1, 660 .buswidth = 32, 661 .num_links = 2, 662 .links = { SA8775P_SLAVE_GEM_NOC_CNOC, 663 SA8775P_SLAVE_LLCC 664 }, 665 }; 666 667 static struct qcom_icc_node qnm_snoc_gc = { 668 .name = "qnm_snoc_gc", 669 .id = SA8775P_MASTER_SNOC_GC_MEM_NOC, 670 .channels = 1, 671 .buswidth = 8, 672 .num_links = 1, 673 .links = { SA8775P_SLAVE_LLCC }, 674 }; 675 676 static struct qcom_icc_node qnm_snoc_sf = { 677 .name = "qnm_snoc_sf", 678 .id = SA8775P_MASTER_SNOC_SF_MEM_NOC, 679 .channels = 1, 680 .buswidth = 16, 681 .num_links = 3, 682 .links = { SA8775P_SLAVE_GEM_NOC_CNOC, 683 SA8775P_SLAVE_LLCC, 684 SA8775P_SLAVE_GEM_NOC_PCIE_CNOC }, 685 }; 686 687 static struct qcom_icc_node qxm_dsp0 = { 688 .name = "qxm_dsp0", 689 .id = SA8775P_MASTER_DSP0, 690 .channels = 1, 691 .buswidth = 16, 692 .num_links = 1, 693 .links = { SA8775P_SLAVE_GP_DSP_SAIL_NOC }, 694 }; 695 696 static struct qcom_icc_node qxm_dsp1 = { 697 .name = "qxm_dsp1", 698 .id = SA8775P_MASTER_DSP1, 699 .channels = 1, 700 .buswidth = 16, 701 .num_links = 1, 702 .links = { SA8775P_SLAVE_GP_DSP_SAIL_NOC }, 703 }; 704 705 static struct qcom_icc_node qhm_config_noc = { 706 .name = "qhm_config_noc", 707 .id = SA8775P_MASTER_CNOC_LPASS_AG_NOC, 708 .channels = 1, 709 .buswidth = 4, 710 .num_links = 6, 711 .links = { SA8775P_SLAVE_LPASS_CORE_CFG, 712 SA8775P_SLAVE_LPASS_LPI_CFG, 713 SA8775P_SLAVE_LPASS_MPU_CFG, 714 SA8775P_SLAVE_LPASS_TOP_CFG, 715 SA8775P_SLAVE_SERVICES_LPASS_AML_NOC, 716 SA8775P_SLAVE_SERVICE_LPASS_AG_NOC 717 }, 718 }; 719 720 static struct qcom_icc_node qxm_lpass_dsp = { 721 .name = "qxm_lpass_dsp", 722 .id = SA8775P_MASTER_LPASS_PROC, 723 .channels = 1, 724 .buswidth = 8, 725 .num_links = 4, 726 .links = { SA8775P_SLAVE_LPASS_TOP_CFG, 727 SA8775P_SLAVE_LPASS_SNOC, 728 SA8775P_SLAVE_SERVICES_LPASS_AML_NOC, 729 SA8775P_SLAVE_SERVICE_LPASS_AG_NOC 730 }, 731 }; 732 733 static struct qcom_icc_node llcc_mc = { 734 .name = "llcc_mc", 735 .id = SA8775P_MASTER_LLCC, 736 .channels = 8, 737 .buswidth = 4, 738 .num_links = 1, 739 .links = { SA8775P_SLAVE_EBI1 }, 740 }; 741 742 static struct qcom_icc_node qnm_camnoc_hf = { 743 .name = "qnm_camnoc_hf", 744 .id = SA8775P_MASTER_CAMNOC_HF, 745 .channels = 1, 746 .buswidth = 32, 747 .num_links = 1, 748 .links = { SA8775P_SLAVE_MNOC_HF_MEM_NOC }, 749 }; 750 751 static struct qcom_icc_node qnm_camnoc_icp = { 752 .name = "qnm_camnoc_icp", 753 .id = SA8775P_MASTER_CAMNOC_ICP, 754 .channels = 1, 755 .buswidth = 8, 756 .num_links = 1, 757 .links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC }, 758 }; 759 760 static struct qcom_icc_node qnm_camnoc_sf = { 761 .name = "qnm_camnoc_sf", 762 .id = SA8775P_MASTER_CAMNOC_SF, 763 .channels = 1, 764 .buswidth = 32, 765 .num_links = 1, 766 .links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC }, 767 }; 768 769 static struct qcom_icc_node qnm_mdp0_0 = { 770 .name = "qnm_mdp0_0", 771 .id = SA8775P_MASTER_MDP0, 772 .channels = 1, 773 .buswidth = 32, 774 .num_links = 1, 775 .links = { SA8775P_SLAVE_MNOC_HF_MEM_NOC }, 776 }; 777 778 static struct qcom_icc_node qnm_mdp0_1 = { 779 .name = "qnm_mdp0_1", 780 .id = SA8775P_MASTER_MDP1, 781 .channels = 1, 782 .buswidth = 32, 783 .num_links = 1, 784 .links = { SA8775P_SLAVE_MNOC_HF_MEM_NOC }, 785 }; 786 787 static struct qcom_icc_node qnm_mdp1_0 = { 788 .name = "qnm_mdp1_0", 789 .id = SA8775P_MASTER_MDP_CORE1_0, 790 .channels = 1, 791 .buswidth = 32, 792 .num_links = 1, 793 .links = { SA8775P_SLAVE_MNOC_HF_MEM_NOC }, 794 }; 795 796 static struct qcom_icc_node qnm_mdp1_1 = { 797 .name = "qnm_mdp1_1", 798 .id = SA8775P_MASTER_MDP_CORE1_1, 799 .channels = 1, 800 .buswidth = 32, 801 .num_links = 1, 802 .links = { SA8775P_SLAVE_MNOC_HF_MEM_NOC }, 803 }; 804 805 static struct qcom_icc_node qnm_mnoc_hf_cfg = { 806 .name = "qnm_mnoc_hf_cfg", 807 .id = SA8775P_MASTER_CNOC_MNOC_HF_CFG, 808 .channels = 1, 809 .buswidth = 4, 810 .num_links = 1, 811 .links = { SA8775P_SLAVE_SERVICE_MNOC_HF }, 812 }; 813 814 static struct qcom_icc_node qnm_mnoc_sf_cfg = { 815 .name = "qnm_mnoc_sf_cfg", 816 .id = SA8775P_MASTER_CNOC_MNOC_SF_CFG, 817 .channels = 1, 818 .buswidth = 4, 819 .num_links = 1, 820 .links = { SA8775P_SLAVE_SERVICE_MNOC_SF }, 821 }; 822 823 static struct qcom_icc_node qnm_video0 = { 824 .name = "qnm_video0", 825 .id = SA8775P_MASTER_VIDEO_P0, 826 .channels = 1, 827 .buswidth = 32, 828 .num_links = 1, 829 .links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC }, 830 }; 831 832 static struct qcom_icc_node qnm_video1 = { 833 .name = "qnm_video1", 834 .id = SA8775P_MASTER_VIDEO_P1, 835 .channels = 1, 836 .buswidth = 32, 837 .num_links = 1, 838 .links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC }, 839 }; 840 841 static struct qcom_icc_node qnm_video_cvp = { 842 .name = "qnm_video_cvp", 843 .id = SA8775P_MASTER_VIDEO_PROC, 844 .channels = 1, 845 .buswidth = 32, 846 .num_links = 1, 847 .links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC }, 848 }; 849 850 static struct qcom_icc_node qnm_video_v_cpu = { 851 .name = "qnm_video_v_cpu", 852 .id = SA8775P_MASTER_VIDEO_V_PROC, 853 .channels = 1, 854 .buswidth = 8, 855 .num_links = 1, 856 .links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC }, 857 }; 858 859 static struct qcom_icc_node qhm_nsp_noc_config = { 860 .name = "qhm_nsp_noc_config", 861 .id = SA8775P_MASTER_CDSP_NOC_CFG, 862 .channels = 1, 863 .buswidth = 4, 864 .num_links = 1, 865 .links = { SA8775P_SLAVE_SERVICE_NSP_NOC }, 866 }; 867 868 static struct qcom_icc_node qxm_nsp = { 869 .name = "qxm_nsp", 870 .id = SA8775P_MASTER_CDSP_PROC, 871 .channels = 2, 872 .buswidth = 32, 873 .num_links = 2, 874 .links = { SA8775P_SLAVE_HCP_A, SLAVE_CDSP_MEM_NOC }, 875 }; 876 877 static struct qcom_icc_node qhm_nspb_noc_config = { 878 .name = "qhm_nspb_noc_config", 879 .id = SA8775P_MASTER_CDSPB_NOC_CFG, 880 .channels = 1, 881 .buswidth = 4, 882 .num_links = 1, 883 .links = { SA8775P_SLAVE_SERVICE_NSPB_NOC }, 884 }; 885 886 static struct qcom_icc_node qxm_nspb = { 887 .name = "qxm_nspb", 888 .id = SA8775P_MASTER_CDSP_PROC_B, 889 .channels = 2, 890 .buswidth = 32, 891 .num_links = 2, 892 .links = { SA8775P_SLAVE_HCP_B, SLAVE_CDSPB_MEM_NOC }, 893 }; 894 895 static struct qcom_icc_node xm_pcie3_0 = { 896 .name = "xm_pcie3_0", 897 .id = SA8775P_MASTER_PCIE_0, 898 .channels = 1, 899 .buswidth = 16, 900 .num_links = 1, 901 .links = { SA8775P_SLAVE_ANOC_PCIE_GEM_NOC }, 902 }; 903 904 static struct qcom_icc_node xm_pcie3_1 = { 905 .name = "xm_pcie3_1", 906 .id = SA8775P_MASTER_PCIE_1, 907 .channels = 1, 908 .buswidth = 32, 909 .num_links = 1, 910 .links = { SA8775P_SLAVE_ANOC_PCIE_GEM_NOC }, 911 }; 912 913 static struct qcom_icc_node qhm_gic = { 914 .name = "qhm_gic", 915 .id = SA8775P_MASTER_GIC_AHB, 916 .channels = 1, 917 .buswidth = 4, 918 .num_links = 1, 919 .links = { SA8775P_SLAVE_SNOC_GEM_NOC_SF }, 920 }; 921 922 static struct qcom_icc_node qnm_aggre1_noc = { 923 .name = "qnm_aggre1_noc", 924 .id = SA8775P_MASTER_A1NOC_SNOC, 925 .channels = 1, 926 .buswidth = 32, 927 .num_links = 1, 928 .links = { SA8775P_SLAVE_SNOC_GEM_NOC_SF }, 929 }; 930 931 static struct qcom_icc_node qnm_aggre2_noc = { 932 .name = "qnm_aggre2_noc", 933 .id = SA8775P_MASTER_A2NOC_SNOC, 934 .channels = 1, 935 .buswidth = 16, 936 .num_links = 1, 937 .links = { SA8775P_SLAVE_SNOC_GEM_NOC_SF }, 938 }; 939 940 static struct qcom_icc_node qnm_lpass_noc = { 941 .name = "qnm_lpass_noc", 942 .id = SA8775P_MASTER_LPASS_ANOC, 943 .channels = 1, 944 .buswidth = 16, 945 .num_links = 1, 946 .links = { SA8775P_SLAVE_SNOC_GEM_NOC_SF }, 947 }; 948 949 static struct qcom_icc_node qnm_snoc_cfg = { 950 .name = "qnm_snoc_cfg", 951 .id = SA8775P_MASTER_SNOC_CFG, 952 .channels = 1, 953 .buswidth = 4, 954 .num_links = 1, 955 .links = { SA8775P_SLAVE_SERVICE_SNOC }, 956 }; 957 958 static struct qcom_icc_node qxm_pimem = { 959 .name = "qxm_pimem", 960 .id = SA8775P_MASTER_PIMEM, 961 .channels = 1, 962 .buswidth = 8, 963 .num_links = 1, 964 .links = { SA8775P_SLAVE_SNOC_GEM_NOC_GC }, 965 }; 966 967 static struct qcom_icc_node xm_gic = { 968 .name = "xm_gic", 969 .id = SA8775P_MASTER_GIC, 970 .channels = 1, 971 .buswidth = 8, 972 .num_links = 1, 973 .links = { SA8775P_SLAVE_SNOC_GEM_NOC_GC }, 974 }; 975 976 static struct qcom_icc_node qns_a1noc_snoc = { 977 .name = "qns_a1noc_snoc", 978 .id = SA8775P_SLAVE_A1NOC_SNOC, 979 .channels = 1, 980 .buswidth = 32, 981 .num_links = 1, 982 .links = { SA8775P_MASTER_A1NOC_SNOC }, 983 }; 984 985 static struct qcom_icc_node qns_a2noc_snoc = { 986 .name = "qns_a2noc_snoc", 987 .id = SA8775P_SLAVE_A2NOC_SNOC, 988 .channels = 1, 989 .buswidth = 16, 990 .num_links = 1, 991 .links = { SA8775P_MASTER_A2NOC_SNOC }, 992 }; 993 994 static struct qcom_icc_node qup0_core_slave = { 995 .name = "qup0_core_slave", 996 .id = SA8775P_SLAVE_QUP_CORE_0, 997 .channels = 1, 998 .buswidth = 4, 999 }; 1000 1001 static struct qcom_icc_node qup1_core_slave = { 1002 .name = "qup1_core_slave", 1003 .id = SA8775P_SLAVE_QUP_CORE_1, 1004 .channels = 1, 1005 .buswidth = 4, 1006 }; 1007 1008 static struct qcom_icc_node qup2_core_slave = { 1009 .name = "qup2_core_slave", 1010 .id = SA8775P_SLAVE_QUP_CORE_2, 1011 .channels = 1, 1012 .buswidth = 4, 1013 }; 1014 1015 static struct qcom_icc_node qup3_core_slave = { 1016 .name = "qup3_core_slave", 1017 .id = SA8775P_SLAVE_QUP_CORE_3, 1018 .channels = 1, 1019 .buswidth = 4, 1020 }; 1021 1022 static struct qcom_icc_node qhs_ahb2phy0 = { 1023 .name = "qhs_ahb2phy0", 1024 .id = SA8775P_SLAVE_AHB2PHY_0, 1025 .channels = 1, 1026 .buswidth = 4, 1027 }; 1028 1029 static struct qcom_icc_node qhs_ahb2phy1 = { 1030 .name = "qhs_ahb2phy1", 1031 .id = SA8775P_SLAVE_AHB2PHY_1, 1032 .channels = 1, 1033 .buswidth = 4, 1034 }; 1035 1036 static struct qcom_icc_node qhs_ahb2phy2 = { 1037 .name = "qhs_ahb2phy2", 1038 .id = SA8775P_SLAVE_AHB2PHY_2, 1039 .channels = 1, 1040 .buswidth = 4, 1041 }; 1042 1043 static struct qcom_icc_node qhs_ahb2phy3 = { 1044 .name = "qhs_ahb2phy3", 1045 .id = SA8775P_SLAVE_AHB2PHY_3, 1046 .channels = 1, 1047 .buswidth = 4, 1048 }; 1049 1050 static struct qcom_icc_node qhs_anoc_throttle_cfg = { 1051 .name = "qhs_anoc_throttle_cfg", 1052 .id = SA8775P_SLAVE_ANOC_THROTTLE_CFG, 1053 .channels = 1, 1054 .buswidth = 4, 1055 }; 1056 1057 static struct qcom_icc_node qhs_aoss = { 1058 .name = "qhs_aoss", 1059 .id = SA8775P_SLAVE_AOSS, 1060 .channels = 1, 1061 .buswidth = 4, 1062 }; 1063 1064 static struct qcom_icc_node qhs_apss = { 1065 .name = "qhs_apss", 1066 .id = SA8775P_SLAVE_APPSS, 1067 .channels = 1, 1068 .buswidth = 8, 1069 }; 1070 1071 static struct qcom_icc_node qhs_boot_rom = { 1072 .name = "qhs_boot_rom", 1073 .id = SA8775P_SLAVE_BOOT_ROM, 1074 .channels = 1, 1075 .buswidth = 4, 1076 }; 1077 1078 static struct qcom_icc_node qhs_camera_cfg = { 1079 .name = "qhs_camera_cfg", 1080 .id = SA8775P_SLAVE_CAMERA_CFG, 1081 .channels = 1, 1082 .buswidth = 4, 1083 }; 1084 1085 static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = { 1086 .name = "qhs_camera_nrt_throttle_cfg", 1087 .id = SA8775P_SLAVE_CAMERA_NRT_THROTTLE_CFG, 1088 .channels = 1, 1089 .buswidth = 4, 1090 }; 1091 1092 static struct qcom_icc_node qhs_camera_rt_throttle_cfg = { 1093 .name = "qhs_camera_rt_throttle_cfg", 1094 .id = SA8775P_SLAVE_CAMERA_RT_THROTTLE_CFG, 1095 .channels = 1, 1096 .buswidth = 4, 1097 }; 1098 1099 static struct qcom_icc_node qhs_clk_ctl = { 1100 .name = "qhs_clk_ctl", 1101 .id = SA8775P_SLAVE_CLK_CTL, 1102 .channels = 1, 1103 .buswidth = 4, 1104 }; 1105 1106 static struct qcom_icc_node qhs_compute0_cfg = { 1107 .name = "qhs_compute0_cfg", 1108 .id = SA8775P_SLAVE_CDSP_CFG, 1109 .channels = 1, 1110 .buswidth = 4, 1111 .num_links = 1, 1112 .links = { SA8775P_MASTER_CDSP_NOC_CFG }, 1113 }; 1114 1115 static struct qcom_icc_node qhs_compute1_cfg = { 1116 .name = "qhs_compute1_cfg", 1117 .id = SA8775P_SLAVE_CDSP1_CFG, 1118 .channels = 1, 1119 .buswidth = 4, 1120 .num_links = 1, 1121 .links = { SA8775P_MASTER_CDSPB_NOC_CFG }, 1122 }; 1123 1124 static struct qcom_icc_node qhs_cpr_cx = { 1125 .name = "qhs_cpr_cx", 1126 .id = SA8775P_SLAVE_RBCPR_CX_CFG, 1127 .channels = 1, 1128 .buswidth = 4, 1129 }; 1130 1131 static struct qcom_icc_node qhs_cpr_mmcx = { 1132 .name = "qhs_cpr_mmcx", 1133 .id = SA8775P_SLAVE_RBCPR_MMCX_CFG, 1134 .channels = 1, 1135 .buswidth = 4, 1136 }; 1137 1138 static struct qcom_icc_node qhs_cpr_mx = { 1139 .name = "qhs_cpr_mx", 1140 .id = SA8775P_SLAVE_RBCPR_MX_CFG, 1141 .channels = 1, 1142 .buswidth = 4, 1143 }; 1144 1145 static struct qcom_icc_node qhs_cpr_nspcx = { 1146 .name = "qhs_cpr_nspcx", 1147 .id = SA8775P_SLAVE_CPR_NSPCX, 1148 .channels = 1, 1149 .buswidth = 4, 1150 }; 1151 1152 static struct qcom_icc_node qhs_crypto0_cfg = { 1153 .name = "qhs_crypto0_cfg", 1154 .id = SA8775P_SLAVE_CRYPTO_0_CFG, 1155 .channels = 1, 1156 .buswidth = 4, 1157 }; 1158 1159 static struct qcom_icc_node qhs_cx_rdpm = { 1160 .name = "qhs_cx_rdpm", 1161 .id = SA8775P_SLAVE_CX_RDPM, 1162 .channels = 1, 1163 .buswidth = 4, 1164 }; 1165 1166 static struct qcom_icc_node qhs_display0_cfg = { 1167 .name = "qhs_display0_cfg", 1168 .id = SA8775P_SLAVE_DISPLAY_CFG, 1169 .channels = 1, 1170 .buswidth = 4, 1171 }; 1172 1173 static struct qcom_icc_node qhs_display0_rt_throttle_cfg = { 1174 .name = "qhs_display0_rt_throttle_cfg", 1175 .id = SA8775P_SLAVE_DISPLAY_RT_THROTTLE_CFG, 1176 .channels = 1, 1177 .buswidth = 4, 1178 }; 1179 1180 static struct qcom_icc_node qhs_display1_cfg = { 1181 .name = "qhs_display1_cfg", 1182 .id = SA8775P_SLAVE_DISPLAY1_CFG, 1183 .channels = 1, 1184 .buswidth = 4, 1185 }; 1186 1187 static struct qcom_icc_node qhs_display1_rt_throttle_cfg = { 1188 .name = "qhs_display1_rt_throttle_cfg", 1189 .id = SA8775P_SLAVE_DISPLAY1_RT_THROTTLE_CFG, 1190 .channels = 1, 1191 .buswidth = 4, 1192 }; 1193 1194 static struct qcom_icc_node qhs_emac0_cfg = { 1195 .name = "qhs_emac0_cfg", 1196 .id = SA8775P_SLAVE_EMAC_CFG, 1197 .channels = 1, 1198 .buswidth = 4, 1199 }; 1200 1201 static struct qcom_icc_node qhs_emac1_cfg = { 1202 .name = "qhs_emac1_cfg", 1203 .id = SA8775P_SLAVE_EMAC1_CFG, 1204 .channels = 1, 1205 .buswidth = 4, 1206 }; 1207 1208 static struct qcom_icc_node qhs_gp_dsp0_cfg = { 1209 .name = "qhs_gp_dsp0_cfg", 1210 .id = SA8775P_SLAVE_GP_DSP0_CFG, 1211 .channels = 1, 1212 .buswidth = 4, 1213 }; 1214 1215 static struct qcom_icc_node qhs_gp_dsp1_cfg = { 1216 .name = "qhs_gp_dsp1_cfg", 1217 .id = SA8775P_SLAVE_GP_DSP1_CFG, 1218 .channels = 1, 1219 .buswidth = 4, 1220 }; 1221 1222 static struct qcom_icc_node qhs_gpdsp0_throttle_cfg = { 1223 .name = "qhs_gpdsp0_throttle_cfg", 1224 .id = SA8775P_SLAVE_GPDSP0_THROTTLE_CFG, 1225 .channels = 1, 1226 .buswidth = 4, 1227 }; 1228 1229 static struct qcom_icc_node qhs_gpdsp1_throttle_cfg = { 1230 .name = "qhs_gpdsp1_throttle_cfg", 1231 .id = SA8775P_SLAVE_GPDSP1_THROTTLE_CFG, 1232 .channels = 1, 1233 .buswidth = 4, 1234 }; 1235 1236 static struct qcom_icc_node qhs_gpu_tcu_throttle_cfg = { 1237 .name = "qhs_gpu_tcu_throttle_cfg", 1238 .id = SA8775P_SLAVE_GPU_TCU_THROTTLE_CFG, 1239 .channels = 1, 1240 .buswidth = 4, 1241 }; 1242 1243 static struct qcom_icc_node qhs_gpuss_cfg = { 1244 .name = "qhs_gpuss_cfg", 1245 .id = SA8775P_SLAVE_GFX3D_CFG, 1246 .channels = 1, 1247 .buswidth = 8, 1248 }; 1249 1250 static struct qcom_icc_node qhs_hwkm = { 1251 .name = "qhs_hwkm", 1252 .id = SA8775P_SLAVE_HWKM, 1253 .channels = 1, 1254 .buswidth = 4, 1255 }; 1256 1257 static struct qcom_icc_node qhs_imem_cfg = { 1258 .name = "qhs_imem_cfg", 1259 .id = SA8775P_SLAVE_IMEM_CFG, 1260 .channels = 1, 1261 .buswidth = 4, 1262 }; 1263 1264 static struct qcom_icc_node qhs_ipa = { 1265 .name = "qhs_ipa", 1266 .id = SA8775P_SLAVE_IPA_CFG, 1267 .channels = 1, 1268 .buswidth = 4, 1269 }; 1270 1271 static struct qcom_icc_node qhs_ipc_router = { 1272 .name = "qhs_ipc_router", 1273 .id = SA8775P_SLAVE_IPC_ROUTER_CFG, 1274 .channels = 1, 1275 .buswidth = 4, 1276 }; 1277 1278 static struct qcom_icc_node qhs_lpass_cfg = { 1279 .name = "qhs_lpass_cfg", 1280 .id = SA8775P_SLAVE_LPASS, 1281 .channels = 1, 1282 .buswidth = 4, 1283 .num_links = 1, 1284 .links = { SA8775P_MASTER_CNOC_LPASS_AG_NOC }, 1285 }; 1286 1287 static struct qcom_icc_node qhs_lpass_throttle_cfg = { 1288 .name = "qhs_lpass_throttle_cfg", 1289 .id = SA8775P_SLAVE_LPASS_THROTTLE_CFG, 1290 .channels = 1, 1291 .buswidth = 4, 1292 }; 1293 1294 static struct qcom_icc_node qhs_mx_rdpm = { 1295 .name = "qhs_mx_rdpm", 1296 .id = SA8775P_SLAVE_MX_RDPM, 1297 .channels = 1, 1298 .buswidth = 4, 1299 }; 1300 1301 static struct qcom_icc_node qhs_mxc_rdpm = { 1302 .name = "qhs_mxc_rdpm", 1303 .id = SA8775P_SLAVE_MXC_RDPM, 1304 .channels = 1, 1305 .buswidth = 4, 1306 }; 1307 1308 static struct qcom_icc_node qhs_pcie0_cfg = { 1309 .name = "qhs_pcie0_cfg", 1310 .id = SA8775P_SLAVE_PCIE_0_CFG, 1311 .channels = 1, 1312 .buswidth = 4, 1313 }; 1314 1315 static struct qcom_icc_node qhs_pcie1_cfg = { 1316 .name = "qhs_pcie1_cfg", 1317 .id = SA8775P_SLAVE_PCIE_1_CFG, 1318 .channels = 1, 1319 .buswidth = 4, 1320 }; 1321 1322 static struct qcom_icc_node qhs_pcie_rsc_cfg = { 1323 .name = "qhs_pcie_rsc_cfg", 1324 .id = SA8775P_SLAVE_PCIE_RSC_CFG, 1325 .channels = 1, 1326 .buswidth = 4, 1327 }; 1328 1329 static struct qcom_icc_node qhs_pcie_tcu_throttle_cfg = { 1330 .name = "qhs_pcie_tcu_throttle_cfg", 1331 .id = SA8775P_SLAVE_PCIE_TCU_THROTTLE_CFG, 1332 .channels = 1, 1333 .buswidth = 4, 1334 }; 1335 1336 static struct qcom_icc_node qhs_pcie_throttle_cfg = { 1337 .name = "qhs_pcie_throttle_cfg", 1338 .id = SA8775P_SLAVE_PCIE_THROTTLE_CFG, 1339 .channels = 1, 1340 .buswidth = 4, 1341 }; 1342 1343 static struct qcom_icc_node qhs_pdm = { 1344 .name = "qhs_pdm", 1345 .id = SA8775P_SLAVE_PDM, 1346 .channels = 1, 1347 .buswidth = 4, 1348 }; 1349 1350 static struct qcom_icc_node qhs_pimem_cfg = { 1351 .name = "qhs_pimem_cfg", 1352 .id = SA8775P_SLAVE_PIMEM_CFG, 1353 .channels = 1, 1354 .buswidth = 4, 1355 }; 1356 1357 static struct qcom_icc_node qhs_pke_wrapper_cfg = { 1358 .name = "qhs_pke_wrapper_cfg", 1359 .id = SA8775P_SLAVE_PKA_WRAPPER_CFG, 1360 .channels = 1, 1361 .buswidth = 4, 1362 }; 1363 1364 static struct qcom_icc_node qhs_qdss_cfg = { 1365 .name = "qhs_qdss_cfg", 1366 .id = SA8775P_SLAVE_QDSS_CFG, 1367 .channels = 1, 1368 .buswidth = 4, 1369 }; 1370 1371 static struct qcom_icc_node qhs_qm_cfg = { 1372 .name = "qhs_qm_cfg", 1373 .id = SA8775P_SLAVE_QM_CFG, 1374 .channels = 1, 1375 .buswidth = 4, 1376 }; 1377 1378 static struct qcom_icc_node qhs_qm_mpu_cfg = { 1379 .name = "qhs_qm_mpu_cfg", 1380 .id = SA8775P_SLAVE_QM_MPU_CFG, 1381 .channels = 1, 1382 .buswidth = 4, 1383 }; 1384 1385 static struct qcom_icc_node qhs_qup0 = { 1386 .name = "qhs_qup0", 1387 .id = SA8775P_SLAVE_QUP_0, 1388 .channels = 1, 1389 .buswidth = 4, 1390 }; 1391 1392 static struct qcom_icc_node qhs_qup1 = { 1393 .name = "qhs_qup1", 1394 .id = SA8775P_SLAVE_QUP_1, 1395 .channels = 1, 1396 .buswidth = 4, 1397 }; 1398 1399 static struct qcom_icc_node qhs_qup2 = { 1400 .name = "qhs_qup2", 1401 .id = SA8775P_SLAVE_QUP_2, 1402 .channels = 1, 1403 .buswidth = 4, 1404 }; 1405 1406 static struct qcom_icc_node qhs_qup3 = { 1407 .name = "qhs_qup3", 1408 .id = SA8775P_SLAVE_QUP_3, 1409 .channels = 1, 1410 .buswidth = 4, 1411 }; 1412 1413 static struct qcom_icc_node qhs_sail_throttle_cfg = { 1414 .name = "qhs_sail_throttle_cfg", 1415 .id = SA8775P_SLAVE_SAIL_THROTTLE_CFG, 1416 .channels = 1, 1417 .buswidth = 4, 1418 }; 1419 1420 static struct qcom_icc_node qhs_sdc1 = { 1421 .name = "qhs_sdc1", 1422 .id = SA8775P_SLAVE_SDC1, 1423 .channels = 1, 1424 .buswidth = 4, 1425 }; 1426 1427 static struct qcom_icc_node qhs_security = { 1428 .name = "qhs_security", 1429 .id = SA8775P_SLAVE_SECURITY, 1430 .channels = 1, 1431 .buswidth = 4, 1432 }; 1433 1434 static struct qcom_icc_node qhs_snoc_throttle_cfg = { 1435 .name = "qhs_snoc_throttle_cfg", 1436 .id = SA8775P_SLAVE_SNOC_THROTTLE_CFG, 1437 .channels = 1, 1438 .buswidth = 4, 1439 }; 1440 1441 static struct qcom_icc_node qhs_tcsr = { 1442 .name = "qhs_tcsr", 1443 .id = SA8775P_SLAVE_TCSR, 1444 .channels = 1, 1445 .buswidth = 4, 1446 }; 1447 1448 static struct qcom_icc_node qhs_tlmm = { 1449 .name = "qhs_tlmm", 1450 .id = SA8775P_SLAVE_TLMM, 1451 .channels = 1, 1452 .buswidth = 4, 1453 }; 1454 1455 static struct qcom_icc_node qhs_tsc_cfg = { 1456 .name = "qhs_tsc_cfg", 1457 .id = SA8775P_SLAVE_TSC_CFG, 1458 .channels = 1, 1459 .buswidth = 4, 1460 }; 1461 1462 static struct qcom_icc_node qhs_ufs_card_cfg = { 1463 .name = "qhs_ufs_card_cfg", 1464 .id = SA8775P_SLAVE_UFS_CARD_CFG, 1465 .channels = 1, 1466 .buswidth = 4, 1467 }; 1468 1469 static struct qcom_icc_node qhs_ufs_mem_cfg = { 1470 .name = "qhs_ufs_mem_cfg", 1471 .id = SA8775P_SLAVE_UFS_MEM_CFG, 1472 .channels = 1, 1473 .buswidth = 4, 1474 }; 1475 1476 static struct qcom_icc_node qhs_usb2_0 = { 1477 .name = "qhs_usb2_0", 1478 .id = SA8775P_SLAVE_USB2, 1479 .channels = 1, 1480 .buswidth = 4, 1481 }; 1482 1483 static struct qcom_icc_node qhs_usb3_0 = { 1484 .name = "qhs_usb3_0", 1485 .id = SA8775P_SLAVE_USB3_0, 1486 .channels = 1, 1487 .buswidth = 4, 1488 }; 1489 1490 static struct qcom_icc_node qhs_usb3_1 = { 1491 .name = "qhs_usb3_1", 1492 .id = SA8775P_SLAVE_USB3_1, 1493 .channels = 1, 1494 .buswidth = 4, 1495 }; 1496 1497 static struct qcom_icc_node qhs_venus_cfg = { 1498 .name = "qhs_venus_cfg", 1499 .id = SA8775P_SLAVE_VENUS_CFG, 1500 .channels = 1, 1501 .buswidth = 4, 1502 }; 1503 1504 static struct qcom_icc_node qhs_venus_cvp_throttle_cfg = { 1505 .name = "qhs_venus_cvp_throttle_cfg", 1506 .id = SA8775P_SLAVE_VENUS_CVP_THROTTLE_CFG, 1507 .channels = 1, 1508 .buswidth = 4, 1509 }; 1510 1511 static struct qcom_icc_node qhs_venus_v_cpu_throttle_cfg = { 1512 .name = "qhs_venus_v_cpu_throttle_cfg", 1513 .id = SA8775P_SLAVE_VENUS_V_CPU_THROTTLE_CFG, 1514 .channels = 1, 1515 .buswidth = 4, 1516 }; 1517 1518 static struct qcom_icc_node qhs_venus_vcodec_throttle_cfg = { 1519 .name = "qhs_venus_vcodec_throttle_cfg", 1520 .id = SA8775P_SLAVE_VENUS_VCODEC_THROTTLE_CFG, 1521 .channels = 1, 1522 .buswidth = 4, 1523 }; 1524 1525 static struct qcom_icc_node qns_ddrss_cfg = { 1526 .name = "qns_ddrss_cfg", 1527 .id = SA8775P_SLAVE_DDRSS_CFG, 1528 .channels = 1, 1529 .buswidth = 4, 1530 .num_links = 1, 1531 .links = { SA8775P_MASTER_CNOC_DC_NOC }, 1532 }; 1533 1534 static struct qcom_icc_node qns_gpdsp_noc_cfg = { 1535 .name = "qns_gpdsp_noc_cfg", 1536 .id = SA8775P_SLAVE_GPDSP_NOC_CFG, 1537 .channels = 1, 1538 .buswidth = 4, 1539 }; 1540 1541 static struct qcom_icc_node qns_mnoc_hf_cfg = { 1542 .name = "qns_mnoc_hf_cfg", 1543 .id = SA8775P_SLAVE_CNOC_MNOC_HF_CFG, 1544 .channels = 1, 1545 .buswidth = 4, 1546 .num_links = 1, 1547 .links = { SA8775P_MASTER_CNOC_MNOC_HF_CFG }, 1548 }; 1549 1550 static struct qcom_icc_node qns_mnoc_sf_cfg = { 1551 .name = "qns_mnoc_sf_cfg", 1552 .id = SA8775P_SLAVE_CNOC_MNOC_SF_CFG, 1553 .channels = 1, 1554 .buswidth = 4, 1555 .num_links = 1, 1556 .links = { SA8775P_MASTER_CNOC_MNOC_SF_CFG }, 1557 }; 1558 1559 static struct qcom_icc_node qns_pcie_anoc_cfg = { 1560 .name = "qns_pcie_anoc_cfg", 1561 .id = SA8775P_SLAVE_PCIE_ANOC_CFG, 1562 .channels = 1, 1563 .buswidth = 4, 1564 }; 1565 1566 static struct qcom_icc_node qns_snoc_cfg = { 1567 .name = "qns_snoc_cfg", 1568 .id = SA8775P_SLAVE_SNOC_CFG, 1569 .channels = 1, 1570 .buswidth = 4, 1571 .num_links = 1, 1572 .links = { SA8775P_MASTER_SNOC_CFG }, 1573 }; 1574 1575 static struct qcom_icc_node qxs_boot_imem = { 1576 .name = "qxs_boot_imem", 1577 .id = SA8775P_SLAVE_BOOT_IMEM, 1578 .channels = 1, 1579 .buswidth = 16, 1580 }; 1581 1582 static struct qcom_icc_node qxs_imem = { 1583 .name = "qxs_imem", 1584 .id = SA8775P_SLAVE_IMEM, 1585 .channels = 1, 1586 .buswidth = 8, 1587 }; 1588 1589 static struct qcom_icc_node qxs_pimem = { 1590 .name = "qxs_pimem", 1591 .id = SA8775P_SLAVE_PIMEM, 1592 .channels = 1, 1593 .buswidth = 8, 1594 }; 1595 1596 static struct qcom_icc_node xs_pcie_0 = { 1597 .name = "xs_pcie_0", 1598 .id = SA8775P_SLAVE_PCIE_0, 1599 .channels = 1, 1600 .buswidth = 16, 1601 }; 1602 1603 static struct qcom_icc_node xs_pcie_1 = { 1604 .name = "xs_pcie_1", 1605 .id = SA8775P_SLAVE_PCIE_1, 1606 .channels = 1, 1607 .buswidth = 32, 1608 }; 1609 1610 static struct qcom_icc_node xs_qdss_stm = { 1611 .name = "xs_qdss_stm", 1612 .id = SA8775P_SLAVE_QDSS_STM, 1613 .channels = 1, 1614 .buswidth = 4, 1615 }; 1616 1617 static struct qcom_icc_node xs_sys_tcu_cfg = { 1618 .name = "xs_sys_tcu_cfg", 1619 .id = SA8775P_SLAVE_TCU, 1620 .channels = 1, 1621 .buswidth = 8, 1622 }; 1623 1624 static struct qcom_icc_node qhs_llcc = { 1625 .name = "qhs_llcc", 1626 .id = SA8775P_SLAVE_LLCC_CFG, 1627 .channels = 1, 1628 .buswidth = 4, 1629 }; 1630 1631 static struct qcom_icc_node qns_gemnoc = { 1632 .name = "qns_gemnoc", 1633 .id = SA8775P_SLAVE_GEM_NOC_CFG, 1634 .channels = 1, 1635 .buswidth = 4, 1636 .num_links = 1, 1637 .links = { SA8775P_MASTER_GEM_NOC_CFG }, 1638 }; 1639 1640 static struct qcom_icc_node qns_gem_noc_cnoc = { 1641 .name = "qns_gem_noc_cnoc", 1642 .id = SA8775P_SLAVE_GEM_NOC_CNOC, 1643 .channels = 1, 1644 .buswidth = 16, 1645 .num_links = 1, 1646 .links = { SA8775P_MASTER_GEM_NOC_CNOC }, 1647 }; 1648 1649 static struct qcom_icc_node qns_llcc = { 1650 .name = "qns_llcc", 1651 .id = SA8775P_SLAVE_LLCC, 1652 .channels = 6, 1653 .buswidth = 16, 1654 .num_links = 1, 1655 .links = { SA8775P_MASTER_LLCC }, 1656 }; 1657 1658 static struct qcom_icc_node qns_pcie = { 1659 .name = "qns_pcie", 1660 .id = SA8775P_SLAVE_GEM_NOC_PCIE_CNOC, 1661 .channels = 1, 1662 .buswidth = 16, 1663 .num_links = 1, 1664 .links = { SA8775P_MASTER_GEM_NOC_PCIE_SNOC }, 1665 }; 1666 1667 static struct qcom_icc_node srvc_even_gemnoc = { 1668 .name = "srvc_even_gemnoc", 1669 .id = SA8775P_SLAVE_SERVICE_GEM_NOC_1, 1670 .channels = 1, 1671 .buswidth = 4, 1672 }; 1673 1674 static struct qcom_icc_node srvc_odd_gemnoc = { 1675 .name = "srvc_odd_gemnoc", 1676 .id = SA8775P_SLAVE_SERVICE_GEM_NOC_2, 1677 .channels = 1, 1678 .buswidth = 4, 1679 }; 1680 1681 static struct qcom_icc_node srvc_sys_gemnoc = { 1682 .name = "srvc_sys_gemnoc", 1683 .id = SA8775P_SLAVE_SERVICE_GEM_NOC, 1684 .channels = 1, 1685 .buswidth = 4, 1686 }; 1687 1688 static struct qcom_icc_node srvc_sys_gemnoc_2 = { 1689 .name = "srvc_sys_gemnoc_2", 1690 .id = SA8775P_SLAVE_SERVICE_GEM_NOC2, 1691 .channels = 1, 1692 .buswidth = 4, 1693 }; 1694 1695 static struct qcom_icc_node qns_gp_dsp_sail_noc = { 1696 .name = "qns_gp_dsp_sail_noc", 1697 .id = SA8775P_SLAVE_GP_DSP_SAIL_NOC, 1698 .channels = 1, 1699 .buswidth = 16, 1700 .num_links = 1, 1701 .links = { SA8775P_MASTER_GPDSP_SAIL }, 1702 }; 1703 1704 static struct qcom_icc_node qhs_lpass_core = { 1705 .name = "qhs_lpass_core", 1706 .id = SA8775P_SLAVE_LPASS_CORE_CFG, 1707 .channels = 1, 1708 .buswidth = 4, 1709 }; 1710 1711 static struct qcom_icc_node qhs_lpass_lpi = { 1712 .name = "qhs_lpass_lpi", 1713 .id = SA8775P_SLAVE_LPASS_LPI_CFG, 1714 .channels = 1, 1715 .buswidth = 4, 1716 }; 1717 1718 static struct qcom_icc_node qhs_lpass_mpu = { 1719 .name = "qhs_lpass_mpu", 1720 .id = SA8775P_SLAVE_LPASS_MPU_CFG, 1721 .channels = 1, 1722 .buswidth = 4, 1723 }; 1724 1725 static struct qcom_icc_node qhs_lpass_top = { 1726 .name = "qhs_lpass_top", 1727 .id = SA8775P_SLAVE_LPASS_TOP_CFG, 1728 .channels = 1, 1729 .buswidth = 4, 1730 }; 1731 1732 static struct qcom_icc_node qns_sysnoc = { 1733 .name = "qns_sysnoc", 1734 .id = SA8775P_SLAVE_LPASS_SNOC, 1735 .channels = 1, 1736 .buswidth = 16, 1737 .num_links = 1, 1738 .links = { SA8775P_MASTER_LPASS_ANOC }, 1739 }; 1740 1741 static struct qcom_icc_node srvc_niu_aml_noc = { 1742 .name = "srvc_niu_aml_noc", 1743 .id = SA8775P_SLAVE_SERVICES_LPASS_AML_NOC, 1744 .channels = 1, 1745 .buswidth = 4, 1746 }; 1747 1748 static struct qcom_icc_node srvc_niu_lpass_agnoc = { 1749 .name = "srvc_niu_lpass_agnoc", 1750 .id = SA8775P_SLAVE_SERVICE_LPASS_AG_NOC, 1751 .channels = 1, 1752 .buswidth = 4, 1753 }; 1754 1755 static struct qcom_icc_node ebi = { 1756 .name = "ebi", 1757 .id = SA8775P_SLAVE_EBI1, 1758 .channels = 8, 1759 .buswidth = 4, 1760 }; 1761 1762 static struct qcom_icc_node qns_mem_noc_hf = { 1763 .name = "qns_mem_noc_hf", 1764 .id = SA8775P_SLAVE_MNOC_HF_MEM_NOC, 1765 .channels = 2, 1766 .buswidth = 32, 1767 .num_links = 1, 1768 .links = { SA8775P_MASTER_MNOC_HF_MEM_NOC }, 1769 }; 1770 1771 static struct qcom_icc_node qns_mem_noc_sf = { 1772 .name = "qns_mem_noc_sf", 1773 .id = SA8775P_SLAVE_MNOC_SF_MEM_NOC, 1774 .channels = 2, 1775 .buswidth = 32, 1776 .num_links = 1, 1777 .links = { SA8775P_MASTER_MNOC_SF_MEM_NOC }, 1778 }; 1779 1780 static struct qcom_icc_node srvc_mnoc_hf = { 1781 .name = "srvc_mnoc_hf", 1782 .id = SA8775P_SLAVE_SERVICE_MNOC_HF, 1783 .channels = 1, 1784 .buswidth = 4, 1785 }; 1786 1787 static struct qcom_icc_node srvc_mnoc_sf = { 1788 .name = "srvc_mnoc_sf", 1789 .id = SA8775P_SLAVE_SERVICE_MNOC_SF, 1790 .channels = 1, 1791 .buswidth = 4, 1792 }; 1793 1794 static struct qcom_icc_node qns_hcp = { 1795 .name = "qns_hcp", 1796 .id = SA8775P_SLAVE_HCP_A, 1797 .channels = 2, 1798 .buswidth = 32, 1799 }; 1800 1801 static struct qcom_icc_node qns_nsp_gemnoc = { 1802 .name = "qns_nsp_gemnoc", 1803 .id = SA8775P_SLAVE_CDSP_MEM_NOC, 1804 .channels = 2, 1805 .buswidth = 32, 1806 .num_links = 1, 1807 .links = { SA8775P_MASTER_COMPUTE_NOC }, 1808 }; 1809 1810 static struct qcom_icc_node service_nsp_noc = { 1811 .name = "service_nsp_noc", 1812 .id = SA8775P_SLAVE_SERVICE_NSP_NOC, 1813 .channels = 1, 1814 .buswidth = 4, 1815 }; 1816 1817 static struct qcom_icc_node qns_nspb_gemnoc = { 1818 .name = "qns_nspb_gemnoc", 1819 .id = SA8775P_SLAVE_CDSPB_MEM_NOC, 1820 .channels = 2, 1821 .buswidth = 32, 1822 .num_links = 1, 1823 .links = { SA8775P_MASTER_COMPUTE_NOC_1 }, 1824 }; 1825 1826 static struct qcom_icc_node qns_nspb_hcp = { 1827 .name = "qns_nspb_hcp", 1828 .id = SA8775P_SLAVE_HCP_B, 1829 .channels = 2, 1830 .buswidth = 32, 1831 }; 1832 1833 static struct qcom_icc_node service_nspb_noc = { 1834 .name = "service_nspb_noc", 1835 .id = SA8775P_SLAVE_SERVICE_NSPB_NOC, 1836 .channels = 1, 1837 .buswidth = 4, 1838 }; 1839 1840 static struct qcom_icc_node qns_pcie_mem_noc = { 1841 .name = "qns_pcie_mem_noc", 1842 .id = SA8775P_SLAVE_ANOC_PCIE_GEM_NOC, 1843 .channels = 1, 1844 .buswidth = 32, 1845 .num_links = 1, 1846 .links = { SA8775P_MASTER_ANOC_PCIE_GEM_NOC }, 1847 }; 1848 1849 static struct qcom_icc_node qns_gemnoc_gc = { 1850 .name = "qns_gemnoc_gc", 1851 .id = SA8775P_SLAVE_SNOC_GEM_NOC_GC, 1852 .channels = 1, 1853 .buswidth = 8, 1854 .num_links = 1, 1855 .links = { SA8775P_MASTER_SNOC_GC_MEM_NOC }, 1856 }; 1857 1858 static struct qcom_icc_node qns_gemnoc_sf = { 1859 .name = "qns_gemnoc_sf", 1860 .id = SA8775P_SLAVE_SNOC_GEM_NOC_SF, 1861 .channels = 1, 1862 .buswidth = 16, 1863 .num_links = 1, 1864 .links = { SA8775P_MASTER_SNOC_SF_MEM_NOC }, 1865 }; 1866 1867 static struct qcom_icc_node srvc_snoc = { 1868 .name = "srvc_snoc", 1869 .id = SA8775P_SLAVE_SERVICE_SNOC, 1870 .channels = 1, 1871 .buswidth = 4, 1872 }; 1873 1874 static struct qcom_icc_bcm bcm_acv = { 1875 .name = "ACV", 1876 .num_nodes = 1, 1877 .nodes = { &ebi }, 1878 }; 1879 1880 static struct qcom_icc_bcm bcm_ce0 = { 1881 .name = "CE0", 1882 .num_nodes = 2, 1883 .nodes = { &qxm_crypto_0, &qxm_crypto_1 }, 1884 }; 1885 1886 static struct qcom_icc_bcm bcm_cn0 = { 1887 .name = "CN0", 1888 .keepalive = true, 1889 .num_nodes = 2, 1890 .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie }, 1891 }; 1892 1893 static struct qcom_icc_bcm bcm_cn1 = { 1894 .name = "CN1", 1895 .num_nodes = 76, 1896 .nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, 1897 &qhs_ahb2phy2, &qhs_ahb2phy3, 1898 &qhs_anoc_throttle_cfg, &qhs_aoss, 1899 &qhs_apss, &qhs_boot_rom, 1900 &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg, 1901 &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, 1902 &qhs_compute0_cfg, &qhs_compute1_cfg, 1903 &qhs_cpr_cx, &qhs_cpr_mmcx, 1904 &qhs_cpr_mx, &qhs_cpr_nspcx, 1905 &qhs_crypto0_cfg, &qhs_cx_rdpm, 1906 &qhs_display0_cfg, &qhs_display0_rt_throttle_cfg, 1907 &qhs_display1_cfg, &qhs_display1_rt_throttle_cfg, 1908 &qhs_emac0_cfg, &qhs_emac1_cfg, 1909 &qhs_gp_dsp0_cfg, &qhs_gp_dsp1_cfg, 1910 &qhs_gpdsp0_throttle_cfg, &qhs_gpdsp1_throttle_cfg, 1911 &qhs_gpu_tcu_throttle_cfg, &qhs_gpuss_cfg, 1912 &qhs_hwkm, &qhs_imem_cfg, 1913 &qhs_ipa, &qhs_ipc_router, 1914 &qhs_lpass_cfg, &qhs_lpass_throttle_cfg, 1915 &qhs_mx_rdpm, &qhs_mxc_rdpm, 1916 &qhs_pcie0_cfg, &qhs_pcie1_cfg, 1917 &qhs_pcie_rsc_cfg, &qhs_pcie_tcu_throttle_cfg, 1918 &qhs_pcie_throttle_cfg, &qhs_pdm, 1919 &qhs_pimem_cfg, &qhs_pke_wrapper_cfg, 1920 &qhs_qdss_cfg, &qhs_qm_cfg, 1921 &qhs_qm_mpu_cfg, &qhs_sail_throttle_cfg, 1922 &qhs_sdc1, &qhs_security, 1923 &qhs_snoc_throttle_cfg, &qhs_tcsr, 1924 &qhs_tlmm, &qhs_tsc_cfg, 1925 &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, 1926 &qhs_usb2_0, &qhs_usb3_0, 1927 &qhs_usb3_1, &qhs_venus_cfg, 1928 &qhs_venus_cvp_throttle_cfg, &qhs_venus_v_cpu_throttle_cfg, 1929 &qhs_venus_vcodec_throttle_cfg, &qns_ddrss_cfg, 1930 &qns_gpdsp_noc_cfg, &qns_mnoc_hf_cfg, 1931 &qns_mnoc_sf_cfg, &qns_pcie_anoc_cfg, 1932 &qns_snoc_cfg, &qxs_boot_imem, 1933 &qxs_imem, &xs_sys_tcu_cfg }, 1934 }; 1935 1936 static struct qcom_icc_bcm bcm_cn2 = { 1937 .name = "CN2", 1938 .num_nodes = 4, 1939 .nodes = { &qhs_qup0, &qhs_qup1, 1940 &qhs_qup2, &qhs_qup3 }, 1941 }; 1942 1943 static struct qcom_icc_bcm bcm_cn3 = { 1944 .name = "CN3", 1945 .num_nodes = 2, 1946 .nodes = { &xs_pcie_0, &xs_pcie_1 }, 1947 }; 1948 1949 static struct qcom_icc_bcm bcm_gna0 = { 1950 .name = "GNA0", 1951 .num_nodes = 1, 1952 .nodes = { &qxm_dsp0 }, 1953 }; 1954 1955 static struct qcom_icc_bcm bcm_gnb0 = { 1956 .name = "GNB0", 1957 .num_nodes = 1, 1958 .nodes = { &qxm_dsp1 }, 1959 }; 1960 1961 static struct qcom_icc_bcm bcm_mc0 = { 1962 .name = "MC0", 1963 .keepalive = true, 1964 .num_nodes = 1, 1965 .nodes = { &ebi }, 1966 }; 1967 1968 static struct qcom_icc_bcm bcm_mm0 = { 1969 .name = "MM0", 1970 .keepalive = true, 1971 .num_nodes = 5, 1972 .nodes = { &qnm_camnoc_hf, &qnm_mdp0_0, 1973 &qnm_mdp0_1, &qnm_mdp1_0, 1974 &qns_mem_noc_hf }, 1975 }; 1976 1977 static struct qcom_icc_bcm bcm_mm1 = { 1978 .name = "MM1", 1979 .num_nodes = 7, 1980 .nodes = { &qnm_camnoc_icp, &qnm_camnoc_sf, 1981 &qnm_video0, &qnm_video1, 1982 &qnm_video_cvp, &qnm_video_v_cpu, 1983 &qns_mem_noc_sf }, 1984 }; 1985 1986 static struct qcom_icc_bcm bcm_nsa0 = { 1987 .name = "NSA0", 1988 .num_nodes = 2, 1989 .nodes = { &qns_hcp, &qns_nsp_gemnoc }, 1990 }; 1991 1992 static struct qcom_icc_bcm bcm_nsa1 = { 1993 .name = "NSA1", 1994 .num_nodes = 1, 1995 .nodes = { &qxm_nsp }, 1996 }; 1997 1998 static struct qcom_icc_bcm bcm_nsb0 = { 1999 .name = "NSB0", 2000 .num_nodes = 2, 2001 .nodes = { &qns_nspb_gemnoc, &qns_nspb_hcp }, 2002 }; 2003 2004 static struct qcom_icc_bcm bcm_nsb1 = { 2005 .name = "NSB1", 2006 .num_nodes = 1, 2007 .nodes = { &qxm_nspb }, 2008 }; 2009 2010 static struct qcom_icc_bcm bcm_pci0 = { 2011 .name = "PCI0", 2012 .num_nodes = 1, 2013 .nodes = { &qns_pcie_mem_noc }, 2014 }; 2015 2016 static struct qcom_icc_bcm bcm_qup0 = { 2017 .name = "QUP0", 2018 .vote_scale = 1, 2019 .num_nodes = 1, 2020 .nodes = { &qup0_core_slave }, 2021 }; 2022 2023 static struct qcom_icc_bcm bcm_qup1 = { 2024 .name = "QUP1", 2025 .vote_scale = 1, 2026 .num_nodes = 1, 2027 .nodes = { &qup1_core_slave }, 2028 }; 2029 2030 static struct qcom_icc_bcm bcm_qup2 = { 2031 .name = "QUP2", 2032 .vote_scale = 1, 2033 .num_nodes = 2, 2034 .nodes = { &qup2_core_slave, &qup3_core_slave }, 2035 }; 2036 2037 static struct qcom_icc_bcm bcm_sh0 = { 2038 .name = "SH0", 2039 .keepalive = true, 2040 .num_nodes = 1, 2041 .nodes = { &qns_llcc }, 2042 }; 2043 2044 static struct qcom_icc_bcm bcm_sh2 = { 2045 .name = "SH2", 2046 .num_nodes = 1, 2047 .nodes = { &chm_apps }, 2048 }; 2049 2050 static struct qcom_icc_bcm bcm_sn0 = { 2051 .name = "SN0", 2052 .keepalive = true, 2053 .num_nodes = 1, 2054 .nodes = { &qns_gemnoc_sf }, 2055 }; 2056 2057 static struct qcom_icc_bcm bcm_sn1 = { 2058 .name = "SN1", 2059 .num_nodes = 1, 2060 .nodes = { &qns_gemnoc_gc }, 2061 }; 2062 2063 static struct qcom_icc_bcm bcm_sn2 = { 2064 .name = "SN2", 2065 .num_nodes = 1, 2066 .nodes = { &qxs_pimem }, 2067 }; 2068 2069 static struct qcom_icc_bcm bcm_sn3 = { 2070 .name = "SN3", 2071 .num_nodes = 2, 2072 .nodes = { &qns_a1noc_snoc, &qnm_aggre1_noc }, 2073 }; 2074 2075 static struct qcom_icc_bcm bcm_sn4 = { 2076 .name = "SN4", 2077 .num_nodes = 2, 2078 .nodes = { &qns_a2noc_snoc, &qnm_aggre2_noc }, 2079 }; 2080 2081 static struct qcom_icc_bcm bcm_sn9 = { 2082 .name = "SN9", 2083 .num_nodes = 2, 2084 .nodes = { &qns_sysnoc, &qnm_lpass_noc }, 2085 }; 2086 2087 static struct qcom_icc_bcm bcm_sn10 = { 2088 .name = "SN10", 2089 .num_nodes = 1, 2090 .nodes = { &xs_qdss_stm }, 2091 }; 2092 2093 static struct qcom_icc_bcm *aggre1_noc_bcms[] = { 2094 &bcm_sn3, 2095 }; 2096 2097 static struct qcom_icc_node *aggre1_noc_nodes[] = { 2098 [MASTER_QUP_3] = &qxm_qup3, 2099 [MASTER_EMAC] = &xm_emac_0, 2100 [MASTER_EMAC_1] = &xm_emac_1, 2101 [MASTER_SDC] = &xm_sdc1, 2102 [MASTER_UFS_MEM] = &xm_ufs_mem, 2103 [MASTER_USB2] = &xm_usb2_2, 2104 [MASTER_USB3_0] = &xm_usb3_0, 2105 [MASTER_USB3_1] = &xm_usb3_1, 2106 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, 2107 }; 2108 2109 static const struct qcom_icc_desc sa8775p_aggre1_noc = { 2110 .nodes = aggre1_noc_nodes, 2111 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 2112 .bcms = aggre1_noc_bcms, 2113 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 2114 }; 2115 2116 static struct qcom_icc_bcm *aggre2_noc_bcms[] = { 2117 &bcm_ce0, 2118 &bcm_sn4, 2119 }; 2120 2121 static struct qcom_icc_node *aggre2_noc_nodes[] = { 2122 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 2123 [MASTER_QUP_0] = &qhm_qup0, 2124 [MASTER_QUP_1] = &qhm_qup1, 2125 [MASTER_QUP_2] = &qhm_qup2, 2126 [MASTER_CNOC_A2NOC] = &qnm_cnoc_datapath, 2127 [MASTER_CRYPTO_CORE0] = &qxm_crypto_0, 2128 [MASTER_CRYPTO_CORE1] = &qxm_crypto_1, 2129 [MASTER_IPA] = &qxm_ipa, 2130 [MASTER_QDSS_ETR_0] = &xm_qdss_etr_0, 2131 [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1, 2132 [MASTER_UFS_CARD] = &xm_ufs_card, 2133 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, 2134 }; 2135 2136 static const struct qcom_icc_desc sa8775p_aggre2_noc = { 2137 .nodes = aggre2_noc_nodes, 2138 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 2139 .bcms = aggre2_noc_bcms, 2140 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 2141 }; 2142 2143 static struct qcom_icc_bcm *clk_virt_bcms[] = { 2144 &bcm_qup0, 2145 &bcm_qup1, 2146 &bcm_qup2, 2147 }; 2148 2149 static struct qcom_icc_node *clk_virt_nodes[] = { 2150 [MASTER_QUP_CORE_0] = &qup0_core_master, 2151 [MASTER_QUP_CORE_1] = &qup1_core_master, 2152 [MASTER_QUP_CORE_2] = &qup2_core_master, 2153 [MASTER_QUP_CORE_3] = &qup3_core_master, 2154 [SLAVE_QUP_CORE_0] = &qup0_core_slave, 2155 [SLAVE_QUP_CORE_1] = &qup1_core_slave, 2156 [SLAVE_QUP_CORE_2] = &qup2_core_slave, 2157 [SLAVE_QUP_CORE_3] = &qup3_core_slave, 2158 }; 2159 2160 static const struct qcom_icc_desc sa8775p_clk_virt = { 2161 .nodes = clk_virt_nodes, 2162 .num_nodes = ARRAY_SIZE(clk_virt_nodes), 2163 .bcms = clk_virt_bcms, 2164 .num_bcms = ARRAY_SIZE(clk_virt_bcms), 2165 }; 2166 2167 static struct qcom_icc_bcm *config_noc_bcms[] = { 2168 &bcm_cn0, 2169 &bcm_cn1, 2170 &bcm_cn2, 2171 &bcm_cn3, 2172 &bcm_sn2, 2173 &bcm_sn10, 2174 }; 2175 2176 static struct qcom_icc_node *config_noc_nodes[] = { 2177 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, 2178 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, 2179 [SLAVE_AHB2PHY_0] = &qhs_ahb2phy0, 2180 [SLAVE_AHB2PHY_1] = &qhs_ahb2phy1, 2181 [SLAVE_AHB2PHY_2] = &qhs_ahb2phy2, 2182 [SLAVE_AHB2PHY_3] = &qhs_ahb2phy3, 2183 [SLAVE_ANOC_THROTTLE_CFG] = &qhs_anoc_throttle_cfg, 2184 [SLAVE_AOSS] = &qhs_aoss, 2185 [SLAVE_APPSS] = &qhs_apss, 2186 [SLAVE_BOOT_ROM] = &qhs_boot_rom, 2187 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 2188 [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_throttle_cfg, 2189 [SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg, 2190 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 2191 [SLAVE_CDSP_CFG] = &qhs_compute0_cfg, 2192 [SLAVE_CDSP1_CFG] = &qhs_compute1_cfg, 2193 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 2194 [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx, 2195 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, 2196 [SLAVE_CPR_NSPCX] = &qhs_cpr_nspcx, 2197 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 2198 [SLAVE_CX_RDPM] = &qhs_cx_rdpm, 2199 [SLAVE_DISPLAY_CFG] = &qhs_display0_cfg, 2200 [SLAVE_DISPLAY_RT_THROTTLE_CFG] = &qhs_display0_rt_throttle_cfg, 2201 [SLAVE_DISPLAY1_CFG] = &qhs_display1_cfg, 2202 [SLAVE_DISPLAY1_RT_THROTTLE_CFG] = &qhs_display1_rt_throttle_cfg, 2203 [SLAVE_EMAC_CFG] = &qhs_emac0_cfg, 2204 [SLAVE_EMAC1_CFG] = &qhs_emac1_cfg, 2205 [SLAVE_GP_DSP0_CFG] = &qhs_gp_dsp0_cfg, 2206 [SLAVE_GP_DSP1_CFG] = &qhs_gp_dsp1_cfg, 2207 [SLAVE_GPDSP0_THROTTLE_CFG] = &qhs_gpdsp0_throttle_cfg, 2208 [SLAVE_GPDSP1_THROTTLE_CFG] = &qhs_gpdsp1_throttle_cfg, 2209 [SLAVE_GPU_TCU_THROTTLE_CFG] = &qhs_gpu_tcu_throttle_cfg, 2210 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, 2211 [SLAVE_HWKM] = &qhs_hwkm, 2212 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 2213 [SLAVE_IPA_CFG] = &qhs_ipa, 2214 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, 2215 [SLAVE_LPASS] = &qhs_lpass_cfg, 2216 [SLAVE_LPASS_THROTTLE_CFG] = &qhs_lpass_throttle_cfg, 2217 [SLAVE_MX_RDPM] = &qhs_mx_rdpm, 2218 [SLAVE_MXC_RDPM] = &qhs_mxc_rdpm, 2219 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, 2220 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, 2221 [SLAVE_PCIE_RSC_CFG] = &qhs_pcie_rsc_cfg, 2222 [SLAVE_PCIE_TCU_THROTTLE_CFG] = &qhs_pcie_tcu_throttle_cfg, 2223 [SLAVE_PCIE_THROTTLE_CFG] = &qhs_pcie_throttle_cfg, 2224 [SLAVE_PDM] = &qhs_pdm, 2225 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 2226 [SLAVE_PKA_WRAPPER_CFG] = &qhs_pke_wrapper_cfg, 2227 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 2228 [SLAVE_QM_CFG] = &qhs_qm_cfg, 2229 [SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg, 2230 [SLAVE_QUP_0] = &qhs_qup0, 2231 [SLAVE_QUP_1] = &qhs_qup1, 2232 [SLAVE_QUP_2] = &qhs_qup2, 2233 [SLAVE_QUP_3] = &qhs_qup3, 2234 [SLAVE_SAIL_THROTTLE_CFG] = &qhs_sail_throttle_cfg, 2235 [SLAVE_SDC1] = &qhs_sdc1, 2236 [SLAVE_SECURITY] = &qhs_security, 2237 [SLAVE_SNOC_THROTTLE_CFG] = &qhs_snoc_throttle_cfg, 2238 [SLAVE_TCSR] = &qhs_tcsr, 2239 [SLAVE_TLMM] = &qhs_tlmm, 2240 [SLAVE_TSC_CFG] = &qhs_tsc_cfg, 2241 [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg, 2242 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 2243 [SLAVE_USB2] = &qhs_usb2_0, 2244 [SLAVE_USB3_0] = &qhs_usb3_0, 2245 [SLAVE_USB3_1] = &qhs_usb3_1, 2246 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 2247 [SLAVE_VENUS_CVP_THROTTLE_CFG] = &qhs_venus_cvp_throttle_cfg, 2248 [SLAVE_VENUS_V_CPU_THROTTLE_CFG] = &qhs_venus_v_cpu_throttle_cfg, 2249 [SLAVE_VENUS_VCODEC_THROTTLE_CFG] = &qhs_venus_vcodec_throttle_cfg, 2250 [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg, 2251 [SLAVE_GPDSP_NOC_CFG] = &qns_gpdsp_noc_cfg, 2252 [SLAVE_CNOC_MNOC_HF_CFG] = &qns_mnoc_hf_cfg, 2253 [SLAVE_CNOC_MNOC_SF_CFG] = &qns_mnoc_sf_cfg, 2254 [SLAVE_PCIE_ANOC_CFG] = &qns_pcie_anoc_cfg, 2255 [SLAVE_SNOC_CFG] = &qns_snoc_cfg, 2256 [SLAVE_BOOT_IMEM] = &qxs_boot_imem, 2257 [SLAVE_IMEM] = &qxs_imem, 2258 [SLAVE_PIMEM] = &qxs_pimem, 2259 [SLAVE_PCIE_0] = &xs_pcie_0, 2260 [SLAVE_PCIE_1] = &xs_pcie_1, 2261 [SLAVE_QDSS_STM] = &xs_qdss_stm, 2262 [SLAVE_TCU] = &xs_sys_tcu_cfg, 2263 }; 2264 2265 static const struct qcom_icc_desc sa8775p_config_noc = { 2266 .nodes = config_noc_nodes, 2267 .num_nodes = ARRAY_SIZE(config_noc_nodes), 2268 .bcms = config_noc_bcms, 2269 .num_bcms = ARRAY_SIZE(config_noc_bcms), 2270 }; 2271 2272 static struct qcom_icc_bcm *dc_noc_bcms[] = { 2273 }; 2274 2275 static struct qcom_icc_node *dc_noc_nodes[] = { 2276 [MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc, 2277 [SLAVE_LLCC_CFG] = &qhs_llcc, 2278 [SLAVE_GEM_NOC_CFG] = &qns_gemnoc, 2279 }; 2280 2281 static const struct qcom_icc_desc sa8775p_dc_noc = { 2282 .nodes = dc_noc_nodes, 2283 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 2284 .bcms = dc_noc_bcms, 2285 .num_bcms = ARRAY_SIZE(dc_noc_bcms), 2286 }; 2287 2288 static struct qcom_icc_bcm *gem_noc_bcms[] = { 2289 &bcm_sh0, 2290 &bcm_sh2, 2291 }; 2292 2293 static struct qcom_icc_node *gem_noc_nodes[] = { 2294 [MASTER_GPU_TCU] = &alm_gpu_tcu, 2295 [MASTER_PCIE_TCU] = &alm_pcie_tcu, 2296 [MASTER_SYS_TCU] = &alm_sys_tcu, 2297 [MASTER_APPSS_PROC] = &chm_apps, 2298 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc0, 2299 [MASTER_COMPUTE_NOC_1] = &qnm_cmpnoc1, 2300 [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg, 2301 [MASTER_GPDSP_SAIL] = &qnm_gpdsp_sail, 2302 [MASTER_GFX3D] = &qnm_gpu, 2303 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 2304 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 2305 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, 2306 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 2307 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 2308 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, 2309 [SLAVE_LLCC] = &qns_llcc, 2310 [SLAVE_GEM_NOC_PCIE_CNOC] = &qns_pcie, 2311 [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc, 2312 [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc, 2313 [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc, 2314 [SLAVE_SERVICE_GEM_NOC2] = &srvc_sys_gemnoc_2, 2315 }; 2316 2317 static const struct qcom_icc_desc sa8775p_gem_noc = { 2318 .nodes = gem_noc_nodes, 2319 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 2320 .bcms = gem_noc_bcms, 2321 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 2322 }; 2323 2324 static struct qcom_icc_bcm *gpdsp_anoc_bcms[] = { 2325 &bcm_gna0, 2326 &bcm_gnb0, 2327 }; 2328 2329 static struct qcom_icc_node *gpdsp_anoc_nodes[] = { 2330 [MASTER_DSP0] = &qxm_dsp0, 2331 [MASTER_DSP1] = &qxm_dsp1, 2332 [SLAVE_GP_DSP_SAIL_NOC] = &qns_gp_dsp_sail_noc, 2333 }; 2334 2335 static const struct qcom_icc_desc sa8775p_gpdsp_anoc = { 2336 .nodes = gpdsp_anoc_nodes, 2337 .num_nodes = ARRAY_SIZE(gpdsp_anoc_nodes), 2338 .bcms = gpdsp_anoc_bcms, 2339 .num_bcms = ARRAY_SIZE(gpdsp_anoc_bcms), 2340 }; 2341 2342 static struct qcom_icc_bcm *lpass_ag_noc_bcms[] = { 2343 &bcm_sn9, 2344 }; 2345 2346 static struct qcom_icc_node *lpass_ag_noc_nodes[] = { 2347 [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc, 2348 [MASTER_LPASS_PROC] = &qxm_lpass_dsp, 2349 [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core, 2350 [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi, 2351 [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu, 2352 [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top, 2353 [SLAVE_LPASS_SNOC] = &qns_sysnoc, 2354 [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc, 2355 [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, 2356 }; 2357 2358 static const struct qcom_icc_desc sa8775p_lpass_ag_noc = { 2359 .nodes = lpass_ag_noc_nodes, 2360 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), 2361 .bcms = lpass_ag_noc_bcms, 2362 .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms), 2363 }; 2364 2365 static struct qcom_icc_bcm *mc_virt_bcms[] = { 2366 &bcm_acv, 2367 &bcm_mc0, 2368 }; 2369 2370 static struct qcom_icc_node *mc_virt_nodes[] = { 2371 [MASTER_LLCC] = &llcc_mc, 2372 [SLAVE_EBI1] = &ebi, 2373 }; 2374 2375 static const struct qcom_icc_desc sa8775p_mc_virt = { 2376 .nodes = mc_virt_nodes, 2377 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 2378 .bcms = mc_virt_bcms, 2379 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 2380 }; 2381 2382 static struct qcom_icc_bcm *mmss_noc_bcms[] = { 2383 &bcm_mm0, 2384 &bcm_mm1, 2385 }; 2386 2387 static struct qcom_icc_node *mmss_noc_nodes[] = { 2388 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, 2389 [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp, 2390 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, 2391 [MASTER_MDP0] = &qnm_mdp0_0, 2392 [MASTER_MDP1] = &qnm_mdp0_1, 2393 [MASTER_MDP_CORE1_0] = &qnm_mdp1_0, 2394 [MASTER_MDP_CORE1_1] = &qnm_mdp1_1, 2395 [MASTER_CNOC_MNOC_HF_CFG] = &qnm_mnoc_hf_cfg, 2396 [MASTER_CNOC_MNOC_SF_CFG] = &qnm_mnoc_sf_cfg, 2397 [MASTER_VIDEO_P0] = &qnm_video0, 2398 [MASTER_VIDEO_P1] = &qnm_video1, 2399 [MASTER_VIDEO_PROC] = &qnm_video_cvp, 2400 [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu, 2401 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 2402 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, 2403 [SLAVE_SERVICE_MNOC_HF] = &srvc_mnoc_hf, 2404 [SLAVE_SERVICE_MNOC_SF] = &srvc_mnoc_sf, 2405 }; 2406 2407 static const struct qcom_icc_desc sa8775p_mmss_noc = { 2408 .nodes = mmss_noc_nodes, 2409 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 2410 .bcms = mmss_noc_bcms, 2411 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 2412 }; 2413 2414 static struct qcom_icc_bcm *nspa_noc_bcms[] = { 2415 &bcm_nsa0, 2416 &bcm_nsa1, 2417 }; 2418 2419 static struct qcom_icc_node *nspa_noc_nodes[] = { 2420 [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config, 2421 [MASTER_CDSP_PROC] = &qxm_nsp, 2422 [SLAVE_HCP_A] = &qns_hcp, 2423 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, 2424 [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, 2425 }; 2426 2427 static const struct qcom_icc_desc sa8775p_nspa_noc = { 2428 .nodes = nspa_noc_nodes, 2429 .num_nodes = ARRAY_SIZE(nspa_noc_nodes), 2430 .bcms = nspa_noc_bcms, 2431 .num_bcms = ARRAY_SIZE(nspa_noc_bcms), 2432 }; 2433 2434 static struct qcom_icc_bcm *nspb_noc_bcms[] = { 2435 &bcm_nsb0, 2436 &bcm_nsb1, 2437 }; 2438 2439 static struct qcom_icc_node *nspb_noc_nodes[] = { 2440 [MASTER_CDSPB_NOC_CFG] = &qhm_nspb_noc_config, 2441 [MASTER_CDSP_PROC_B] = &qxm_nspb, 2442 [SLAVE_CDSPB_MEM_NOC] = &qns_nspb_gemnoc, 2443 [SLAVE_HCP_B] = &qns_nspb_hcp, 2444 [SLAVE_SERVICE_NSPB_NOC] = &service_nspb_noc, 2445 }; 2446 2447 static const struct qcom_icc_desc sa8775p_nspb_noc = { 2448 .nodes = nspb_noc_nodes, 2449 .num_nodes = ARRAY_SIZE(nspb_noc_nodes), 2450 .bcms = nspb_noc_bcms, 2451 .num_bcms = ARRAY_SIZE(nspb_noc_bcms), 2452 }; 2453 2454 static struct qcom_icc_bcm *pcie_anoc_bcms[] = { 2455 &bcm_pci0, 2456 }; 2457 2458 static struct qcom_icc_node *pcie_anoc_nodes[] = { 2459 [MASTER_PCIE_0] = &xm_pcie3_0, 2460 [MASTER_PCIE_1] = &xm_pcie3_1, 2461 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, 2462 }; 2463 2464 static const struct qcom_icc_desc sa8775p_pcie_anoc = { 2465 .nodes = pcie_anoc_nodes, 2466 .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), 2467 .bcms = pcie_anoc_bcms, 2468 .num_bcms = ARRAY_SIZE(pcie_anoc_bcms), 2469 }; 2470 2471 static struct qcom_icc_bcm *system_noc_bcms[] = { 2472 &bcm_sn0, 2473 &bcm_sn1, 2474 &bcm_sn3, 2475 &bcm_sn4, 2476 &bcm_sn9, 2477 }; 2478 2479 static struct qcom_icc_node *system_noc_nodes[] = { 2480 [MASTER_GIC_AHB] = &qhm_gic, 2481 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, 2482 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, 2483 [MASTER_LPASS_ANOC] = &qnm_lpass_noc, 2484 [MASTER_SNOC_CFG] = &qnm_snoc_cfg, 2485 [MASTER_PIMEM] = &qxm_pimem, 2486 [MASTER_GIC] = &xm_gic, 2487 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, 2488 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 2489 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 2490 }; 2491 2492 static const struct qcom_icc_desc sa8775p_system_noc = { 2493 .nodes = system_noc_nodes, 2494 .num_nodes = ARRAY_SIZE(system_noc_nodes), 2495 .bcms = system_noc_bcms, 2496 .num_bcms = ARRAY_SIZE(system_noc_bcms), 2497 }; 2498 2499 static const struct of_device_id qnoc_of_match[] = { 2500 { .compatible = "qcom,sa8775p-aggre1-noc", .data = &sa8775p_aggre1_noc, }, 2501 { .compatible = "qcom,sa8775p-aggre2-noc", .data = &sa8775p_aggre2_noc, }, 2502 { .compatible = "qcom,sa8775p-clk-virt", .data = &sa8775p_clk_virt, }, 2503 { .compatible = "qcom,sa8775p-config-noc", .data = &sa8775p_config_noc, }, 2504 { .compatible = "qcom,sa8775p-dc-noc", .data = &sa8775p_dc_noc, }, 2505 { .compatible = "qcom,sa8775p-gem-noc", .data = &sa8775p_gem_noc, }, 2506 { .compatible = "qcom,sa8775p-gpdsp-anoc", .data = &sa8775p_gpdsp_anoc, }, 2507 { .compatible = "qcom,sa8775p-lpass-ag-noc", .data = &sa8775p_lpass_ag_noc, }, 2508 { .compatible = "qcom,sa8775p-mc-virt", .data = &sa8775p_mc_virt, }, 2509 { .compatible = "qcom,sa8775p-mmss-noc", .data = &sa8775p_mmss_noc, }, 2510 { .compatible = "qcom,sa8775p-nspa-noc", .data = &sa8775p_nspa_noc, }, 2511 { .compatible = "qcom,sa8775p-nspb-noc", .data = &sa8775p_nspb_noc, }, 2512 { .compatible = "qcom,sa8775p-pcie-anoc", .data = &sa8775p_pcie_anoc, }, 2513 { .compatible = "qcom,sa8775p-system-noc", .data = &sa8775p_system_noc, }, 2514 { } 2515 }; 2516 MODULE_DEVICE_TABLE(of, qnoc_of_match); 2517 2518 static struct platform_driver qnoc_driver = { 2519 .probe = qcom_icc_rpmh_probe, 2520 .remove = qcom_icc_rpmh_remove, 2521 .driver = { 2522 .name = "qnoc-sa8775p", 2523 .of_match_table = qnoc_of_match, 2524 .sync_state = icc_sync_state, 2525 }, 2526 }; 2527 2528 static int __init qnoc_driver_init(void) 2529 { 2530 return platform_driver_register(&qnoc_driver); 2531 } 2532 core_initcall(qnoc_driver_init); 2533 2534 static void __exit qnoc_driver_exit(void) 2535 { 2536 platform_driver_unregister(&qnoc_driver); 2537 } 2538 module_exit(qnoc_driver_exit); 2539 2540 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. SA8775P NoC driver"); 2541 MODULE_LICENSE("GPL"); 2542