1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2023, Linaro Limited 5 */ 6 7 #include <linux/device.h> 8 #include <linux/interconnect.h> 9 #include <linux/interconnect-provider.h> 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> 13 14 #include "bcm-voter.h" 15 #include "icc-rpmh.h" 16 17 static struct qcom_icc_node qxm_qup3; 18 static struct qcom_icc_node xm_emac_0; 19 static struct qcom_icc_node xm_emac_1; 20 static struct qcom_icc_node xm_sdc1; 21 static struct qcom_icc_node xm_ufs_mem; 22 static struct qcom_icc_node xm_usb2_2; 23 static struct qcom_icc_node xm_usb3_0; 24 static struct qcom_icc_node xm_usb3_1; 25 static struct qcom_icc_node qns_a1noc_snoc; 26 static struct qcom_icc_node qhm_qdss_bam; 27 static struct qcom_icc_node qhm_qup0; 28 static struct qcom_icc_node qhm_qup1; 29 static struct qcom_icc_node qhm_qup2; 30 static struct qcom_icc_node qnm_cnoc_datapath; 31 static struct qcom_icc_node qxm_crypto_0; 32 static struct qcom_icc_node qxm_crypto_1; 33 static struct qcom_icc_node qxm_ipa; 34 static struct qcom_icc_node xm_qdss_etr_0; 35 static struct qcom_icc_node xm_qdss_etr_1; 36 static struct qcom_icc_node xm_ufs_card; 37 static struct qcom_icc_node qns_a2noc_snoc; 38 static struct qcom_icc_node qup0_core_master; 39 static struct qcom_icc_node qup1_core_master; 40 static struct qcom_icc_node qup2_core_master; 41 static struct qcom_icc_node qup3_core_master; 42 static struct qcom_icc_node qup0_core_slave; 43 static struct qcom_icc_node qup1_core_slave; 44 static struct qcom_icc_node qup2_core_slave; 45 static struct qcom_icc_node qup3_core_slave; 46 static struct qcom_icc_node qnm_gemnoc_cnoc; 47 static struct qcom_icc_node qnm_gemnoc_pcie; 48 static struct qcom_icc_node qhs_ahb2phy0; 49 static struct qcom_icc_node qhs_ahb2phy1; 50 static struct qcom_icc_node qhs_ahb2phy2; 51 static struct qcom_icc_node qhs_ahb2phy3; 52 static struct qcom_icc_node qhs_anoc_throttle_cfg; 53 static struct qcom_icc_node qhs_aoss; 54 static struct qcom_icc_node qhs_apss; 55 static struct qcom_icc_node qhs_boot_rom; 56 static struct qcom_icc_node qhs_camera_cfg; 57 static struct qcom_icc_node qhs_camera_nrt_throttle_cfg; 58 static struct qcom_icc_node qhs_camera_rt_throttle_cfg; 59 static struct qcom_icc_node qhs_clk_ctl; 60 static struct qcom_icc_node qhs_compute0_cfg; 61 static struct qcom_icc_node qhs_compute1_cfg; 62 static struct qcom_icc_node qhs_cpr_cx; 63 static struct qcom_icc_node qhs_cpr_mmcx; 64 static struct qcom_icc_node qhs_cpr_mx; 65 static struct qcom_icc_node qhs_cpr_nspcx; 66 static struct qcom_icc_node qhs_crypto0_cfg; 67 static struct qcom_icc_node qhs_cx_rdpm; 68 static struct qcom_icc_node qhs_display0_cfg; 69 static struct qcom_icc_node qhs_display0_rt_throttle_cfg; 70 static struct qcom_icc_node qhs_display1_cfg; 71 static struct qcom_icc_node qhs_display1_rt_throttle_cfg; 72 static struct qcom_icc_node qhs_emac0_cfg; 73 static struct qcom_icc_node qhs_emac1_cfg; 74 static struct qcom_icc_node qhs_gp_dsp0_cfg; 75 static struct qcom_icc_node qhs_gp_dsp1_cfg; 76 static struct qcom_icc_node qhs_gpdsp0_throttle_cfg; 77 static struct qcom_icc_node qhs_gpdsp1_throttle_cfg; 78 static struct qcom_icc_node qhs_gpu_tcu_throttle_cfg; 79 static struct qcom_icc_node qhs_gpuss_cfg; 80 static struct qcom_icc_node qhs_hwkm; 81 static struct qcom_icc_node qhs_imem_cfg; 82 static struct qcom_icc_node qhs_ipa; 83 static struct qcom_icc_node qhs_ipc_router; 84 static struct qcom_icc_node qhs_lpass_cfg; 85 static struct qcom_icc_node qhs_lpass_throttle_cfg; 86 static struct qcom_icc_node qhs_mx_rdpm; 87 static struct qcom_icc_node qhs_mxc_rdpm; 88 static struct qcom_icc_node qhs_pcie0_cfg; 89 static struct qcom_icc_node qhs_pcie1_cfg; 90 static struct qcom_icc_node qhs_pcie_rsc_cfg; 91 static struct qcom_icc_node qhs_pcie_tcu_throttle_cfg; 92 static struct qcom_icc_node qhs_pcie_throttle_cfg; 93 static struct qcom_icc_node qhs_pdm; 94 static struct qcom_icc_node qhs_pimem_cfg; 95 static struct qcom_icc_node qhs_pke_wrapper_cfg; 96 static struct qcom_icc_node qhs_qdss_cfg; 97 static struct qcom_icc_node qhs_qm_cfg; 98 static struct qcom_icc_node qhs_qm_mpu_cfg; 99 static struct qcom_icc_node qhs_qup0; 100 static struct qcom_icc_node qhs_qup1; 101 static struct qcom_icc_node qhs_qup2; 102 static struct qcom_icc_node qhs_qup3; 103 static struct qcom_icc_node qhs_sail_throttle_cfg; 104 static struct qcom_icc_node qhs_sdc1; 105 static struct qcom_icc_node qhs_security; 106 static struct qcom_icc_node qhs_snoc_throttle_cfg; 107 static struct qcom_icc_node qhs_tcsr; 108 static struct qcom_icc_node qhs_tlmm; 109 static struct qcom_icc_node qhs_tsc_cfg; 110 static struct qcom_icc_node qhs_ufs_card_cfg; 111 static struct qcom_icc_node qhs_ufs_mem_cfg; 112 static struct qcom_icc_node qhs_usb2_0; 113 static struct qcom_icc_node qhs_usb3_0; 114 static struct qcom_icc_node qhs_usb3_1; 115 static struct qcom_icc_node qhs_venus_cfg; 116 static struct qcom_icc_node qhs_venus_cvp_throttle_cfg; 117 static struct qcom_icc_node qhs_venus_v_cpu_throttle_cfg; 118 static struct qcom_icc_node qhs_venus_vcodec_throttle_cfg; 119 static struct qcom_icc_node qns_ddrss_cfg; 120 static struct qcom_icc_node qns_gpdsp_noc_cfg; 121 static struct qcom_icc_node qns_mnoc_hf_cfg; 122 static struct qcom_icc_node qns_mnoc_sf_cfg; 123 static struct qcom_icc_node qns_pcie_anoc_cfg; 124 static struct qcom_icc_node qns_snoc_cfg; 125 static struct qcom_icc_node qxs_boot_imem; 126 static struct qcom_icc_node qxs_imem; 127 static struct qcom_icc_node qxs_pimem; 128 static struct qcom_icc_node xs_pcie_0; 129 static struct qcom_icc_node xs_pcie_1; 130 static struct qcom_icc_node xs_qdss_stm; 131 static struct qcom_icc_node xs_sys_tcu_cfg; 132 static struct qcom_icc_node qnm_cnoc_dc_noc; 133 static struct qcom_icc_node qhs_llcc; 134 static struct qcom_icc_node qns_gemnoc; 135 static struct qcom_icc_node alm_gpu_tcu; 136 static struct qcom_icc_node alm_pcie_tcu; 137 static struct qcom_icc_node alm_sys_tcu; 138 static struct qcom_icc_node chm_apps; 139 static struct qcom_icc_node qnm_cmpnoc0; 140 static struct qcom_icc_node qnm_cmpnoc1; 141 static struct qcom_icc_node qnm_gemnoc_cfg; 142 static struct qcom_icc_node qnm_gpdsp_sail; 143 static struct qcom_icc_node qnm_gpu; 144 static struct qcom_icc_node qnm_mnoc_hf; 145 static struct qcom_icc_node qnm_mnoc_sf; 146 static struct qcom_icc_node qnm_pcie; 147 static struct qcom_icc_node qnm_snoc_gc; 148 static struct qcom_icc_node qnm_snoc_sf; 149 static struct qcom_icc_node qns_gem_noc_cnoc; 150 static struct qcom_icc_node qns_llcc; 151 static struct qcom_icc_node qns_pcie; 152 static struct qcom_icc_node srvc_even_gemnoc; 153 static struct qcom_icc_node srvc_odd_gemnoc; 154 static struct qcom_icc_node srvc_sys_gemnoc; 155 static struct qcom_icc_node srvc_sys_gemnoc_2; 156 static struct qcom_icc_node qxm_dsp0; 157 static struct qcom_icc_node qxm_dsp1; 158 static struct qcom_icc_node qns_gp_dsp_sail_noc; 159 static struct qcom_icc_node qhm_config_noc; 160 static struct qcom_icc_node qxm_lpass_dsp; 161 static struct qcom_icc_node qhs_lpass_core; 162 static struct qcom_icc_node qhs_lpass_lpi; 163 static struct qcom_icc_node qhs_lpass_mpu; 164 static struct qcom_icc_node qhs_lpass_top; 165 static struct qcom_icc_node qns_sysnoc; 166 static struct qcom_icc_node srvc_niu_aml_noc; 167 static struct qcom_icc_node srvc_niu_lpass_agnoc; 168 static struct qcom_icc_node llcc_mc; 169 static struct qcom_icc_node ebi; 170 static struct qcom_icc_node qnm_camnoc_hf; 171 static struct qcom_icc_node qnm_camnoc_icp; 172 static struct qcom_icc_node qnm_camnoc_sf; 173 static struct qcom_icc_node qnm_mdp0_0; 174 static struct qcom_icc_node qnm_mdp0_1; 175 static struct qcom_icc_node qnm_mdp1_0; 176 static struct qcom_icc_node qnm_mdp1_1; 177 static struct qcom_icc_node qnm_mnoc_hf_cfg; 178 static struct qcom_icc_node qnm_mnoc_sf_cfg; 179 static struct qcom_icc_node qnm_video0; 180 static struct qcom_icc_node qnm_video1; 181 static struct qcom_icc_node qnm_video_cvp; 182 static struct qcom_icc_node qnm_video_v_cpu; 183 static struct qcom_icc_node qns_mem_noc_hf; 184 static struct qcom_icc_node qns_mem_noc_sf; 185 static struct qcom_icc_node srvc_mnoc_hf; 186 static struct qcom_icc_node srvc_mnoc_sf; 187 static struct qcom_icc_node qhm_nsp_noc_config; 188 static struct qcom_icc_node qxm_nsp; 189 static struct qcom_icc_node qns_hcp; 190 static struct qcom_icc_node qns_nsp_gemnoc; 191 static struct qcom_icc_node service_nsp_noc; 192 static struct qcom_icc_node qhm_nspb_noc_config; 193 static struct qcom_icc_node qxm_nspb; 194 static struct qcom_icc_node qns_nspb_gemnoc; 195 static struct qcom_icc_node qns_nspb_hcp; 196 static struct qcom_icc_node service_nspb_noc; 197 static struct qcom_icc_node xm_pcie3_0; 198 static struct qcom_icc_node xm_pcie3_1; 199 static struct qcom_icc_node qns_pcie_mem_noc; 200 static struct qcom_icc_node qhm_gic; 201 static struct qcom_icc_node qnm_aggre1_noc; 202 static struct qcom_icc_node qnm_aggre2_noc; 203 static struct qcom_icc_node qnm_lpass_noc; 204 static struct qcom_icc_node qnm_snoc_cfg; 205 static struct qcom_icc_node qxm_pimem; 206 static struct qcom_icc_node xm_gic; 207 static struct qcom_icc_node qns_gemnoc_gc; 208 static struct qcom_icc_node qns_gemnoc_sf; 209 static struct qcom_icc_node srvc_snoc; 210 211 static struct qcom_icc_node qxm_qup3 = { 212 .name = "qxm_qup3", 213 .channels = 1, 214 .buswidth = 8, 215 .qosbox = &(const struct qcom_icc_qosbox) { 216 .num_ports = 1, 217 .port_offsets = { 0x11000 }, 218 .prio_fwd_disable = 1, 219 .prio = 2, 220 .urg_fwd = 0, 221 }, 222 .num_links = 1, 223 .link_nodes = { &qns_a1noc_snoc }, 224 }; 225 226 static struct qcom_icc_node xm_emac_0 = { 227 .name = "xm_emac_0", 228 .channels = 1, 229 .buswidth = 8, 230 .qosbox = &(const struct qcom_icc_qosbox) { 231 .num_ports = 1, 232 .port_offsets = { 0x12000 }, 233 .prio_fwd_disable = 1, 234 .prio = 2, 235 .urg_fwd = 0, 236 }, 237 .num_links = 1, 238 .link_nodes = { &qns_a1noc_snoc }, 239 }; 240 241 static struct qcom_icc_node xm_emac_1 = { 242 .name = "xm_emac_1", 243 .channels = 1, 244 .buswidth = 8, 245 .qosbox = &(const struct qcom_icc_qosbox) { 246 .num_ports = 1, 247 .port_offsets = { 0x13000 }, 248 .prio_fwd_disable = 1, 249 .prio = 2, 250 .urg_fwd = 0, 251 }, 252 .num_links = 1, 253 .link_nodes = { &qns_a1noc_snoc }, 254 }; 255 256 static struct qcom_icc_node xm_sdc1 = { 257 .name = "xm_sdc1", 258 .channels = 1, 259 .buswidth = 8, 260 .qosbox = &(const struct qcom_icc_qosbox) { 261 .num_ports = 1, 262 .port_offsets = { 0x14000 }, 263 .prio_fwd_disable = 1, 264 .prio = 2, 265 .urg_fwd = 0, 266 }, 267 .num_links = 1, 268 .link_nodes = { &qns_a1noc_snoc }, 269 }; 270 271 static struct qcom_icc_node xm_ufs_mem = { 272 .name = "xm_ufs_mem", 273 .channels = 1, 274 .buswidth = 8, 275 .qosbox = &(const struct qcom_icc_qosbox) { 276 .num_ports = 1, 277 .port_offsets = { 0x15000 }, 278 .prio_fwd_disable = 1, 279 .prio = 2, 280 .urg_fwd = 0, 281 }, 282 .num_links = 1, 283 .link_nodes = { &qns_a1noc_snoc }, 284 }; 285 286 static struct qcom_icc_node xm_usb2_2 = { 287 .name = "xm_usb2_2", 288 .channels = 1, 289 .buswidth = 8, 290 .qosbox = &(const struct qcom_icc_qosbox) { 291 .num_ports = 1, 292 .port_offsets = { 0x16000 }, 293 .prio_fwd_disable = 1, 294 .prio = 2, 295 .urg_fwd = 0, 296 }, 297 .num_links = 1, 298 .link_nodes = { &qns_a1noc_snoc }, 299 }; 300 301 static struct qcom_icc_node xm_usb3_0 = { 302 .name = "xm_usb3_0", 303 .channels = 1, 304 .buswidth = 8, 305 .qosbox = &(const struct qcom_icc_qosbox) { 306 .num_ports = 1, 307 .port_offsets = { 0x17000 }, 308 .prio_fwd_disable = 1, 309 .prio = 2, 310 .urg_fwd = 0, 311 }, 312 .num_links = 1, 313 .link_nodes = { &qns_a1noc_snoc }, 314 }; 315 316 static struct qcom_icc_node xm_usb3_1 = { 317 .name = "xm_usb3_1", 318 .channels = 1, 319 .buswidth = 8, 320 .qosbox = &(const struct qcom_icc_qosbox) { 321 .num_ports = 1, 322 .port_offsets = { 0x18000 }, 323 .prio_fwd_disable = 1, 324 .prio = 2, 325 .urg_fwd = 0, 326 }, 327 .num_links = 1, 328 .link_nodes = { &qns_a1noc_snoc }, 329 }; 330 331 static struct qcom_icc_node qhm_qdss_bam = { 332 .name = "qhm_qdss_bam", 333 .channels = 1, 334 .buswidth = 4, 335 .qosbox = &(const struct qcom_icc_qosbox) { 336 .num_ports = 1, 337 .port_offsets = { 0x14000 }, 338 .prio_fwd_disable = 1, 339 .prio = 2, 340 .urg_fwd = 0, 341 }, 342 .num_links = 1, 343 .link_nodes = { &qns_a2noc_snoc }, 344 }; 345 346 static struct qcom_icc_node qhm_qup0 = { 347 .name = "qhm_qup0", 348 .channels = 1, 349 .buswidth = 4, 350 .qosbox = &(const struct qcom_icc_qosbox) { 351 .num_ports = 1, 352 .port_offsets = { 0x17000 }, 353 .prio_fwd_disable = 1, 354 .prio = 2, 355 .urg_fwd = 0, 356 }, 357 .num_links = 1, 358 .link_nodes = { &qns_a2noc_snoc }, 359 }; 360 361 static struct qcom_icc_node qhm_qup1 = { 362 .name = "qhm_qup1", 363 .channels = 1, 364 .buswidth = 4, 365 .qosbox = &(const struct qcom_icc_qosbox) { 366 .num_ports = 1, 367 .port_offsets = { 0x12000 }, 368 .prio_fwd_disable = 1, 369 .prio = 2, 370 .urg_fwd = 0, 371 }, 372 .num_links = 1, 373 .link_nodes = { &qns_a2noc_snoc }, 374 }; 375 376 static struct qcom_icc_node qhm_qup2 = { 377 .name = "qhm_qup2", 378 .channels = 1, 379 .buswidth = 4, 380 .qosbox = &(const struct qcom_icc_qosbox) { 381 .num_ports = 1, 382 .port_offsets = { 0x15000 }, 383 .prio_fwd_disable = 1, 384 .prio = 2, 385 .urg_fwd = 0, 386 }, 387 .num_links = 1, 388 .link_nodes = { &qns_a2noc_snoc }, 389 }; 390 391 static struct qcom_icc_node qnm_cnoc_datapath = { 392 .name = "qnm_cnoc_datapath", 393 .channels = 1, 394 .buswidth = 8, 395 .qosbox = &(const struct qcom_icc_qosbox) { 396 .num_ports = 1, 397 .port_offsets = { 0x16000 }, 398 .prio_fwd_disable = 1, 399 .prio = 2, 400 .urg_fwd = 0, 401 }, 402 .num_links = 1, 403 .link_nodes = { &qns_a2noc_snoc }, 404 }; 405 406 static struct qcom_icc_node qxm_crypto_0 = { 407 .name = "qxm_crypto_0", 408 .channels = 1, 409 .buswidth = 8, 410 .qosbox = &(const struct qcom_icc_qosbox) { 411 .num_ports = 1, 412 .port_offsets = { 0x18000 }, 413 .prio_fwd_disable = 1, 414 .prio = 2, 415 .urg_fwd = 0, 416 }, 417 .num_links = 1, 418 .link_nodes = { &qns_a2noc_snoc }, 419 }; 420 421 static struct qcom_icc_node qxm_crypto_1 = { 422 .name = "qxm_crypto_1", 423 .channels = 1, 424 .buswidth = 8, 425 .qosbox = &(const struct qcom_icc_qosbox) { 426 .num_ports = 1, 427 .port_offsets = { 0x1a000 }, 428 .prio_fwd_disable = 1, 429 .prio = 2, 430 .urg_fwd = 0, 431 }, 432 .num_links = 1, 433 .link_nodes = { &qns_a2noc_snoc }, 434 }; 435 436 static struct qcom_icc_node qxm_ipa = { 437 .name = "qxm_ipa", 438 .channels = 1, 439 .buswidth = 8, 440 .qosbox = &(const struct qcom_icc_qosbox) { 441 .num_ports = 1, 442 .port_offsets = { 0x11000 }, 443 .prio_fwd_disable = 1, 444 .prio = 2, 445 .urg_fwd = 0, 446 }, 447 .num_links = 1, 448 .link_nodes = { &qns_a2noc_snoc }, 449 }; 450 451 static struct qcom_icc_node xm_qdss_etr_0 = { 452 .name = "xm_qdss_etr_0", 453 .channels = 1, 454 .buswidth = 8, 455 .qosbox = &(const struct qcom_icc_qosbox) { 456 .num_ports = 1, 457 .port_offsets = { 0x13000 }, 458 .prio_fwd_disable = 1, 459 .prio = 2, 460 .urg_fwd = 0, 461 }, 462 .num_links = 1, 463 .link_nodes = { &qns_a2noc_snoc }, 464 }; 465 466 static struct qcom_icc_node xm_qdss_etr_1 = { 467 .name = "xm_qdss_etr_1", 468 .channels = 1, 469 .buswidth = 8, 470 .qosbox = &(const struct qcom_icc_qosbox) { 471 .num_ports = 1, 472 .port_offsets = { 0x19000 }, 473 .prio_fwd_disable = 1, 474 .prio = 2, 475 .urg_fwd = 0, 476 }, 477 .num_links = 1, 478 .link_nodes = { &qns_a2noc_snoc }, 479 }; 480 481 static struct qcom_icc_node xm_ufs_card = { 482 .name = "xm_ufs_card", 483 .channels = 1, 484 .buswidth = 8, 485 .qosbox = &(const struct qcom_icc_qosbox) { 486 .num_ports = 1, 487 .port_offsets = { 0x1b000 }, 488 .prio_fwd_disable = 1, 489 .prio = 2, 490 .urg_fwd = 0, 491 }, 492 .num_links = 1, 493 .link_nodes = { &qns_a2noc_snoc }, 494 }; 495 496 static struct qcom_icc_node qup0_core_master = { 497 .name = "qup0_core_master", 498 .channels = 1, 499 .buswidth = 4, 500 .num_links = 1, 501 .link_nodes = { &qup0_core_slave }, 502 }; 503 504 static struct qcom_icc_node qup1_core_master = { 505 .name = "qup1_core_master", 506 .channels = 1, 507 .buswidth = 4, 508 .num_links = 1, 509 .link_nodes = { &qup1_core_slave }, 510 }; 511 512 static struct qcom_icc_node qup2_core_master = { 513 .name = "qup2_core_master", 514 .channels = 1, 515 .buswidth = 4, 516 .num_links = 1, 517 .link_nodes = { &qup2_core_slave }, 518 }; 519 520 static struct qcom_icc_node qup3_core_master = { 521 .name = "qup3_core_master", 522 .channels = 1, 523 .buswidth = 4, 524 .num_links = 1, 525 .link_nodes = { &qup3_core_slave }, 526 }; 527 528 static struct qcom_icc_node qnm_gemnoc_cnoc = { 529 .name = "qnm_gemnoc_cnoc", 530 .channels = 1, 531 .buswidth = 16, 532 .num_links = 82, 533 .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, 534 &qhs_ahb2phy2, &qhs_ahb2phy3, 535 &qhs_anoc_throttle_cfg, &qhs_aoss, 536 &qhs_apss, &qhs_boot_rom, 537 &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg, 538 &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, 539 &qhs_compute0_cfg, &qhs_compute1_cfg, 540 &qhs_cpr_cx, &qhs_cpr_mmcx, 541 &qhs_cpr_mx, &qhs_cpr_nspcx, 542 &qhs_crypto0_cfg, &qhs_cx_rdpm, 543 &qhs_display0_cfg, &qhs_display0_rt_throttle_cfg, 544 &qhs_display1_cfg, &qhs_display1_rt_throttle_cfg, 545 &qhs_emac0_cfg, &qhs_emac1_cfg, 546 &qhs_gp_dsp0_cfg, &qhs_gp_dsp1_cfg, 547 &qhs_gpdsp0_throttle_cfg, &qhs_gpdsp1_throttle_cfg, 548 &qhs_gpu_tcu_throttle_cfg, &qhs_gpuss_cfg, 549 &qhs_hwkm, &qhs_imem_cfg, 550 &qhs_ipa, &qhs_ipc_router, 551 &qhs_lpass_cfg, &qhs_lpass_throttle_cfg, 552 &qhs_mx_rdpm, &qhs_mxc_rdpm, 553 &qhs_pcie0_cfg, &qhs_pcie1_cfg, 554 &qhs_pcie_rsc_cfg, &qhs_pcie_tcu_throttle_cfg, 555 &qhs_pcie_throttle_cfg, &qhs_pdm, 556 &qhs_pimem_cfg, &qhs_pke_wrapper_cfg, 557 &qhs_qdss_cfg, &qhs_qm_cfg, 558 &qhs_qm_mpu_cfg, &qhs_qup0, 559 &qhs_qup1, &qhs_qup2, 560 &qhs_qup3, &qhs_sail_throttle_cfg, 561 &qhs_sdc1, &qhs_security, 562 &qhs_snoc_throttle_cfg, &qhs_tcsr, 563 &qhs_tlmm, &qhs_tsc_cfg, 564 &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, 565 &qhs_usb2_0, &qhs_usb3_0, 566 &qhs_usb3_1, &qhs_venus_cfg, 567 &qhs_venus_cvp_throttle_cfg, &qhs_venus_v_cpu_throttle_cfg, 568 &qhs_venus_vcodec_throttle_cfg, &qns_ddrss_cfg, 569 &qns_gpdsp_noc_cfg, &qns_mnoc_hf_cfg, 570 &qns_mnoc_sf_cfg, &qns_pcie_anoc_cfg, 571 &qns_snoc_cfg, &qxs_boot_imem, 572 &qxs_imem, &qxs_pimem, 573 &xs_qdss_stm, &xs_sys_tcu_cfg }, 574 }; 575 576 static struct qcom_icc_node qnm_gemnoc_pcie = { 577 .name = "qnm_gemnoc_pcie", 578 .channels = 1, 579 .buswidth = 16, 580 .num_links = 2, 581 .link_nodes = { &xs_pcie_0, &xs_pcie_1 }, 582 }; 583 584 static struct qcom_icc_node qnm_cnoc_dc_noc = { 585 .name = "qnm_cnoc_dc_noc", 586 .channels = 1, 587 .buswidth = 4, 588 .num_links = 2, 589 .link_nodes = { &qhs_llcc, &qns_gemnoc }, 590 }; 591 592 static struct qcom_icc_node alm_gpu_tcu = { 593 .name = "alm_gpu_tcu", 594 .channels = 1, 595 .buswidth = 8, 596 .qosbox = &(const struct qcom_icc_qosbox) { 597 .num_ports = 1, 598 .port_offsets = { 0xb4000 }, 599 .prio_fwd_disable = 1, 600 .prio = 1, 601 .urg_fwd = 0, 602 }, 603 .num_links = 2, 604 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 605 }; 606 607 static struct qcom_icc_node alm_pcie_tcu = { 608 .name = "alm_pcie_tcu", 609 .channels = 1, 610 .buswidth = 8, 611 .qosbox = &(const struct qcom_icc_qosbox) { 612 .num_ports = 1, 613 .port_offsets = { 0xb5000 }, 614 .prio_fwd_disable = 1, 615 .prio = 3, 616 .urg_fwd = 0, 617 }, 618 .num_links = 2, 619 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 620 }; 621 622 static struct qcom_icc_node alm_sys_tcu = { 623 .name = "alm_sys_tcu", 624 .channels = 1, 625 .buswidth = 8, 626 .qosbox = &(const struct qcom_icc_qosbox) { 627 .num_ports = 1, 628 .port_offsets = { 0xb6000 }, 629 .prio_fwd_disable = 1, 630 .prio = 6, 631 .urg_fwd = 0, 632 }, 633 .num_links = 2, 634 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 635 }; 636 637 static struct qcom_icc_node chm_apps = { 638 .name = "chm_apps", 639 .channels = 4, 640 .buswidth = 32, 641 .num_links = 3, 642 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 643 &qns_pcie }, 644 }; 645 646 static struct qcom_icc_node qnm_cmpnoc0 = { 647 .name = "qnm_cmpnoc0", 648 .channels = 2, 649 .buswidth = 32, 650 .qosbox = &(const struct qcom_icc_qosbox) { 651 .num_ports = 2, 652 .port_offsets = { 0xf3000, 0xf4000 }, 653 .prio_fwd_disable = 1, 654 .prio = 0, 655 .urg_fwd = 0, 656 }, 657 .num_links = 2, 658 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 659 }; 660 661 static struct qcom_icc_node qnm_cmpnoc1 = { 662 .name = "qnm_cmpnoc1", 663 .channels = 2, 664 .buswidth = 32, 665 .qosbox = &(const struct qcom_icc_qosbox) { 666 .num_ports = 2, 667 .port_offsets = { 0xf5000, 0xf6000 }, 668 .prio_fwd_disable = 1, 669 .prio = 0, 670 .urg_fwd = 0, 671 }, 672 .num_links = 2, 673 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 674 }; 675 676 static struct qcom_icc_node qnm_gemnoc_cfg = { 677 .name = "qnm_gemnoc_cfg", 678 .channels = 1, 679 .buswidth = 4, 680 .num_links = 4, 681 .link_nodes = { &srvc_even_gemnoc, &srvc_odd_gemnoc, 682 &srvc_sys_gemnoc, &srvc_sys_gemnoc_2 }, 683 }; 684 685 static struct qcom_icc_node qnm_gpdsp_sail = { 686 .name = "qnm_gpdsp_sail", 687 .channels = 1, 688 .buswidth = 16, 689 .num_links = 2, 690 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 691 }; 692 693 static struct qcom_icc_node qnm_gpu = { 694 .name = "qnm_gpu", 695 .channels = 2, 696 .buswidth = 32, 697 .qosbox = &(const struct qcom_icc_qosbox) { 698 .num_ports = 2, 699 .port_offsets = { 0xed000, 0xee000 }, 700 .prio_fwd_disable = 1, 701 .prio = 0, 702 .urg_fwd = 0, 703 }, 704 .num_links = 2, 705 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 706 }; 707 708 static struct qcom_icc_node qnm_mnoc_hf = { 709 .name = "qnm_mnoc_hf", 710 .channels = 2, 711 .buswidth = 32, 712 .qosbox = &(const struct qcom_icc_qosbox) { 713 .num_ports = 2, 714 .port_offsets = { 0xef000, 0xf0000 }, 715 .prio_fwd_disable = 0, 716 .prio = 0, 717 .urg_fwd = 1, 718 }, 719 .num_links = 2, 720 .link_nodes = { &qns_llcc, &qns_pcie }, 721 }; 722 723 static struct qcom_icc_node qnm_mnoc_sf = { 724 .name = "qnm_mnoc_sf", 725 .channels = 2, 726 .buswidth = 32, 727 .qosbox = &(const struct qcom_icc_qosbox) { 728 .num_ports = 2, 729 .port_offsets = { 0xf1000, 0xf2000 }, 730 .prio_fwd_disable = 0, 731 .prio = 0, 732 .urg_fwd = 1, 733 }, 734 .num_links = 3, 735 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 736 &qns_pcie }, 737 }; 738 739 static struct qcom_icc_node qnm_pcie = { 740 .name = "qnm_pcie", 741 .channels = 1, 742 .buswidth = 32, 743 .qosbox = &(const struct qcom_icc_qosbox) { 744 .num_ports = 1, 745 .port_offsets = { 0xb8000 }, 746 .prio_fwd_disable = 1, 747 .prio = 2, 748 .urg_fwd = 0, 749 }, 750 .num_links = 2, 751 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 752 }; 753 754 static struct qcom_icc_node qnm_snoc_gc = { 755 .name = "qnm_snoc_gc", 756 .channels = 1, 757 .buswidth = 8, 758 .qosbox = &(const struct qcom_icc_qosbox) { 759 .num_ports = 1, 760 .port_offsets = { 0xb9000 }, 761 .prio_fwd_disable = 0, 762 .prio = 0, 763 .urg_fwd = 1, 764 }, 765 .num_links = 1, 766 .link_nodes = { &qns_llcc }, 767 }; 768 769 static struct qcom_icc_node qnm_snoc_sf = { 770 .name = "qnm_snoc_sf", 771 .channels = 1, 772 .buswidth = 16, 773 .qosbox = &(const struct qcom_icc_qosbox) { 774 .num_ports = 1, 775 .port_offsets = { 0xba000 }, 776 .prio_fwd_disable = 0, 777 .prio = 0, 778 .urg_fwd = 1, 779 }, 780 .num_links = 3, 781 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 782 &qns_pcie }, 783 }; 784 785 static struct qcom_icc_node qxm_dsp0 = { 786 .name = "qxm_dsp0", 787 .channels = 1, 788 .buswidth = 16, 789 .num_links = 1, 790 .link_nodes = { &qns_gp_dsp_sail_noc }, 791 }; 792 793 static struct qcom_icc_node qxm_dsp1 = { 794 .name = "qxm_dsp1", 795 .channels = 1, 796 .buswidth = 16, 797 .num_links = 1, 798 .link_nodes = { &qns_gp_dsp_sail_noc }, 799 }; 800 801 static struct qcom_icc_node qhm_config_noc = { 802 .name = "qhm_config_noc", 803 .channels = 1, 804 .buswidth = 4, 805 .num_links = 6, 806 .link_nodes = { &qhs_lpass_core, &qhs_lpass_lpi, 807 &qhs_lpass_mpu, &qhs_lpass_top, 808 &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, 809 }; 810 811 static struct qcom_icc_node qxm_lpass_dsp = { 812 .name = "qxm_lpass_dsp", 813 .channels = 1, 814 .buswidth = 8, 815 .num_links = 4, 816 .link_nodes = { &qhs_lpass_top, &qns_sysnoc, 817 &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, 818 }; 819 820 static struct qcom_icc_node llcc_mc = { 821 .name = "llcc_mc", 822 .channels = 8, 823 .buswidth = 4, 824 .num_links = 1, 825 .link_nodes = { &ebi }, 826 }; 827 828 static struct qcom_icc_node qnm_camnoc_hf = { 829 .name = "qnm_camnoc_hf", 830 .channels = 1, 831 .buswidth = 32, 832 .qosbox = &(const struct qcom_icc_qosbox) { 833 .num_ports = 1, 834 .port_offsets = { 0xa000 }, 835 .prio_fwd_disable = 0, 836 .prio = 0, 837 .urg_fwd = 1, 838 }, 839 .num_links = 1, 840 .link_nodes = { &qns_mem_noc_hf }, 841 }; 842 843 static struct qcom_icc_node qnm_camnoc_icp = { 844 .name = "qnm_camnoc_icp", 845 .channels = 1, 846 .buswidth = 8, 847 .qosbox = &(const struct qcom_icc_qosbox) { 848 .num_ports = 1, 849 .port_offsets = { 0x2a000 }, 850 .prio_fwd_disable = 0, 851 .prio = 0, 852 .urg_fwd = 1, 853 }, 854 .num_links = 1, 855 .link_nodes = { &qns_mem_noc_sf }, 856 }; 857 858 static struct qcom_icc_node qnm_camnoc_sf = { 859 .name = "qnm_camnoc_sf", 860 .channels = 1, 861 .buswidth = 32, 862 .qosbox = &(const struct qcom_icc_qosbox) { 863 .num_ports = 1, 864 .port_offsets = { 0x2a080 }, 865 .prio_fwd_disable = 0, 866 .prio = 0, 867 .urg_fwd = 1, 868 }, 869 .num_links = 1, 870 .link_nodes = { &qns_mem_noc_sf }, 871 }; 872 873 static struct qcom_icc_node qnm_mdp0_0 = { 874 .name = "qnm_mdp0_0", 875 .channels = 1, 876 .buswidth = 32, 877 .qosbox = &(const struct qcom_icc_qosbox) { 878 .num_ports = 1, 879 .port_offsets = { 0xa080 }, 880 .prio_fwd_disable = 0, 881 .prio = 0, 882 .urg_fwd = 1, 883 }, 884 .num_links = 1, 885 .link_nodes = { &qns_mem_noc_hf }, 886 }; 887 888 static struct qcom_icc_node qnm_mdp0_1 = { 889 .name = "qnm_mdp0_1", 890 .channels = 1, 891 .buswidth = 32, 892 .qosbox = &(const struct qcom_icc_qosbox) { 893 .num_ports = 1, 894 .port_offsets = { 0xa180 }, 895 .prio_fwd_disable = 0, 896 .prio = 0, 897 .urg_fwd = 1, 898 }, 899 .num_links = 1, 900 .link_nodes = { &qns_mem_noc_hf }, 901 }; 902 903 static struct qcom_icc_node qnm_mdp1_0 = { 904 .name = "qnm_mdp1_0", 905 .channels = 1, 906 .buswidth = 32, 907 .qosbox = &(const struct qcom_icc_qosbox) { 908 .num_ports = 1, 909 .port_offsets = { 0xa100 }, 910 .prio_fwd_disable = 0, 911 .prio = 0, 912 .urg_fwd = 1, 913 }, 914 .num_links = 1, 915 .link_nodes = { &qns_mem_noc_hf }, 916 }; 917 918 static struct qcom_icc_node qnm_mdp1_1 = { 919 .name = "qnm_mdp1_1", 920 .channels = 1, 921 .buswidth = 32, 922 .qosbox = &(const struct qcom_icc_qosbox) { 923 .num_ports = 1, 924 .port_offsets = { 0xa200 }, 925 .prio_fwd_disable = 0, 926 .prio = 0, 927 .urg_fwd = 1, 928 }, 929 .num_links = 1, 930 .link_nodes = { &qns_mem_noc_hf }, 931 }; 932 933 static struct qcom_icc_node qnm_mnoc_hf_cfg = { 934 .name = "qnm_mnoc_hf_cfg", 935 .channels = 1, 936 .buswidth = 4, 937 .num_links = 1, 938 .link_nodes = { &srvc_mnoc_hf }, 939 }; 940 941 static struct qcom_icc_node qnm_mnoc_sf_cfg = { 942 .name = "qnm_mnoc_sf_cfg", 943 .channels = 1, 944 .buswidth = 4, 945 .num_links = 1, 946 .link_nodes = { &srvc_mnoc_sf }, 947 }; 948 949 static struct qcom_icc_node qnm_video0 = { 950 .name = "qnm_video0", 951 .channels = 1, 952 .buswidth = 32, 953 .qosbox = &(const struct qcom_icc_qosbox) { 954 .num_ports = 1, 955 .port_offsets = { 0x2a100 }, 956 .prio_fwd_disable = 0, 957 .prio = 0, 958 .urg_fwd = 1, 959 }, 960 .num_links = 1, 961 .link_nodes = { &qns_mem_noc_sf }, 962 }; 963 964 static struct qcom_icc_node qnm_video1 = { 965 .name = "qnm_video1", 966 .channels = 1, 967 .buswidth = 32, 968 .qosbox = &(const struct qcom_icc_qosbox) { 969 .num_ports = 1, 970 .port_offsets = { 0x2a180 }, 971 .prio_fwd_disable = 0, 972 .prio = 0, 973 .urg_fwd = 1, 974 }, 975 .num_links = 1, 976 .link_nodes = { &qns_mem_noc_sf }, 977 }; 978 979 static struct qcom_icc_node qnm_video_cvp = { 980 .name = "qnm_video_cvp", 981 .channels = 1, 982 .buswidth = 32, 983 .qosbox = &(const struct qcom_icc_qosbox) { 984 .num_ports = 1, 985 .port_offsets = { 0x2a200 }, 986 .prio_fwd_disable = 0, 987 .prio = 0, 988 .urg_fwd = 1, 989 }, 990 .num_links = 1, 991 .link_nodes = { &qns_mem_noc_sf }, 992 }; 993 994 static struct qcom_icc_node qnm_video_v_cpu = { 995 .name = "qnm_video_v_cpu", 996 .channels = 1, 997 .buswidth = 8, 998 .qosbox = &(const struct qcom_icc_qosbox) { 999 .num_ports = 1, 1000 .port_offsets = { 0x2a280 }, 1001 .prio_fwd_disable = 0, 1002 .prio = 0, 1003 .urg_fwd = 1, 1004 }, 1005 .num_links = 1, 1006 .link_nodes = { &qns_mem_noc_sf }, 1007 }; 1008 1009 static struct qcom_icc_node qhm_nsp_noc_config = { 1010 .name = "qhm_nsp_noc_config", 1011 .channels = 1, 1012 .buswidth = 4, 1013 .num_links = 1, 1014 .link_nodes = { &service_nsp_noc }, 1015 }; 1016 1017 static struct qcom_icc_node qxm_nsp = { 1018 .name = "qxm_nsp", 1019 .channels = 2, 1020 .buswidth = 32, 1021 .num_links = 2, 1022 .link_nodes = { &qns_hcp, &qns_nsp_gemnoc }, 1023 }; 1024 1025 static struct qcom_icc_node qhm_nspb_noc_config = { 1026 .name = "qhm_nspb_noc_config", 1027 .channels = 1, 1028 .buswidth = 4, 1029 .num_links = 1, 1030 .link_nodes = { &service_nspb_noc }, 1031 }; 1032 1033 static struct qcom_icc_node qxm_nspb = { 1034 .name = "qxm_nspb", 1035 .channels = 2, 1036 .buswidth = 32, 1037 .num_links = 2, 1038 .link_nodes = { &qns_nspb_hcp, &qns_nspb_gemnoc }, 1039 }; 1040 1041 static struct qcom_icc_node xm_pcie3_0 = { 1042 .name = "xm_pcie3_0", 1043 .channels = 1, 1044 .buswidth = 16, 1045 .qosbox = &(const struct qcom_icc_qosbox) { 1046 .num_ports = 1, 1047 .port_offsets = { 0xb000 }, 1048 .prio_fwd_disable = 1, 1049 .prio = 2, 1050 .urg_fwd = 0, 1051 }, 1052 .num_links = 1, 1053 .link_nodes = { &qns_pcie_mem_noc }, 1054 }; 1055 1056 static struct qcom_icc_node xm_pcie3_1 = { 1057 .name = "xm_pcie3_1", 1058 .channels = 1, 1059 .buswidth = 32, 1060 .qosbox = &(const struct qcom_icc_qosbox) { 1061 .num_ports = 1, 1062 .port_offsets = { 0xc000 }, 1063 .prio_fwd_disable = 1, 1064 .prio = 2, 1065 .urg_fwd = 0, 1066 }, 1067 .num_links = 1, 1068 .link_nodes = { &qns_pcie_mem_noc }, 1069 }; 1070 1071 static struct qcom_icc_node qhm_gic = { 1072 .name = "qhm_gic", 1073 .channels = 1, 1074 .buswidth = 4, 1075 .qosbox = &(const struct qcom_icc_qosbox) { 1076 .num_ports = 1, 1077 .port_offsets = { 0x14000 }, 1078 .prio_fwd_disable = 1, 1079 .prio = 2, 1080 .urg_fwd = 0, 1081 }, 1082 .num_links = 1, 1083 .link_nodes = { &qns_gemnoc_sf }, 1084 }; 1085 1086 static struct qcom_icc_node qnm_aggre1_noc = { 1087 .name = "qnm_aggre1_noc", 1088 .channels = 1, 1089 .buswidth = 32, 1090 .num_links = 1, 1091 .link_nodes = { &qns_gemnoc_sf }, 1092 }; 1093 1094 static struct qcom_icc_node qnm_aggre2_noc = { 1095 .name = "qnm_aggre2_noc", 1096 .channels = 1, 1097 .buswidth = 16, 1098 .num_links = 1, 1099 .link_nodes = { &qns_gemnoc_sf }, 1100 }; 1101 1102 static struct qcom_icc_node qnm_lpass_noc = { 1103 .name = "qnm_lpass_noc", 1104 .channels = 1, 1105 .buswidth = 16, 1106 .qosbox = &(const struct qcom_icc_qosbox) { 1107 .num_ports = 1, 1108 .port_offsets = { 0x12000 }, 1109 .prio_fwd_disable = 0, 1110 .prio = 0, 1111 .urg_fwd = 1, 1112 }, 1113 .num_links = 1, 1114 .link_nodes = { &qns_gemnoc_sf }, 1115 }; 1116 1117 static struct qcom_icc_node qnm_snoc_cfg = { 1118 .name = "qnm_snoc_cfg", 1119 .channels = 1, 1120 .buswidth = 4, 1121 .num_links = 1, 1122 .link_nodes = { &srvc_snoc }, 1123 }; 1124 1125 static struct qcom_icc_node qxm_pimem = { 1126 .name = "qxm_pimem", 1127 .channels = 1, 1128 .buswidth = 8, 1129 .qosbox = &(const struct qcom_icc_qosbox) { 1130 .num_ports = 1, 1131 .port_offsets = { 0x13000 }, 1132 .prio_fwd_disable = 1, 1133 .prio = 2, 1134 .urg_fwd = 0, 1135 }, 1136 .num_links = 1, 1137 .link_nodes = { &qns_gemnoc_gc }, 1138 }; 1139 1140 static struct qcom_icc_node xm_gic = { 1141 .name = "xm_gic", 1142 .channels = 1, 1143 .buswidth = 8, 1144 .qosbox = &(const struct qcom_icc_qosbox) { 1145 .num_ports = 1, 1146 .port_offsets = { 0x15000 }, 1147 .prio_fwd_disable = 1, 1148 .prio = 2, 1149 .urg_fwd = 0, 1150 }, 1151 .num_links = 1, 1152 .link_nodes = { &qns_gemnoc_gc }, 1153 }; 1154 1155 static struct qcom_icc_node qns_a1noc_snoc = { 1156 .name = "qns_a1noc_snoc", 1157 .channels = 1, 1158 .buswidth = 32, 1159 .num_links = 1, 1160 .link_nodes = { &qnm_aggre1_noc }, 1161 }; 1162 1163 static struct qcom_icc_node qns_a2noc_snoc = { 1164 .name = "qns_a2noc_snoc", 1165 .channels = 1, 1166 .buswidth = 16, 1167 .num_links = 1, 1168 .link_nodes = { &qnm_aggre2_noc }, 1169 }; 1170 1171 static struct qcom_icc_node qup0_core_slave = { 1172 .name = "qup0_core_slave", 1173 .channels = 1, 1174 .buswidth = 4, 1175 }; 1176 1177 static struct qcom_icc_node qup1_core_slave = { 1178 .name = "qup1_core_slave", 1179 .channels = 1, 1180 .buswidth = 4, 1181 }; 1182 1183 static struct qcom_icc_node qup2_core_slave = { 1184 .name = "qup2_core_slave", 1185 .channels = 1, 1186 .buswidth = 4, 1187 }; 1188 1189 static struct qcom_icc_node qup3_core_slave = { 1190 .name = "qup3_core_slave", 1191 .channels = 1, 1192 .buswidth = 4, 1193 }; 1194 1195 static struct qcom_icc_node qhs_ahb2phy0 = { 1196 .name = "qhs_ahb2phy0", 1197 .channels = 1, 1198 .buswidth = 4, 1199 }; 1200 1201 static struct qcom_icc_node qhs_ahb2phy1 = { 1202 .name = "qhs_ahb2phy1", 1203 .channels = 1, 1204 .buswidth = 4, 1205 }; 1206 1207 static struct qcom_icc_node qhs_ahb2phy2 = { 1208 .name = "qhs_ahb2phy2", 1209 .channels = 1, 1210 .buswidth = 4, 1211 }; 1212 1213 static struct qcom_icc_node qhs_ahb2phy3 = { 1214 .name = "qhs_ahb2phy3", 1215 .channels = 1, 1216 .buswidth = 4, 1217 }; 1218 1219 static struct qcom_icc_node qhs_anoc_throttle_cfg = { 1220 .name = "qhs_anoc_throttle_cfg", 1221 .channels = 1, 1222 .buswidth = 4, 1223 }; 1224 1225 static struct qcom_icc_node qhs_aoss = { 1226 .name = "qhs_aoss", 1227 .channels = 1, 1228 .buswidth = 4, 1229 }; 1230 1231 static struct qcom_icc_node qhs_apss = { 1232 .name = "qhs_apss", 1233 .channels = 1, 1234 .buswidth = 8, 1235 }; 1236 1237 static struct qcom_icc_node qhs_boot_rom = { 1238 .name = "qhs_boot_rom", 1239 .channels = 1, 1240 .buswidth = 4, 1241 }; 1242 1243 static struct qcom_icc_node qhs_camera_cfg = { 1244 .name = "qhs_camera_cfg", 1245 .channels = 1, 1246 .buswidth = 4, 1247 }; 1248 1249 static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = { 1250 .name = "qhs_camera_nrt_throttle_cfg", 1251 .channels = 1, 1252 .buswidth = 4, 1253 }; 1254 1255 static struct qcom_icc_node qhs_camera_rt_throttle_cfg = { 1256 .name = "qhs_camera_rt_throttle_cfg", 1257 .channels = 1, 1258 .buswidth = 4, 1259 }; 1260 1261 static struct qcom_icc_node qhs_clk_ctl = { 1262 .name = "qhs_clk_ctl", 1263 .channels = 1, 1264 .buswidth = 4, 1265 }; 1266 1267 static struct qcom_icc_node qhs_compute0_cfg = { 1268 .name = "qhs_compute0_cfg", 1269 .channels = 1, 1270 .buswidth = 4, 1271 .num_links = 1, 1272 .link_nodes = { &qhm_nsp_noc_config }, 1273 }; 1274 1275 static struct qcom_icc_node qhs_compute1_cfg = { 1276 .name = "qhs_compute1_cfg", 1277 .channels = 1, 1278 .buswidth = 4, 1279 .num_links = 1, 1280 .link_nodes = { &qhm_nspb_noc_config }, 1281 }; 1282 1283 static struct qcom_icc_node qhs_cpr_cx = { 1284 .name = "qhs_cpr_cx", 1285 .channels = 1, 1286 .buswidth = 4, 1287 }; 1288 1289 static struct qcom_icc_node qhs_cpr_mmcx = { 1290 .name = "qhs_cpr_mmcx", 1291 .channels = 1, 1292 .buswidth = 4, 1293 }; 1294 1295 static struct qcom_icc_node qhs_cpr_mx = { 1296 .name = "qhs_cpr_mx", 1297 .channels = 1, 1298 .buswidth = 4, 1299 }; 1300 1301 static struct qcom_icc_node qhs_cpr_nspcx = { 1302 .name = "qhs_cpr_nspcx", 1303 .channels = 1, 1304 .buswidth = 4, 1305 }; 1306 1307 static struct qcom_icc_node qhs_crypto0_cfg = { 1308 .name = "qhs_crypto0_cfg", 1309 .channels = 1, 1310 .buswidth = 4, 1311 }; 1312 1313 static struct qcom_icc_node qhs_cx_rdpm = { 1314 .name = "qhs_cx_rdpm", 1315 .channels = 1, 1316 .buswidth = 4, 1317 }; 1318 1319 static struct qcom_icc_node qhs_display0_cfg = { 1320 .name = "qhs_display0_cfg", 1321 .channels = 1, 1322 .buswidth = 4, 1323 }; 1324 1325 static struct qcom_icc_node qhs_display0_rt_throttle_cfg = { 1326 .name = "qhs_display0_rt_throttle_cfg", 1327 .channels = 1, 1328 .buswidth = 4, 1329 }; 1330 1331 static struct qcom_icc_node qhs_display1_cfg = { 1332 .name = "qhs_display1_cfg", 1333 .channels = 1, 1334 .buswidth = 4, 1335 }; 1336 1337 static struct qcom_icc_node qhs_display1_rt_throttle_cfg = { 1338 .name = "qhs_display1_rt_throttle_cfg", 1339 .channels = 1, 1340 .buswidth = 4, 1341 }; 1342 1343 static struct qcom_icc_node qhs_emac0_cfg = { 1344 .name = "qhs_emac0_cfg", 1345 .channels = 1, 1346 .buswidth = 4, 1347 }; 1348 1349 static struct qcom_icc_node qhs_emac1_cfg = { 1350 .name = "qhs_emac1_cfg", 1351 .channels = 1, 1352 .buswidth = 4, 1353 }; 1354 1355 static struct qcom_icc_node qhs_gp_dsp0_cfg = { 1356 .name = "qhs_gp_dsp0_cfg", 1357 .channels = 1, 1358 .buswidth = 4, 1359 }; 1360 1361 static struct qcom_icc_node qhs_gp_dsp1_cfg = { 1362 .name = "qhs_gp_dsp1_cfg", 1363 .channels = 1, 1364 .buswidth = 4, 1365 }; 1366 1367 static struct qcom_icc_node qhs_gpdsp0_throttle_cfg = { 1368 .name = "qhs_gpdsp0_throttle_cfg", 1369 .channels = 1, 1370 .buswidth = 4, 1371 }; 1372 1373 static struct qcom_icc_node qhs_gpdsp1_throttle_cfg = { 1374 .name = "qhs_gpdsp1_throttle_cfg", 1375 .channels = 1, 1376 .buswidth = 4, 1377 }; 1378 1379 static struct qcom_icc_node qhs_gpu_tcu_throttle_cfg = { 1380 .name = "qhs_gpu_tcu_throttle_cfg", 1381 .channels = 1, 1382 .buswidth = 4, 1383 }; 1384 1385 static struct qcom_icc_node qhs_gpuss_cfg = { 1386 .name = "qhs_gpuss_cfg", 1387 .channels = 1, 1388 .buswidth = 8, 1389 }; 1390 1391 static struct qcom_icc_node qhs_hwkm = { 1392 .name = "qhs_hwkm", 1393 .channels = 1, 1394 .buswidth = 4, 1395 }; 1396 1397 static struct qcom_icc_node qhs_imem_cfg = { 1398 .name = "qhs_imem_cfg", 1399 .channels = 1, 1400 .buswidth = 4, 1401 }; 1402 1403 static struct qcom_icc_node qhs_ipa = { 1404 .name = "qhs_ipa", 1405 .channels = 1, 1406 .buswidth = 4, 1407 }; 1408 1409 static struct qcom_icc_node qhs_ipc_router = { 1410 .name = "qhs_ipc_router", 1411 .channels = 1, 1412 .buswidth = 4, 1413 }; 1414 1415 static struct qcom_icc_node qhs_lpass_cfg = { 1416 .name = "qhs_lpass_cfg", 1417 .channels = 1, 1418 .buswidth = 4, 1419 .num_links = 1, 1420 .link_nodes = { &qhm_config_noc }, 1421 }; 1422 1423 static struct qcom_icc_node qhs_lpass_throttle_cfg = { 1424 .name = "qhs_lpass_throttle_cfg", 1425 .channels = 1, 1426 .buswidth = 4, 1427 }; 1428 1429 static struct qcom_icc_node qhs_mx_rdpm = { 1430 .name = "qhs_mx_rdpm", 1431 .channels = 1, 1432 .buswidth = 4, 1433 }; 1434 1435 static struct qcom_icc_node qhs_mxc_rdpm = { 1436 .name = "qhs_mxc_rdpm", 1437 .channels = 1, 1438 .buswidth = 4, 1439 }; 1440 1441 static struct qcom_icc_node qhs_pcie0_cfg = { 1442 .name = "qhs_pcie0_cfg", 1443 .channels = 1, 1444 .buswidth = 4, 1445 }; 1446 1447 static struct qcom_icc_node qhs_pcie1_cfg = { 1448 .name = "qhs_pcie1_cfg", 1449 .channels = 1, 1450 .buswidth = 4, 1451 }; 1452 1453 static struct qcom_icc_node qhs_pcie_rsc_cfg = { 1454 .name = "qhs_pcie_rsc_cfg", 1455 .channels = 1, 1456 .buswidth = 4, 1457 }; 1458 1459 static struct qcom_icc_node qhs_pcie_tcu_throttle_cfg = { 1460 .name = "qhs_pcie_tcu_throttle_cfg", 1461 .channels = 1, 1462 .buswidth = 4, 1463 }; 1464 1465 static struct qcom_icc_node qhs_pcie_throttle_cfg = { 1466 .name = "qhs_pcie_throttle_cfg", 1467 .channels = 1, 1468 .buswidth = 4, 1469 }; 1470 1471 static struct qcom_icc_node qhs_pdm = { 1472 .name = "qhs_pdm", 1473 .channels = 1, 1474 .buswidth = 4, 1475 }; 1476 1477 static struct qcom_icc_node qhs_pimem_cfg = { 1478 .name = "qhs_pimem_cfg", 1479 .channels = 1, 1480 .buswidth = 4, 1481 }; 1482 1483 static struct qcom_icc_node qhs_pke_wrapper_cfg = { 1484 .name = "qhs_pke_wrapper_cfg", 1485 .channels = 1, 1486 .buswidth = 4, 1487 }; 1488 1489 static struct qcom_icc_node qhs_qdss_cfg = { 1490 .name = "qhs_qdss_cfg", 1491 .channels = 1, 1492 .buswidth = 4, 1493 }; 1494 1495 static struct qcom_icc_node qhs_qm_cfg = { 1496 .name = "qhs_qm_cfg", 1497 .channels = 1, 1498 .buswidth = 4, 1499 }; 1500 1501 static struct qcom_icc_node qhs_qm_mpu_cfg = { 1502 .name = "qhs_qm_mpu_cfg", 1503 .channels = 1, 1504 .buswidth = 4, 1505 }; 1506 1507 static struct qcom_icc_node qhs_qup0 = { 1508 .name = "qhs_qup0", 1509 .channels = 1, 1510 .buswidth = 4, 1511 }; 1512 1513 static struct qcom_icc_node qhs_qup1 = { 1514 .name = "qhs_qup1", 1515 .channels = 1, 1516 .buswidth = 4, 1517 }; 1518 1519 static struct qcom_icc_node qhs_qup2 = { 1520 .name = "qhs_qup2", 1521 .channels = 1, 1522 .buswidth = 4, 1523 }; 1524 1525 static struct qcom_icc_node qhs_qup3 = { 1526 .name = "qhs_qup3", 1527 .channels = 1, 1528 .buswidth = 4, 1529 }; 1530 1531 static struct qcom_icc_node qhs_sail_throttle_cfg = { 1532 .name = "qhs_sail_throttle_cfg", 1533 .channels = 1, 1534 .buswidth = 4, 1535 }; 1536 1537 static struct qcom_icc_node qhs_sdc1 = { 1538 .name = "qhs_sdc1", 1539 .channels = 1, 1540 .buswidth = 4, 1541 }; 1542 1543 static struct qcom_icc_node qhs_security = { 1544 .name = "qhs_security", 1545 .channels = 1, 1546 .buswidth = 4, 1547 }; 1548 1549 static struct qcom_icc_node qhs_snoc_throttle_cfg = { 1550 .name = "qhs_snoc_throttle_cfg", 1551 .channels = 1, 1552 .buswidth = 4, 1553 }; 1554 1555 static struct qcom_icc_node qhs_tcsr = { 1556 .name = "qhs_tcsr", 1557 .channels = 1, 1558 .buswidth = 4, 1559 }; 1560 1561 static struct qcom_icc_node qhs_tlmm = { 1562 .name = "qhs_tlmm", 1563 .channels = 1, 1564 .buswidth = 4, 1565 }; 1566 1567 static struct qcom_icc_node qhs_tsc_cfg = { 1568 .name = "qhs_tsc_cfg", 1569 .channels = 1, 1570 .buswidth = 4, 1571 }; 1572 1573 static struct qcom_icc_node qhs_ufs_card_cfg = { 1574 .name = "qhs_ufs_card_cfg", 1575 .channels = 1, 1576 .buswidth = 4, 1577 }; 1578 1579 static struct qcom_icc_node qhs_ufs_mem_cfg = { 1580 .name = "qhs_ufs_mem_cfg", 1581 .channels = 1, 1582 .buswidth = 4, 1583 }; 1584 1585 static struct qcom_icc_node qhs_usb2_0 = { 1586 .name = "qhs_usb2_0", 1587 .channels = 1, 1588 .buswidth = 4, 1589 }; 1590 1591 static struct qcom_icc_node qhs_usb3_0 = { 1592 .name = "qhs_usb3_0", 1593 .channels = 1, 1594 .buswidth = 4, 1595 }; 1596 1597 static struct qcom_icc_node qhs_usb3_1 = { 1598 .name = "qhs_usb3_1", 1599 .channels = 1, 1600 .buswidth = 4, 1601 }; 1602 1603 static struct qcom_icc_node qhs_venus_cfg = { 1604 .name = "qhs_venus_cfg", 1605 .channels = 1, 1606 .buswidth = 4, 1607 }; 1608 1609 static struct qcom_icc_node qhs_venus_cvp_throttle_cfg = { 1610 .name = "qhs_venus_cvp_throttle_cfg", 1611 .channels = 1, 1612 .buswidth = 4, 1613 }; 1614 1615 static struct qcom_icc_node qhs_venus_v_cpu_throttle_cfg = { 1616 .name = "qhs_venus_v_cpu_throttle_cfg", 1617 .channels = 1, 1618 .buswidth = 4, 1619 }; 1620 1621 static struct qcom_icc_node qhs_venus_vcodec_throttle_cfg = { 1622 .name = "qhs_venus_vcodec_throttle_cfg", 1623 .channels = 1, 1624 .buswidth = 4, 1625 }; 1626 1627 static struct qcom_icc_node qns_ddrss_cfg = { 1628 .name = "qns_ddrss_cfg", 1629 .channels = 1, 1630 .buswidth = 4, 1631 .num_links = 1, 1632 .link_nodes = { &qnm_cnoc_dc_noc }, 1633 }; 1634 1635 static struct qcom_icc_node qns_gpdsp_noc_cfg = { 1636 .name = "qns_gpdsp_noc_cfg", 1637 .channels = 1, 1638 .buswidth = 4, 1639 }; 1640 1641 static struct qcom_icc_node qns_mnoc_hf_cfg = { 1642 .name = "qns_mnoc_hf_cfg", 1643 .channels = 1, 1644 .buswidth = 4, 1645 .num_links = 1, 1646 .link_nodes = { &qnm_mnoc_hf_cfg }, 1647 }; 1648 1649 static struct qcom_icc_node qns_mnoc_sf_cfg = { 1650 .name = "qns_mnoc_sf_cfg", 1651 .channels = 1, 1652 .buswidth = 4, 1653 .num_links = 1, 1654 .link_nodes = { &qnm_mnoc_sf_cfg }, 1655 }; 1656 1657 static struct qcom_icc_node qns_pcie_anoc_cfg = { 1658 .name = "qns_pcie_anoc_cfg", 1659 .channels = 1, 1660 .buswidth = 4, 1661 }; 1662 1663 static struct qcom_icc_node qns_snoc_cfg = { 1664 .name = "qns_snoc_cfg", 1665 .channels = 1, 1666 .buswidth = 4, 1667 .num_links = 1, 1668 .link_nodes = { &qnm_snoc_cfg }, 1669 }; 1670 1671 static struct qcom_icc_node qxs_boot_imem = { 1672 .name = "qxs_boot_imem", 1673 .channels = 1, 1674 .buswidth = 16, 1675 }; 1676 1677 static struct qcom_icc_node qxs_imem = { 1678 .name = "qxs_imem", 1679 .channels = 1, 1680 .buswidth = 8, 1681 }; 1682 1683 static struct qcom_icc_node qxs_pimem = { 1684 .name = "qxs_pimem", 1685 .channels = 1, 1686 .buswidth = 8, 1687 }; 1688 1689 static struct qcom_icc_node xs_pcie_0 = { 1690 .name = "xs_pcie_0", 1691 .channels = 1, 1692 .buswidth = 16, 1693 }; 1694 1695 static struct qcom_icc_node xs_pcie_1 = { 1696 .name = "xs_pcie_1", 1697 .channels = 1, 1698 .buswidth = 32, 1699 }; 1700 1701 static struct qcom_icc_node xs_qdss_stm = { 1702 .name = "xs_qdss_stm", 1703 .channels = 1, 1704 .buswidth = 4, 1705 }; 1706 1707 static struct qcom_icc_node xs_sys_tcu_cfg = { 1708 .name = "xs_sys_tcu_cfg", 1709 .channels = 1, 1710 .buswidth = 8, 1711 }; 1712 1713 static struct qcom_icc_node qhs_llcc = { 1714 .name = "qhs_llcc", 1715 .channels = 1, 1716 .buswidth = 4, 1717 }; 1718 1719 static struct qcom_icc_node qns_gemnoc = { 1720 .name = "qns_gemnoc", 1721 .channels = 1, 1722 .buswidth = 4, 1723 .num_links = 1, 1724 .link_nodes = { &qnm_gemnoc_cfg }, 1725 }; 1726 1727 static struct qcom_icc_node qns_gem_noc_cnoc = { 1728 .name = "qns_gem_noc_cnoc", 1729 .channels = 1, 1730 .buswidth = 16, 1731 .num_links = 1, 1732 .link_nodes = { &qnm_gemnoc_cnoc }, 1733 }; 1734 1735 static struct qcom_icc_node qns_llcc = { 1736 .name = "qns_llcc", 1737 .channels = 6, 1738 .buswidth = 16, 1739 .num_links = 1, 1740 .link_nodes = { &llcc_mc }, 1741 }; 1742 1743 static struct qcom_icc_node qns_pcie = { 1744 .name = "qns_pcie", 1745 .channels = 1, 1746 .buswidth = 16, 1747 .num_links = 1, 1748 .link_nodes = { &qnm_gemnoc_pcie }, 1749 }; 1750 1751 static struct qcom_icc_node srvc_even_gemnoc = { 1752 .name = "srvc_even_gemnoc", 1753 .channels = 1, 1754 .buswidth = 4, 1755 }; 1756 1757 static struct qcom_icc_node srvc_odd_gemnoc = { 1758 .name = "srvc_odd_gemnoc", 1759 .channels = 1, 1760 .buswidth = 4, 1761 }; 1762 1763 static struct qcom_icc_node srvc_sys_gemnoc = { 1764 .name = "srvc_sys_gemnoc", 1765 .channels = 1, 1766 .buswidth = 4, 1767 }; 1768 1769 static struct qcom_icc_node srvc_sys_gemnoc_2 = { 1770 .name = "srvc_sys_gemnoc_2", 1771 .channels = 1, 1772 .buswidth = 4, 1773 }; 1774 1775 static struct qcom_icc_node qns_gp_dsp_sail_noc = { 1776 .name = "qns_gp_dsp_sail_noc", 1777 .channels = 1, 1778 .buswidth = 16, 1779 .num_links = 1, 1780 .link_nodes = { &qnm_gpdsp_sail }, 1781 }; 1782 1783 static struct qcom_icc_node qhs_lpass_core = { 1784 .name = "qhs_lpass_core", 1785 .channels = 1, 1786 .buswidth = 4, 1787 }; 1788 1789 static struct qcom_icc_node qhs_lpass_lpi = { 1790 .name = "qhs_lpass_lpi", 1791 .channels = 1, 1792 .buswidth = 4, 1793 }; 1794 1795 static struct qcom_icc_node qhs_lpass_mpu = { 1796 .name = "qhs_lpass_mpu", 1797 .channels = 1, 1798 .buswidth = 4, 1799 }; 1800 1801 static struct qcom_icc_node qhs_lpass_top = { 1802 .name = "qhs_lpass_top", 1803 .channels = 1, 1804 .buswidth = 4, 1805 }; 1806 1807 static struct qcom_icc_node qns_sysnoc = { 1808 .name = "qns_sysnoc", 1809 .channels = 1, 1810 .buswidth = 16, 1811 .num_links = 1, 1812 .link_nodes = { &qnm_lpass_noc }, 1813 }; 1814 1815 static struct qcom_icc_node srvc_niu_aml_noc = { 1816 .name = "srvc_niu_aml_noc", 1817 .channels = 1, 1818 .buswidth = 4, 1819 }; 1820 1821 static struct qcom_icc_node srvc_niu_lpass_agnoc = { 1822 .name = "srvc_niu_lpass_agnoc", 1823 .channels = 1, 1824 .buswidth = 4, 1825 }; 1826 1827 static struct qcom_icc_node ebi = { 1828 .name = "ebi", 1829 .channels = 8, 1830 .buswidth = 4, 1831 }; 1832 1833 static struct qcom_icc_node qns_mem_noc_hf = { 1834 .name = "qns_mem_noc_hf", 1835 .channels = 2, 1836 .buswidth = 32, 1837 .num_links = 1, 1838 .link_nodes = { &qnm_mnoc_hf }, 1839 }; 1840 1841 static struct qcom_icc_node qns_mem_noc_sf = { 1842 .name = "qns_mem_noc_sf", 1843 .channels = 2, 1844 .buswidth = 32, 1845 .num_links = 1, 1846 .link_nodes = { &qnm_mnoc_sf }, 1847 }; 1848 1849 static struct qcom_icc_node srvc_mnoc_hf = { 1850 .name = "srvc_mnoc_hf", 1851 .channels = 1, 1852 .buswidth = 4, 1853 }; 1854 1855 static struct qcom_icc_node srvc_mnoc_sf = { 1856 .name = "srvc_mnoc_sf", 1857 .channels = 1, 1858 .buswidth = 4, 1859 }; 1860 1861 static struct qcom_icc_node qns_hcp = { 1862 .name = "qns_hcp", 1863 .channels = 2, 1864 .buswidth = 32, 1865 }; 1866 1867 static struct qcom_icc_node qns_nsp_gemnoc = { 1868 .name = "qns_nsp_gemnoc", 1869 .channels = 2, 1870 .buswidth = 32, 1871 .num_links = 1, 1872 .link_nodes = { &qnm_cmpnoc0 }, 1873 }; 1874 1875 static struct qcom_icc_node service_nsp_noc = { 1876 .name = "service_nsp_noc", 1877 .channels = 1, 1878 .buswidth = 4, 1879 }; 1880 1881 static struct qcom_icc_node qns_nspb_gemnoc = { 1882 .name = "qns_nspb_gemnoc", 1883 .channels = 2, 1884 .buswidth = 32, 1885 .num_links = 1, 1886 .link_nodes = { &qnm_cmpnoc1 }, 1887 }; 1888 1889 static struct qcom_icc_node qns_nspb_hcp = { 1890 .name = "qns_nspb_hcp", 1891 .channels = 2, 1892 .buswidth = 32, 1893 }; 1894 1895 static struct qcom_icc_node service_nspb_noc = { 1896 .name = "service_nspb_noc", 1897 .channels = 1, 1898 .buswidth = 4, 1899 }; 1900 1901 static struct qcom_icc_node qns_pcie_mem_noc = { 1902 .name = "qns_pcie_mem_noc", 1903 .channels = 1, 1904 .buswidth = 32, 1905 .num_links = 1, 1906 .link_nodes = { &qnm_pcie }, 1907 }; 1908 1909 static struct qcom_icc_node qns_gemnoc_gc = { 1910 .name = "qns_gemnoc_gc", 1911 .channels = 1, 1912 .buswidth = 8, 1913 .num_links = 1, 1914 .link_nodes = { &qnm_snoc_gc }, 1915 }; 1916 1917 static struct qcom_icc_node qns_gemnoc_sf = { 1918 .name = "qns_gemnoc_sf", 1919 .channels = 1, 1920 .buswidth = 16, 1921 .num_links = 1, 1922 .link_nodes = { &qnm_snoc_sf }, 1923 }; 1924 1925 static struct qcom_icc_node srvc_snoc = { 1926 .name = "srvc_snoc", 1927 .channels = 1, 1928 .buswidth = 4, 1929 }; 1930 1931 static struct qcom_icc_bcm bcm_acv = { 1932 .name = "ACV", 1933 .enable_mask = 0x8, 1934 .num_nodes = 1, 1935 .nodes = { &ebi }, 1936 }; 1937 1938 static struct qcom_icc_bcm bcm_ce0 = { 1939 .name = "CE0", 1940 .num_nodes = 2, 1941 .nodes = { &qxm_crypto_0, &qxm_crypto_1 }, 1942 }; 1943 1944 static struct qcom_icc_bcm bcm_cn0 = { 1945 .name = "CN0", 1946 .keepalive = true, 1947 .num_nodes = 2, 1948 .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie }, 1949 }; 1950 1951 static struct qcom_icc_bcm bcm_cn1 = { 1952 .name = "CN1", 1953 .num_nodes = 76, 1954 .nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, 1955 &qhs_ahb2phy2, &qhs_ahb2phy3, 1956 &qhs_anoc_throttle_cfg, &qhs_aoss, 1957 &qhs_apss, &qhs_boot_rom, 1958 &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg, 1959 &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, 1960 &qhs_compute0_cfg, &qhs_compute1_cfg, 1961 &qhs_cpr_cx, &qhs_cpr_mmcx, 1962 &qhs_cpr_mx, &qhs_cpr_nspcx, 1963 &qhs_crypto0_cfg, &qhs_cx_rdpm, 1964 &qhs_display0_cfg, &qhs_display0_rt_throttle_cfg, 1965 &qhs_display1_cfg, &qhs_display1_rt_throttle_cfg, 1966 &qhs_emac0_cfg, &qhs_emac1_cfg, 1967 &qhs_gp_dsp0_cfg, &qhs_gp_dsp1_cfg, 1968 &qhs_gpdsp0_throttle_cfg, &qhs_gpdsp1_throttle_cfg, 1969 &qhs_gpu_tcu_throttle_cfg, &qhs_gpuss_cfg, 1970 &qhs_hwkm, &qhs_imem_cfg, 1971 &qhs_ipa, &qhs_ipc_router, 1972 &qhs_lpass_cfg, &qhs_lpass_throttle_cfg, 1973 &qhs_mx_rdpm, &qhs_mxc_rdpm, 1974 &qhs_pcie0_cfg, &qhs_pcie1_cfg, 1975 &qhs_pcie_rsc_cfg, &qhs_pcie_tcu_throttle_cfg, 1976 &qhs_pcie_throttle_cfg, &qhs_pdm, 1977 &qhs_pimem_cfg, &qhs_pke_wrapper_cfg, 1978 &qhs_qdss_cfg, &qhs_qm_cfg, 1979 &qhs_qm_mpu_cfg, &qhs_sail_throttle_cfg, 1980 &qhs_sdc1, &qhs_security, 1981 &qhs_snoc_throttle_cfg, &qhs_tcsr, 1982 &qhs_tlmm, &qhs_tsc_cfg, 1983 &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, 1984 &qhs_usb2_0, &qhs_usb3_0, 1985 &qhs_usb3_1, &qhs_venus_cfg, 1986 &qhs_venus_cvp_throttle_cfg, &qhs_venus_v_cpu_throttle_cfg, 1987 &qhs_venus_vcodec_throttle_cfg, &qns_ddrss_cfg, 1988 &qns_gpdsp_noc_cfg, &qns_mnoc_hf_cfg, 1989 &qns_mnoc_sf_cfg, &qns_pcie_anoc_cfg, 1990 &qns_snoc_cfg, &qxs_boot_imem, 1991 &qxs_imem, &xs_sys_tcu_cfg }, 1992 }; 1993 1994 static struct qcom_icc_bcm bcm_cn2 = { 1995 .name = "CN2", 1996 .num_nodes = 4, 1997 .nodes = { &qhs_qup0, &qhs_qup1, 1998 &qhs_qup2, &qhs_qup3 }, 1999 }; 2000 2001 static struct qcom_icc_bcm bcm_cn3 = { 2002 .name = "CN3", 2003 .num_nodes = 2, 2004 .nodes = { &xs_pcie_0, &xs_pcie_1 }, 2005 }; 2006 2007 static struct qcom_icc_bcm bcm_gna0 = { 2008 .name = "GNA0", 2009 .num_nodes = 1, 2010 .nodes = { &qxm_dsp0 }, 2011 }; 2012 2013 static struct qcom_icc_bcm bcm_gnb0 = { 2014 .name = "GNB0", 2015 .num_nodes = 1, 2016 .nodes = { &qxm_dsp1 }, 2017 }; 2018 2019 static struct qcom_icc_bcm bcm_mc0 = { 2020 .name = "MC0", 2021 .keepalive = true, 2022 .num_nodes = 1, 2023 .nodes = { &ebi }, 2024 }; 2025 2026 static struct qcom_icc_bcm bcm_mm0 = { 2027 .name = "MM0", 2028 .keepalive = true, 2029 .num_nodes = 5, 2030 .nodes = { &qnm_camnoc_hf, &qnm_mdp0_0, 2031 &qnm_mdp0_1, &qnm_mdp1_0, 2032 &qns_mem_noc_hf }, 2033 }; 2034 2035 static struct qcom_icc_bcm bcm_mm1 = { 2036 .name = "MM1", 2037 .num_nodes = 7, 2038 .nodes = { &qnm_camnoc_icp, &qnm_camnoc_sf, 2039 &qnm_video0, &qnm_video1, 2040 &qnm_video_cvp, &qnm_video_v_cpu, 2041 &qns_mem_noc_sf }, 2042 }; 2043 2044 static struct qcom_icc_bcm bcm_nsa0 = { 2045 .name = "NSA0", 2046 .num_nodes = 2, 2047 .nodes = { &qns_hcp, &qns_nsp_gemnoc }, 2048 }; 2049 2050 static struct qcom_icc_bcm bcm_nsa1 = { 2051 .name = "NSA1", 2052 .num_nodes = 1, 2053 .nodes = { &qxm_nsp }, 2054 }; 2055 2056 static struct qcom_icc_bcm bcm_nsb0 = { 2057 .name = "NSB0", 2058 .num_nodes = 2, 2059 .nodes = { &qns_nspb_gemnoc, &qns_nspb_hcp }, 2060 }; 2061 2062 static struct qcom_icc_bcm bcm_nsb1 = { 2063 .name = "NSB1", 2064 .num_nodes = 1, 2065 .nodes = { &qxm_nspb }, 2066 }; 2067 2068 static struct qcom_icc_bcm bcm_pci0 = { 2069 .name = "PCI0", 2070 .num_nodes = 1, 2071 .nodes = { &qns_pcie_mem_noc }, 2072 }; 2073 2074 static struct qcom_icc_bcm bcm_qup0 = { 2075 .name = "QUP0", 2076 .vote_scale = 1, 2077 .num_nodes = 1, 2078 .nodes = { &qup0_core_slave }, 2079 }; 2080 2081 static struct qcom_icc_bcm bcm_qup1 = { 2082 .name = "QUP1", 2083 .vote_scale = 1, 2084 .num_nodes = 1, 2085 .nodes = { &qup1_core_slave }, 2086 }; 2087 2088 static struct qcom_icc_bcm bcm_qup2 = { 2089 .name = "QUP2", 2090 .vote_scale = 1, 2091 .num_nodes = 2, 2092 .nodes = { &qup2_core_slave, &qup3_core_slave }, 2093 }; 2094 2095 static struct qcom_icc_bcm bcm_sh0 = { 2096 .name = "SH0", 2097 .keepalive = true, 2098 .num_nodes = 1, 2099 .nodes = { &qns_llcc }, 2100 }; 2101 2102 static struct qcom_icc_bcm bcm_sh2 = { 2103 .name = "SH2", 2104 .num_nodes = 1, 2105 .nodes = { &chm_apps }, 2106 }; 2107 2108 static struct qcom_icc_bcm bcm_sn0 = { 2109 .name = "SN0", 2110 .keepalive = true, 2111 .num_nodes = 1, 2112 .nodes = { &qns_gemnoc_sf }, 2113 }; 2114 2115 static struct qcom_icc_bcm bcm_sn1 = { 2116 .name = "SN1", 2117 .num_nodes = 1, 2118 .nodes = { &qns_gemnoc_gc }, 2119 }; 2120 2121 static struct qcom_icc_bcm bcm_sn2 = { 2122 .name = "SN2", 2123 .num_nodes = 1, 2124 .nodes = { &qxs_pimem }, 2125 }; 2126 2127 static struct qcom_icc_bcm bcm_sn3 = { 2128 .name = "SN3", 2129 .num_nodes = 2, 2130 .nodes = { &qns_a1noc_snoc, &qnm_aggre1_noc }, 2131 }; 2132 2133 static struct qcom_icc_bcm bcm_sn4 = { 2134 .name = "SN4", 2135 .num_nodes = 2, 2136 .nodes = { &qns_a2noc_snoc, &qnm_aggre2_noc }, 2137 }; 2138 2139 static struct qcom_icc_bcm bcm_sn9 = { 2140 .name = "SN9", 2141 .num_nodes = 2, 2142 .nodes = { &qns_sysnoc, &qnm_lpass_noc }, 2143 }; 2144 2145 static struct qcom_icc_bcm bcm_sn10 = { 2146 .name = "SN10", 2147 .num_nodes = 1, 2148 .nodes = { &xs_qdss_stm }, 2149 }; 2150 2151 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 2152 &bcm_sn3, 2153 }; 2154 2155 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 2156 [MASTER_QUP_3] = &qxm_qup3, 2157 [MASTER_EMAC] = &xm_emac_0, 2158 [MASTER_EMAC_1] = &xm_emac_1, 2159 [MASTER_SDC] = &xm_sdc1, 2160 [MASTER_UFS_MEM] = &xm_ufs_mem, 2161 [MASTER_USB2] = &xm_usb2_2, 2162 [MASTER_USB3_0] = &xm_usb3_0, 2163 [MASTER_USB3_1] = &xm_usb3_1, 2164 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, 2165 }; 2166 2167 static const struct regmap_config sa8775p_aggre1_noc_regmap_config = { 2168 .reg_bits = 32, 2169 .reg_stride = 4, 2170 .val_bits = 32, 2171 .max_register = 0x18080, 2172 .fast_io = true, 2173 }; 2174 2175 static const struct qcom_icc_desc sa8775p_aggre1_noc = { 2176 .config = &sa8775p_aggre1_noc_regmap_config, 2177 .nodes = aggre1_noc_nodes, 2178 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 2179 .bcms = aggre1_noc_bcms, 2180 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 2181 .qos_requires_clocks = true, 2182 }; 2183 2184 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 2185 &bcm_ce0, 2186 &bcm_sn4, 2187 }; 2188 2189 static struct qcom_icc_node * const aggre2_noc_nodes[] = { 2190 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 2191 [MASTER_QUP_0] = &qhm_qup0, 2192 [MASTER_QUP_1] = &qhm_qup1, 2193 [MASTER_QUP_2] = &qhm_qup2, 2194 [MASTER_CNOC_A2NOC] = &qnm_cnoc_datapath, 2195 [MASTER_CRYPTO_CORE0] = &qxm_crypto_0, 2196 [MASTER_CRYPTO_CORE1] = &qxm_crypto_1, 2197 [MASTER_IPA] = &qxm_ipa, 2198 [MASTER_QDSS_ETR_0] = &xm_qdss_etr_0, 2199 [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1, 2200 [MASTER_UFS_CARD] = &xm_ufs_card, 2201 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, 2202 }; 2203 2204 static const struct regmap_config sa8775p_aggre2_noc_regmap_config = { 2205 .reg_bits = 32, 2206 .reg_stride = 4, 2207 .val_bits = 32, 2208 .max_register = 0x1b080, 2209 .fast_io = true, 2210 }; 2211 2212 static const struct qcom_icc_desc sa8775p_aggre2_noc = { 2213 .config = &sa8775p_aggre2_noc_regmap_config, 2214 .nodes = aggre2_noc_nodes, 2215 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 2216 .bcms = aggre2_noc_bcms, 2217 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 2218 .qos_requires_clocks = true, 2219 }; 2220 2221 static struct qcom_icc_bcm * const clk_virt_bcms[] = { 2222 &bcm_qup0, 2223 &bcm_qup1, 2224 &bcm_qup2, 2225 }; 2226 2227 static struct qcom_icc_node * const clk_virt_nodes[] = { 2228 [MASTER_QUP_CORE_0] = &qup0_core_master, 2229 [MASTER_QUP_CORE_1] = &qup1_core_master, 2230 [MASTER_QUP_CORE_2] = &qup2_core_master, 2231 [MASTER_QUP_CORE_3] = &qup3_core_master, 2232 [SLAVE_QUP_CORE_0] = &qup0_core_slave, 2233 [SLAVE_QUP_CORE_1] = &qup1_core_slave, 2234 [SLAVE_QUP_CORE_2] = &qup2_core_slave, 2235 [SLAVE_QUP_CORE_3] = &qup3_core_slave, 2236 }; 2237 2238 static const struct qcom_icc_desc sa8775p_clk_virt = { 2239 .nodes = clk_virt_nodes, 2240 .num_nodes = ARRAY_SIZE(clk_virt_nodes), 2241 .bcms = clk_virt_bcms, 2242 .num_bcms = ARRAY_SIZE(clk_virt_bcms), 2243 }; 2244 2245 static struct qcom_icc_bcm * const config_noc_bcms[] = { 2246 &bcm_cn0, 2247 &bcm_cn1, 2248 &bcm_cn2, 2249 &bcm_cn3, 2250 &bcm_sn2, 2251 &bcm_sn10, 2252 }; 2253 2254 static struct qcom_icc_node * const config_noc_nodes[] = { 2255 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, 2256 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, 2257 [SLAVE_AHB2PHY_0] = &qhs_ahb2phy0, 2258 [SLAVE_AHB2PHY_1] = &qhs_ahb2phy1, 2259 [SLAVE_AHB2PHY_2] = &qhs_ahb2phy2, 2260 [SLAVE_AHB2PHY_3] = &qhs_ahb2phy3, 2261 [SLAVE_ANOC_THROTTLE_CFG] = &qhs_anoc_throttle_cfg, 2262 [SLAVE_AOSS] = &qhs_aoss, 2263 [SLAVE_APPSS] = &qhs_apss, 2264 [SLAVE_BOOT_ROM] = &qhs_boot_rom, 2265 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 2266 [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_throttle_cfg, 2267 [SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg, 2268 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 2269 [SLAVE_CDSP_CFG] = &qhs_compute0_cfg, 2270 [SLAVE_CDSP1_CFG] = &qhs_compute1_cfg, 2271 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 2272 [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx, 2273 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, 2274 [SLAVE_CPR_NSPCX] = &qhs_cpr_nspcx, 2275 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 2276 [SLAVE_CX_RDPM] = &qhs_cx_rdpm, 2277 [SLAVE_DISPLAY_CFG] = &qhs_display0_cfg, 2278 [SLAVE_DISPLAY_RT_THROTTLE_CFG] = &qhs_display0_rt_throttle_cfg, 2279 [SLAVE_DISPLAY1_CFG] = &qhs_display1_cfg, 2280 [SLAVE_DISPLAY1_RT_THROTTLE_CFG] = &qhs_display1_rt_throttle_cfg, 2281 [SLAVE_EMAC_CFG] = &qhs_emac0_cfg, 2282 [SLAVE_EMAC1_CFG] = &qhs_emac1_cfg, 2283 [SLAVE_GP_DSP0_CFG] = &qhs_gp_dsp0_cfg, 2284 [SLAVE_GP_DSP1_CFG] = &qhs_gp_dsp1_cfg, 2285 [SLAVE_GPDSP0_THROTTLE_CFG] = &qhs_gpdsp0_throttle_cfg, 2286 [SLAVE_GPDSP1_THROTTLE_CFG] = &qhs_gpdsp1_throttle_cfg, 2287 [SLAVE_GPU_TCU_THROTTLE_CFG] = &qhs_gpu_tcu_throttle_cfg, 2288 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, 2289 [SLAVE_HWKM] = &qhs_hwkm, 2290 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 2291 [SLAVE_IPA_CFG] = &qhs_ipa, 2292 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, 2293 [SLAVE_LPASS] = &qhs_lpass_cfg, 2294 [SLAVE_LPASS_THROTTLE_CFG] = &qhs_lpass_throttle_cfg, 2295 [SLAVE_MX_RDPM] = &qhs_mx_rdpm, 2296 [SLAVE_MXC_RDPM] = &qhs_mxc_rdpm, 2297 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, 2298 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, 2299 [SLAVE_PCIE_RSC_CFG] = &qhs_pcie_rsc_cfg, 2300 [SLAVE_PCIE_TCU_THROTTLE_CFG] = &qhs_pcie_tcu_throttle_cfg, 2301 [SLAVE_PCIE_THROTTLE_CFG] = &qhs_pcie_throttle_cfg, 2302 [SLAVE_PDM] = &qhs_pdm, 2303 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 2304 [SLAVE_PKA_WRAPPER_CFG] = &qhs_pke_wrapper_cfg, 2305 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 2306 [SLAVE_QM_CFG] = &qhs_qm_cfg, 2307 [SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg, 2308 [SLAVE_QUP_0] = &qhs_qup0, 2309 [SLAVE_QUP_1] = &qhs_qup1, 2310 [SLAVE_QUP_2] = &qhs_qup2, 2311 [SLAVE_QUP_3] = &qhs_qup3, 2312 [SLAVE_SAIL_THROTTLE_CFG] = &qhs_sail_throttle_cfg, 2313 [SLAVE_SDC1] = &qhs_sdc1, 2314 [SLAVE_SECURITY] = &qhs_security, 2315 [SLAVE_SNOC_THROTTLE_CFG] = &qhs_snoc_throttle_cfg, 2316 [SLAVE_TCSR] = &qhs_tcsr, 2317 [SLAVE_TLMM] = &qhs_tlmm, 2318 [SLAVE_TSC_CFG] = &qhs_tsc_cfg, 2319 [SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg, 2320 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 2321 [SLAVE_USB2] = &qhs_usb2_0, 2322 [SLAVE_USB3_0] = &qhs_usb3_0, 2323 [SLAVE_USB3_1] = &qhs_usb3_1, 2324 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 2325 [SLAVE_VENUS_CVP_THROTTLE_CFG] = &qhs_venus_cvp_throttle_cfg, 2326 [SLAVE_VENUS_V_CPU_THROTTLE_CFG] = &qhs_venus_v_cpu_throttle_cfg, 2327 [SLAVE_VENUS_VCODEC_THROTTLE_CFG] = &qhs_venus_vcodec_throttle_cfg, 2328 [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg, 2329 [SLAVE_GPDSP_NOC_CFG] = &qns_gpdsp_noc_cfg, 2330 [SLAVE_CNOC_MNOC_HF_CFG] = &qns_mnoc_hf_cfg, 2331 [SLAVE_CNOC_MNOC_SF_CFG] = &qns_mnoc_sf_cfg, 2332 [SLAVE_PCIE_ANOC_CFG] = &qns_pcie_anoc_cfg, 2333 [SLAVE_SNOC_CFG] = &qns_snoc_cfg, 2334 [SLAVE_BOOT_IMEM] = &qxs_boot_imem, 2335 [SLAVE_IMEM] = &qxs_imem, 2336 [SLAVE_PIMEM] = &qxs_pimem, 2337 [SLAVE_PCIE_0] = &xs_pcie_0, 2338 [SLAVE_PCIE_1] = &xs_pcie_1, 2339 [SLAVE_QDSS_STM] = &xs_qdss_stm, 2340 [SLAVE_TCU] = &xs_sys_tcu_cfg, 2341 }; 2342 2343 static const struct regmap_config sa8775p_config_noc_regmap_config = { 2344 .reg_bits = 32, 2345 .reg_stride = 4, 2346 .val_bits = 32, 2347 .max_register = 0x13080, 2348 .fast_io = true, 2349 }; 2350 2351 static const struct qcom_icc_desc sa8775p_config_noc = { 2352 .config = &sa8775p_config_noc_regmap_config, 2353 .nodes = config_noc_nodes, 2354 .num_nodes = ARRAY_SIZE(config_noc_nodes), 2355 .bcms = config_noc_bcms, 2356 .num_bcms = ARRAY_SIZE(config_noc_bcms), 2357 }; 2358 2359 static struct qcom_icc_bcm * const dc_noc_bcms[] = { 2360 }; 2361 2362 static struct qcom_icc_node * const dc_noc_nodes[] = { 2363 [MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc, 2364 [SLAVE_LLCC_CFG] = &qhs_llcc, 2365 [SLAVE_GEM_NOC_CFG] = &qns_gemnoc, 2366 }; 2367 2368 static const struct regmap_config sa8775p_dc_noc_regmap_config = { 2369 .reg_bits = 32, 2370 .reg_stride = 4, 2371 .val_bits = 32, 2372 .max_register = 0x5080, 2373 .fast_io = true, 2374 }; 2375 2376 static const struct qcom_icc_desc sa8775p_dc_noc = { 2377 .config = &sa8775p_dc_noc_regmap_config, 2378 .nodes = dc_noc_nodes, 2379 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 2380 .bcms = dc_noc_bcms, 2381 .num_bcms = ARRAY_SIZE(dc_noc_bcms), 2382 }; 2383 2384 static struct qcom_icc_bcm * const gem_noc_bcms[] = { 2385 &bcm_sh0, 2386 &bcm_sh2, 2387 }; 2388 2389 static struct qcom_icc_node * const gem_noc_nodes[] = { 2390 [MASTER_GPU_TCU] = &alm_gpu_tcu, 2391 [MASTER_PCIE_TCU] = &alm_pcie_tcu, 2392 [MASTER_SYS_TCU] = &alm_sys_tcu, 2393 [MASTER_APPSS_PROC] = &chm_apps, 2394 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc0, 2395 [MASTER_COMPUTE_NOC_1] = &qnm_cmpnoc1, 2396 [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg, 2397 [MASTER_GPDSP_SAIL] = &qnm_gpdsp_sail, 2398 [MASTER_GFX3D] = &qnm_gpu, 2399 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 2400 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 2401 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, 2402 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 2403 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 2404 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, 2405 [SLAVE_LLCC] = &qns_llcc, 2406 [SLAVE_GEM_NOC_PCIE_CNOC] = &qns_pcie, 2407 [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc, 2408 [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc, 2409 [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc, 2410 [SLAVE_SERVICE_GEM_NOC2] = &srvc_sys_gemnoc_2, 2411 }; 2412 2413 static const struct regmap_config sa8775p_gem_noc_regmap_config = { 2414 .reg_bits = 32, 2415 .reg_stride = 4, 2416 .val_bits = 32, 2417 .max_register = 0xf6080, 2418 .fast_io = true, 2419 }; 2420 2421 static const struct qcom_icc_desc sa8775p_gem_noc = { 2422 .config = &sa8775p_gem_noc_regmap_config, 2423 .nodes = gem_noc_nodes, 2424 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 2425 .bcms = gem_noc_bcms, 2426 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 2427 }; 2428 2429 static struct qcom_icc_bcm * const gpdsp_anoc_bcms[] = { 2430 &bcm_gna0, 2431 &bcm_gnb0, 2432 }; 2433 2434 static struct qcom_icc_node * const gpdsp_anoc_nodes[] = { 2435 [MASTER_DSP0] = &qxm_dsp0, 2436 [MASTER_DSP1] = &qxm_dsp1, 2437 [SLAVE_GP_DSP_SAIL_NOC] = &qns_gp_dsp_sail_noc, 2438 }; 2439 2440 static const struct regmap_config sa8775p_gpdsp_anoc_regmap_config = { 2441 .reg_bits = 32, 2442 .reg_stride = 4, 2443 .val_bits = 32, 2444 .max_register = 0xe080, 2445 .fast_io = true, 2446 }; 2447 2448 static const struct qcom_icc_desc sa8775p_gpdsp_anoc = { 2449 .config = &sa8775p_gpdsp_anoc_regmap_config, 2450 .nodes = gpdsp_anoc_nodes, 2451 .num_nodes = ARRAY_SIZE(gpdsp_anoc_nodes), 2452 .bcms = gpdsp_anoc_bcms, 2453 .num_bcms = ARRAY_SIZE(gpdsp_anoc_bcms), 2454 }; 2455 2456 static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = { 2457 &bcm_sn9, 2458 }; 2459 2460 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { 2461 [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc, 2462 [MASTER_LPASS_PROC] = &qxm_lpass_dsp, 2463 [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core, 2464 [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi, 2465 [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu, 2466 [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top, 2467 [SLAVE_LPASS_SNOC] = &qns_sysnoc, 2468 [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc, 2469 [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, 2470 }; 2471 2472 static const struct regmap_config sa8775p_lpass_ag_noc_regmap_config = { 2473 .reg_bits = 32, 2474 .reg_stride = 4, 2475 .val_bits = 32, 2476 .max_register = 0x17200, 2477 .fast_io = true, 2478 }; 2479 2480 static const struct qcom_icc_desc sa8775p_lpass_ag_noc = { 2481 .config = &sa8775p_lpass_ag_noc_regmap_config, 2482 .nodes = lpass_ag_noc_nodes, 2483 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), 2484 .bcms = lpass_ag_noc_bcms, 2485 .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms), 2486 }; 2487 2488 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 2489 &bcm_acv, 2490 &bcm_mc0, 2491 }; 2492 2493 static struct qcom_icc_node * const mc_virt_nodes[] = { 2494 [MASTER_LLCC] = &llcc_mc, 2495 [SLAVE_EBI1] = &ebi, 2496 }; 2497 2498 static const struct qcom_icc_desc sa8775p_mc_virt = { 2499 .nodes = mc_virt_nodes, 2500 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 2501 .bcms = mc_virt_bcms, 2502 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 2503 }; 2504 2505 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 2506 &bcm_mm0, 2507 &bcm_mm1, 2508 }; 2509 2510 static struct qcom_icc_node * const mmss_noc_nodes[] = { 2511 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, 2512 [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp, 2513 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, 2514 [MASTER_MDP0] = &qnm_mdp0_0, 2515 [MASTER_MDP1] = &qnm_mdp0_1, 2516 [MASTER_MDP_CORE1_0] = &qnm_mdp1_0, 2517 [MASTER_MDP_CORE1_1] = &qnm_mdp1_1, 2518 [MASTER_CNOC_MNOC_HF_CFG] = &qnm_mnoc_hf_cfg, 2519 [MASTER_CNOC_MNOC_SF_CFG] = &qnm_mnoc_sf_cfg, 2520 [MASTER_VIDEO_P0] = &qnm_video0, 2521 [MASTER_VIDEO_P1] = &qnm_video1, 2522 [MASTER_VIDEO_PROC] = &qnm_video_cvp, 2523 [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu, 2524 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 2525 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, 2526 [SLAVE_SERVICE_MNOC_HF] = &srvc_mnoc_hf, 2527 [SLAVE_SERVICE_MNOC_SF] = &srvc_mnoc_sf, 2528 }; 2529 2530 static const struct regmap_config sa8775p_mmss_noc_regmap_config = { 2531 .reg_bits = 32, 2532 .reg_stride = 4, 2533 .val_bits = 32, 2534 .max_register = 0x40000, 2535 .fast_io = true, 2536 }; 2537 2538 static const struct qcom_icc_desc sa8775p_mmss_noc = { 2539 .config = &sa8775p_mmss_noc_regmap_config, 2540 .nodes = mmss_noc_nodes, 2541 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 2542 .bcms = mmss_noc_bcms, 2543 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 2544 }; 2545 2546 static struct qcom_icc_bcm * const nspa_noc_bcms[] = { 2547 &bcm_nsa0, 2548 &bcm_nsa1, 2549 }; 2550 2551 static struct qcom_icc_node * const nspa_noc_nodes[] = { 2552 [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config, 2553 [MASTER_CDSP_PROC] = &qxm_nsp, 2554 [SLAVE_HCP_A] = &qns_hcp, 2555 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, 2556 [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, 2557 }; 2558 2559 static const struct regmap_config sa8775p_nspa_noc_regmap_config = { 2560 .reg_bits = 32, 2561 .reg_stride = 4, 2562 .val_bits = 32, 2563 .max_register = 0x16080, 2564 .fast_io = true, 2565 }; 2566 2567 static const struct qcom_icc_desc sa8775p_nspa_noc = { 2568 .config = &sa8775p_nspa_noc_regmap_config, 2569 .nodes = nspa_noc_nodes, 2570 .num_nodes = ARRAY_SIZE(nspa_noc_nodes), 2571 .bcms = nspa_noc_bcms, 2572 .num_bcms = ARRAY_SIZE(nspa_noc_bcms), 2573 }; 2574 2575 static struct qcom_icc_bcm * const nspb_noc_bcms[] = { 2576 &bcm_nsb0, 2577 &bcm_nsb1, 2578 }; 2579 2580 static const struct regmap_config sa8775p_nspb_noc_regmap_config = { 2581 .reg_bits = 32, 2582 .reg_stride = 4, 2583 .val_bits = 32, 2584 .max_register = 0x16080, 2585 .fast_io = true, 2586 }; 2587 2588 static struct qcom_icc_node * const nspb_noc_nodes[] = { 2589 [MASTER_CDSPB_NOC_CFG] = &qhm_nspb_noc_config, 2590 [MASTER_CDSP_PROC_B] = &qxm_nspb, 2591 [SLAVE_CDSPB_MEM_NOC] = &qns_nspb_gemnoc, 2592 [SLAVE_HCP_B] = &qns_nspb_hcp, 2593 [SLAVE_SERVICE_NSPB_NOC] = &service_nspb_noc, 2594 }; 2595 2596 static const struct qcom_icc_desc sa8775p_nspb_noc = { 2597 .config = &sa8775p_nspb_noc_regmap_config, 2598 .nodes = nspb_noc_nodes, 2599 .num_nodes = ARRAY_SIZE(nspb_noc_nodes), 2600 .bcms = nspb_noc_bcms, 2601 .num_bcms = ARRAY_SIZE(nspb_noc_bcms), 2602 }; 2603 2604 static struct qcom_icc_bcm * const pcie_anoc_bcms[] = { 2605 &bcm_pci0, 2606 }; 2607 2608 static struct qcom_icc_node * const pcie_anoc_nodes[] = { 2609 [MASTER_PCIE_0] = &xm_pcie3_0, 2610 [MASTER_PCIE_1] = &xm_pcie3_1, 2611 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, 2612 }; 2613 2614 static const struct regmap_config sa8775p_pcie_anoc_regmap_config = { 2615 .reg_bits = 32, 2616 .reg_stride = 4, 2617 .val_bits = 32, 2618 .max_register = 0xc080, 2619 .fast_io = true, 2620 }; 2621 2622 static const struct qcom_icc_desc sa8775p_pcie_anoc = { 2623 .config = &sa8775p_pcie_anoc_regmap_config, 2624 .nodes = pcie_anoc_nodes, 2625 .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), 2626 .bcms = pcie_anoc_bcms, 2627 .num_bcms = ARRAY_SIZE(pcie_anoc_bcms), 2628 }; 2629 2630 static struct qcom_icc_bcm * const system_noc_bcms[] = { 2631 &bcm_sn0, 2632 &bcm_sn1, 2633 &bcm_sn3, 2634 &bcm_sn4, 2635 &bcm_sn9, 2636 }; 2637 2638 static struct qcom_icc_node * const system_noc_nodes[] = { 2639 [MASTER_GIC_AHB] = &qhm_gic, 2640 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, 2641 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, 2642 [MASTER_LPASS_ANOC] = &qnm_lpass_noc, 2643 [MASTER_SNOC_CFG] = &qnm_snoc_cfg, 2644 [MASTER_PIMEM] = &qxm_pimem, 2645 [MASTER_GIC] = &xm_gic, 2646 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, 2647 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 2648 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 2649 }; 2650 2651 static const struct regmap_config sa8775p_system_noc_regmap_config = { 2652 .reg_bits = 32, 2653 .reg_stride = 4, 2654 .val_bits = 32, 2655 .max_register = 0x15080, 2656 .fast_io = true, 2657 }; 2658 2659 static const struct qcom_icc_desc sa8775p_system_noc = { 2660 .config = &sa8775p_system_noc_regmap_config, 2661 .nodes = system_noc_nodes, 2662 .num_nodes = ARRAY_SIZE(system_noc_nodes), 2663 .bcms = system_noc_bcms, 2664 .num_bcms = ARRAY_SIZE(system_noc_bcms), 2665 }; 2666 2667 static const struct of_device_id qnoc_of_match[] = { 2668 { .compatible = "qcom,sa8775p-aggre1-noc", .data = &sa8775p_aggre1_noc, }, 2669 { .compatible = "qcom,sa8775p-aggre2-noc", .data = &sa8775p_aggre2_noc, }, 2670 { .compatible = "qcom,sa8775p-clk-virt", .data = &sa8775p_clk_virt, }, 2671 { .compatible = "qcom,sa8775p-config-noc", .data = &sa8775p_config_noc, }, 2672 { .compatible = "qcom,sa8775p-dc-noc", .data = &sa8775p_dc_noc, }, 2673 { .compatible = "qcom,sa8775p-gem-noc", .data = &sa8775p_gem_noc, }, 2674 { .compatible = "qcom,sa8775p-gpdsp-anoc", .data = &sa8775p_gpdsp_anoc, }, 2675 { .compatible = "qcom,sa8775p-lpass-ag-noc", .data = &sa8775p_lpass_ag_noc, }, 2676 { .compatible = "qcom,sa8775p-mc-virt", .data = &sa8775p_mc_virt, }, 2677 { .compatible = "qcom,sa8775p-mmss-noc", .data = &sa8775p_mmss_noc, }, 2678 { .compatible = "qcom,sa8775p-nspa-noc", .data = &sa8775p_nspa_noc, }, 2679 { .compatible = "qcom,sa8775p-nspb-noc", .data = &sa8775p_nspb_noc, }, 2680 { .compatible = "qcom,sa8775p-pcie-anoc", .data = &sa8775p_pcie_anoc, }, 2681 { .compatible = "qcom,sa8775p-system-noc", .data = &sa8775p_system_noc, }, 2682 { } 2683 }; 2684 MODULE_DEVICE_TABLE(of, qnoc_of_match); 2685 2686 static struct platform_driver qnoc_driver = { 2687 .probe = qcom_icc_rpmh_probe, 2688 .remove = qcom_icc_rpmh_remove, 2689 .driver = { 2690 .name = "qnoc-sa8775p", 2691 .of_match_table = qnoc_of_match, 2692 .sync_state = icc_sync_state, 2693 }, 2694 }; 2695 2696 static int __init qnoc_driver_init(void) 2697 { 2698 return platform_driver_register(&qnoc_driver); 2699 } 2700 core_initcall(qnoc_driver_init); 2701 2702 static void __exit qnoc_driver_exit(void) 2703 { 2704 platform_driver_unregister(&qnoc_driver); 2705 } 2706 module_exit(qnoc_driver_exit); 2707 2708 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. SA8775P NoC driver"); 2709 MODULE_LICENSE("GPL"); 2710