1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 */ 6 7 #include <linux/device.h> 8 #include <linux/interconnect.h> 9 #include <linux/interconnect-provider.h> 10 #include <linux/module.h> 11 #include <linux/of_platform.h> 12 #include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h> 13 14 #include "bcm-voter.h" 15 #include "icc-rpmh.h" 16 17 static struct qcom_icc_node qxm_qup3; 18 static struct qcom_icc_node xm_emac_0; 19 static struct qcom_icc_node xm_sdc1; 20 static struct qcom_icc_node xm_ufs_mem; 21 static struct qcom_icc_node xm_usb2_2; 22 static struct qcom_icc_node xm_usb3_0; 23 static struct qcom_icc_node qhm_qdss_bam; 24 static struct qcom_icc_node qhm_qup0; 25 static struct qcom_icc_node qhm_qup1; 26 static struct qcom_icc_node qnm_cnoc_datapath; 27 static struct qcom_icc_node qxm_crypto_0; 28 static struct qcom_icc_node qxm_crypto_1; 29 static struct qcom_icc_node qxm_ipa; 30 static struct qcom_icc_node xm_qdss_etr_0; 31 static struct qcom_icc_node xm_qdss_etr_1; 32 static struct qcom_icc_node qup0_core_master; 33 static struct qcom_icc_node qup1_core_master; 34 static struct qcom_icc_node qup3_core_master; 35 static struct qcom_icc_node qnm_gemnoc_cnoc; 36 static struct qcom_icc_node qnm_gemnoc_pcie; 37 static struct qcom_icc_node qnm_cnoc_dc_noc; 38 static struct qcom_icc_node alm_gpu_tcu; 39 static struct qcom_icc_node alm_pcie_tcu; 40 static struct qcom_icc_node alm_sys_tcu; 41 static struct qcom_icc_node chm_apps; 42 static struct qcom_icc_node qnm_cmpnoc0; 43 static struct qcom_icc_node qnm_gemnoc_cfg; 44 static struct qcom_icc_node qnm_gpdsp_sail; 45 static struct qcom_icc_node qnm_gpu; 46 static struct qcom_icc_node qnm_mnoc_hf; 47 static struct qcom_icc_node qnm_mnoc_sf; 48 static struct qcom_icc_node qnm_pcie; 49 static struct qcom_icc_node qnm_snoc_gc; 50 static struct qcom_icc_node qnm_snoc_sf; 51 static struct qcom_icc_node qnm_sailss_md0; 52 static struct qcom_icc_node qxm_dsp0; 53 static struct qcom_icc_node qhm_config_noc; 54 static struct qcom_icc_node qxm_lpass_dsp; 55 static struct qcom_icc_node llcc_mc; 56 static struct qcom_icc_node qnm_camnoc_hf; 57 static struct qcom_icc_node qnm_camnoc_icp; 58 static struct qcom_icc_node qnm_camnoc_sf; 59 static struct qcom_icc_node qnm_mdp0_0; 60 static struct qcom_icc_node qnm_mdp0_1; 61 static struct qcom_icc_node qnm_mnoc_hf_cfg; 62 static struct qcom_icc_node qnm_mnoc_sf_cfg; 63 static struct qcom_icc_node qnm_video0; 64 static struct qcom_icc_node qnm_video_cvp; 65 static struct qcom_icc_node qnm_video_v_cpu; 66 static struct qcom_icc_node qhm_nsp_noc_config; 67 static struct qcom_icc_node qxm_nsp; 68 static struct qcom_icc_node xm_pcie3_0; 69 static struct qcom_icc_node xm_pcie3_1; 70 static struct qcom_icc_node qhm_gic; 71 static struct qcom_icc_node qnm_aggre1_noc; 72 static struct qcom_icc_node qnm_aggre2_noc; 73 static struct qcom_icc_node qnm_lpass_noc; 74 static struct qcom_icc_node qnm_snoc_cfg; 75 static struct qcom_icc_node qxm_pimem; 76 static struct qcom_icc_node xm_gic; 77 static struct qcom_icc_node qns_a1noc_snoc; 78 static struct qcom_icc_node qns_a2noc_snoc; 79 static struct qcom_icc_node qup0_core_slave; 80 static struct qcom_icc_node qup1_core_slave; 81 static struct qcom_icc_node qup3_core_slave; 82 static struct qcom_icc_node qhs_ahb2phy2; 83 static struct qcom_icc_node qhs_ahb2phy3; 84 static struct qcom_icc_node qhs_anoc_throttle_cfg; 85 static struct qcom_icc_node qhs_aoss; 86 static struct qcom_icc_node qhs_apss; 87 static struct qcom_icc_node qhs_boot_rom; 88 static struct qcom_icc_node qhs_camera_cfg; 89 static struct qcom_icc_node qhs_camera_nrt_throttle_cfg; 90 static struct qcom_icc_node qhs_camera_rt_throttle_cfg; 91 static struct qcom_icc_node qhs_clk_ctl; 92 static struct qcom_icc_node qhs_compute0_cfg; 93 static struct qcom_icc_node qhs_cpr_cx; 94 static struct qcom_icc_node qhs_cpr_mmcx; 95 static struct qcom_icc_node qhs_cpr_mx; 96 static struct qcom_icc_node qhs_cpr_nspcx; 97 static struct qcom_icc_node qhs_cpr_nsphmx; 98 static struct qcom_icc_node qhs_crypto0_cfg; 99 static struct qcom_icc_node qhs_cx_rdpm; 100 static struct qcom_icc_node qhs_display0_cfg; 101 static struct qcom_icc_node qhs_display0_rt_throttle_cfg; 102 static struct qcom_icc_node qhs_emac0_cfg; 103 static struct qcom_icc_node qhs_gp_dsp0_cfg; 104 static struct qcom_icc_node qhs_gpdsp0_throttle_cfg; 105 static struct qcom_icc_node qhs_gpu_tcu_throttle_cfg; 106 static struct qcom_icc_node qhs_gpuss_cfg; 107 static struct qcom_icc_node qhs_hwkm; 108 static struct qcom_icc_node qhs_imem_cfg; 109 static struct qcom_icc_node qhs_ipa; 110 static struct qcom_icc_node qhs_ipc_router; 111 static struct qcom_icc_node qhs_lpass_cfg; 112 static struct qcom_icc_node qhs_lpass_throttle_cfg; 113 static struct qcom_icc_node qhs_mx_rdpm; 114 static struct qcom_icc_node qhs_mxc_rdpm; 115 static struct qcom_icc_node qhs_pcie0_cfg; 116 static struct qcom_icc_node qhs_pcie1_cfg; 117 static struct qcom_icc_node qhs_pcie_tcu_throttle_cfg; 118 static struct qcom_icc_node qhs_pcie_throttle_cfg; 119 static struct qcom_icc_node qhs_pdm; 120 static struct qcom_icc_node qhs_pimem_cfg; 121 static struct qcom_icc_node qhs_pke_wrapper_cfg; 122 static struct qcom_icc_node qhs_qdss_cfg; 123 static struct qcom_icc_node qhs_qm_cfg; 124 static struct qcom_icc_node qhs_qm_mpu_cfg; 125 static struct qcom_icc_node qhs_qup0; 126 static struct qcom_icc_node qhs_qup1; 127 static struct qcom_icc_node qhs_qup3; 128 static struct qcom_icc_node qhs_sail_throttle_cfg; 129 static struct qcom_icc_node qhs_sdc1; 130 static struct qcom_icc_node qhs_security; 131 static struct qcom_icc_node qhs_snoc_throttle_cfg; 132 static struct qcom_icc_node qhs_tcsr; 133 static struct qcom_icc_node qhs_tlmm; 134 static struct qcom_icc_node qhs_tsc_cfg; 135 static struct qcom_icc_node qhs_ufs_mem_cfg; 136 static struct qcom_icc_node qhs_usb2_0; 137 static struct qcom_icc_node qhs_usb3_0; 138 static struct qcom_icc_node qhs_venus_cfg; 139 static struct qcom_icc_node qhs_venus_cvp_throttle_cfg; 140 static struct qcom_icc_node qhs_venus_v_cpu_throttle_cfg; 141 static struct qcom_icc_node qhs_venus_vcodec_throttle_cfg; 142 static struct qcom_icc_node qns_ddrss_cfg; 143 static struct qcom_icc_node qns_gpdsp_noc_cfg; 144 static struct qcom_icc_node qns_mnoc_hf_cfg; 145 static struct qcom_icc_node qns_mnoc_sf_cfg; 146 static struct qcom_icc_node qns_pcie_anoc_cfg; 147 static struct qcom_icc_node qns_snoc_cfg; 148 static struct qcom_icc_node qxs_boot_imem; 149 static struct qcom_icc_node qxs_imem; 150 static struct qcom_icc_node qxs_pimem; 151 static struct qcom_icc_node xs_pcie_0; 152 static struct qcom_icc_node xs_pcie_1; 153 static struct qcom_icc_node xs_qdss_stm; 154 static struct qcom_icc_node xs_sys_tcu_cfg; 155 static struct qcom_icc_node qhs_llcc; 156 static struct qcom_icc_node qns_gemnoc; 157 static struct qcom_icc_node qns_gem_noc_cnoc; 158 static struct qcom_icc_node qns_llcc; 159 static struct qcom_icc_node qns_pcie; 160 static struct qcom_icc_node srvc_even_gemnoc; 161 static struct qcom_icc_node srvc_odd_gemnoc; 162 static struct qcom_icc_node srvc_sys_gemnoc; 163 static struct qcom_icc_node srvc_sys_gemnoc_2; 164 static struct qcom_icc_node qns_gp_dsp_sail_noc; 165 static struct qcom_icc_node qhs_lpass_core; 166 static struct qcom_icc_node qhs_lpass_lpi; 167 static struct qcom_icc_node qhs_lpass_mpu; 168 static struct qcom_icc_node qhs_lpass_top; 169 static struct qcom_icc_node qns_sysnoc; 170 static struct qcom_icc_node srvc_niu_aml_noc; 171 static struct qcom_icc_node srvc_niu_lpass_agnoc; 172 static struct qcom_icc_node ebi; 173 static struct qcom_icc_node qns_mem_noc_hf; 174 static struct qcom_icc_node qns_mem_noc_sf; 175 static struct qcom_icc_node srvc_mnoc_hf; 176 static struct qcom_icc_node srvc_mnoc_sf; 177 static struct qcom_icc_node qns_hcp; 178 static struct qcom_icc_node qns_nsp_gemnoc; 179 static struct qcom_icc_node service_nsp_noc; 180 static struct qcom_icc_node qns_pcie_mem_noc; 181 static struct qcom_icc_node qns_gemnoc_gc; 182 static struct qcom_icc_node qns_gemnoc_sf; 183 static struct qcom_icc_node srvc_snoc; 184 185 static struct qcom_icc_node qxm_qup3 = { 186 .name = "qxm_qup3", 187 .channels = 1, 188 .buswidth = 8, 189 .num_links = 1, 190 .link_nodes = { &qns_a1noc_snoc }, 191 }; 192 193 static struct qcom_icc_node xm_emac_0 = { 194 .name = "xm_emac_0", 195 .channels = 1, 196 .buswidth = 8, 197 .num_links = 1, 198 .link_nodes = { &qns_a1noc_snoc }, 199 }; 200 201 static struct qcom_icc_node xm_sdc1 = { 202 .name = "xm_sdc1", 203 .channels = 1, 204 .buswidth = 8, 205 .num_links = 1, 206 .link_nodes = { &qns_a1noc_snoc }, 207 }; 208 209 static struct qcom_icc_node xm_ufs_mem = { 210 .name = "xm_ufs_mem", 211 .channels = 1, 212 .buswidth = 8, 213 .num_links = 1, 214 .link_nodes = { &qns_a1noc_snoc }, 215 }; 216 217 static struct qcom_icc_node xm_usb2_2 = { 218 .name = "xm_usb2_2", 219 .channels = 1, 220 .buswidth = 8, 221 .num_links = 1, 222 .link_nodes = { &qns_a1noc_snoc }, 223 }; 224 225 static struct qcom_icc_node xm_usb3_0 = { 226 .name = "xm_usb3_0", 227 .channels = 1, 228 .buswidth = 8, 229 .num_links = 1, 230 .link_nodes = { &qns_a1noc_snoc }, 231 }; 232 233 static struct qcom_icc_node qhm_qdss_bam = { 234 .name = "qhm_qdss_bam", 235 .channels = 1, 236 .buswidth = 4, 237 .num_links = 1, 238 .link_nodes = { &qns_a2noc_snoc }, 239 }; 240 241 static struct qcom_icc_node qhm_qup0 = { 242 .name = "qhm_qup0", 243 .channels = 1, 244 .buswidth = 4, 245 .num_links = 1, 246 .link_nodes = { &qns_a2noc_snoc }, 247 }; 248 249 static struct qcom_icc_node qhm_qup1 = { 250 .name = "qhm_qup1", 251 .channels = 1, 252 .buswidth = 4, 253 .num_links = 1, 254 .link_nodes = { &qns_a2noc_snoc }, 255 }; 256 257 static struct qcom_icc_node qnm_cnoc_datapath = { 258 .name = "qnm_cnoc_datapath", 259 .channels = 1, 260 .buswidth = 8, 261 .num_links = 1, 262 .link_nodes = { &qns_a2noc_snoc }, 263 }; 264 265 static struct qcom_icc_node qxm_crypto_0 = { 266 .name = "qxm_crypto_0", 267 .channels = 1, 268 .buswidth = 8, 269 .num_links = 1, 270 .link_nodes = { &qns_a2noc_snoc }, 271 }; 272 273 static struct qcom_icc_node qxm_crypto_1 = { 274 .name = "qxm_crypto_1", 275 .channels = 1, 276 .buswidth = 8, 277 .num_links = 1, 278 .link_nodes = { &qns_a2noc_snoc }, 279 }; 280 281 static struct qcom_icc_node qxm_ipa = { 282 .name = "qxm_ipa", 283 .channels = 1, 284 .buswidth = 8, 285 .num_links = 1, 286 .link_nodes = { &qns_a2noc_snoc }, 287 }; 288 289 static struct qcom_icc_node xm_qdss_etr_0 = { 290 .name = "xm_qdss_etr_0", 291 .channels = 1, 292 .buswidth = 8, 293 .num_links = 1, 294 .link_nodes = { &qns_a2noc_snoc }, 295 }; 296 297 static struct qcom_icc_node xm_qdss_etr_1 = { 298 .name = "xm_qdss_etr_1", 299 .channels = 1, 300 .buswidth = 8, 301 .num_links = 1, 302 .link_nodes = { &qns_a2noc_snoc }, 303 }; 304 305 static struct qcom_icc_node qup0_core_master = { 306 .name = "qup0_core_master", 307 .channels = 1, 308 .buswidth = 4, 309 .num_links = 1, 310 .link_nodes = { &qup0_core_slave }, 311 }; 312 313 static struct qcom_icc_node qup1_core_master = { 314 .name = "qup1_core_master", 315 .channels = 1, 316 .buswidth = 4, 317 .num_links = 1, 318 .link_nodes = { &qup1_core_slave }, 319 }; 320 321 static struct qcom_icc_node qup3_core_master = { 322 .name = "qup3_core_master", 323 .channels = 1, 324 .buswidth = 4, 325 .num_links = 1, 326 .link_nodes = { &qup3_core_slave }, 327 }; 328 329 static struct qcom_icc_node qnm_gemnoc_cnoc = { 330 .name = "qnm_gemnoc_cnoc", 331 .channels = 1, 332 .buswidth = 16, 333 .num_links = 71, 334 .link_nodes = { &qhs_ahb2phy2, &qhs_ahb2phy3, 335 &qhs_anoc_throttle_cfg, &qhs_aoss, 336 &qhs_apss, &qhs_boot_rom, 337 &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg, 338 &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, 339 &qhs_compute0_cfg, &qhs_cpr_cx, 340 &qhs_cpr_mmcx, &qhs_cpr_mx, 341 &qhs_cpr_nspcx, &qhs_cpr_nsphmx, 342 &qhs_crypto0_cfg, &qhs_cx_rdpm, 343 &qhs_display0_cfg, &qhs_display0_rt_throttle_cfg, 344 &qhs_emac0_cfg, &qhs_gp_dsp0_cfg, 345 &qhs_gpdsp0_throttle_cfg, &qhs_gpu_tcu_throttle_cfg, 346 &qhs_gpuss_cfg, &qhs_hwkm, 347 &qhs_imem_cfg, &qhs_ipa, 348 &qhs_ipc_router, &qhs_lpass_cfg, 349 &qhs_lpass_throttle_cfg, &qhs_mx_rdpm, 350 &qhs_mxc_rdpm, &qhs_pcie0_cfg, 351 &qhs_pcie1_cfg, &qhs_pcie_tcu_throttle_cfg, 352 &qhs_pcie_throttle_cfg, &qhs_pdm, 353 &qhs_pimem_cfg, &qhs_pke_wrapper_cfg, 354 &qhs_qdss_cfg, &qhs_qm_cfg, 355 &qhs_qm_mpu_cfg, &qhs_qup0, 356 &qhs_qup1, &qhs_qup3, 357 &qhs_sail_throttle_cfg, &qhs_sdc1, 358 &qhs_security, &qhs_snoc_throttle_cfg, 359 &qhs_tcsr, &qhs_tlmm, 360 &qhs_tsc_cfg, &qhs_ufs_mem_cfg, 361 &qhs_usb2_0, &qhs_usb3_0, 362 &qhs_venus_cfg, &qhs_venus_cvp_throttle_cfg, 363 &qhs_venus_v_cpu_throttle_cfg, 364 &qhs_venus_vcodec_throttle_cfg, 365 &qns_ddrss_cfg, &qns_gpdsp_noc_cfg, 366 &qns_mnoc_hf_cfg, &qns_mnoc_sf_cfg, 367 &qns_pcie_anoc_cfg, &qns_snoc_cfg, 368 &qxs_boot_imem, &qxs_imem, 369 &qxs_pimem, &xs_qdss_stm, 370 &xs_sys_tcu_cfg }, 371 }; 372 373 static struct qcom_icc_node qnm_gemnoc_pcie = { 374 .name = "qnm_gemnoc_pcie", 375 .channels = 1, 376 .buswidth = 16, 377 .num_links = 2, 378 .link_nodes = { &xs_pcie_0, &xs_pcie_1 }, 379 }; 380 381 static struct qcom_icc_node qnm_cnoc_dc_noc = { 382 .name = "qnm_cnoc_dc_noc", 383 .channels = 1, 384 .buswidth = 4, 385 .num_links = 2, 386 .link_nodes = { &qhs_llcc, &qns_gemnoc }, 387 }; 388 389 static struct qcom_icc_node alm_gpu_tcu = { 390 .name = "alm_gpu_tcu", 391 .channels = 1, 392 .buswidth = 8, 393 .num_links = 2, 394 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 395 }; 396 397 static struct qcom_icc_node alm_pcie_tcu = { 398 .name = "alm_pcie_tcu", 399 .channels = 1, 400 .buswidth = 8, 401 .num_links = 2, 402 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 403 }; 404 405 static struct qcom_icc_node alm_sys_tcu = { 406 .name = "alm_sys_tcu", 407 .channels = 1, 408 .buswidth = 8, 409 .num_links = 2, 410 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 411 }; 412 413 static struct qcom_icc_node chm_apps = { 414 .name = "chm_apps", 415 .channels = 4, 416 .buswidth = 32, 417 .num_links = 3, 418 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 419 &qns_pcie }, 420 }; 421 422 static struct qcom_icc_node qnm_cmpnoc0 = { 423 .name = "qnm_cmpnoc0", 424 .channels = 2, 425 .buswidth = 32, 426 .num_links = 2, 427 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 428 }; 429 430 static struct qcom_icc_node qnm_gemnoc_cfg = { 431 .name = "qnm_gemnoc_cfg", 432 .channels = 1, 433 .buswidth = 4, 434 .num_links = 4, 435 .link_nodes = { &srvc_even_gemnoc, &srvc_odd_gemnoc, 436 &srvc_sys_gemnoc, &srvc_sys_gemnoc_2 }, 437 }; 438 439 static struct qcom_icc_node qnm_gpdsp_sail = { 440 .name = "qnm_gpdsp_sail", 441 .channels = 1, 442 .buswidth = 16, 443 .num_links = 2, 444 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 445 }; 446 447 static struct qcom_icc_node qnm_gpu = { 448 .name = "qnm_gpu", 449 .channels = 2, 450 .buswidth = 32, 451 .num_links = 2, 452 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 453 }; 454 455 static struct qcom_icc_node qnm_mnoc_hf = { 456 .name = "qnm_mnoc_hf", 457 .channels = 2, 458 .buswidth = 32, 459 .num_links = 2, 460 .link_nodes = { &qns_llcc, &qns_pcie }, 461 }; 462 463 static struct qcom_icc_node qnm_mnoc_sf = { 464 .name = "qnm_mnoc_sf", 465 .channels = 2, 466 .buswidth = 32, 467 .num_links = 3, 468 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 469 &qns_pcie }, 470 }; 471 472 static struct qcom_icc_node qnm_pcie = { 473 .name = "qnm_pcie", 474 .channels = 1, 475 .buswidth = 32, 476 .num_links = 2, 477 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 478 }; 479 480 static struct qcom_icc_node qnm_snoc_gc = { 481 .name = "qnm_snoc_gc", 482 .channels = 1, 483 .buswidth = 8, 484 .num_links = 1, 485 .link_nodes = { &qns_llcc }, 486 }; 487 488 static struct qcom_icc_node qnm_snoc_sf = { 489 .name = "qnm_snoc_sf", 490 .channels = 1, 491 .buswidth = 16, 492 .num_links = 3, 493 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 494 &qns_pcie }, 495 }; 496 497 static struct qcom_icc_node qnm_sailss_md0 = { 498 .name = "qnm_sailss_md0", 499 .channels = 1, 500 .buswidth = 16, 501 .num_links = 1, 502 .link_nodes = { &qns_gp_dsp_sail_noc }, 503 }; 504 505 static struct qcom_icc_node qxm_dsp0 = { 506 .name = "qxm_dsp0", 507 .channels = 1, 508 .buswidth = 16, 509 .num_links = 1, 510 .link_nodes = { &qns_gp_dsp_sail_noc }, 511 }; 512 513 static struct qcom_icc_node qhm_config_noc = { 514 .name = "qhm_config_noc", 515 .channels = 1, 516 .buswidth = 4, 517 .num_links = 6, 518 .link_nodes = { &qhs_lpass_core, &qhs_lpass_lpi, 519 &qhs_lpass_mpu, &qhs_lpass_top, 520 &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, 521 }; 522 523 static struct qcom_icc_node qxm_lpass_dsp = { 524 .name = "qxm_lpass_dsp", 525 .channels = 1, 526 .buswidth = 8, 527 .num_links = 4, 528 .link_nodes = { &qhs_lpass_top, &qns_sysnoc, 529 &srvc_niu_aml_noc, &srvc_niu_lpass_agnoc }, 530 }; 531 532 static struct qcom_icc_node llcc_mc = { 533 .name = "llcc_mc", 534 .channels = 8, 535 .buswidth = 4, 536 .num_links = 1, 537 .link_nodes = { &ebi }, 538 }; 539 540 static struct qcom_icc_node qnm_camnoc_hf = { 541 .name = "qnm_camnoc_hf", 542 .channels = 1, 543 .buswidth = 32, 544 .num_links = 1, 545 .link_nodes = { &qns_mem_noc_hf }, 546 }; 547 548 static struct qcom_icc_node qnm_camnoc_icp = { 549 .name = "qnm_camnoc_icp", 550 .channels = 1, 551 .buswidth = 8, 552 .num_links = 1, 553 .link_nodes = { &qns_mem_noc_sf }, 554 }; 555 556 static struct qcom_icc_node qnm_camnoc_sf = { 557 .name = "qnm_camnoc_sf", 558 .channels = 1, 559 .buswidth = 32, 560 .num_links = 1, 561 .link_nodes = { &qns_mem_noc_sf }, 562 }; 563 564 static struct qcom_icc_node qnm_mdp0_0 = { 565 .name = "qnm_mdp0_0", 566 .channels = 1, 567 .buswidth = 32, 568 .num_links = 1, 569 .link_nodes = { &qns_mem_noc_hf }, 570 }; 571 572 static struct qcom_icc_node qnm_mdp0_1 = { 573 .name = "qnm_mdp0_1", 574 .channels = 1, 575 .buswidth = 32, 576 .num_links = 1, 577 .link_nodes = { &qns_mem_noc_hf }, 578 }; 579 580 static struct qcom_icc_node qnm_mnoc_hf_cfg = { 581 .name = "qnm_mnoc_hf_cfg", 582 .channels = 1, 583 .buswidth = 4, 584 .num_links = 1, 585 .link_nodes = { &srvc_mnoc_hf }, 586 }; 587 588 static struct qcom_icc_node qnm_mnoc_sf_cfg = { 589 .name = "qnm_mnoc_sf_cfg", 590 .channels = 1, 591 .buswidth = 4, 592 .num_links = 1, 593 .link_nodes = { &srvc_mnoc_sf }, 594 }; 595 596 static struct qcom_icc_node qnm_video0 = { 597 .name = "qnm_video0", 598 .channels = 1, 599 .buswidth = 32, 600 .num_links = 1, 601 .link_nodes = { &qns_mem_noc_sf }, 602 }; 603 604 static struct qcom_icc_node qnm_video_cvp = { 605 .name = "qnm_video_cvp", 606 .channels = 1, 607 .buswidth = 32, 608 .num_links = 1, 609 .link_nodes = { &qns_mem_noc_sf }, 610 }; 611 612 static struct qcom_icc_node qnm_video_v_cpu = { 613 .name = "qnm_video_v_cpu", 614 .channels = 1, 615 .buswidth = 8, 616 .num_links = 1, 617 .link_nodes = { &qns_mem_noc_sf }, 618 }; 619 620 static struct qcom_icc_node qhm_nsp_noc_config = { 621 .name = "qhm_nsp_noc_config", 622 .channels = 1, 623 .buswidth = 4, 624 .num_links = 1, 625 .link_nodes = { &service_nsp_noc }, 626 }; 627 628 static struct qcom_icc_node qxm_nsp = { 629 .name = "qxm_nsp", 630 .channels = 2, 631 .buswidth = 32, 632 .num_links = 1, 633 .link_nodes = { &qns_hcp, &qns_nsp_gemnoc }, 634 }; 635 636 static struct qcom_icc_node xm_pcie3_0 = { 637 .name = "xm_pcie3_0", 638 .channels = 1, 639 .buswidth = 16, 640 .num_links = 1, 641 .link_nodes = { &qns_pcie_mem_noc }, 642 }; 643 644 static struct qcom_icc_node xm_pcie3_1 = { 645 .name = "xm_pcie3_1", 646 .channels = 1, 647 .buswidth = 32, 648 .num_links = 1, 649 .link_nodes = { &qns_pcie_mem_noc }, 650 }; 651 652 static struct qcom_icc_node qhm_gic = { 653 .name = "qhm_gic", 654 .channels = 1, 655 .buswidth = 4, 656 .num_links = 1, 657 .link_nodes = { &qns_gemnoc_sf }, 658 }; 659 660 static struct qcom_icc_node qnm_aggre1_noc = { 661 .name = "qnm_aggre1_noc", 662 .channels = 1, 663 .buswidth = 32, 664 .num_links = 1, 665 .link_nodes = { &qns_gemnoc_sf }, 666 }; 667 668 static struct qcom_icc_node qnm_aggre2_noc = { 669 .name = "qnm_aggre2_noc", 670 .channels = 1, 671 .buswidth = 16, 672 .num_links = 1, 673 .link_nodes = { &qns_gemnoc_sf }, 674 }; 675 676 static struct qcom_icc_node qnm_lpass_noc = { 677 .name = "qnm_lpass_noc", 678 .channels = 1, 679 .buswidth = 16, 680 .num_links = 1, 681 .link_nodes = { &qns_gemnoc_sf }, 682 }; 683 684 static struct qcom_icc_node qnm_snoc_cfg = { 685 .name = "qnm_snoc_cfg", 686 .channels = 1, 687 .buswidth = 4, 688 .num_links = 1, 689 .link_nodes = { &srvc_snoc }, 690 }; 691 692 static struct qcom_icc_node qxm_pimem = { 693 .name = "qxm_pimem", 694 .channels = 1, 695 .buswidth = 8, 696 .num_links = 1, 697 .link_nodes = { &qns_gemnoc_gc }, 698 }; 699 700 static struct qcom_icc_node xm_gic = { 701 .name = "xm_gic", 702 .channels = 1, 703 .buswidth = 8, 704 .num_links = 1, 705 .link_nodes = { &qns_gemnoc_gc }, 706 }; 707 708 static struct qcom_icc_node qns_a1noc_snoc = { 709 .name = "qns_a1noc_snoc", 710 .channels = 1, 711 .buswidth = 32, 712 .num_links = 1, 713 .link_nodes = { &qnm_aggre1_noc }, 714 }; 715 716 static struct qcom_icc_node qns_a2noc_snoc = { 717 .name = "qns_a2noc_snoc", 718 .channels = 1, 719 .buswidth = 16, 720 .num_links = 1, 721 .link_nodes = { &qnm_aggre2_noc }, 722 }; 723 724 static struct qcom_icc_node qup0_core_slave = { 725 .name = "qup0_core_slave", 726 .channels = 1, 727 .buswidth = 4, 728 }; 729 730 static struct qcom_icc_node qup1_core_slave = { 731 .name = "qup1_core_slave", 732 .channels = 1, 733 .buswidth = 4, 734 }; 735 736 static struct qcom_icc_node qup3_core_slave = { 737 .name = "qup3_core_slave", 738 .channels = 1, 739 .buswidth = 4, 740 }; 741 742 static struct qcom_icc_node qhs_ahb2phy2 = { 743 .name = "qhs_ahb2phy2", 744 .channels = 1, 745 .buswidth = 4, 746 }; 747 748 static struct qcom_icc_node qhs_ahb2phy3 = { 749 .name = "qhs_ahb2phy3", 750 .channels = 1, 751 .buswidth = 4, 752 }; 753 754 static struct qcom_icc_node qhs_anoc_throttle_cfg = { 755 .name = "qhs_anoc_throttle_cfg", 756 .channels = 1, 757 .buswidth = 4, 758 }; 759 760 static struct qcom_icc_node qhs_aoss = { 761 .name = "qhs_aoss", 762 .channels = 1, 763 .buswidth = 4, 764 }; 765 766 static struct qcom_icc_node qhs_apss = { 767 .name = "qhs_apss", 768 .channels = 1, 769 .buswidth = 8, 770 }; 771 772 static struct qcom_icc_node qhs_boot_rom = { 773 .name = "qhs_boot_rom", 774 .channels = 1, 775 .buswidth = 4, 776 }; 777 778 static struct qcom_icc_node qhs_camera_cfg = { 779 .name = "qhs_camera_cfg", 780 .channels = 1, 781 .buswidth = 4, 782 }; 783 784 static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = { 785 .name = "qhs_camera_nrt_throttle_cfg", 786 .channels = 1, 787 .buswidth = 4, 788 }; 789 790 static struct qcom_icc_node qhs_camera_rt_throttle_cfg = { 791 .name = "qhs_camera_rt_throttle_cfg", 792 .channels = 1, 793 .buswidth = 4, 794 }; 795 796 static struct qcom_icc_node qhs_clk_ctl = { 797 .name = "qhs_clk_ctl", 798 .channels = 1, 799 .buswidth = 4, 800 }; 801 802 static struct qcom_icc_node qhs_compute0_cfg = { 803 .name = "qhs_compute0_cfg", 804 .channels = 1, 805 .buswidth = 4, 806 .num_links = 1, 807 .link_nodes = { &qhm_nsp_noc_config }, 808 }; 809 810 static struct qcom_icc_node qhs_cpr_cx = { 811 .name = "qhs_cpr_cx", 812 .channels = 1, 813 .buswidth = 4, 814 }; 815 816 static struct qcom_icc_node qhs_cpr_mmcx = { 817 .name = "qhs_cpr_mmcx", 818 .channels = 1, 819 .buswidth = 4, 820 }; 821 822 static struct qcom_icc_node qhs_cpr_mx = { 823 .name = "qhs_cpr_mx", 824 .channels = 1, 825 .buswidth = 4, 826 }; 827 828 static struct qcom_icc_node qhs_cpr_nspcx = { 829 .name = "qhs_cpr_nspcx", 830 .channels = 1, 831 .buswidth = 4, 832 }; 833 834 static struct qcom_icc_node qhs_cpr_nsphmx = { 835 .name = "qhs_cpr_nsphmx", 836 .channels = 1, 837 .buswidth = 4, 838 }; 839 840 static struct qcom_icc_node qhs_crypto0_cfg = { 841 .name = "qhs_crypto0_cfg", 842 .channels = 1, 843 .buswidth = 4, 844 }; 845 846 static struct qcom_icc_node qhs_cx_rdpm = { 847 .name = "qhs_cx_rdpm", 848 .channels = 1, 849 .buswidth = 4, 850 }; 851 852 static struct qcom_icc_node qhs_display0_cfg = { 853 .name = "qhs_display0_cfg", 854 .channels = 1, 855 .buswidth = 4, 856 }; 857 858 static struct qcom_icc_node qhs_display0_rt_throttle_cfg = { 859 .name = "qhs_display0_rt_throttle_cfg", 860 .channels = 1, 861 .buswidth = 4, 862 }; 863 864 static struct qcom_icc_node qhs_emac0_cfg = { 865 .name = "qhs_emac0_cfg", 866 .channels = 1, 867 .buswidth = 4, 868 }; 869 870 static struct qcom_icc_node qhs_gp_dsp0_cfg = { 871 .name = "qhs_gp_dsp0_cfg", 872 .channels = 1, 873 .buswidth = 4, 874 }; 875 876 static struct qcom_icc_node qhs_gpdsp0_throttle_cfg = { 877 .name = "qhs_gpdsp0_throttle_cfg", 878 .channels = 1, 879 .buswidth = 4, 880 }; 881 882 static struct qcom_icc_node qhs_gpu_tcu_throttle_cfg = { 883 .name = "qhs_gpu_tcu_throttle_cfg", 884 .channels = 1, 885 .buswidth = 4, 886 }; 887 888 static struct qcom_icc_node qhs_gpuss_cfg = { 889 .name = "qhs_gpuss_cfg", 890 .channels = 1, 891 .buswidth = 8, 892 }; 893 894 static struct qcom_icc_node qhs_hwkm = { 895 .name = "qhs_hwkm", 896 .channels = 1, 897 .buswidth = 4, 898 }; 899 900 static struct qcom_icc_node qhs_imem_cfg = { 901 .name = "qhs_imem_cfg", 902 .channels = 1, 903 .buswidth = 4, 904 }; 905 906 static struct qcom_icc_node qhs_ipa = { 907 .name = "qhs_ipa", 908 .channels = 1, 909 .buswidth = 4, 910 }; 911 912 static struct qcom_icc_node qhs_ipc_router = { 913 .name = "qhs_ipc_router", 914 .channels = 1, 915 .buswidth = 4, 916 }; 917 918 static struct qcom_icc_node qhs_lpass_cfg = { 919 .name = "qhs_lpass_cfg", 920 .channels = 1, 921 .buswidth = 4, 922 .num_links = 1, 923 .link_nodes = { &qhm_config_noc }, 924 }; 925 926 static struct qcom_icc_node qhs_lpass_throttle_cfg = { 927 .name = "qhs_lpass_throttle_cfg", 928 .channels = 1, 929 .buswidth = 4, 930 }; 931 932 static struct qcom_icc_node qhs_mx_rdpm = { 933 .name = "qhs_mx_rdpm", 934 .channels = 1, 935 .buswidth = 4, 936 }; 937 938 static struct qcom_icc_node qhs_mxc_rdpm = { 939 .name = "qhs_mxc_rdpm", 940 .channels = 1, 941 .buswidth = 4, 942 }; 943 944 static struct qcom_icc_node qhs_pcie0_cfg = { 945 .name = "qhs_pcie0_cfg", 946 .channels = 1, 947 .buswidth = 4, 948 }; 949 950 static struct qcom_icc_node qhs_pcie1_cfg = { 951 .name = "qhs_pcie1_cfg", 952 .channels = 1, 953 .buswidth = 4, 954 }; 955 956 static struct qcom_icc_node qhs_pcie_tcu_throttle_cfg = { 957 .name = "qhs_pcie_tcu_throttle_cfg", 958 .channels = 1, 959 .buswidth = 4, 960 }; 961 962 static struct qcom_icc_node qhs_pcie_throttle_cfg = { 963 .name = "qhs_pcie_throttle_cfg", 964 .channels = 1, 965 .buswidth = 4, 966 }; 967 968 static struct qcom_icc_node qhs_pdm = { 969 .name = "qhs_pdm", 970 .channels = 1, 971 .buswidth = 4, 972 }; 973 974 static struct qcom_icc_node qhs_pimem_cfg = { 975 .name = "qhs_pimem_cfg", 976 .channels = 1, 977 .buswidth = 4, 978 }; 979 980 static struct qcom_icc_node qhs_pke_wrapper_cfg = { 981 .name = "qhs_pke_wrapper_cfg", 982 .channels = 1, 983 .buswidth = 4, 984 }; 985 986 static struct qcom_icc_node qhs_qdss_cfg = { 987 .name = "qhs_qdss_cfg", 988 .channels = 1, 989 .buswidth = 4, 990 }; 991 992 static struct qcom_icc_node qhs_qm_cfg = { 993 .name = "qhs_qm_cfg", 994 .channels = 1, 995 .buswidth = 4, 996 }; 997 998 static struct qcom_icc_node qhs_qm_mpu_cfg = { 999 .name = "qhs_qm_mpu_cfg", 1000 .channels = 1, 1001 .buswidth = 4, 1002 }; 1003 1004 static struct qcom_icc_node qhs_qup0 = { 1005 .name = "qhs_qup0", 1006 .channels = 1, 1007 .buswidth = 4, 1008 }; 1009 1010 static struct qcom_icc_node qhs_qup1 = { 1011 .name = "qhs_qup1", 1012 .channels = 1, 1013 .buswidth = 4, 1014 }; 1015 1016 static struct qcom_icc_node qhs_qup3 = { 1017 .name = "qhs_qup3", 1018 .channels = 1, 1019 .buswidth = 4, 1020 }; 1021 1022 static struct qcom_icc_node qhs_sail_throttle_cfg = { 1023 .name = "qhs_sail_throttle_cfg", 1024 .channels = 1, 1025 .buswidth = 4, 1026 }; 1027 1028 static struct qcom_icc_node qhs_sdc1 = { 1029 .name = "qhs_sdc1", 1030 .channels = 1, 1031 .buswidth = 4, 1032 }; 1033 1034 static struct qcom_icc_node qhs_security = { 1035 .name = "qhs_security", 1036 .channels = 1, 1037 .buswidth = 4, 1038 }; 1039 1040 static struct qcom_icc_node qhs_snoc_throttle_cfg = { 1041 .name = "qhs_snoc_throttle_cfg", 1042 .channels = 1, 1043 .buswidth = 4, 1044 }; 1045 1046 static struct qcom_icc_node qhs_tcsr = { 1047 .name = "qhs_tcsr", 1048 .channels = 1, 1049 .buswidth = 4, 1050 }; 1051 1052 static struct qcom_icc_node qhs_tlmm = { 1053 .name = "qhs_tlmm", 1054 .channels = 1, 1055 .buswidth = 4, 1056 }; 1057 1058 static struct qcom_icc_node qhs_tsc_cfg = { 1059 .name = "qhs_tsc_cfg", 1060 .channels = 1, 1061 .buswidth = 4, 1062 }; 1063 1064 static struct qcom_icc_node qhs_ufs_mem_cfg = { 1065 .name = "qhs_ufs_mem_cfg", 1066 .channels = 1, 1067 .buswidth = 4, 1068 }; 1069 1070 static struct qcom_icc_node qhs_usb2_0 = { 1071 .name = "qhs_usb2_0", 1072 .channels = 1, 1073 .buswidth = 4, 1074 }; 1075 1076 static struct qcom_icc_node qhs_usb3_0 = { 1077 .name = "qhs_usb3_0", 1078 .channels = 1, 1079 .buswidth = 4, 1080 }; 1081 1082 static struct qcom_icc_node qhs_venus_cfg = { 1083 .name = "qhs_venus_cfg", 1084 .channels = 1, 1085 .buswidth = 4, 1086 }; 1087 1088 static struct qcom_icc_node qhs_venus_cvp_throttle_cfg = { 1089 .name = "qhs_venus_cvp_throttle_cfg", 1090 .channels = 1, 1091 .buswidth = 4, 1092 }; 1093 1094 static struct qcom_icc_node qhs_venus_v_cpu_throttle_cfg = { 1095 .name = "qhs_venus_v_cpu_throttle_cfg", 1096 .channels = 1, 1097 .buswidth = 4, 1098 }; 1099 1100 static struct qcom_icc_node qhs_venus_vcodec_throttle_cfg = { 1101 .name = "qhs_venus_vcodec_throttle_cfg", 1102 .channels = 1, 1103 .buswidth = 4, 1104 }; 1105 1106 static struct qcom_icc_node qns_ddrss_cfg = { 1107 .name = "qns_ddrss_cfg", 1108 .channels = 1, 1109 .buswidth = 4, 1110 .num_links = 1, 1111 .link_nodes = { &qnm_cnoc_dc_noc }, 1112 }; 1113 1114 static struct qcom_icc_node qns_gpdsp_noc_cfg = { 1115 .name = "qns_gpdsp_noc_cfg", 1116 .channels = 1, 1117 .buswidth = 4, 1118 }; 1119 1120 static struct qcom_icc_node qns_mnoc_hf_cfg = { 1121 .name = "qns_mnoc_hf_cfg", 1122 .channels = 1, 1123 .buswidth = 4, 1124 .num_links = 1, 1125 .link_nodes = { &qnm_mnoc_hf_cfg }, 1126 }; 1127 1128 static struct qcom_icc_node qns_mnoc_sf_cfg = { 1129 .name = "qns_mnoc_sf_cfg", 1130 .channels = 1, 1131 .buswidth = 4, 1132 .num_links = 1, 1133 .link_nodes = { &qnm_mnoc_sf_cfg }, 1134 }; 1135 1136 static struct qcom_icc_node qns_pcie_anoc_cfg = { 1137 .name = "qns_pcie_anoc_cfg", 1138 .channels = 1, 1139 .buswidth = 4, 1140 }; 1141 1142 static struct qcom_icc_node qns_snoc_cfg = { 1143 .name = "qns_snoc_cfg", 1144 .channels = 1, 1145 .buswidth = 4, 1146 .num_links = 1, 1147 .link_nodes = { &qnm_snoc_cfg }, 1148 }; 1149 1150 static struct qcom_icc_node qxs_boot_imem = { 1151 .name = "qxs_boot_imem", 1152 .channels = 1, 1153 .buswidth = 16, 1154 }; 1155 1156 static struct qcom_icc_node qxs_imem = { 1157 .name = "qxs_imem", 1158 .channels = 1, 1159 .buswidth = 8, 1160 }; 1161 1162 static struct qcom_icc_node qxs_pimem = { 1163 .name = "qxs_pimem", 1164 .channels = 1, 1165 .buswidth = 8, 1166 }; 1167 1168 static struct qcom_icc_node xs_pcie_0 = { 1169 .name = "xs_pcie_0", 1170 .channels = 1, 1171 .buswidth = 16, 1172 }; 1173 1174 static struct qcom_icc_node xs_pcie_1 = { 1175 .name = "xs_pcie_1", 1176 .channels = 1, 1177 .buswidth = 32, 1178 }; 1179 1180 static struct qcom_icc_node xs_qdss_stm = { 1181 .name = "xs_qdss_stm", 1182 .channels = 1, 1183 .buswidth = 4, 1184 }; 1185 1186 static struct qcom_icc_node xs_sys_tcu_cfg = { 1187 .name = "xs_sys_tcu_cfg", 1188 .channels = 1, 1189 .buswidth = 8, 1190 }; 1191 1192 static struct qcom_icc_node qhs_llcc = { 1193 .name = "qhs_llcc", 1194 .channels = 1, 1195 .buswidth = 4, 1196 }; 1197 1198 static struct qcom_icc_node qns_gemnoc = { 1199 .name = "qns_gemnoc", 1200 .channels = 1, 1201 .buswidth = 4, 1202 .num_links = 1, 1203 .link_nodes = { &qnm_gemnoc_cfg }, 1204 }; 1205 1206 static struct qcom_icc_node qns_gem_noc_cnoc = { 1207 .name = "qns_gem_noc_cnoc", 1208 .channels = 1, 1209 .buswidth = 16, 1210 .num_links = 1, 1211 .link_nodes = { &qnm_gemnoc_cnoc }, 1212 }; 1213 1214 static struct qcom_icc_node qns_llcc = { 1215 .name = "qns_llcc", 1216 .channels = 4, 1217 .buswidth = 16, 1218 .num_links = 1, 1219 .link_nodes = { &llcc_mc }, 1220 }; 1221 1222 static struct qcom_icc_node qns_pcie = { 1223 .name = "qns_pcie", 1224 .channels = 1, 1225 .buswidth = 16, 1226 .num_links = 1, 1227 .link_nodes = { &qnm_gemnoc_pcie }, 1228 }; 1229 1230 static struct qcom_icc_node srvc_even_gemnoc = { 1231 .name = "srvc_even_gemnoc", 1232 .channels = 1, 1233 .buswidth = 4, 1234 }; 1235 1236 static struct qcom_icc_node srvc_odd_gemnoc = { 1237 .name = "srvc_odd_gemnoc", 1238 .channels = 1, 1239 .buswidth = 4, 1240 }; 1241 1242 static struct qcom_icc_node srvc_sys_gemnoc = { 1243 .name = "srvc_sys_gemnoc", 1244 .channels = 1, 1245 .buswidth = 4, 1246 }; 1247 1248 static struct qcom_icc_node srvc_sys_gemnoc_2 = { 1249 .name = "srvc_sys_gemnoc_2", 1250 .channels = 1, 1251 .buswidth = 4, 1252 }; 1253 1254 static struct qcom_icc_node qns_gp_dsp_sail_noc = { 1255 .name = "qns_gp_dsp_sail_noc", 1256 .channels = 1, 1257 .buswidth = 16, 1258 .num_links = 1, 1259 .link_nodes = { &qnm_gpdsp_sail }, 1260 }; 1261 1262 static struct qcom_icc_node qhs_lpass_core = { 1263 .name = "qhs_lpass_core", 1264 .channels = 1, 1265 .buswidth = 4, 1266 }; 1267 1268 static struct qcom_icc_node qhs_lpass_lpi = { 1269 .name = "qhs_lpass_lpi", 1270 .channels = 1, 1271 .buswidth = 4, 1272 }; 1273 1274 static struct qcom_icc_node qhs_lpass_mpu = { 1275 .name = "qhs_lpass_mpu", 1276 .channels = 1, 1277 .buswidth = 4, 1278 }; 1279 1280 static struct qcom_icc_node qhs_lpass_top = { 1281 .name = "qhs_lpass_top", 1282 .channels = 1, 1283 .buswidth = 4, 1284 }; 1285 1286 static struct qcom_icc_node qns_sysnoc = { 1287 .name = "qns_sysnoc", 1288 .channels = 1, 1289 .buswidth = 16, 1290 .num_links = 1, 1291 .link_nodes = { &qnm_lpass_noc }, 1292 }; 1293 1294 static struct qcom_icc_node srvc_niu_aml_noc = { 1295 .name = "srvc_niu_aml_noc", 1296 .channels = 1, 1297 .buswidth = 4, 1298 }; 1299 1300 static struct qcom_icc_node srvc_niu_lpass_agnoc = { 1301 .name = "srvc_niu_lpass_agnoc", 1302 .channels = 1, 1303 .buswidth = 4, 1304 }; 1305 1306 static struct qcom_icc_node ebi = { 1307 .name = "ebi", 1308 .channels = 8, 1309 .buswidth = 4, 1310 }; 1311 1312 static struct qcom_icc_node qns_mem_noc_hf = { 1313 .name = "qns_mem_noc_hf", 1314 .channels = 2, 1315 .buswidth = 32, 1316 .num_links = 1, 1317 .link_nodes = { &qnm_mnoc_hf }, 1318 }; 1319 1320 static struct qcom_icc_node qns_mem_noc_sf = { 1321 .name = "qns_mem_noc_sf", 1322 .channels = 2, 1323 .buswidth = 32, 1324 .num_links = 1, 1325 .link_nodes = { &qnm_mnoc_sf }, 1326 }; 1327 1328 static struct qcom_icc_node srvc_mnoc_hf = { 1329 .name = "srvc_mnoc_hf", 1330 .channels = 1, 1331 .buswidth = 4, 1332 }; 1333 1334 static struct qcom_icc_node srvc_mnoc_sf = { 1335 .name = "srvc_mnoc_sf", 1336 .channels = 1, 1337 .buswidth = 4, 1338 }; 1339 1340 static struct qcom_icc_node qns_hcp = { 1341 .name = "qns_hcp", 1342 .channels = 2, 1343 .buswidth = 32, 1344 }; 1345 1346 static struct qcom_icc_node qns_nsp_gemnoc = { 1347 .name = "qns_nsp_gemnoc", 1348 .channels = 2, 1349 .buswidth = 32, 1350 .num_links = 1, 1351 .link_nodes = { &qnm_cmpnoc0 }, 1352 }; 1353 1354 static struct qcom_icc_node service_nsp_noc = { 1355 .name = "service_nsp_noc", 1356 .channels = 1, 1357 .buswidth = 4, 1358 }; 1359 1360 static struct qcom_icc_node qns_pcie_mem_noc = { 1361 .name = "qns_pcie_mem_noc", 1362 .channels = 1, 1363 .buswidth = 32, 1364 .num_links = 1, 1365 .link_nodes = { &qnm_pcie }, 1366 }; 1367 1368 static struct qcom_icc_node qns_gemnoc_gc = { 1369 .name = "qns_gemnoc_gc", 1370 .channels = 1, 1371 .buswidth = 8, 1372 .num_links = 1, 1373 .link_nodes = { &qnm_snoc_gc }, 1374 }; 1375 1376 static struct qcom_icc_node qns_gemnoc_sf = { 1377 .name = "qns_gemnoc_sf", 1378 .channels = 1, 1379 .buswidth = 16, 1380 .num_links = 1, 1381 .link_nodes = { &qnm_snoc_sf }, 1382 }; 1383 1384 static struct qcom_icc_node srvc_snoc = { 1385 .name = "srvc_snoc", 1386 .channels = 1, 1387 .buswidth = 4, 1388 }; 1389 1390 static struct qcom_icc_bcm bcm_acv = { 1391 .name = "ACV", 1392 .enable_mask = BIT(3), 1393 .num_nodes = 1, 1394 .nodes = { &ebi }, 1395 }; 1396 1397 static struct qcom_icc_bcm bcm_ce0 = { 1398 .name = "CE0", 1399 .num_nodes = 2, 1400 .nodes = { &qxm_crypto_0, &qxm_crypto_1 }, 1401 }; 1402 1403 static struct qcom_icc_bcm bcm_cn0 = { 1404 .name = "CN0", 1405 .keepalive = true, 1406 .num_nodes = 2, 1407 .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie }, 1408 }; 1409 1410 static struct qcom_icc_bcm bcm_cn1 = { 1411 .name = "CN1", 1412 .num_nodes = 66, 1413 .nodes = { &qhs_ahb2phy2, &qhs_ahb2phy3, 1414 &qhs_anoc_throttle_cfg, &qhs_aoss, 1415 &qhs_apss, &qhs_boot_rom, 1416 &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg, 1417 &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, 1418 &qhs_compute0_cfg, &qhs_cpr_cx, 1419 &qhs_cpr_mmcx, &qhs_cpr_mx, 1420 &qhs_cpr_nspcx, &qhs_cpr_nsphmx, 1421 &qhs_crypto0_cfg, &qhs_cx_rdpm, 1422 &qhs_display0_cfg, &qhs_display0_rt_throttle_cfg, 1423 &qhs_emac0_cfg, &qhs_gp_dsp0_cfg, 1424 &qhs_gpdsp0_throttle_cfg, &qhs_gpu_tcu_throttle_cfg, 1425 &qhs_gpuss_cfg, &qhs_hwkm, 1426 &qhs_imem_cfg, &qhs_ipa, 1427 &qhs_ipc_router, &qhs_lpass_cfg, 1428 &qhs_lpass_throttle_cfg, &qhs_mx_rdpm, 1429 &qhs_mxc_rdpm, &qhs_pcie0_cfg, 1430 &qhs_pcie1_cfg, &qhs_pcie_tcu_throttle_cfg, 1431 &qhs_pcie_throttle_cfg, &qhs_pdm, 1432 &qhs_pimem_cfg, &qhs_pke_wrapper_cfg, 1433 &qhs_qdss_cfg, &qhs_qm_cfg, 1434 &qhs_qm_mpu_cfg, &qhs_sail_throttle_cfg, 1435 &qhs_sdc1, &qhs_security, 1436 &qhs_snoc_throttle_cfg, &qhs_tcsr, 1437 &qhs_tlmm, &qhs_tsc_cfg, 1438 &qhs_ufs_mem_cfg, &qhs_usb2_0, 1439 &qhs_usb3_0, &qhs_venus_cfg, 1440 &qhs_venus_cvp_throttle_cfg, &qhs_venus_v_cpu_throttle_cfg, 1441 &qhs_venus_vcodec_throttle_cfg, &qns_ddrss_cfg, 1442 &qns_gpdsp_noc_cfg, &qns_mnoc_hf_cfg, 1443 &qns_mnoc_sf_cfg, &qns_pcie_anoc_cfg, 1444 &qns_snoc_cfg, &qxs_boot_imem, 1445 &qxs_imem, &xs_sys_tcu_cfg }, 1446 }; 1447 1448 static struct qcom_icc_bcm bcm_cn2 = { 1449 .name = "CN2", 1450 .num_nodes = 3, 1451 .nodes = { &qhs_qup0, &qhs_qup1, 1452 &qhs_qup3 }, 1453 }; 1454 1455 static struct qcom_icc_bcm bcm_cn3 = { 1456 .name = "CN3", 1457 .num_nodes = 2, 1458 .nodes = { &xs_pcie_0, &xs_pcie_1 }, 1459 }; 1460 1461 static struct qcom_icc_bcm bcm_gna0 = { 1462 .name = "GNA0", 1463 .num_nodes = 1, 1464 .nodes = { &qxm_dsp0 }, 1465 }; 1466 1467 static struct qcom_icc_bcm bcm_mc0 = { 1468 .name = "MC0", 1469 .keepalive = true, 1470 .num_nodes = 1, 1471 .nodes = { &ebi }, 1472 }; 1473 1474 static struct qcom_icc_bcm bcm_mm0 = { 1475 .name = "MM0", 1476 .keepalive = true, 1477 .num_nodes = 4, 1478 .nodes = { &qnm_camnoc_hf, &qnm_mdp0_0, 1479 &qnm_mdp0_1, &qns_mem_noc_hf }, 1480 }; 1481 1482 static struct qcom_icc_bcm bcm_mm1 = { 1483 .name = "MM1", 1484 .num_nodes = 6, 1485 .nodes = { &qnm_camnoc_icp, &qnm_camnoc_sf, 1486 &qnm_video0, &qnm_video_cvp, 1487 &qnm_video_v_cpu, &qns_mem_noc_sf }, 1488 }; 1489 1490 static struct qcom_icc_bcm bcm_nsa0 = { 1491 .name = "NSA0", 1492 .num_nodes = 2, 1493 .nodes = { &qns_hcp, &qns_nsp_gemnoc }, 1494 }; 1495 1496 static struct qcom_icc_bcm bcm_nsa1 = { 1497 .name = "NSA1", 1498 .num_nodes = 1, 1499 .nodes = { &qxm_nsp }, 1500 }; 1501 1502 static struct qcom_icc_bcm bcm_pci0 = { 1503 .name = "PCI0", 1504 .num_nodes = 1, 1505 .nodes = { &qns_pcie_mem_noc }, 1506 }; 1507 1508 static struct qcom_icc_bcm bcm_qup0 = { 1509 .name = "QUP0", 1510 .vote_scale = 1, 1511 .keepalive = true, 1512 .num_nodes = 1, 1513 .nodes = { &qup0_core_slave }, 1514 }; 1515 1516 static struct qcom_icc_bcm bcm_qup1 = { 1517 .name = "QUP1", 1518 .vote_scale = 1, 1519 .keepalive = true, 1520 .num_nodes = 1, 1521 .nodes = { &qup1_core_slave }, 1522 }; 1523 1524 static struct qcom_icc_bcm bcm_qup2 = { 1525 .name = "QUP2", 1526 .vote_scale = 1, 1527 .keepalive = true, 1528 .num_nodes = 1, 1529 .nodes = { &qup3_core_slave }, 1530 }; 1531 1532 static struct qcom_icc_bcm bcm_sh0 = { 1533 .name = "SH0", 1534 .keepalive = true, 1535 .num_nodes = 1, 1536 .nodes = { &qns_llcc }, 1537 }; 1538 1539 static struct qcom_icc_bcm bcm_sh2 = { 1540 .name = "SH2", 1541 .num_nodes = 1, 1542 .nodes = { &chm_apps }, 1543 }; 1544 1545 static struct qcom_icc_bcm bcm_sn0 = { 1546 .name = "SN0", 1547 .keepalive = true, 1548 .num_nodes = 1, 1549 .nodes = { &qns_gemnoc_sf }, 1550 }; 1551 1552 static struct qcom_icc_bcm bcm_sn1 = { 1553 .name = "SN1", 1554 .num_nodes = 1, 1555 .nodes = { &qns_gemnoc_gc }, 1556 }; 1557 1558 static struct qcom_icc_bcm bcm_sn2 = { 1559 .name = "SN2", 1560 .num_nodes = 1, 1561 .nodes = { &qxs_pimem }, 1562 }; 1563 1564 static struct qcom_icc_bcm bcm_sn3 = { 1565 .name = "SN3", 1566 .num_nodes = 2, 1567 .nodes = { &qns_a1noc_snoc, &qnm_aggre1_noc }, 1568 }; 1569 1570 static struct qcom_icc_bcm bcm_sn4 = { 1571 .name = "SN4", 1572 .num_nodes = 2, 1573 .nodes = { &qns_a2noc_snoc, &qnm_aggre2_noc }, 1574 }; 1575 1576 static struct qcom_icc_bcm bcm_sn9 = { 1577 .name = "SN9", 1578 .num_nodes = 2, 1579 .nodes = { &qns_sysnoc, &qnm_lpass_noc }, 1580 }; 1581 1582 static struct qcom_icc_bcm bcm_sn10 = { 1583 .name = "SN10", 1584 .num_nodes = 1, 1585 .nodes = { &xs_qdss_stm }, 1586 }; 1587 1588 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 1589 &bcm_sn3, 1590 }; 1591 1592 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1593 [MASTER_QUP_3] = &qxm_qup3, 1594 [MASTER_EMAC] = &xm_emac_0, 1595 [MASTER_SDC] = &xm_sdc1, 1596 [MASTER_UFS_MEM] = &xm_ufs_mem, 1597 [MASTER_USB2] = &xm_usb2_2, 1598 [MASTER_USB3_0] = &xm_usb3_0, 1599 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, 1600 }; 1601 1602 static const struct qcom_icc_desc qcs8300_aggre1_noc = { 1603 .nodes = aggre1_noc_nodes, 1604 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 1605 .bcms = aggre1_noc_bcms, 1606 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 1607 }; 1608 1609 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 1610 &bcm_ce0, 1611 &bcm_sn4, 1612 }; 1613 1614 static struct qcom_icc_node * const aggre2_noc_nodes[] = { 1615 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 1616 [MASTER_QUP_0] = &qhm_qup0, 1617 [MASTER_QUP_1] = &qhm_qup1, 1618 [MASTER_CNOC_A2NOC] = &qnm_cnoc_datapath, 1619 [MASTER_CRYPTO_CORE0] = &qxm_crypto_0, 1620 [MASTER_CRYPTO_CORE1] = &qxm_crypto_1, 1621 [MASTER_IPA] = &qxm_ipa, 1622 [MASTER_QDSS_ETR_0] = &xm_qdss_etr_0, 1623 [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1, 1624 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, 1625 }; 1626 1627 static const struct qcom_icc_desc qcs8300_aggre2_noc = { 1628 .nodes = aggre2_noc_nodes, 1629 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 1630 .bcms = aggre2_noc_bcms, 1631 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 1632 }; 1633 1634 static struct qcom_icc_bcm * const clk_virt_bcms[] = { 1635 &bcm_qup0, 1636 &bcm_qup1, 1637 &bcm_qup2, 1638 }; 1639 1640 static struct qcom_icc_node * const clk_virt_nodes[] = { 1641 [MASTER_QUP_CORE_0] = &qup0_core_master, 1642 [MASTER_QUP_CORE_1] = &qup1_core_master, 1643 [MASTER_QUP_CORE_3] = &qup3_core_master, 1644 [SLAVE_QUP_CORE_0] = &qup0_core_slave, 1645 [SLAVE_QUP_CORE_1] = &qup1_core_slave, 1646 [SLAVE_QUP_CORE_3] = &qup3_core_slave, 1647 }; 1648 1649 static const struct qcom_icc_desc qcs8300_clk_virt = { 1650 .nodes = clk_virt_nodes, 1651 .num_nodes = ARRAY_SIZE(clk_virt_nodes), 1652 .bcms = clk_virt_bcms, 1653 .num_bcms = ARRAY_SIZE(clk_virt_bcms), 1654 }; 1655 1656 static struct qcom_icc_bcm * const config_noc_bcms[] = { 1657 &bcm_cn0, 1658 &bcm_cn1, 1659 &bcm_cn2, 1660 &bcm_cn3, 1661 &bcm_sn2, 1662 &bcm_sn10, 1663 }; 1664 1665 static struct qcom_icc_node * const config_noc_nodes[] = { 1666 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, 1667 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, 1668 [SLAVE_AHB2PHY_2] = &qhs_ahb2phy2, 1669 [SLAVE_AHB2PHY_3] = &qhs_ahb2phy3, 1670 [SLAVE_ANOC_THROTTLE_CFG] = &qhs_anoc_throttle_cfg, 1671 [SLAVE_AOSS] = &qhs_aoss, 1672 [SLAVE_APPSS] = &qhs_apss, 1673 [SLAVE_BOOT_ROM] = &qhs_boot_rom, 1674 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 1675 [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_throttle_cfg, 1676 [SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg, 1677 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1678 [SLAVE_CDSP_CFG] = &qhs_compute0_cfg, 1679 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 1680 [SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx, 1681 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, 1682 [SLAVE_CPR_NSPCX] = &qhs_cpr_nspcx, 1683 [SLAVE_CPR_NSPHMX] = &qhs_cpr_nsphmx, 1684 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1685 [SLAVE_CX_RDPM] = &qhs_cx_rdpm, 1686 [SLAVE_DISPLAY_CFG] = &qhs_display0_cfg, 1687 [SLAVE_DISPLAY_RT_THROTTLE_CFG] = &qhs_display0_rt_throttle_cfg, 1688 [SLAVE_EMAC_CFG] = &qhs_emac0_cfg, 1689 [SLAVE_GP_DSP0_CFG] = &qhs_gp_dsp0_cfg, 1690 [SLAVE_GPDSP0_THROTTLE_CFG] = &qhs_gpdsp0_throttle_cfg, 1691 [SLAVE_GPU_TCU_THROTTLE_CFG] = &qhs_gpu_tcu_throttle_cfg, 1692 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, 1693 [SLAVE_HWKM] = &qhs_hwkm, 1694 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1695 [SLAVE_IPA_CFG] = &qhs_ipa, 1696 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, 1697 [SLAVE_LPASS] = &qhs_lpass_cfg, 1698 [SLAVE_LPASS_THROTTLE_CFG] = &qhs_lpass_throttle_cfg, 1699 [SLAVE_MX_RDPM] = &qhs_mx_rdpm, 1700 [SLAVE_MXC_RDPM] = &qhs_mxc_rdpm, 1701 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, 1702 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, 1703 [SLAVE_PCIE_TCU_THROTTLE_CFG] = &qhs_pcie_tcu_throttle_cfg, 1704 [SLAVE_PCIE_THROTTLE_CFG] = &qhs_pcie_throttle_cfg, 1705 [SLAVE_PDM] = &qhs_pdm, 1706 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 1707 [SLAVE_PKA_WRAPPER_CFG] = &qhs_pke_wrapper_cfg, 1708 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1709 [SLAVE_QM_CFG] = &qhs_qm_cfg, 1710 [SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg, 1711 [SLAVE_QUP_0] = &qhs_qup0, 1712 [SLAVE_QUP_1] = &qhs_qup1, 1713 [SLAVE_QUP_3] = &qhs_qup3, 1714 [SLAVE_SAIL_THROTTLE_CFG] = &qhs_sail_throttle_cfg, 1715 [SLAVE_SDC1] = &qhs_sdc1, 1716 [SLAVE_SECURITY] = &qhs_security, 1717 [SLAVE_SNOC_THROTTLE_CFG] = &qhs_snoc_throttle_cfg, 1718 [SLAVE_TCSR] = &qhs_tcsr, 1719 [SLAVE_TLMM] = &qhs_tlmm, 1720 [SLAVE_TSC_CFG] = &qhs_tsc_cfg, 1721 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 1722 [SLAVE_USB2] = &qhs_usb2_0, 1723 [SLAVE_USB3_0] = &qhs_usb3_0, 1724 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1725 [SLAVE_VENUS_CVP_THROTTLE_CFG] = &qhs_venus_cvp_throttle_cfg, 1726 [SLAVE_VENUS_V_CPU_THROTTLE_CFG] = &qhs_venus_v_cpu_throttle_cfg, 1727 [SLAVE_VENUS_VCODEC_THROTTLE_CFG] = &qhs_venus_vcodec_throttle_cfg, 1728 [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg, 1729 [SLAVE_GPDSP_NOC_CFG] = &qns_gpdsp_noc_cfg, 1730 [SLAVE_CNOC_MNOC_HF_CFG] = &qns_mnoc_hf_cfg, 1731 [SLAVE_CNOC_MNOC_SF_CFG] = &qns_mnoc_sf_cfg, 1732 [SLAVE_PCIE_ANOC_CFG] = &qns_pcie_anoc_cfg, 1733 [SLAVE_SNOC_CFG] = &qns_snoc_cfg, 1734 [SLAVE_BOOT_IMEM] = &qxs_boot_imem, 1735 [SLAVE_IMEM] = &qxs_imem, 1736 [SLAVE_PIMEM] = &qxs_pimem, 1737 [SLAVE_PCIE_0] = &xs_pcie_0, 1738 [SLAVE_PCIE_1] = &xs_pcie_1, 1739 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1740 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1741 }; 1742 1743 static const struct qcom_icc_desc qcs8300_config_noc = { 1744 .nodes = config_noc_nodes, 1745 .num_nodes = ARRAY_SIZE(config_noc_nodes), 1746 .bcms = config_noc_bcms, 1747 .num_bcms = ARRAY_SIZE(config_noc_bcms), 1748 }; 1749 1750 static struct qcom_icc_node * const dc_noc_nodes[] = { 1751 [MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc, 1752 [SLAVE_LLCC_CFG] = &qhs_llcc, 1753 [SLAVE_GEM_NOC_CFG] = &qns_gemnoc, 1754 }; 1755 1756 static const struct qcom_icc_desc qcs8300_dc_noc = { 1757 .nodes = dc_noc_nodes, 1758 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 1759 }; 1760 1761 static struct qcom_icc_bcm * const gem_noc_bcms[] = { 1762 &bcm_sh0, 1763 &bcm_sh2, 1764 }; 1765 1766 static struct qcom_icc_node * const gem_noc_nodes[] = { 1767 [MASTER_GPU_TCU] = &alm_gpu_tcu, 1768 [MASTER_PCIE_TCU] = &alm_pcie_tcu, 1769 [MASTER_SYS_TCU] = &alm_sys_tcu, 1770 [MASTER_APPSS_PROC] = &chm_apps, 1771 [MASTER_COMPUTE_NOC] = &qnm_cmpnoc0, 1772 [MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg, 1773 [MASTER_GPDSP_SAIL] = &qnm_gpdsp_sail, 1774 [MASTER_GFX3D] = &qnm_gpu, 1775 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 1776 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 1777 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, 1778 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 1779 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 1780 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, 1781 [SLAVE_LLCC] = &qns_llcc, 1782 [SLAVE_GEM_NOC_PCIE_CNOC] = &qns_pcie, 1783 [SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc, 1784 [SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc, 1785 [SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc, 1786 [SLAVE_SERVICE_GEM_NOC2] = &srvc_sys_gemnoc_2, 1787 }; 1788 1789 static const struct qcom_icc_desc qcs8300_gem_noc = { 1790 .nodes = gem_noc_nodes, 1791 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 1792 .bcms = gem_noc_bcms, 1793 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 1794 }; 1795 1796 static struct qcom_icc_bcm * const gpdsp_anoc_bcms[] = { 1797 &bcm_gna0, 1798 }; 1799 1800 static struct qcom_icc_node * const gpdsp_anoc_nodes[] = { 1801 [MASTER_SAILSS_MD0] = &qnm_sailss_md0, 1802 [MASTER_DSP0] = &qxm_dsp0, 1803 [SLAVE_GP_DSP_SAIL_NOC] = &qns_gp_dsp_sail_noc, 1804 }; 1805 1806 static const struct qcom_icc_desc qcs8300_gpdsp_anoc = { 1807 .nodes = gpdsp_anoc_nodes, 1808 .num_nodes = ARRAY_SIZE(gpdsp_anoc_nodes), 1809 .bcms = gpdsp_anoc_bcms, 1810 .num_bcms = ARRAY_SIZE(gpdsp_anoc_bcms), 1811 }; 1812 1813 static struct qcom_icc_bcm * const lpass_ag_noc_bcms[] = { 1814 &bcm_sn9, 1815 }; 1816 1817 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { 1818 [MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc, 1819 [MASTER_LPASS_PROC] = &qxm_lpass_dsp, 1820 [SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core, 1821 [SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi, 1822 [SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu, 1823 [SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top, 1824 [SLAVE_LPASS_SNOC] = &qns_sysnoc, 1825 [SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc, 1826 [SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc, 1827 }; 1828 1829 static const struct qcom_icc_desc qcs8300_lpass_ag_noc = { 1830 .nodes = lpass_ag_noc_nodes, 1831 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), 1832 .bcms = lpass_ag_noc_bcms, 1833 .num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms), 1834 }; 1835 1836 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 1837 &bcm_acv, 1838 &bcm_mc0, 1839 }; 1840 1841 static struct qcom_icc_node * const mc_virt_nodes[] = { 1842 [MASTER_LLCC] = &llcc_mc, 1843 [SLAVE_EBI1] = &ebi, 1844 }; 1845 1846 static const struct qcom_icc_desc qcs8300_mc_virt = { 1847 .nodes = mc_virt_nodes, 1848 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 1849 .bcms = mc_virt_bcms, 1850 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 1851 }; 1852 1853 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 1854 &bcm_mm0, 1855 &bcm_mm1, 1856 }; 1857 1858 static struct qcom_icc_node * const mmss_noc_nodes[] = { 1859 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, 1860 [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp, 1861 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, 1862 [MASTER_MDP0] = &qnm_mdp0_0, 1863 [MASTER_MDP1] = &qnm_mdp0_1, 1864 [MASTER_CNOC_MNOC_HF_CFG] = &qnm_mnoc_hf_cfg, 1865 [MASTER_CNOC_MNOC_SF_CFG] = &qnm_mnoc_sf_cfg, 1866 [MASTER_VIDEO_P0] = &qnm_video0, 1867 [MASTER_VIDEO_PROC] = &qnm_video_cvp, 1868 [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu, 1869 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 1870 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, 1871 [SLAVE_SERVICE_MNOC_HF] = &srvc_mnoc_hf, 1872 [SLAVE_SERVICE_MNOC_SF] = &srvc_mnoc_sf, 1873 }; 1874 1875 static const struct qcom_icc_desc qcs8300_mmss_noc = { 1876 .nodes = mmss_noc_nodes, 1877 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 1878 .bcms = mmss_noc_bcms, 1879 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 1880 }; 1881 1882 static struct qcom_icc_bcm * const nspa_noc_bcms[] = { 1883 &bcm_nsa0, 1884 &bcm_nsa1, 1885 }; 1886 1887 static struct qcom_icc_node * const nspa_noc_nodes[] = { 1888 [MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config, 1889 [MASTER_CDSP_PROC] = &qxm_nsp, 1890 [SLAVE_HCP_A] = &qns_hcp, 1891 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, 1892 [SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc, 1893 }; 1894 1895 static const struct qcom_icc_desc qcs8300_nspa_noc = { 1896 .nodes = nspa_noc_nodes, 1897 .num_nodes = ARRAY_SIZE(nspa_noc_nodes), 1898 .bcms = nspa_noc_bcms, 1899 .num_bcms = ARRAY_SIZE(nspa_noc_bcms), 1900 }; 1901 1902 static struct qcom_icc_bcm * const pcie_anoc_bcms[] = { 1903 &bcm_pci0, 1904 }; 1905 1906 static struct qcom_icc_node * const pcie_anoc_nodes[] = { 1907 [MASTER_PCIE_0] = &xm_pcie3_0, 1908 [MASTER_PCIE_1] = &xm_pcie3_1, 1909 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, 1910 }; 1911 1912 static const struct qcom_icc_desc qcs8300_pcie_anoc = { 1913 .nodes = pcie_anoc_nodes, 1914 .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), 1915 .bcms = pcie_anoc_bcms, 1916 .num_bcms = ARRAY_SIZE(pcie_anoc_bcms), 1917 }; 1918 1919 static struct qcom_icc_bcm * const system_noc_bcms[] = { 1920 &bcm_sn0, 1921 &bcm_sn1, 1922 &bcm_sn3, 1923 &bcm_sn4, 1924 &bcm_sn9, 1925 }; 1926 1927 static struct qcom_icc_node * const system_noc_nodes[] = { 1928 [MASTER_GIC_AHB] = &qhm_gic, 1929 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, 1930 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, 1931 [MASTER_LPASS_ANOC] = &qnm_lpass_noc, 1932 [MASTER_SNOC_CFG] = &qnm_snoc_cfg, 1933 [MASTER_PIMEM] = &qxm_pimem, 1934 [MASTER_GIC] = &xm_gic, 1935 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc, 1936 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 1937 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 1938 }; 1939 1940 static const struct qcom_icc_desc qcs8300_system_noc = { 1941 .nodes = system_noc_nodes, 1942 .num_nodes = ARRAY_SIZE(system_noc_nodes), 1943 .bcms = system_noc_bcms, 1944 .num_bcms = ARRAY_SIZE(system_noc_bcms), 1945 }; 1946 1947 static const struct of_device_id qnoc_of_match[] = { 1948 { .compatible = "qcom,qcs8300-aggre1-noc", 1949 .data = &qcs8300_aggre1_noc}, 1950 { .compatible = "qcom,qcs8300-aggre2-noc", 1951 .data = &qcs8300_aggre2_noc}, 1952 { .compatible = "qcom,qcs8300-clk-virt", 1953 .data = &qcs8300_clk_virt}, 1954 { .compatible = "qcom,qcs8300-config-noc", 1955 .data = &qcs8300_config_noc}, 1956 { .compatible = "qcom,qcs8300-dc-noc", 1957 .data = &qcs8300_dc_noc}, 1958 { .compatible = "qcom,qcs8300-gem-noc", 1959 .data = &qcs8300_gem_noc}, 1960 { .compatible = "qcom,qcs8300-gpdsp-anoc", 1961 .data = &qcs8300_gpdsp_anoc}, 1962 { .compatible = "qcom,qcs8300-lpass-ag-noc", 1963 .data = &qcs8300_lpass_ag_noc}, 1964 { .compatible = "qcom,qcs8300-mc-virt", 1965 .data = &qcs8300_mc_virt}, 1966 { .compatible = "qcom,qcs8300-mmss-noc", 1967 .data = &qcs8300_mmss_noc}, 1968 { .compatible = "qcom,qcs8300-nspa-noc", 1969 .data = &qcs8300_nspa_noc}, 1970 { .compatible = "qcom,qcs8300-pcie-anoc", 1971 .data = &qcs8300_pcie_anoc}, 1972 { .compatible = "qcom,qcs8300-system-noc", 1973 .data = &qcs8300_system_noc}, 1974 { } 1975 }; 1976 MODULE_DEVICE_TABLE(of, qnoc_of_match); 1977 1978 static struct platform_driver qnoc_driver = { 1979 .probe = qcom_icc_rpmh_probe, 1980 .remove = qcom_icc_rpmh_remove, 1981 .driver = { 1982 .name = "qnoc-qcs8300", 1983 .of_match_table = qnoc_of_match, 1984 .sync_state = icc_sync_state, 1985 }, 1986 }; 1987 1988 static int __init qnoc_driver_init(void) 1989 { 1990 return platform_driver_register(&qnoc_driver); 1991 } 1992 core_initcall(qnoc_driver_init); 1993 1994 static void __exit qnoc_driver_exit(void) 1995 { 1996 platform_driver_unregister(&qnoc_driver); 1997 } 1998 module_exit(qnoc_driver_exit); 1999 2000 MODULE_DESCRIPTION("QCS8300 NoC driver"); 2001 MODULE_LICENSE("GPL"); 2002