1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 */ 6 7 #include <linux/device.h> 8 #include <linux/interconnect.h> 9 #include <linux/interconnect-provider.h> 10 #include <linux/module.h> 11 #include <linux/of_platform.h> 12 #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h> 13 14 #include "bcm-voter.h" 15 #include "icc-rpmh.h" 16 #include "qcs615.h" 17 18 static struct qcom_icc_node qhm_a1noc_cfg = { 19 .name = "qhm_a1noc_cfg", 20 .id = QCS615_MASTER_A1NOC_CFG, 21 .channels = 1, 22 .buswidth = 4, 23 .num_links = 1, 24 .links = { QCS615_SLAVE_SERVICE_A2NOC }, 25 }; 26 27 static struct qcom_icc_node qhm_qdss_bam = { 28 .name = "qhm_qdss_bam", 29 .id = QCS615_MASTER_QDSS_BAM, 30 .channels = 1, 31 .buswidth = 4, 32 .num_links = 1, 33 .links = { QCS615_SLAVE_A1NOC_SNOC }, 34 }; 35 36 static struct qcom_icc_node qhm_qspi = { 37 .name = "qhm_qspi", 38 .id = QCS615_MASTER_QSPI, 39 .channels = 1, 40 .buswidth = 4, 41 .num_links = 1, 42 .links = { QCS615_SLAVE_A1NOC_SNOC }, 43 }; 44 45 static struct qcom_icc_node qhm_qup0 = { 46 .name = "qhm_qup0", 47 .id = QCS615_MASTER_QUP_0, 48 .channels = 1, 49 .buswidth = 4, 50 .num_links = 1, 51 .links = { QCS615_SLAVE_A1NOC_SNOC }, 52 }; 53 54 static struct qcom_icc_node qhm_qup1 = { 55 .name = "qhm_qup1", 56 .id = QCS615_MASTER_BLSP_1, 57 .channels = 1, 58 .buswidth = 4, 59 .num_links = 1, 60 .links = { QCS615_SLAVE_A1NOC_SNOC }, 61 }; 62 63 static struct qcom_icc_node qnm_cnoc = { 64 .name = "qnm_cnoc", 65 .id = QCS615_MASTER_CNOC_A2NOC, 66 .channels = 1, 67 .buswidth = 8, 68 .num_links = 1, 69 .links = { QCS615_SLAVE_A1NOC_SNOC }, 70 }; 71 72 static struct qcom_icc_node qxm_crypto = { 73 .name = "qxm_crypto", 74 .id = QCS615_MASTER_CRYPTO, 75 .channels = 1, 76 .buswidth = 8, 77 .num_links = 1, 78 .links = { QCS615_SLAVE_A1NOC_SNOC }, 79 }; 80 81 static struct qcom_icc_node qxm_ipa = { 82 .name = "qxm_ipa", 83 .id = QCS615_MASTER_IPA, 84 .channels = 1, 85 .buswidth = 8, 86 .num_links = 1, 87 .links = { QCS615_SLAVE_LPASS_SNOC }, 88 }; 89 90 static struct qcom_icc_node xm_emac_avb = { 91 .name = "xm_emac_avb", 92 .id = QCS615_MASTER_EMAC_EVB, 93 .channels = 1, 94 .buswidth = 8, 95 .num_links = 1, 96 .links = { QCS615_SLAVE_A1NOC_SNOC }, 97 }; 98 99 static struct qcom_icc_node xm_pcie = { 100 .name = "xm_pcie", 101 .id = QCS615_MASTER_PCIE, 102 .channels = 1, 103 .buswidth = 8, 104 .num_links = 1, 105 .links = { QCS615_SLAVE_ANOC_PCIE_SNOC }, 106 }; 107 108 static struct qcom_icc_node xm_qdss_etr = { 109 .name = "xm_qdss_etr", 110 .id = QCS615_MASTER_QDSS_ETR, 111 .channels = 1, 112 .buswidth = 8, 113 .num_links = 1, 114 .links = { QCS615_SLAVE_A1NOC_SNOC }, 115 }; 116 117 static struct qcom_icc_node xm_sdc1 = { 118 .name = "xm_sdc1", 119 .id = QCS615_MASTER_SDCC_1, 120 .channels = 1, 121 .buswidth = 8, 122 .num_links = 1, 123 .links = { QCS615_SLAVE_A1NOC_SNOC }, 124 }; 125 126 static struct qcom_icc_node xm_sdc2 = { 127 .name = "xm_sdc2", 128 .id = QCS615_MASTER_SDCC_2, 129 .channels = 1, 130 .buswidth = 8, 131 .num_links = 1, 132 .links = { QCS615_SLAVE_A1NOC_SNOC }, 133 }; 134 135 static struct qcom_icc_node xm_ufs_mem = { 136 .name = "xm_ufs_mem", 137 .id = QCS615_MASTER_UFS_MEM, 138 .channels = 1, 139 .buswidth = 8, 140 .num_links = 1, 141 .links = { QCS615_SLAVE_A1NOC_SNOC }, 142 }; 143 144 static struct qcom_icc_node xm_usb2 = { 145 .name = "xm_usb2", 146 .id = QCS615_MASTER_USB2, 147 .channels = 1, 148 .buswidth = 8, 149 .num_links = 1, 150 .links = { QCS615_SLAVE_A1NOC_SNOC }, 151 }; 152 153 static struct qcom_icc_node xm_usb3_0 = { 154 .name = "xm_usb3_0", 155 .id = QCS615_MASTER_USB3_0, 156 .channels = 1, 157 .buswidth = 8, 158 .num_links = 1, 159 .links = { QCS615_SLAVE_A1NOC_SNOC }, 160 }; 161 162 static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { 163 .name = "qxm_camnoc_hf0_uncomp", 164 .id = QCS615_MASTER_CAMNOC_HF0_UNCOMP, 165 .channels = 1, 166 .buswidth = 32, 167 .num_links = 1, 168 .links = { QCS615_SLAVE_CAMNOC_UNCOMP }, 169 }; 170 171 static struct qcom_icc_node qxm_camnoc_hf1_uncomp = { 172 .name = "qxm_camnoc_hf1_uncomp", 173 .id = QCS615_MASTER_CAMNOC_HF1_UNCOMP, 174 .channels = 1, 175 .buswidth = 32, 176 .num_links = 1, 177 .links = { QCS615_SLAVE_CAMNOC_UNCOMP }, 178 }; 179 180 static struct qcom_icc_node qxm_camnoc_sf_uncomp = { 181 .name = "qxm_camnoc_sf_uncomp", 182 .id = QCS615_MASTER_CAMNOC_SF_UNCOMP, 183 .channels = 1, 184 .buswidth = 32, 185 .num_links = 1, 186 .links = { QCS615_SLAVE_CAMNOC_UNCOMP }, 187 }; 188 189 static struct qcom_icc_node qhm_spdm = { 190 .name = "qhm_spdm", 191 .id = QCS615_MASTER_SPDM, 192 .channels = 1, 193 .buswidth = 4, 194 .num_links = 1, 195 .links = { QCS615_SLAVE_CNOC_A2NOC }, 196 }; 197 198 static struct qcom_icc_node qnm_snoc = { 199 .name = "qnm_snoc", 200 .id = QCS615_MASTER_SNOC_CNOC, 201 .channels = 1, 202 .buswidth = 8, 203 .num_links = 39, 204 .links = { QCS615_SLAVE_A1NOC_CFG, QCS615_SLAVE_AHB2PHY_EAST, 205 QCS615_SLAVE_AHB2PHY_WEST, QCS615_SLAVE_AOP, 206 QCS615_SLAVE_AOSS, QCS615_SLAVE_CAMERA_CFG, 207 QCS615_SLAVE_CLK_CTL, QCS615_SLAVE_RBCPR_CX_CFG, 208 QCS615_SLAVE_RBCPR_MX_CFG, QCS615_SLAVE_CRYPTO_0_CFG, 209 QCS615_SLAVE_CNOC_DDRSS, QCS615_SLAVE_DISPLAY_CFG, 210 QCS615_SLAVE_EMAC_AVB_CFG, QCS615_SLAVE_GLM, 211 QCS615_SLAVE_GFX3D_CFG, QCS615_SLAVE_IMEM_CFG, 212 QCS615_SLAVE_IPA_CFG, QCS615_SLAVE_CNOC_MNOC_CFG, 213 QCS615_SLAVE_PCIE_CFG, QCS615_SLAVE_PIMEM_CFG, 214 QCS615_SLAVE_PRNG, QCS615_SLAVE_QDSS_CFG, 215 QCS615_SLAVE_QSPI, QCS615_SLAVE_QUP_0, 216 QCS615_SLAVE_QUP_1, QCS615_SLAVE_SDCC_1, 217 QCS615_SLAVE_SDCC_2, QCS615_SLAVE_SNOC_CFG, 218 QCS615_SLAVE_SPDM_WRAPPER, QCS615_SLAVE_TCSR, 219 QCS615_SLAVE_TLMM_EAST, QCS615_SLAVE_TLMM_SOUTH, 220 QCS615_SLAVE_TLMM_WEST, QCS615_SLAVE_UFS_MEM_CFG, 221 QCS615_SLAVE_USB2, QCS615_SLAVE_USB3, 222 QCS615_SLAVE_VENUS_CFG, QCS615_SLAVE_VSENSE_CTRL_CFG, 223 QCS615_SLAVE_SERVICE_CNOC }, 224 }; 225 226 static struct qcom_icc_node xm_qdss_dap = { 227 .name = "xm_qdss_dap", 228 .id = QCS615_MASTER_QDSS_DAP, 229 .channels = 1, 230 .buswidth = 8, 231 .num_links = 40, 232 .links = { QCS615_SLAVE_A1NOC_CFG, QCS615_SLAVE_AHB2PHY_EAST, 233 QCS615_SLAVE_AHB2PHY_WEST, QCS615_SLAVE_AOP, 234 QCS615_SLAVE_AOSS, QCS615_SLAVE_CAMERA_CFG, 235 QCS615_SLAVE_CLK_CTL, QCS615_SLAVE_RBCPR_CX_CFG, 236 QCS615_SLAVE_RBCPR_MX_CFG, QCS615_SLAVE_CRYPTO_0_CFG, 237 QCS615_SLAVE_CNOC_DDRSS, QCS615_SLAVE_DISPLAY_CFG, 238 QCS615_SLAVE_EMAC_AVB_CFG, QCS615_SLAVE_GLM, 239 QCS615_SLAVE_GFX3D_CFG, QCS615_SLAVE_IMEM_CFG, 240 QCS615_SLAVE_IPA_CFG, QCS615_SLAVE_CNOC_MNOC_CFG, 241 QCS615_SLAVE_PCIE_CFG, QCS615_SLAVE_PIMEM_CFG, 242 QCS615_SLAVE_PRNG, QCS615_SLAVE_QDSS_CFG, 243 QCS615_SLAVE_QSPI, QCS615_SLAVE_QUP_0, 244 QCS615_SLAVE_QUP_1, QCS615_SLAVE_SDCC_1, 245 QCS615_SLAVE_SDCC_2, QCS615_SLAVE_SNOC_CFG, 246 QCS615_SLAVE_SPDM_WRAPPER, QCS615_SLAVE_TCSR, 247 QCS615_SLAVE_TLMM_EAST, QCS615_SLAVE_TLMM_SOUTH, 248 QCS615_SLAVE_TLMM_WEST, QCS615_SLAVE_UFS_MEM_CFG, 249 QCS615_SLAVE_USB2, QCS615_SLAVE_USB3, 250 QCS615_SLAVE_VENUS_CFG, QCS615_SLAVE_VSENSE_CTRL_CFG, 251 QCS615_SLAVE_CNOC_A2NOC, QCS615_SLAVE_SERVICE_CNOC }, 252 }; 253 254 static struct qcom_icc_node qhm_cnoc = { 255 .name = "qhm_cnoc", 256 .id = QCS615_MASTER_CNOC_DC_NOC, 257 .channels = 1, 258 .buswidth = 4, 259 .num_links = 2, 260 .links = { QCS615_SLAVE_DC_NOC_GEMNOC, QCS615_SLAVE_LLCC_CFG }, 261 }; 262 263 static struct qcom_icc_node acm_apps = { 264 .name = "acm_apps", 265 .id = QCS615_MASTER_APPSS_PROC, 266 .channels = 1, 267 .buswidth = 16, 268 .num_links = 3, 269 .links = { QCS615_SLAVE_GEM_NOC_SNOC, QCS615_SLAVE_LLCC, 270 QCS615_SLAVE_MEM_NOC_PCIE_SNOC }, 271 }; 272 273 static struct qcom_icc_node acm_gpu_tcu = { 274 .name = "acm_gpu_tcu", 275 .id = QCS615_MASTER_GPU_TCU, 276 .channels = 1, 277 .buswidth = 8, 278 .num_links = 2, 279 .links = { QCS615_SLAVE_GEM_NOC_SNOC, QCS615_SLAVE_LLCC }, 280 }; 281 282 static struct qcom_icc_node acm_sys_tcu = { 283 .name = "acm_sys_tcu", 284 .id = QCS615_MASTER_SYS_TCU, 285 .channels = 1, 286 .buswidth = 8, 287 .num_links = 2, 288 .links = { QCS615_SLAVE_GEM_NOC_SNOC, QCS615_SLAVE_LLCC }, 289 }; 290 291 static struct qcom_icc_node qhm_gemnoc_cfg = { 292 .name = "qhm_gemnoc_cfg", 293 .id = QCS615_MASTER_GEM_NOC_CFG, 294 .channels = 1, 295 .buswidth = 4, 296 .num_links = 2, 297 .links = { QCS615_SLAVE_MSS_PROC_MS_MPU_CFG, QCS615_SLAVE_SERVICE_GEM_NOC }, 298 }; 299 300 static struct qcom_icc_node qnm_gpu = { 301 .name = "qnm_gpu", 302 .id = QCS615_MASTER_GFX3D, 303 .channels = 2, 304 .buswidth = 32, 305 .num_links = 2, 306 .links = { QCS615_SLAVE_GEM_NOC_SNOC, QCS615_SLAVE_LLCC }, 307 }; 308 309 static struct qcom_icc_node qnm_mnoc_hf = { 310 .name = "qnm_mnoc_hf", 311 .id = QCS615_MASTER_MNOC_HF_MEM_NOC, 312 .channels = 1, 313 .buswidth = 32, 314 .num_links = 1, 315 .links = { QCS615_SLAVE_LLCC }, 316 }; 317 318 static struct qcom_icc_node qnm_mnoc_sf = { 319 .name = "qnm_mnoc_sf", 320 .id = QCS615_MASTER_MNOC_SF_MEM_NOC, 321 .channels = 1, 322 .buswidth = 32, 323 .num_links = 2, 324 .links = { QCS615_SLAVE_GEM_NOC_SNOC, QCS615_SLAVE_LLCC }, 325 }; 326 327 static struct qcom_icc_node qnm_snoc_gc = { 328 .name = "qnm_snoc_gc", 329 .id = QCS615_MASTER_SNOC_GC_MEM_NOC, 330 .channels = 1, 331 .buswidth = 8, 332 .num_links = 1, 333 .links = { QCS615_SLAVE_LLCC }, 334 }; 335 336 static struct qcom_icc_node qnm_snoc_sf = { 337 .name = "qnm_snoc_sf", 338 .id = QCS615_MASTER_SNOC_SF_MEM_NOC, 339 .channels = 1, 340 .buswidth = 16, 341 .num_links = 1, 342 .links = { QCS615_SLAVE_LLCC }, 343 }; 344 345 static struct qcom_icc_node llcc_mc = { 346 .name = "llcc_mc", 347 .id = QCS615_MASTER_LLCC, 348 .channels = 2, 349 .buswidth = 4, 350 .num_links = 1, 351 .links = { QCS615_SLAVE_EBI1 }, 352 }; 353 354 static struct qcom_icc_node qhm_mnoc_cfg = { 355 .name = "qhm_mnoc_cfg", 356 .id = QCS615_MASTER_CNOC_MNOC_CFG, 357 .channels = 1, 358 .buswidth = 4, 359 .num_links = 1, 360 .links = { QCS615_SLAVE_SERVICE_MNOC }, 361 }; 362 363 static struct qcom_icc_node qxm_camnoc_hf0 = { 364 .name = "qxm_camnoc_hf0", 365 .id = QCS615_MASTER_CAMNOC_HF0, 366 .channels = 1, 367 .buswidth = 32, 368 .num_links = 1, 369 .links = { QCS615_SLAVE_MNOC_HF_MEM_NOC }, 370 }; 371 372 static struct qcom_icc_node qxm_camnoc_hf1 = { 373 .name = "qxm_camnoc_hf1", 374 .id = QCS615_MASTER_CAMNOC_HF1, 375 .channels = 1, 376 .buswidth = 32, 377 .num_links = 1, 378 .links = { QCS615_SLAVE_MNOC_HF_MEM_NOC }, 379 }; 380 381 static struct qcom_icc_node qxm_camnoc_sf = { 382 .name = "qxm_camnoc_sf", 383 .id = QCS615_MASTER_CAMNOC_SF, 384 .channels = 1, 385 .buswidth = 32, 386 .num_links = 1, 387 .links = { QCS615_SLAVE_MNOC_SF_MEM_NOC }, 388 }; 389 390 static struct qcom_icc_node qxm_mdp0 = { 391 .name = "qxm_mdp0", 392 .id = QCS615_MASTER_MDP0, 393 .channels = 1, 394 .buswidth = 32, 395 .num_links = 1, 396 .links = { QCS615_SLAVE_MNOC_HF_MEM_NOC }, 397 }; 398 399 static struct qcom_icc_node qxm_rot = { 400 .name = "qxm_rot", 401 .id = QCS615_MASTER_ROTATOR, 402 .channels = 1, 403 .buswidth = 32, 404 .num_links = 1, 405 .links = { QCS615_SLAVE_MNOC_SF_MEM_NOC }, 406 }; 407 408 static struct qcom_icc_node qxm_venus0 = { 409 .name = "qxm_venus0", 410 .id = QCS615_MASTER_VIDEO_P0, 411 .channels = 1, 412 .buswidth = 32, 413 .num_links = 1, 414 .links = { QCS615_SLAVE_MNOC_SF_MEM_NOC }, 415 }; 416 417 static struct qcom_icc_node qxm_venus_arm9 = { 418 .name = "qxm_venus_arm9", 419 .id = QCS615_MASTER_VIDEO_PROC, 420 .channels = 1, 421 .buswidth = 8, 422 .num_links = 1, 423 .links = { QCS615_SLAVE_MNOC_SF_MEM_NOC }, 424 }; 425 426 static struct qcom_icc_node qhm_snoc_cfg = { 427 .name = "qhm_snoc_cfg", 428 .id = QCS615_MASTER_SNOC_CFG, 429 .channels = 1, 430 .buswidth = 4, 431 .num_links = 1, 432 .links = { QCS615_SLAVE_SERVICE_SNOC }, 433 }; 434 435 static struct qcom_icc_node qnm_aggre1_noc = { 436 .name = "qnm_aggre1_noc", 437 .id = QCS615_MASTER_A1NOC_SNOC, 438 .channels = 1, 439 .buswidth = 16, 440 .num_links = 8, 441 .links = { QCS615_SLAVE_APPSS, QCS615_SLAVE_SNOC_CNOC, 442 QCS615_SLAVE_SNOC_GEM_NOC_SF, QCS615_SLAVE_IMEM, 443 QCS615_SLAVE_PIMEM, QCS615_SLAVE_PCIE_0, 444 QCS615_SLAVE_QDSS_STM, QCS615_SLAVE_TCU }, 445 }; 446 447 static struct qcom_icc_node qnm_gemnoc = { 448 .name = "qnm_gemnoc", 449 .id = QCS615_MASTER_GEM_NOC_SNOC, 450 .channels = 1, 451 .buswidth = 8, 452 .num_links = 6, 453 .links = { QCS615_SLAVE_APPSS, QCS615_SLAVE_SNOC_CNOC, 454 QCS615_SLAVE_IMEM, QCS615_SLAVE_PIMEM, 455 QCS615_SLAVE_QDSS_STM, QCS615_SLAVE_TCU }, 456 }; 457 458 static struct qcom_icc_node qnm_gemnoc_pcie = { 459 .name = "qnm_gemnoc_pcie", 460 .id = QCS615_MASTER_GEM_NOC_PCIE_SNOC, 461 .channels = 1, 462 .buswidth = 8, 463 .num_links = 1, 464 .links = { QCS615_SLAVE_PCIE_0 }, 465 }; 466 467 static struct qcom_icc_node qnm_lpass_anoc = { 468 .name = "qnm_lpass_anoc", 469 .id = QCS615_MASTER_LPASS_ANOC, 470 .channels = 1, 471 .buswidth = 8, 472 .num_links = 7, 473 .links = { QCS615_SLAVE_APPSS, QCS615_SLAVE_SNOC_CNOC, 474 QCS615_SLAVE_SNOC_GEM_NOC_SF, QCS615_SLAVE_IMEM, 475 QCS615_SLAVE_PIMEM, QCS615_SLAVE_PCIE_0, 476 QCS615_SLAVE_QDSS_STM }, 477 }; 478 479 static struct qcom_icc_node qnm_pcie_anoc = { 480 .name = "qnm_pcie_anoc", 481 .id = QCS615_MASTER_ANOC_PCIE_SNOC, 482 .channels = 1, 483 .buswidth = 8, 484 .num_links = 5, 485 .links = { QCS615_SLAVE_APPSS, QCS615_SLAVE_SNOC_CNOC, 486 QCS615_SLAVE_SNOC_GEM_NOC_SF, QCS615_SLAVE_IMEM, 487 QCS615_SLAVE_QDSS_STM }, 488 }; 489 490 static struct qcom_icc_node qxm_pimem = { 491 .name = "qxm_pimem", 492 .id = QCS615_MASTER_PIMEM, 493 .channels = 1, 494 .buswidth = 8, 495 .num_links = 2, 496 .links = { QCS615_SLAVE_SNOC_MEM_NOC_GC, QCS615_SLAVE_IMEM }, 497 }; 498 499 static struct qcom_icc_node xm_gic = { 500 .name = "xm_gic", 501 .id = QCS615_MASTER_GIC, 502 .channels = 1, 503 .buswidth = 8, 504 .num_links = 2, 505 .links = { QCS615_SLAVE_SNOC_MEM_NOC_GC, QCS615_SLAVE_IMEM }, 506 }; 507 508 static struct qcom_icc_node qns_a1noc_snoc = { 509 .name = "qns_a1noc_snoc", 510 .id = QCS615_SLAVE_A1NOC_SNOC, 511 .channels = 1, 512 .buswidth = 16, 513 .num_links = 1, 514 .links = { QCS615_MASTER_A1NOC_SNOC }, 515 }; 516 517 static struct qcom_icc_node qns_lpass_snoc = { 518 .name = "qns_lpass_snoc", 519 .id = QCS615_SLAVE_LPASS_SNOC, 520 .channels = 1, 521 .buswidth = 8, 522 .num_links = 1, 523 .links = { QCS615_MASTER_LPASS_ANOC }, 524 }; 525 526 static struct qcom_icc_node qns_pcie_snoc = { 527 .name = "qns_pcie_snoc", 528 .id = QCS615_SLAVE_ANOC_PCIE_SNOC, 529 .channels = 1, 530 .buswidth = 8, 531 .num_links = 1, 532 .links = { QCS615_MASTER_ANOC_PCIE_SNOC }, 533 }; 534 535 static struct qcom_icc_node srvc_aggre2_noc = { 536 .name = "srvc_aggre2_noc", 537 .id = QCS615_SLAVE_SERVICE_A2NOC, 538 .channels = 1, 539 .buswidth = 4, 540 .num_links = 0, 541 }; 542 543 static struct qcom_icc_node qns_camnoc_uncomp = { 544 .name = "qns_camnoc_uncomp", 545 .id = QCS615_SLAVE_CAMNOC_UNCOMP, 546 .channels = 1, 547 .buswidth = 32, 548 .num_links = 0, 549 }; 550 551 static struct qcom_icc_node qhs_a1_noc_cfg = { 552 .name = "qhs_a1_noc_cfg", 553 .id = QCS615_SLAVE_A1NOC_CFG, 554 .channels = 1, 555 .buswidth = 4, 556 .num_links = 1, 557 .links = { QCS615_MASTER_A1NOC_CFG }, 558 }; 559 560 static struct qcom_icc_node qhs_ahb2phy_east = { 561 .name = "qhs_ahb2phy_east", 562 .id = QCS615_SLAVE_AHB2PHY_EAST, 563 .channels = 1, 564 .buswidth = 4, 565 .num_links = 0, 566 }; 567 568 static struct qcom_icc_node qhs_ahb2phy_west = { 569 .name = "qhs_ahb2phy_west", 570 .id = QCS615_SLAVE_AHB2PHY_WEST, 571 .channels = 1, 572 .buswidth = 4, 573 .num_links = 0, 574 }; 575 576 static struct qcom_icc_node qhs_aop = { 577 .name = "qhs_aop", 578 .id = QCS615_SLAVE_AOP, 579 .channels = 1, 580 .buswidth = 4, 581 .num_links = 0, 582 }; 583 584 static struct qcom_icc_node qhs_aoss = { 585 .name = "qhs_aoss", 586 .id = QCS615_SLAVE_AOSS, 587 .channels = 1, 588 .buswidth = 4, 589 .num_links = 0, 590 }; 591 592 static struct qcom_icc_node qhs_camera_cfg = { 593 .name = "qhs_camera_cfg", 594 .id = QCS615_SLAVE_CAMERA_CFG, 595 .channels = 1, 596 .buswidth = 4, 597 .num_links = 0, 598 }; 599 600 static struct qcom_icc_node qhs_clk_ctl = { 601 .name = "qhs_clk_ctl", 602 .id = QCS615_SLAVE_CLK_CTL, 603 .channels = 1, 604 .buswidth = 4, 605 .num_links = 0, 606 }; 607 608 static struct qcom_icc_node qhs_cpr_cx = { 609 .name = "qhs_cpr_cx", 610 .id = QCS615_SLAVE_RBCPR_CX_CFG, 611 .channels = 1, 612 .buswidth = 4, 613 .num_links = 0, 614 }; 615 616 static struct qcom_icc_node qhs_cpr_mx = { 617 .name = "qhs_cpr_mx", 618 .id = QCS615_SLAVE_RBCPR_MX_CFG, 619 .channels = 1, 620 .buswidth = 4, 621 .num_links = 0, 622 }; 623 624 static struct qcom_icc_node qhs_crypto0_cfg = { 625 .name = "qhs_crypto0_cfg", 626 .id = QCS615_SLAVE_CRYPTO_0_CFG, 627 .channels = 1, 628 .buswidth = 4, 629 .num_links = 0, 630 }; 631 632 static struct qcom_icc_node qhs_ddrss_cfg = { 633 .name = "qhs_ddrss_cfg", 634 .id = QCS615_SLAVE_CNOC_DDRSS, 635 .channels = 1, 636 .buswidth = 4, 637 .num_links = 1, 638 .links = { QCS615_MASTER_CNOC_DC_NOC }, 639 }; 640 641 static struct qcom_icc_node qhs_display_cfg = { 642 .name = "qhs_display_cfg", 643 .id = QCS615_SLAVE_DISPLAY_CFG, 644 .channels = 1, 645 .buswidth = 4, 646 .num_links = 0, 647 }; 648 649 static struct qcom_icc_node qhs_emac_avb_cfg = { 650 .name = "qhs_emac_avb_cfg", 651 .id = QCS615_SLAVE_EMAC_AVB_CFG, 652 .channels = 1, 653 .buswidth = 4, 654 .num_links = 0, 655 }; 656 657 static struct qcom_icc_node qhs_glm = { 658 .name = "qhs_glm", 659 .id = QCS615_SLAVE_GLM, 660 .channels = 1, 661 .buswidth = 4, 662 .num_links = 0, 663 }; 664 665 static struct qcom_icc_node qhs_gpuss_cfg = { 666 .name = "qhs_gpuss_cfg", 667 .id = QCS615_SLAVE_GFX3D_CFG, 668 .channels = 1, 669 .buswidth = 8, 670 .num_links = 0, 671 }; 672 673 static struct qcom_icc_node qhs_imem_cfg = { 674 .name = "qhs_imem_cfg", 675 .id = QCS615_SLAVE_IMEM_CFG, 676 .channels = 1, 677 .buswidth = 4, 678 .num_links = 0, 679 }; 680 681 static struct qcom_icc_node qhs_ipa = { 682 .name = "qhs_ipa", 683 .id = QCS615_SLAVE_IPA_CFG, 684 .channels = 1, 685 .buswidth = 4, 686 .num_links = 0, 687 }; 688 689 static struct qcom_icc_node qhs_mnoc_cfg = { 690 .name = "qhs_mnoc_cfg", 691 .id = QCS615_SLAVE_CNOC_MNOC_CFG, 692 .channels = 1, 693 .buswidth = 4, 694 .num_links = 1, 695 .links = { QCS615_MASTER_CNOC_MNOC_CFG }, 696 }; 697 698 static struct qcom_icc_node qhs_pcie_config = { 699 .name = "qhs_pcie_config", 700 .id = QCS615_SLAVE_PCIE_CFG, 701 .channels = 1, 702 .buswidth = 4, 703 .num_links = 0, 704 }; 705 706 static struct qcom_icc_node qhs_pimem_cfg = { 707 .name = "qhs_pimem_cfg", 708 .id = QCS615_SLAVE_PIMEM_CFG, 709 .channels = 1, 710 .buswidth = 4, 711 .num_links = 0, 712 }; 713 714 static struct qcom_icc_node qhs_prng = { 715 .name = "qhs_prng", 716 .id = QCS615_SLAVE_PRNG, 717 .channels = 1, 718 .buswidth = 4, 719 .num_links = 0, 720 }; 721 722 static struct qcom_icc_node qhs_qdss_cfg = { 723 .name = "qhs_qdss_cfg", 724 .id = QCS615_SLAVE_QDSS_CFG, 725 .channels = 1, 726 .buswidth = 4, 727 .num_links = 0, 728 }; 729 730 static struct qcom_icc_node qhs_qspi = { 731 .name = "qhs_qspi", 732 .id = QCS615_SLAVE_QSPI, 733 .channels = 1, 734 .buswidth = 4, 735 .num_links = 0, 736 }; 737 738 static struct qcom_icc_node qhs_qup0 = { 739 .name = "qhs_qup0", 740 .id = QCS615_SLAVE_QUP_0, 741 .channels = 1, 742 .buswidth = 4, 743 .num_links = 0, 744 }; 745 746 static struct qcom_icc_node qhs_qup1 = { 747 .name = "qhs_qup1", 748 .id = QCS615_SLAVE_QUP_1, 749 .channels = 1, 750 .buswidth = 4, 751 .num_links = 0, 752 }; 753 754 static struct qcom_icc_node qhs_sdc1 = { 755 .name = "qhs_sdc1", 756 .id = QCS615_SLAVE_SDCC_1, 757 .channels = 1, 758 .buswidth = 4, 759 .num_links = 0, 760 }; 761 762 static struct qcom_icc_node qhs_sdc2 = { 763 .name = "qhs_sdc2", 764 .id = QCS615_SLAVE_SDCC_2, 765 .channels = 1, 766 .buswidth = 4, 767 .num_links = 0, 768 }; 769 770 static struct qcom_icc_node qhs_snoc_cfg = { 771 .name = "qhs_snoc_cfg", 772 .id = QCS615_SLAVE_SNOC_CFG, 773 .channels = 1, 774 .buswidth = 4, 775 .num_links = 1, 776 .links = { QCS615_MASTER_SNOC_CFG }, 777 }; 778 779 static struct qcom_icc_node qhs_spdm = { 780 .name = "qhs_spdm", 781 .id = QCS615_SLAVE_SPDM_WRAPPER, 782 .channels = 1, 783 .buswidth = 4, 784 .num_links = 0, 785 }; 786 787 static struct qcom_icc_node qhs_tcsr = { 788 .name = "qhs_tcsr", 789 .id = QCS615_SLAVE_TCSR, 790 .channels = 1, 791 .buswidth = 4, 792 .num_links = 0, 793 }; 794 795 static struct qcom_icc_node qhs_tlmm_east = { 796 .name = "qhs_tlmm_east", 797 .id = QCS615_SLAVE_TLMM_EAST, 798 .channels = 1, 799 .buswidth = 4, 800 .num_links = 0, 801 }; 802 803 static struct qcom_icc_node qhs_tlmm_south = { 804 .name = "qhs_tlmm_south", 805 .id = QCS615_SLAVE_TLMM_SOUTH, 806 .channels = 1, 807 .buswidth = 4, 808 .num_links = 0, 809 }; 810 811 static struct qcom_icc_node qhs_tlmm_west = { 812 .name = "qhs_tlmm_west", 813 .id = QCS615_SLAVE_TLMM_WEST, 814 .channels = 1, 815 .buswidth = 4, 816 .num_links = 0, 817 }; 818 819 static struct qcom_icc_node qhs_ufs_mem_cfg = { 820 .name = "qhs_ufs_mem_cfg", 821 .id = QCS615_SLAVE_UFS_MEM_CFG, 822 .channels = 1, 823 .buswidth = 4, 824 .num_links = 0, 825 }; 826 827 static struct qcom_icc_node qhs_usb2 = { 828 .name = "qhs_usb2", 829 .id = QCS615_SLAVE_USB2, 830 .channels = 1, 831 .buswidth = 4, 832 .num_links = 0, 833 }; 834 835 static struct qcom_icc_node qhs_usb3 = { 836 .name = "qhs_usb3", 837 .id = QCS615_SLAVE_USB3, 838 .channels = 1, 839 .buswidth = 4, 840 .num_links = 0, 841 }; 842 843 static struct qcom_icc_node qhs_venus_cfg = { 844 .name = "qhs_venus_cfg", 845 .id = QCS615_SLAVE_VENUS_CFG, 846 .channels = 1, 847 .buswidth = 4, 848 .num_links = 0, 849 }; 850 851 static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 852 .name = "qhs_vsense_ctrl_cfg", 853 .id = QCS615_SLAVE_VSENSE_CTRL_CFG, 854 .channels = 1, 855 .buswidth = 4, 856 .num_links = 0, 857 }; 858 859 static struct qcom_icc_node qns_cnoc_a2noc = { 860 .name = "qns_cnoc_a2noc", 861 .id = QCS615_SLAVE_CNOC_A2NOC, 862 .channels = 1, 863 .buswidth = 8, 864 .num_links = 1, 865 .links = { QCS615_MASTER_CNOC_A2NOC }, 866 }; 867 868 static struct qcom_icc_node srvc_cnoc = { 869 .name = "srvc_cnoc", 870 .id = QCS615_SLAVE_SERVICE_CNOC, 871 .channels = 1, 872 .buswidth = 4, 873 .num_links = 0, 874 }; 875 876 static struct qcom_icc_node qhs_dc_noc_gemnoc = { 877 .name = "qhs_dc_noc_gemnoc", 878 .id = QCS615_SLAVE_DC_NOC_GEMNOC, 879 .channels = 1, 880 .buswidth = 4, 881 .num_links = 1, 882 .links = { QCS615_MASTER_GEM_NOC_CFG }, 883 }; 884 885 static struct qcom_icc_node qhs_llcc = { 886 .name = "qhs_llcc", 887 .id = QCS615_SLAVE_LLCC_CFG, 888 .channels = 1, 889 .buswidth = 4, 890 .num_links = 0, 891 }; 892 893 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { 894 .name = "qhs_mdsp_ms_mpu_cfg", 895 .id = QCS615_SLAVE_MSS_PROC_MS_MPU_CFG, 896 .channels = 1, 897 .buswidth = 4, 898 .num_links = 0, 899 }; 900 901 static struct qcom_icc_node qns_gem_noc_snoc = { 902 .name = "qns_gem_noc_snoc", 903 .id = QCS615_SLAVE_GEM_NOC_SNOC, 904 .channels = 1, 905 .buswidth = 8, 906 .num_links = 1, 907 .links = { QCS615_MASTER_GEM_NOC_SNOC }, 908 }; 909 910 static struct qcom_icc_node qns_llcc = { 911 .name = "qns_llcc", 912 .id = QCS615_SLAVE_LLCC, 913 .channels = 1, 914 .buswidth = 16, 915 .num_links = 1, 916 .links = { QCS615_MASTER_LLCC }, 917 }; 918 919 static struct qcom_icc_node qns_sys_pcie = { 920 .name = "qns_sys_pcie", 921 .id = QCS615_SLAVE_MEM_NOC_PCIE_SNOC, 922 .channels = 1, 923 .buswidth = 8, 924 .num_links = 1, 925 .links = { QCS615_MASTER_GEM_NOC_PCIE_SNOC }, 926 }; 927 928 static struct qcom_icc_node srvc_gemnoc = { 929 .name = "srvc_gemnoc", 930 .id = QCS615_SLAVE_SERVICE_GEM_NOC, 931 .channels = 1, 932 .buswidth = 4, 933 .num_links = 0, 934 }; 935 936 static struct qcom_icc_node ebi = { 937 .name = "ebi", 938 .id = QCS615_SLAVE_EBI1, 939 .channels = 2, 940 .buswidth = 4, 941 .num_links = 0, 942 }; 943 944 static struct qcom_icc_node qns2_mem_noc = { 945 .name = "qns2_mem_noc", 946 .id = QCS615_SLAVE_MNOC_SF_MEM_NOC, 947 .channels = 1, 948 .buswidth = 32, 949 .num_links = 1, 950 .links = { QCS615_MASTER_MNOC_SF_MEM_NOC }, 951 }; 952 953 static struct qcom_icc_node qns_mem_noc_hf = { 954 .name = "qns_mem_noc_hf", 955 .id = QCS615_SLAVE_MNOC_HF_MEM_NOC, 956 .channels = 1, 957 .buswidth = 32, 958 .num_links = 1, 959 .links = { QCS615_MASTER_MNOC_HF_MEM_NOC }, 960 }; 961 962 static struct qcom_icc_node srvc_mnoc = { 963 .name = "srvc_mnoc", 964 .id = QCS615_SLAVE_SERVICE_MNOC, 965 .channels = 1, 966 .buswidth = 4, 967 .num_links = 0, 968 }; 969 970 static struct qcom_icc_node qhs_apss = { 971 .name = "qhs_apss", 972 .id = QCS615_SLAVE_APPSS, 973 .channels = 1, 974 .buswidth = 8, 975 .num_links = 0, 976 }; 977 978 static struct qcom_icc_node qns_cnoc = { 979 .name = "qns_cnoc", 980 .id = QCS615_SLAVE_SNOC_CNOC, 981 .channels = 1, 982 .buswidth = 8, 983 .num_links = 1, 984 .links = { QCS615_MASTER_SNOC_CNOC }, 985 }; 986 987 static struct qcom_icc_node qns_gemnoc_sf = { 988 .name = "qns_gemnoc_sf", 989 .id = QCS615_SLAVE_SNOC_GEM_NOC_SF, 990 .channels = 1, 991 .buswidth = 16, 992 .num_links = 1, 993 .links = { QCS615_MASTER_SNOC_SF_MEM_NOC }, 994 }; 995 996 static struct qcom_icc_node qns_memnoc_gc = { 997 .name = "qns_memnoc_gc", 998 .id = QCS615_SLAVE_SNOC_MEM_NOC_GC, 999 .channels = 1, 1000 .buswidth = 8, 1001 .num_links = 1, 1002 .links = { QCS615_MASTER_SNOC_GC_MEM_NOC }, 1003 }; 1004 1005 static struct qcom_icc_node qxs_imem = { 1006 .name = "qxs_imem", 1007 .id = QCS615_SLAVE_IMEM, 1008 .channels = 1, 1009 .buswidth = 8, 1010 .num_links = 0, 1011 }; 1012 1013 static struct qcom_icc_node qxs_pimem = { 1014 .name = "qxs_pimem", 1015 .id = QCS615_SLAVE_PIMEM, 1016 .channels = 1, 1017 .buswidth = 8, 1018 .num_links = 0, 1019 }; 1020 1021 static struct qcom_icc_node srvc_snoc = { 1022 .name = "srvc_snoc", 1023 .id = QCS615_SLAVE_SERVICE_SNOC, 1024 .channels = 1, 1025 .buswidth = 4, 1026 .num_links = 0, 1027 }; 1028 1029 static struct qcom_icc_node xs_pcie = { 1030 .name = "xs_pcie", 1031 .id = QCS615_SLAVE_PCIE_0, 1032 .channels = 1, 1033 .buswidth = 8, 1034 .num_links = 0, 1035 }; 1036 1037 static struct qcom_icc_node xs_qdss_stm = { 1038 .name = "xs_qdss_stm", 1039 .id = QCS615_SLAVE_QDSS_STM, 1040 .channels = 1, 1041 .buswidth = 4, 1042 .num_links = 0, 1043 }; 1044 1045 static struct qcom_icc_node xs_sys_tcu_cfg = { 1046 .name = "xs_sys_tcu_cfg", 1047 .id = QCS615_SLAVE_TCU, 1048 .channels = 1, 1049 .buswidth = 8, 1050 .num_links = 0, 1051 }; 1052 1053 static struct qcom_icc_bcm bcm_acv = { 1054 .name = "ACV", 1055 .num_nodes = 1, 1056 .nodes = { &ebi }, 1057 }; 1058 1059 static struct qcom_icc_bcm bcm_ce0 = { 1060 .name = "CE0", 1061 .num_nodes = 1, 1062 .nodes = { &qxm_crypto }, 1063 }; 1064 1065 static struct qcom_icc_bcm bcm_cn0 = { 1066 .name = "CN0", 1067 .keepalive = true, 1068 .num_nodes = 37, 1069 .nodes = { &qhm_spdm, &qnm_snoc, 1070 &qhs_a1_noc_cfg, &qhs_aop, 1071 &qhs_aoss, &qhs_camera_cfg, 1072 &qhs_clk_ctl, &qhs_cpr_cx, 1073 &qhs_cpr_mx, &qhs_crypto0_cfg, 1074 &qhs_ddrss_cfg, &qhs_display_cfg, 1075 &qhs_emac_avb_cfg, &qhs_glm, 1076 &qhs_gpuss_cfg, &qhs_imem_cfg, 1077 &qhs_ipa, &qhs_mnoc_cfg, 1078 &qhs_pcie_config, &qhs_pimem_cfg, 1079 &qhs_prng, &qhs_qdss_cfg, 1080 &qhs_qup0, &qhs_qup1, 1081 &qhs_snoc_cfg, &qhs_spdm, 1082 &qhs_tcsr, &qhs_tlmm_east, 1083 &qhs_tlmm_south, &qhs_tlmm_west, 1084 &qhs_ufs_mem_cfg, &qhs_usb2, 1085 &qhs_usb3, &qhs_venus_cfg, 1086 &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, 1087 &srvc_cnoc }, 1088 }; 1089 1090 static struct qcom_icc_bcm bcm_cn1 = { 1091 .name = "CN1", 1092 .num_nodes = 8, 1093 .nodes = { &qhm_qspi, &xm_sdc1, 1094 &xm_sdc2, &qhs_ahb2phy_east, 1095 &qhs_ahb2phy_west, &qhs_qspi, 1096 &qhs_sdc1, &qhs_sdc2 }, 1097 }; 1098 1099 static struct qcom_icc_bcm bcm_mc0 = { 1100 .name = "MC0", 1101 .keepalive = true, 1102 .num_nodes = 1, 1103 .nodes = { &ebi }, 1104 }; 1105 1106 static struct qcom_icc_bcm bcm_mm0 = { 1107 .name = "MM0", 1108 .keepalive = true, 1109 .num_nodes = 1, 1110 .nodes = { &qns_mem_noc_hf }, 1111 }; 1112 1113 static struct qcom_icc_bcm bcm_mm1 = { 1114 .name = "MM1", 1115 .num_nodes = 7, 1116 .nodes = { &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, 1117 &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0, 1118 &qxm_camnoc_hf1, &qxm_mdp0, 1119 &qxm_rot }, 1120 }; 1121 1122 static struct qcom_icc_bcm bcm_mm2 = { 1123 .name = "MM2", 1124 .num_nodes = 2, 1125 .nodes = { &qxm_camnoc_sf, &qns2_mem_noc }, 1126 }; 1127 1128 static struct qcom_icc_bcm bcm_mm3 = { 1129 .name = "MM3", 1130 .num_nodes = 2, 1131 .nodes = { &qxm_venus0, &qxm_venus_arm9 }, 1132 }; 1133 1134 static struct qcom_icc_bcm bcm_qup0 = { 1135 .name = "QUP0", 1136 .keepalive = true, 1137 .vote_scale = 1, 1138 .num_nodes = 2, 1139 .nodes = { &qhm_qup0, &qhm_qup1 }, 1140 }; 1141 1142 static struct qcom_icc_bcm bcm_sh0 = { 1143 .name = "SH0", 1144 .keepalive = true, 1145 .num_nodes = 1, 1146 .nodes = { &qns_llcc }, 1147 }; 1148 1149 static struct qcom_icc_bcm bcm_sh2 = { 1150 .name = "SH2", 1151 .num_nodes = 1, 1152 .nodes = { &acm_apps }, 1153 }; 1154 1155 static struct qcom_icc_bcm bcm_sh3 = { 1156 .name = "SH3", 1157 .num_nodes = 1, 1158 .nodes = { &qns_gem_noc_snoc }, 1159 }; 1160 1161 static struct qcom_icc_bcm bcm_sn0 = { 1162 .name = "SN0", 1163 .keepalive = true, 1164 .num_nodes = 1, 1165 .nodes = { &qns_gemnoc_sf }, 1166 }; 1167 1168 static struct qcom_icc_bcm bcm_sn1 = { 1169 .name = "SN1", 1170 .num_nodes = 1, 1171 .nodes = { &qxs_imem }, 1172 }; 1173 1174 static struct qcom_icc_bcm bcm_sn2 = { 1175 .name = "SN2", 1176 .num_nodes = 1, 1177 .nodes = { &qns_memnoc_gc }, 1178 }; 1179 1180 static struct qcom_icc_bcm bcm_sn3 = { 1181 .name = "SN3", 1182 .num_nodes = 2, 1183 .nodes = { &srvc_aggre2_noc, &qns_cnoc }, 1184 }; 1185 1186 static struct qcom_icc_bcm bcm_sn4 = { 1187 .name = "SN4", 1188 .num_nodes = 1, 1189 .nodes = { &qxs_pimem }, 1190 }; 1191 1192 static struct qcom_icc_bcm bcm_sn5 = { 1193 .name = "SN5", 1194 .num_nodes = 1, 1195 .nodes = { &xs_qdss_stm }, 1196 }; 1197 1198 static struct qcom_icc_bcm bcm_sn8 = { 1199 .name = "SN8", 1200 .num_nodes = 2, 1201 .nodes = { &qnm_gemnoc_pcie, &xs_pcie }, 1202 }; 1203 1204 static struct qcom_icc_bcm bcm_sn9 = { 1205 .name = "SN9", 1206 .num_nodes = 1, 1207 .nodes = { &qnm_aggre1_noc }, 1208 }; 1209 1210 static struct qcom_icc_bcm bcm_sn12 = { 1211 .name = "SN12", 1212 .num_nodes = 2, 1213 .nodes = { &qxm_pimem, &xm_gic }, 1214 }; 1215 1216 static struct qcom_icc_bcm bcm_sn13 = { 1217 .name = "SN13", 1218 .num_nodes = 1, 1219 .nodes = { &qnm_lpass_anoc }, 1220 }; 1221 1222 static struct qcom_icc_bcm bcm_sn14 = { 1223 .name = "SN14", 1224 .num_nodes = 1, 1225 .nodes = { &qns_pcie_snoc }, 1226 }; 1227 1228 static struct qcom_icc_bcm bcm_sn15 = { 1229 .name = "SN15", 1230 .num_nodes = 1, 1231 .nodes = { &qnm_gemnoc }, 1232 }; 1233 1234 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 1235 &bcm_ce0, 1236 &bcm_cn1, 1237 &bcm_qup0, 1238 &bcm_sn3, 1239 &bcm_sn14, 1240 }; 1241 1242 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1243 [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg, 1244 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 1245 [MASTER_QSPI] = &qhm_qspi, 1246 [MASTER_QUP_0] = &qhm_qup0, 1247 [MASTER_BLSP_1] = &qhm_qup1, 1248 [MASTER_CNOC_A2NOC] = &qnm_cnoc, 1249 [MASTER_CRYPTO] = &qxm_crypto, 1250 [MASTER_IPA] = &qxm_ipa, 1251 [MASTER_EMAC_EVB] = &xm_emac_avb, 1252 [MASTER_PCIE] = &xm_pcie, 1253 [MASTER_QDSS_ETR] = &xm_qdss_etr, 1254 [MASTER_SDCC_1] = &xm_sdc1, 1255 [MASTER_SDCC_2] = &xm_sdc2, 1256 [MASTER_UFS_MEM] = &xm_ufs_mem, 1257 [MASTER_USB2] = &xm_usb2, 1258 [MASTER_USB3_0] = &xm_usb3_0, 1259 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, 1260 [SLAVE_LPASS_SNOC] = &qns_lpass_snoc, 1261 [SLAVE_ANOC_PCIE_SNOC] = &qns_pcie_snoc, 1262 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, 1263 }; 1264 1265 static const struct qcom_icc_desc qcs615_aggre1_noc = { 1266 .nodes = aggre1_noc_nodes, 1267 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 1268 .bcms = aggre1_noc_bcms, 1269 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 1270 }; 1271 1272 static struct qcom_icc_bcm * const camnoc_virt_bcms[] = { 1273 &bcm_mm1, 1274 }; 1275 1276 static struct qcom_icc_node * const camnoc_virt_nodes[] = { 1277 [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp, 1278 [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp, 1279 [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp, 1280 [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp, 1281 }; 1282 1283 static const struct qcom_icc_desc qcs615_camnoc_virt = { 1284 .nodes = camnoc_virt_nodes, 1285 .num_nodes = ARRAY_SIZE(camnoc_virt_nodes), 1286 .bcms = camnoc_virt_bcms, 1287 .num_bcms = ARRAY_SIZE(camnoc_virt_bcms), 1288 }; 1289 1290 static struct qcom_icc_bcm * const config_noc_bcms[] = { 1291 &bcm_cn0, 1292 &bcm_cn1, 1293 }; 1294 1295 static struct qcom_icc_node * const config_noc_nodes[] = { 1296 [MASTER_SPDM] = &qhm_spdm, 1297 [MASTER_SNOC_CNOC] = &qnm_snoc, 1298 [MASTER_QDSS_DAP] = &xm_qdss_dap, 1299 [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg, 1300 [SLAVE_AHB2PHY_EAST] = &qhs_ahb2phy_east, 1301 [SLAVE_AHB2PHY_WEST] = &qhs_ahb2phy_west, 1302 [SLAVE_AOP] = &qhs_aop, 1303 [SLAVE_AOSS] = &qhs_aoss, 1304 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 1305 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1306 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 1307 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, 1308 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1309 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg, 1310 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 1311 [SLAVE_EMAC_AVB_CFG] = &qhs_emac_avb_cfg, 1312 [SLAVE_GLM] = &qhs_glm, 1313 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, 1314 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1315 [SLAVE_IPA_CFG] = &qhs_ipa, 1316 [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg, 1317 [SLAVE_PCIE_CFG] = &qhs_pcie_config, 1318 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 1319 [SLAVE_PRNG] = &qhs_prng, 1320 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1321 [SLAVE_QSPI] = &qhs_qspi, 1322 [SLAVE_QUP_0] = &qhs_qup0, 1323 [SLAVE_QUP_1] = &qhs_qup1, 1324 [SLAVE_SDCC_1] = &qhs_sdc1, 1325 [SLAVE_SDCC_2] = &qhs_sdc2, 1326 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, 1327 [SLAVE_SPDM_WRAPPER] = &qhs_spdm, 1328 [SLAVE_TCSR] = &qhs_tcsr, 1329 [SLAVE_TLMM_EAST] = &qhs_tlmm_east, 1330 [SLAVE_TLMM_SOUTH] = &qhs_tlmm_south, 1331 [SLAVE_TLMM_WEST] = &qhs_tlmm_west, 1332 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 1333 [SLAVE_USB2] = &qhs_usb2, 1334 [SLAVE_USB3] = &qhs_usb3, 1335 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1336 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 1337 [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc, 1338 [SLAVE_SERVICE_CNOC] = &srvc_cnoc, 1339 }; 1340 1341 static const struct qcom_icc_desc qcs615_config_noc = { 1342 .nodes = config_noc_nodes, 1343 .num_nodes = ARRAY_SIZE(config_noc_nodes), 1344 .bcms = config_noc_bcms, 1345 .num_bcms = ARRAY_SIZE(config_noc_bcms), 1346 }; 1347 1348 static struct qcom_icc_node * const dc_noc_nodes[] = { 1349 [MASTER_CNOC_DC_NOC] = &qhm_cnoc, 1350 [SLAVE_DC_NOC_GEMNOC] = &qhs_dc_noc_gemnoc, 1351 [SLAVE_LLCC_CFG] = &qhs_llcc, 1352 }; 1353 1354 static const struct qcom_icc_desc qcs615_dc_noc = { 1355 .nodes = dc_noc_nodes, 1356 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 1357 }; 1358 1359 static struct qcom_icc_bcm * const gem_noc_bcms[] = { 1360 &bcm_sh0, 1361 &bcm_sh2, 1362 &bcm_sh3, 1363 &bcm_mm1, 1364 }; 1365 1366 static struct qcom_icc_node * const gem_noc_nodes[] = { 1367 [MASTER_APPSS_PROC] = &acm_apps, 1368 [MASTER_GPU_TCU] = &acm_gpu_tcu, 1369 [MASTER_SYS_TCU] = &acm_sys_tcu, 1370 [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg, 1371 [MASTER_GFX3D] = &qnm_gpu, 1372 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 1373 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 1374 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 1375 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 1376 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg, 1377 [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc, 1378 [SLAVE_LLCC] = &qns_llcc, 1379 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_sys_pcie, 1380 [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc, 1381 }; 1382 1383 static const struct qcom_icc_desc qcs615_gem_noc = { 1384 .nodes = gem_noc_nodes, 1385 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 1386 .bcms = gem_noc_bcms, 1387 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 1388 }; 1389 1390 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 1391 &bcm_acv, 1392 &bcm_mc0, 1393 }; 1394 1395 static struct qcom_icc_node * const mc_virt_nodes[] = { 1396 [MASTER_LLCC] = &llcc_mc, 1397 [SLAVE_EBI1] = &ebi, 1398 }; 1399 1400 static const struct qcom_icc_desc qcs615_mc_virt = { 1401 .nodes = mc_virt_nodes, 1402 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 1403 .bcms = mc_virt_bcms, 1404 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 1405 }; 1406 1407 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 1408 &bcm_mm0, 1409 &bcm_mm1, 1410 &bcm_mm2, 1411 &bcm_mm3, 1412 }; 1413 1414 static struct qcom_icc_node * const mmss_noc_nodes[] = { 1415 [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg, 1416 [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0, 1417 [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1, 1418 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf, 1419 [MASTER_MDP0] = &qxm_mdp0, 1420 [MASTER_ROTATOR] = &qxm_rot, 1421 [MASTER_VIDEO_P0] = &qxm_venus0, 1422 [MASTER_VIDEO_PROC] = &qxm_venus_arm9, 1423 [SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc, 1424 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 1425 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 1426 }; 1427 1428 static const struct qcom_icc_desc qcs615_mmss_noc = { 1429 .nodes = mmss_noc_nodes, 1430 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 1431 .bcms = mmss_noc_bcms, 1432 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 1433 }; 1434 1435 static struct qcom_icc_bcm * const system_noc_bcms[] = { 1436 &bcm_sn0, 1437 &bcm_sn1, 1438 &bcm_sn2, 1439 &bcm_sn3, 1440 &bcm_sn4, 1441 &bcm_sn5, 1442 &bcm_sn8, 1443 &bcm_sn9, 1444 &bcm_sn12, 1445 &bcm_sn13, 1446 &bcm_sn15, 1447 }; 1448 1449 static struct qcom_icc_node * const system_noc_nodes[] = { 1450 [MASTER_SNOC_CFG] = &qhm_snoc_cfg, 1451 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, 1452 [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc, 1453 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, 1454 [MASTER_LPASS_ANOC] = &qnm_lpass_anoc, 1455 [MASTER_ANOC_PCIE_SNOC] = &qnm_pcie_anoc, 1456 [MASTER_PIMEM] = &qxm_pimem, 1457 [MASTER_GIC] = &xm_gic, 1458 [SLAVE_APPSS] = &qhs_apss, 1459 [SLAVE_SNOC_CNOC] = &qns_cnoc, 1460 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 1461 [SLAVE_SNOC_MEM_NOC_GC] = &qns_memnoc_gc, 1462 [SLAVE_IMEM] = &qxs_imem, 1463 [SLAVE_PIMEM] = &qxs_pimem, 1464 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 1465 [SLAVE_PCIE_0] = &xs_pcie, 1466 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1467 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1468 }; 1469 1470 static const struct qcom_icc_desc qcs615_system_noc = { 1471 .nodes = system_noc_nodes, 1472 .num_nodes = ARRAY_SIZE(system_noc_nodes), 1473 .bcms = system_noc_bcms, 1474 .num_bcms = ARRAY_SIZE(system_noc_bcms), 1475 }; 1476 1477 static const struct of_device_id qnoc_of_match[] = { 1478 { .compatible = "qcom,qcs615-aggre1-noc", 1479 .data = &qcs615_aggre1_noc}, 1480 { .compatible = "qcom,qcs615-camnoc-virt", 1481 .data = &qcs615_camnoc_virt}, 1482 { .compatible = "qcom,qcs615-config-noc", 1483 .data = &qcs615_config_noc}, 1484 { .compatible = "qcom,qcs615-dc-noc", 1485 .data = &qcs615_dc_noc}, 1486 { .compatible = "qcom,qcs615-gem-noc", 1487 .data = &qcs615_gem_noc}, 1488 { .compatible = "qcom,qcs615-mc-virt", 1489 .data = &qcs615_mc_virt}, 1490 { .compatible = "qcom,qcs615-mmss-noc", 1491 .data = &qcs615_mmss_noc}, 1492 { .compatible = "qcom,qcs615-system-noc", 1493 .data = &qcs615_system_noc}, 1494 { } 1495 }; 1496 MODULE_DEVICE_TABLE(of, qnoc_of_match); 1497 1498 static struct platform_driver qnoc_driver = { 1499 .probe = qcom_icc_rpmh_probe, 1500 .remove = qcom_icc_rpmh_remove, 1501 .driver = { 1502 .name = "qnoc-qcs615", 1503 .of_match_table = qnoc_of_match, 1504 .sync_state = icc_sync_state, 1505 }, 1506 }; 1507 1508 static int __init qnoc_driver_init(void) 1509 { 1510 return platform_driver_register(&qnoc_driver); 1511 } 1512 core_initcall(qnoc_driver_init); 1513 1514 static void __exit qnoc_driver_exit(void) 1515 { 1516 platform_driver_unregister(&qnoc_driver); 1517 } 1518 module_exit(qnoc_driver_exit); 1519 1520 MODULE_DESCRIPTION("qcs615 NoC driver"); 1521 MODULE_LICENSE("GPL"); 1522