1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 */ 6 7 #include <linux/device.h> 8 #include <linux/interconnect.h> 9 #include <linux/interconnect-provider.h> 10 #include <linux/module.h> 11 #include <linux/of_platform.h> 12 #include <dt-bindings/interconnect/qcom,qcs615-rpmh.h> 13 14 #include "bcm-voter.h" 15 #include "icc-rpmh.h" 16 17 static struct qcom_icc_node qhm_a1noc_cfg; 18 static struct qcom_icc_node qhm_qdss_bam; 19 static struct qcom_icc_node qhm_qspi; 20 static struct qcom_icc_node qhm_qup0; 21 static struct qcom_icc_node qhm_qup1; 22 static struct qcom_icc_node qnm_cnoc; 23 static struct qcom_icc_node qxm_crypto; 24 static struct qcom_icc_node qxm_ipa; 25 static struct qcom_icc_node xm_emac_avb; 26 static struct qcom_icc_node xm_pcie; 27 static struct qcom_icc_node xm_qdss_etr; 28 static struct qcom_icc_node xm_sdc1; 29 static struct qcom_icc_node xm_sdc2; 30 static struct qcom_icc_node xm_ufs_mem; 31 static struct qcom_icc_node xm_usb2; 32 static struct qcom_icc_node xm_usb3_0; 33 static struct qcom_icc_node qxm_camnoc_hf0_uncomp; 34 static struct qcom_icc_node qxm_camnoc_hf1_uncomp; 35 static struct qcom_icc_node qxm_camnoc_sf_uncomp; 36 static struct qcom_icc_node qhm_spdm; 37 static struct qcom_icc_node qnm_snoc; 38 static struct qcom_icc_node xm_qdss_dap; 39 static struct qcom_icc_node qhm_cnoc; 40 static struct qcom_icc_node acm_apps; 41 static struct qcom_icc_node acm_gpu_tcu; 42 static struct qcom_icc_node acm_sys_tcu; 43 static struct qcom_icc_node qhm_gemnoc_cfg; 44 static struct qcom_icc_node qnm_gpu; 45 static struct qcom_icc_node qnm_mnoc_hf; 46 static struct qcom_icc_node qnm_mnoc_sf; 47 static struct qcom_icc_node qnm_snoc_gc; 48 static struct qcom_icc_node qnm_snoc_sf; 49 static struct qcom_icc_node llcc_mc; 50 static struct qcom_icc_node qhm_mnoc_cfg; 51 static struct qcom_icc_node qxm_camnoc_hf0; 52 static struct qcom_icc_node qxm_camnoc_hf1; 53 static struct qcom_icc_node qxm_camnoc_sf; 54 static struct qcom_icc_node qxm_mdp0; 55 static struct qcom_icc_node qxm_rot; 56 static struct qcom_icc_node qxm_venus0; 57 static struct qcom_icc_node qxm_venus_arm9; 58 static struct qcom_icc_node qhm_snoc_cfg; 59 static struct qcom_icc_node qnm_aggre1_noc; 60 static struct qcom_icc_node qnm_gemnoc; 61 static struct qcom_icc_node qnm_gemnoc_pcie; 62 static struct qcom_icc_node qnm_lpass_anoc; 63 static struct qcom_icc_node qnm_pcie_anoc; 64 static struct qcom_icc_node qxm_pimem; 65 static struct qcom_icc_node xm_gic; 66 static struct qcom_icc_node qns_a1noc_snoc; 67 static struct qcom_icc_node qns_lpass_snoc; 68 static struct qcom_icc_node qns_pcie_snoc; 69 static struct qcom_icc_node srvc_aggre2_noc; 70 static struct qcom_icc_node qns_camnoc_uncomp; 71 static struct qcom_icc_node qhs_a1_noc_cfg; 72 static struct qcom_icc_node qhs_ahb2phy_east; 73 static struct qcom_icc_node qhs_ahb2phy_west; 74 static struct qcom_icc_node qhs_aop; 75 static struct qcom_icc_node qhs_aoss; 76 static struct qcom_icc_node qhs_camera_cfg; 77 static struct qcom_icc_node qhs_clk_ctl; 78 static struct qcom_icc_node qhs_cpr_cx; 79 static struct qcom_icc_node qhs_cpr_mx; 80 static struct qcom_icc_node qhs_crypto0_cfg; 81 static struct qcom_icc_node qhs_ddrss_cfg; 82 static struct qcom_icc_node qhs_display_cfg; 83 static struct qcom_icc_node qhs_emac_avb_cfg; 84 static struct qcom_icc_node qhs_glm; 85 static struct qcom_icc_node qhs_gpuss_cfg; 86 static struct qcom_icc_node qhs_imem_cfg; 87 static struct qcom_icc_node qhs_ipa; 88 static struct qcom_icc_node qhs_mnoc_cfg; 89 static struct qcom_icc_node qhs_pcie_config; 90 static struct qcom_icc_node qhs_pimem_cfg; 91 static struct qcom_icc_node qhs_prng; 92 static struct qcom_icc_node qhs_qdss_cfg; 93 static struct qcom_icc_node qhs_qspi; 94 static struct qcom_icc_node qhs_qup0; 95 static struct qcom_icc_node qhs_qup1; 96 static struct qcom_icc_node qhs_sdc1; 97 static struct qcom_icc_node qhs_sdc2; 98 static struct qcom_icc_node qhs_snoc_cfg; 99 static struct qcom_icc_node qhs_spdm; 100 static struct qcom_icc_node qhs_tcsr; 101 static struct qcom_icc_node qhs_tlmm_east; 102 static struct qcom_icc_node qhs_tlmm_south; 103 static struct qcom_icc_node qhs_tlmm_west; 104 static struct qcom_icc_node qhs_ufs_mem_cfg; 105 static struct qcom_icc_node qhs_usb2; 106 static struct qcom_icc_node qhs_usb3; 107 static struct qcom_icc_node qhs_venus_cfg; 108 static struct qcom_icc_node qhs_vsense_ctrl_cfg; 109 static struct qcom_icc_node qns_cnoc_a2noc; 110 static struct qcom_icc_node srvc_cnoc; 111 static struct qcom_icc_node qhs_dc_noc_gemnoc; 112 static struct qcom_icc_node qhs_llcc; 113 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg; 114 static struct qcom_icc_node qns_gem_noc_snoc; 115 static struct qcom_icc_node qns_llcc; 116 static struct qcom_icc_node qns_sys_pcie; 117 static struct qcom_icc_node srvc_gemnoc; 118 static struct qcom_icc_node ebi; 119 static struct qcom_icc_node qns2_mem_noc; 120 static struct qcom_icc_node qns_mem_noc_hf; 121 static struct qcom_icc_node srvc_mnoc; 122 static struct qcom_icc_node qhs_apss; 123 static struct qcom_icc_node qns_cnoc; 124 static struct qcom_icc_node qns_gemnoc_sf; 125 static struct qcom_icc_node qns_memnoc_gc; 126 static struct qcom_icc_node qxs_imem; 127 static struct qcom_icc_node qxs_pimem; 128 static struct qcom_icc_node srvc_snoc; 129 static struct qcom_icc_node xs_pcie; 130 static struct qcom_icc_node xs_qdss_stm; 131 static struct qcom_icc_node xs_sys_tcu_cfg; 132 133 static struct qcom_icc_node qhm_a1noc_cfg = { 134 .name = "qhm_a1noc_cfg", 135 .channels = 1, 136 .buswidth = 4, 137 .num_links = 1, 138 .link_nodes = { &srvc_aggre2_noc }, 139 }; 140 141 static struct qcom_icc_node qhm_qdss_bam = { 142 .name = "qhm_qdss_bam", 143 .channels = 1, 144 .buswidth = 4, 145 .num_links = 1, 146 .link_nodes = { &qns_a1noc_snoc }, 147 }; 148 149 static struct qcom_icc_node qhm_qspi = { 150 .name = "qhm_qspi", 151 .channels = 1, 152 .buswidth = 4, 153 .num_links = 1, 154 .link_nodes = { &qns_a1noc_snoc }, 155 }; 156 157 static struct qcom_icc_node qhm_qup0 = { 158 .name = "qhm_qup0", 159 .channels = 1, 160 .buswidth = 4, 161 .num_links = 1, 162 .link_nodes = { &qns_a1noc_snoc }, 163 }; 164 165 static struct qcom_icc_node qhm_qup1 = { 166 .name = "qhm_qup1", 167 .channels = 1, 168 .buswidth = 4, 169 .num_links = 1, 170 .link_nodes = { &qns_a1noc_snoc }, 171 }; 172 173 static struct qcom_icc_node qnm_cnoc = { 174 .name = "qnm_cnoc", 175 .channels = 1, 176 .buswidth = 8, 177 .num_links = 1, 178 .link_nodes = { &qns_a1noc_snoc }, 179 }; 180 181 static struct qcom_icc_node qxm_crypto = { 182 .name = "qxm_crypto", 183 .channels = 1, 184 .buswidth = 8, 185 .num_links = 1, 186 .link_nodes = { &qns_a1noc_snoc }, 187 }; 188 189 static struct qcom_icc_node qxm_ipa = { 190 .name = "qxm_ipa", 191 .channels = 1, 192 .buswidth = 8, 193 .num_links = 1, 194 .link_nodes = { &qns_lpass_snoc }, 195 }; 196 197 static struct qcom_icc_node xm_emac_avb = { 198 .name = "xm_emac_avb", 199 .channels = 1, 200 .buswidth = 8, 201 .num_links = 1, 202 .link_nodes = { &qns_a1noc_snoc }, 203 }; 204 205 static struct qcom_icc_node xm_pcie = { 206 .name = "xm_pcie", 207 .channels = 1, 208 .buswidth = 8, 209 .num_links = 1, 210 .link_nodes = { &qns_pcie_snoc }, 211 }; 212 213 static struct qcom_icc_node xm_qdss_etr = { 214 .name = "xm_qdss_etr", 215 .channels = 1, 216 .buswidth = 8, 217 .num_links = 1, 218 .link_nodes = { &qns_a1noc_snoc }, 219 }; 220 221 static struct qcom_icc_node xm_sdc1 = { 222 .name = "xm_sdc1", 223 .channels = 1, 224 .buswidth = 8, 225 .num_links = 1, 226 .link_nodes = { &qns_a1noc_snoc }, 227 }; 228 229 static struct qcom_icc_node xm_sdc2 = { 230 .name = "xm_sdc2", 231 .channels = 1, 232 .buswidth = 8, 233 .num_links = 1, 234 .link_nodes = { &qns_a1noc_snoc }, 235 }; 236 237 static struct qcom_icc_node xm_ufs_mem = { 238 .name = "xm_ufs_mem", 239 .channels = 1, 240 .buswidth = 8, 241 .num_links = 1, 242 .link_nodes = { &qns_a1noc_snoc }, 243 }; 244 245 static struct qcom_icc_node xm_usb2 = { 246 .name = "xm_usb2", 247 .channels = 1, 248 .buswidth = 8, 249 .num_links = 1, 250 .link_nodes = { &qns_a1noc_snoc }, 251 }; 252 253 static struct qcom_icc_node xm_usb3_0 = { 254 .name = "xm_usb3_0", 255 .channels = 1, 256 .buswidth = 8, 257 .num_links = 1, 258 .link_nodes = { &qns_a1noc_snoc }, 259 }; 260 261 static struct qcom_icc_node qxm_camnoc_hf0_uncomp = { 262 .name = "qxm_camnoc_hf0_uncomp", 263 .channels = 1, 264 .buswidth = 32, 265 .num_links = 1, 266 .link_nodes = { &qns_camnoc_uncomp }, 267 }; 268 269 static struct qcom_icc_node qxm_camnoc_hf1_uncomp = { 270 .name = "qxm_camnoc_hf1_uncomp", 271 .channels = 1, 272 .buswidth = 32, 273 .num_links = 1, 274 .link_nodes = { &qns_camnoc_uncomp }, 275 }; 276 277 static struct qcom_icc_node qxm_camnoc_sf_uncomp = { 278 .name = "qxm_camnoc_sf_uncomp", 279 .channels = 1, 280 .buswidth = 32, 281 .num_links = 1, 282 .link_nodes = { &qns_camnoc_uncomp }, 283 }; 284 285 static struct qcom_icc_node qhm_spdm = { 286 .name = "qhm_spdm", 287 .channels = 1, 288 .buswidth = 4, 289 .num_links = 1, 290 .link_nodes = { &qns_cnoc_a2noc }, 291 }; 292 293 static struct qcom_icc_node qnm_snoc = { 294 .name = "qnm_snoc", 295 .channels = 1, 296 .buswidth = 8, 297 .num_links = 39, 298 .link_nodes = { &qhs_a1_noc_cfg, &qhs_ahb2phy_east, 299 &qhs_ahb2phy_west, &qhs_aop, 300 &qhs_aoss, &qhs_camera_cfg, 301 &qhs_clk_ctl, &qhs_cpr_cx, 302 &qhs_cpr_mx, &qhs_crypto0_cfg, 303 &qhs_ddrss_cfg, &qhs_display_cfg, 304 &qhs_emac_avb_cfg, &qhs_glm, 305 &qhs_gpuss_cfg, &qhs_imem_cfg, 306 &qhs_ipa, &qhs_mnoc_cfg, 307 &qhs_pcie_config, &qhs_pimem_cfg, 308 &qhs_prng, &qhs_qdss_cfg, 309 &qhs_qspi, &qhs_qup0, 310 &qhs_qup1, &qhs_sdc1, 311 &qhs_sdc2, &qhs_snoc_cfg, 312 &qhs_spdm, &qhs_tcsr, 313 &qhs_tlmm_east, &qhs_tlmm_south, 314 &qhs_tlmm_west, &qhs_ufs_mem_cfg, 315 &qhs_usb2, &qhs_usb3, 316 &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, 317 &srvc_cnoc }, 318 }; 319 320 static struct qcom_icc_node xm_qdss_dap = { 321 .name = "xm_qdss_dap", 322 .channels = 1, 323 .buswidth = 8, 324 .num_links = 40, 325 .link_nodes = { &qhs_a1_noc_cfg, &qhs_ahb2phy_east, 326 &qhs_ahb2phy_west, &qhs_aop, 327 &qhs_aoss, &qhs_camera_cfg, 328 &qhs_clk_ctl, &qhs_cpr_cx, 329 &qhs_cpr_mx, &qhs_crypto0_cfg, 330 &qhs_ddrss_cfg, &qhs_display_cfg, 331 &qhs_emac_avb_cfg, &qhs_glm, 332 &qhs_gpuss_cfg, &qhs_imem_cfg, 333 &qhs_ipa, &qhs_mnoc_cfg, 334 &qhs_pcie_config, &qhs_pimem_cfg, 335 &qhs_prng, &qhs_qdss_cfg, 336 &qhs_qspi, &qhs_qup0, 337 &qhs_qup1, &qhs_sdc1, 338 &qhs_sdc2, &qhs_snoc_cfg, 339 &qhs_spdm, &qhs_tcsr, 340 &qhs_tlmm_east, &qhs_tlmm_south, 341 &qhs_tlmm_west, &qhs_ufs_mem_cfg, 342 &qhs_usb2, &qhs_usb3, 343 &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, 344 &qns_cnoc_a2noc, &srvc_cnoc }, 345 }; 346 347 static struct qcom_icc_node qhm_cnoc = { 348 .name = "qhm_cnoc", 349 .channels = 1, 350 .buswidth = 4, 351 .num_links = 2, 352 .link_nodes = { &qhs_dc_noc_gemnoc, &qhs_llcc }, 353 }; 354 355 static struct qcom_icc_node acm_apps = { 356 .name = "acm_apps", 357 .channels = 1, 358 .buswidth = 16, 359 .num_links = 3, 360 .link_nodes = { &qns_gem_noc_snoc, &qns_llcc, 361 &qns_sys_pcie }, 362 }; 363 364 static struct qcom_icc_node acm_gpu_tcu = { 365 .name = "acm_gpu_tcu", 366 .channels = 1, 367 .buswidth = 8, 368 .num_links = 2, 369 .link_nodes = { &qns_gem_noc_snoc, &qns_llcc }, 370 }; 371 372 static struct qcom_icc_node acm_sys_tcu = { 373 .name = "acm_sys_tcu", 374 .channels = 1, 375 .buswidth = 8, 376 .num_links = 2, 377 .link_nodes = { &qns_gem_noc_snoc, &qns_llcc }, 378 }; 379 380 static struct qcom_icc_node qhm_gemnoc_cfg = { 381 .name = "qhm_gemnoc_cfg", 382 .channels = 1, 383 .buswidth = 4, 384 .num_links = 2, 385 .link_nodes = { &qhs_mdsp_ms_mpu_cfg, &srvc_gemnoc }, 386 }; 387 388 static struct qcom_icc_node qnm_gpu = { 389 .name = "qnm_gpu", 390 .channels = 2, 391 .buswidth = 32, 392 .num_links = 2, 393 .link_nodes = { &qns_gem_noc_snoc, &qns_llcc }, 394 }; 395 396 static struct qcom_icc_node qnm_mnoc_hf = { 397 .name = "qnm_mnoc_hf", 398 .channels = 1, 399 .buswidth = 32, 400 .num_links = 1, 401 .link_nodes = { &qns_llcc }, 402 }; 403 404 static struct qcom_icc_node qnm_mnoc_sf = { 405 .name = "qnm_mnoc_sf", 406 .channels = 1, 407 .buswidth = 32, 408 .num_links = 2, 409 .link_nodes = { &qns_gem_noc_snoc, &qns_llcc }, 410 }; 411 412 static struct qcom_icc_node qnm_snoc_gc = { 413 .name = "qnm_snoc_gc", 414 .channels = 1, 415 .buswidth = 8, 416 .num_links = 1, 417 .link_nodes = { &qns_llcc }, 418 }; 419 420 static struct qcom_icc_node qnm_snoc_sf = { 421 .name = "qnm_snoc_sf", 422 .channels = 1, 423 .buswidth = 16, 424 .num_links = 1, 425 .link_nodes = { &qns_llcc }, 426 }; 427 428 static struct qcom_icc_node llcc_mc = { 429 .name = "llcc_mc", 430 .channels = 2, 431 .buswidth = 4, 432 .num_links = 1, 433 .link_nodes = { &ebi }, 434 }; 435 436 static struct qcom_icc_node qhm_mnoc_cfg = { 437 .name = "qhm_mnoc_cfg", 438 .channels = 1, 439 .buswidth = 4, 440 .num_links = 1, 441 .link_nodes = { &srvc_mnoc }, 442 }; 443 444 static struct qcom_icc_node qxm_camnoc_hf0 = { 445 .name = "qxm_camnoc_hf0", 446 .channels = 1, 447 .buswidth = 32, 448 .num_links = 1, 449 .link_nodes = { &qns_mem_noc_hf }, 450 }; 451 452 static struct qcom_icc_node qxm_camnoc_hf1 = { 453 .name = "qxm_camnoc_hf1", 454 .channels = 1, 455 .buswidth = 32, 456 .num_links = 1, 457 .link_nodes = { &qns_mem_noc_hf }, 458 }; 459 460 static struct qcom_icc_node qxm_camnoc_sf = { 461 .name = "qxm_camnoc_sf", 462 .channels = 1, 463 .buswidth = 32, 464 .num_links = 1, 465 .link_nodes = { &qns2_mem_noc }, 466 }; 467 468 static struct qcom_icc_node qxm_mdp0 = { 469 .name = "qxm_mdp0", 470 .channels = 1, 471 .buswidth = 32, 472 .num_links = 1, 473 .link_nodes = { &qns_mem_noc_hf }, 474 }; 475 476 static struct qcom_icc_node qxm_rot = { 477 .name = "qxm_rot", 478 .channels = 1, 479 .buswidth = 32, 480 .num_links = 1, 481 .link_nodes = { &qns2_mem_noc }, 482 }; 483 484 static struct qcom_icc_node qxm_venus0 = { 485 .name = "qxm_venus0", 486 .channels = 1, 487 .buswidth = 32, 488 .num_links = 1, 489 .link_nodes = { &qns2_mem_noc }, 490 }; 491 492 static struct qcom_icc_node qxm_venus_arm9 = { 493 .name = "qxm_venus_arm9", 494 .channels = 1, 495 .buswidth = 8, 496 .num_links = 1, 497 .link_nodes = { &qns2_mem_noc }, 498 }; 499 500 static struct qcom_icc_node qhm_snoc_cfg = { 501 .name = "qhm_snoc_cfg", 502 .channels = 1, 503 .buswidth = 4, 504 .num_links = 1, 505 .link_nodes = { &srvc_snoc }, 506 }; 507 508 static struct qcom_icc_node qnm_aggre1_noc = { 509 .name = "qnm_aggre1_noc", 510 .channels = 1, 511 .buswidth = 16, 512 .num_links = 8, 513 .link_nodes = { &qhs_apss, &qns_cnoc, 514 &qns_gemnoc_sf, &qxs_imem, 515 &qxs_pimem, &xs_pcie, 516 &xs_qdss_stm, &xs_sys_tcu_cfg }, 517 }; 518 519 static struct qcom_icc_node qnm_gemnoc = { 520 .name = "qnm_gemnoc", 521 .channels = 1, 522 .buswidth = 8, 523 .num_links = 6, 524 .link_nodes = { &qhs_apss, &qns_cnoc, 525 &qxs_imem, &qxs_pimem, 526 &xs_qdss_stm, &xs_sys_tcu_cfg }, 527 }; 528 529 static struct qcom_icc_node qnm_gemnoc_pcie = { 530 .name = "qnm_gemnoc_pcie", 531 .channels = 1, 532 .buswidth = 8, 533 .num_links = 1, 534 .link_nodes = { &xs_pcie }, 535 }; 536 537 static struct qcom_icc_node qnm_lpass_anoc = { 538 .name = "qnm_lpass_anoc", 539 .channels = 1, 540 .buswidth = 8, 541 .num_links = 7, 542 .link_nodes = { &qhs_apss, &qns_cnoc, 543 &qns_gemnoc_sf, &qxs_imem, 544 &qxs_pimem, &xs_pcie, 545 &xs_qdss_stm }, 546 }; 547 548 static struct qcom_icc_node qnm_pcie_anoc = { 549 .name = "qnm_pcie_anoc", 550 .channels = 1, 551 .buswidth = 8, 552 .num_links = 5, 553 .link_nodes = { &qhs_apss, &qns_cnoc, 554 &qns_gemnoc_sf, &qxs_imem, 555 &xs_qdss_stm }, 556 }; 557 558 static struct qcom_icc_node qxm_pimem = { 559 .name = "qxm_pimem", 560 .channels = 1, 561 .buswidth = 8, 562 .num_links = 2, 563 .link_nodes = { &qns_memnoc_gc, &qxs_imem }, 564 }; 565 566 static struct qcom_icc_node xm_gic = { 567 .name = "xm_gic", 568 .channels = 1, 569 .buswidth = 8, 570 .num_links = 2, 571 .link_nodes = { &qns_memnoc_gc, &qxs_imem }, 572 }; 573 574 static struct qcom_icc_node qns_a1noc_snoc = { 575 .name = "qns_a1noc_snoc", 576 .channels = 1, 577 .buswidth = 16, 578 .num_links = 1, 579 .link_nodes = { &qnm_aggre1_noc }, 580 }; 581 582 static struct qcom_icc_node qns_lpass_snoc = { 583 .name = "qns_lpass_snoc", 584 .channels = 1, 585 .buswidth = 8, 586 .num_links = 1, 587 .link_nodes = { &qnm_lpass_anoc }, 588 }; 589 590 static struct qcom_icc_node qns_pcie_snoc = { 591 .name = "qns_pcie_snoc", 592 .channels = 1, 593 .buswidth = 8, 594 .num_links = 1, 595 .link_nodes = { &qnm_pcie_anoc }, 596 }; 597 598 static struct qcom_icc_node srvc_aggre2_noc = { 599 .name = "srvc_aggre2_noc", 600 .channels = 1, 601 .buswidth = 4, 602 }; 603 604 static struct qcom_icc_node qns_camnoc_uncomp = { 605 .name = "qns_camnoc_uncomp", 606 .channels = 1, 607 .buswidth = 32, 608 }; 609 610 static struct qcom_icc_node qhs_a1_noc_cfg = { 611 .name = "qhs_a1_noc_cfg", 612 .channels = 1, 613 .buswidth = 4, 614 .num_links = 1, 615 .link_nodes = { &qhm_a1noc_cfg }, 616 }; 617 618 static struct qcom_icc_node qhs_ahb2phy_east = { 619 .name = "qhs_ahb2phy_east", 620 .channels = 1, 621 .buswidth = 4, 622 }; 623 624 static struct qcom_icc_node qhs_ahb2phy_west = { 625 .name = "qhs_ahb2phy_west", 626 .channels = 1, 627 .buswidth = 4, 628 }; 629 630 static struct qcom_icc_node qhs_aop = { 631 .name = "qhs_aop", 632 .channels = 1, 633 .buswidth = 4, 634 }; 635 636 static struct qcom_icc_node qhs_aoss = { 637 .name = "qhs_aoss", 638 .channels = 1, 639 .buswidth = 4, 640 }; 641 642 static struct qcom_icc_node qhs_camera_cfg = { 643 .name = "qhs_camera_cfg", 644 .channels = 1, 645 .buswidth = 4, 646 }; 647 648 static struct qcom_icc_node qhs_clk_ctl = { 649 .name = "qhs_clk_ctl", 650 .channels = 1, 651 .buswidth = 4, 652 }; 653 654 static struct qcom_icc_node qhs_cpr_cx = { 655 .name = "qhs_cpr_cx", 656 .channels = 1, 657 .buswidth = 4, 658 }; 659 660 static struct qcom_icc_node qhs_cpr_mx = { 661 .name = "qhs_cpr_mx", 662 .channels = 1, 663 .buswidth = 4, 664 }; 665 666 static struct qcom_icc_node qhs_crypto0_cfg = { 667 .name = "qhs_crypto0_cfg", 668 .channels = 1, 669 .buswidth = 4, 670 }; 671 672 static struct qcom_icc_node qhs_ddrss_cfg = { 673 .name = "qhs_ddrss_cfg", 674 .channels = 1, 675 .buswidth = 4, 676 .num_links = 1, 677 .link_nodes = { &qhm_cnoc }, 678 }; 679 680 static struct qcom_icc_node qhs_display_cfg = { 681 .name = "qhs_display_cfg", 682 .channels = 1, 683 .buswidth = 4, 684 }; 685 686 static struct qcom_icc_node qhs_emac_avb_cfg = { 687 .name = "qhs_emac_avb_cfg", 688 .channels = 1, 689 .buswidth = 4, 690 }; 691 692 static struct qcom_icc_node qhs_glm = { 693 .name = "qhs_glm", 694 .channels = 1, 695 .buswidth = 4, 696 }; 697 698 static struct qcom_icc_node qhs_gpuss_cfg = { 699 .name = "qhs_gpuss_cfg", 700 .channels = 1, 701 .buswidth = 8, 702 }; 703 704 static struct qcom_icc_node qhs_imem_cfg = { 705 .name = "qhs_imem_cfg", 706 .channels = 1, 707 .buswidth = 4, 708 }; 709 710 static struct qcom_icc_node qhs_ipa = { 711 .name = "qhs_ipa", 712 .channels = 1, 713 .buswidth = 4, 714 }; 715 716 static struct qcom_icc_node qhs_mnoc_cfg = { 717 .name = "qhs_mnoc_cfg", 718 .channels = 1, 719 .buswidth = 4, 720 .num_links = 1, 721 .link_nodes = { &qhm_mnoc_cfg }, 722 }; 723 724 static struct qcom_icc_node qhs_pcie_config = { 725 .name = "qhs_pcie_config", 726 .channels = 1, 727 .buswidth = 4, 728 }; 729 730 static struct qcom_icc_node qhs_pimem_cfg = { 731 .name = "qhs_pimem_cfg", 732 .channels = 1, 733 .buswidth = 4, 734 }; 735 736 static struct qcom_icc_node qhs_prng = { 737 .name = "qhs_prng", 738 .channels = 1, 739 .buswidth = 4, 740 }; 741 742 static struct qcom_icc_node qhs_qdss_cfg = { 743 .name = "qhs_qdss_cfg", 744 .channels = 1, 745 .buswidth = 4, 746 }; 747 748 static struct qcom_icc_node qhs_qspi = { 749 .name = "qhs_qspi", 750 .channels = 1, 751 .buswidth = 4, 752 }; 753 754 static struct qcom_icc_node qhs_qup0 = { 755 .name = "qhs_qup0", 756 .channels = 1, 757 .buswidth = 4, 758 }; 759 760 static struct qcom_icc_node qhs_qup1 = { 761 .name = "qhs_qup1", 762 .channels = 1, 763 .buswidth = 4, 764 }; 765 766 static struct qcom_icc_node qhs_sdc1 = { 767 .name = "qhs_sdc1", 768 .channels = 1, 769 .buswidth = 4, 770 }; 771 772 static struct qcom_icc_node qhs_sdc2 = { 773 .name = "qhs_sdc2", 774 .channels = 1, 775 .buswidth = 4, 776 }; 777 778 static struct qcom_icc_node qhs_snoc_cfg = { 779 .name = "qhs_snoc_cfg", 780 .channels = 1, 781 .buswidth = 4, 782 .num_links = 1, 783 .link_nodes = { &qhm_snoc_cfg }, 784 }; 785 786 static struct qcom_icc_node qhs_spdm = { 787 .name = "qhs_spdm", 788 .channels = 1, 789 .buswidth = 4, 790 }; 791 792 static struct qcom_icc_node qhs_tcsr = { 793 .name = "qhs_tcsr", 794 .channels = 1, 795 .buswidth = 4, 796 }; 797 798 static struct qcom_icc_node qhs_tlmm_east = { 799 .name = "qhs_tlmm_east", 800 .channels = 1, 801 .buswidth = 4, 802 }; 803 804 static struct qcom_icc_node qhs_tlmm_south = { 805 .name = "qhs_tlmm_south", 806 .channels = 1, 807 .buswidth = 4, 808 }; 809 810 static struct qcom_icc_node qhs_tlmm_west = { 811 .name = "qhs_tlmm_west", 812 .channels = 1, 813 .buswidth = 4, 814 }; 815 816 static struct qcom_icc_node qhs_ufs_mem_cfg = { 817 .name = "qhs_ufs_mem_cfg", 818 .channels = 1, 819 .buswidth = 4, 820 }; 821 822 static struct qcom_icc_node qhs_usb2 = { 823 .name = "qhs_usb2", 824 .channels = 1, 825 .buswidth = 4, 826 }; 827 828 static struct qcom_icc_node qhs_usb3 = { 829 .name = "qhs_usb3", 830 .channels = 1, 831 .buswidth = 4, 832 }; 833 834 static struct qcom_icc_node qhs_venus_cfg = { 835 .name = "qhs_venus_cfg", 836 .channels = 1, 837 .buswidth = 4, 838 }; 839 840 static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 841 .name = "qhs_vsense_ctrl_cfg", 842 .channels = 1, 843 .buswidth = 4, 844 }; 845 846 static struct qcom_icc_node qns_cnoc_a2noc = { 847 .name = "qns_cnoc_a2noc", 848 .channels = 1, 849 .buswidth = 8, 850 .num_links = 1, 851 .link_nodes = { &qnm_cnoc }, 852 }; 853 854 static struct qcom_icc_node srvc_cnoc = { 855 .name = "srvc_cnoc", 856 .channels = 1, 857 .buswidth = 4, 858 }; 859 860 static struct qcom_icc_node qhs_dc_noc_gemnoc = { 861 .name = "qhs_dc_noc_gemnoc", 862 .channels = 1, 863 .buswidth = 4, 864 .num_links = 1, 865 .link_nodes = { &qhm_gemnoc_cfg }, 866 }; 867 868 static struct qcom_icc_node qhs_llcc = { 869 .name = "qhs_llcc", 870 .channels = 1, 871 .buswidth = 4, 872 }; 873 874 static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = { 875 .name = "qhs_mdsp_ms_mpu_cfg", 876 .channels = 1, 877 .buswidth = 4, 878 }; 879 880 static struct qcom_icc_node qns_gem_noc_snoc = { 881 .name = "qns_gem_noc_snoc", 882 .channels = 1, 883 .buswidth = 8, 884 .num_links = 1, 885 .link_nodes = { &qnm_gemnoc }, 886 }; 887 888 static struct qcom_icc_node qns_llcc = { 889 .name = "qns_llcc", 890 .channels = 1, 891 .buswidth = 16, 892 .num_links = 1, 893 .link_nodes = { &llcc_mc }, 894 }; 895 896 static struct qcom_icc_node qns_sys_pcie = { 897 .name = "qns_sys_pcie", 898 .channels = 1, 899 .buswidth = 8, 900 .num_links = 1, 901 .link_nodes = { &qnm_gemnoc_pcie }, 902 }; 903 904 static struct qcom_icc_node srvc_gemnoc = { 905 .name = "srvc_gemnoc", 906 .channels = 1, 907 .buswidth = 4, 908 }; 909 910 static struct qcom_icc_node ebi = { 911 .name = "ebi", 912 .channels = 2, 913 .buswidth = 4, 914 }; 915 916 static struct qcom_icc_node qns2_mem_noc = { 917 .name = "qns2_mem_noc", 918 .channels = 1, 919 .buswidth = 32, 920 .num_links = 1, 921 .link_nodes = { &qnm_mnoc_sf }, 922 }; 923 924 static struct qcom_icc_node qns_mem_noc_hf = { 925 .name = "qns_mem_noc_hf", 926 .channels = 1, 927 .buswidth = 32, 928 .num_links = 1, 929 .link_nodes = { &qnm_mnoc_hf }, 930 }; 931 932 static struct qcom_icc_node srvc_mnoc = { 933 .name = "srvc_mnoc", 934 .channels = 1, 935 .buswidth = 4, 936 }; 937 938 static struct qcom_icc_node qhs_apss = { 939 .name = "qhs_apss", 940 .channels = 1, 941 .buswidth = 8, 942 }; 943 944 static struct qcom_icc_node qns_cnoc = { 945 .name = "qns_cnoc", 946 .channels = 1, 947 .buswidth = 8, 948 .num_links = 1, 949 .link_nodes = { &qnm_snoc }, 950 }; 951 952 static struct qcom_icc_node qns_gemnoc_sf = { 953 .name = "qns_gemnoc_sf", 954 .channels = 1, 955 .buswidth = 16, 956 .num_links = 1, 957 .link_nodes = { &qnm_snoc_sf }, 958 }; 959 960 static struct qcom_icc_node qns_memnoc_gc = { 961 .name = "qns_memnoc_gc", 962 .channels = 1, 963 .buswidth = 8, 964 .num_links = 1, 965 .link_nodes = { &qnm_snoc_gc }, 966 }; 967 968 static struct qcom_icc_node qxs_imem = { 969 .name = "qxs_imem", 970 .channels = 1, 971 .buswidth = 8, 972 }; 973 974 static struct qcom_icc_node qxs_pimem = { 975 .name = "qxs_pimem", 976 .channels = 1, 977 .buswidth = 8, 978 }; 979 980 static struct qcom_icc_node srvc_snoc = { 981 .name = "srvc_snoc", 982 .channels = 1, 983 .buswidth = 4, 984 }; 985 986 static struct qcom_icc_node xs_pcie = { 987 .name = "xs_pcie", 988 .channels = 1, 989 .buswidth = 8, 990 }; 991 992 static struct qcom_icc_node xs_qdss_stm = { 993 .name = "xs_qdss_stm", 994 .channels = 1, 995 .buswidth = 4, 996 }; 997 998 static struct qcom_icc_node xs_sys_tcu_cfg = { 999 .name = "xs_sys_tcu_cfg", 1000 .channels = 1, 1001 .buswidth = 8, 1002 }; 1003 1004 static struct qcom_icc_bcm bcm_acv = { 1005 .name = "ACV", 1006 .num_nodes = 1, 1007 .nodes = { &ebi }, 1008 }; 1009 1010 static struct qcom_icc_bcm bcm_ce0 = { 1011 .name = "CE0", 1012 .num_nodes = 1, 1013 .nodes = { &qxm_crypto }, 1014 }; 1015 1016 static struct qcom_icc_bcm bcm_cn0 = { 1017 .name = "CN0", 1018 .keepalive = true, 1019 .num_nodes = 37, 1020 .nodes = { &qhm_spdm, &qnm_snoc, 1021 &qhs_a1_noc_cfg, &qhs_aop, 1022 &qhs_aoss, &qhs_camera_cfg, 1023 &qhs_clk_ctl, &qhs_cpr_cx, 1024 &qhs_cpr_mx, &qhs_crypto0_cfg, 1025 &qhs_ddrss_cfg, &qhs_display_cfg, 1026 &qhs_emac_avb_cfg, &qhs_glm, 1027 &qhs_gpuss_cfg, &qhs_imem_cfg, 1028 &qhs_ipa, &qhs_mnoc_cfg, 1029 &qhs_pcie_config, &qhs_pimem_cfg, 1030 &qhs_prng, &qhs_qdss_cfg, 1031 &qhs_qup0, &qhs_qup1, 1032 &qhs_snoc_cfg, &qhs_spdm, 1033 &qhs_tcsr, &qhs_tlmm_east, 1034 &qhs_tlmm_south, &qhs_tlmm_west, 1035 &qhs_ufs_mem_cfg, &qhs_usb2, 1036 &qhs_usb3, &qhs_venus_cfg, 1037 &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, 1038 &srvc_cnoc }, 1039 }; 1040 1041 static struct qcom_icc_bcm bcm_cn1 = { 1042 .name = "CN1", 1043 .num_nodes = 8, 1044 .nodes = { &qhm_qspi, &xm_sdc1, 1045 &xm_sdc2, &qhs_ahb2phy_east, 1046 &qhs_ahb2phy_west, &qhs_qspi, 1047 &qhs_sdc1, &qhs_sdc2 }, 1048 }; 1049 1050 static struct qcom_icc_bcm bcm_mc0 = { 1051 .name = "MC0", 1052 .keepalive = true, 1053 .num_nodes = 1, 1054 .nodes = { &ebi }, 1055 }; 1056 1057 static struct qcom_icc_bcm bcm_mm0 = { 1058 .name = "MM0", 1059 .keepalive = true, 1060 .num_nodes = 1, 1061 .nodes = { &qns_mem_noc_hf }, 1062 }; 1063 1064 static struct qcom_icc_bcm bcm_mm1 = { 1065 .name = "MM1", 1066 .num_nodes = 7, 1067 .nodes = { &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, 1068 &qxm_camnoc_sf_uncomp, &qxm_camnoc_hf0, 1069 &qxm_camnoc_hf1, &qxm_mdp0, 1070 &qxm_rot }, 1071 }; 1072 1073 static struct qcom_icc_bcm bcm_mm2 = { 1074 .name = "MM2", 1075 .num_nodes = 2, 1076 .nodes = { &qxm_camnoc_sf, &qns2_mem_noc }, 1077 }; 1078 1079 static struct qcom_icc_bcm bcm_mm3 = { 1080 .name = "MM3", 1081 .num_nodes = 2, 1082 .nodes = { &qxm_venus0, &qxm_venus_arm9 }, 1083 }; 1084 1085 static struct qcom_icc_bcm bcm_qup0 = { 1086 .name = "QUP0", 1087 .keepalive = true, 1088 .vote_scale = 1, 1089 .num_nodes = 2, 1090 .nodes = { &qhm_qup0, &qhm_qup1 }, 1091 }; 1092 1093 static struct qcom_icc_bcm bcm_sh0 = { 1094 .name = "SH0", 1095 .keepalive = true, 1096 .num_nodes = 1, 1097 .nodes = { &qns_llcc }, 1098 }; 1099 1100 static struct qcom_icc_bcm bcm_sh2 = { 1101 .name = "SH2", 1102 .num_nodes = 1, 1103 .nodes = { &acm_apps }, 1104 }; 1105 1106 static struct qcom_icc_bcm bcm_sh3 = { 1107 .name = "SH3", 1108 .num_nodes = 1, 1109 .nodes = { &qns_gem_noc_snoc }, 1110 }; 1111 1112 static struct qcom_icc_bcm bcm_sn0 = { 1113 .name = "SN0", 1114 .keepalive = true, 1115 .num_nodes = 1, 1116 .nodes = { &qns_gemnoc_sf }, 1117 }; 1118 1119 static struct qcom_icc_bcm bcm_sn1 = { 1120 .name = "SN1", 1121 .num_nodes = 1, 1122 .nodes = { &qxs_imem }, 1123 }; 1124 1125 static struct qcom_icc_bcm bcm_sn2 = { 1126 .name = "SN2", 1127 .num_nodes = 1, 1128 .nodes = { &qns_memnoc_gc }, 1129 }; 1130 1131 static struct qcom_icc_bcm bcm_sn3 = { 1132 .name = "SN3", 1133 .num_nodes = 2, 1134 .nodes = { &srvc_aggre2_noc, &qns_cnoc }, 1135 }; 1136 1137 static struct qcom_icc_bcm bcm_sn4 = { 1138 .name = "SN4", 1139 .num_nodes = 1, 1140 .nodes = { &qxs_pimem }, 1141 }; 1142 1143 static struct qcom_icc_bcm bcm_sn5 = { 1144 .name = "SN5", 1145 .num_nodes = 1, 1146 .nodes = { &xs_qdss_stm }, 1147 }; 1148 1149 static struct qcom_icc_bcm bcm_sn8 = { 1150 .name = "SN8", 1151 .num_nodes = 2, 1152 .nodes = { &qnm_gemnoc_pcie, &xs_pcie }, 1153 }; 1154 1155 static struct qcom_icc_bcm bcm_sn9 = { 1156 .name = "SN9", 1157 .num_nodes = 1, 1158 .nodes = { &qnm_aggre1_noc }, 1159 }; 1160 1161 static struct qcom_icc_bcm bcm_sn12 = { 1162 .name = "SN12", 1163 .num_nodes = 2, 1164 .nodes = { &qxm_pimem, &xm_gic }, 1165 }; 1166 1167 static struct qcom_icc_bcm bcm_sn13 = { 1168 .name = "SN13", 1169 .num_nodes = 1, 1170 .nodes = { &qnm_lpass_anoc }, 1171 }; 1172 1173 static struct qcom_icc_bcm bcm_sn14 = { 1174 .name = "SN14", 1175 .num_nodes = 1, 1176 .nodes = { &qns_pcie_snoc }, 1177 }; 1178 1179 static struct qcom_icc_bcm bcm_sn15 = { 1180 .name = "SN15", 1181 .num_nodes = 1, 1182 .nodes = { &qnm_gemnoc }, 1183 }; 1184 1185 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 1186 &bcm_ce0, 1187 &bcm_cn1, 1188 &bcm_qup0, 1189 &bcm_sn3, 1190 &bcm_sn14, 1191 }; 1192 1193 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1194 [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg, 1195 [MASTER_QDSS_BAM] = &qhm_qdss_bam, 1196 [MASTER_QSPI] = &qhm_qspi, 1197 [MASTER_QUP_0] = &qhm_qup0, 1198 [MASTER_BLSP_1] = &qhm_qup1, 1199 [MASTER_CNOC_A2NOC] = &qnm_cnoc, 1200 [MASTER_CRYPTO] = &qxm_crypto, 1201 [MASTER_IPA] = &qxm_ipa, 1202 [MASTER_EMAC_EVB] = &xm_emac_avb, 1203 [MASTER_PCIE] = &xm_pcie, 1204 [MASTER_QDSS_ETR] = &xm_qdss_etr, 1205 [MASTER_SDCC_1] = &xm_sdc1, 1206 [MASTER_SDCC_2] = &xm_sdc2, 1207 [MASTER_UFS_MEM] = &xm_ufs_mem, 1208 [MASTER_USB2] = &xm_usb2, 1209 [MASTER_USB3_0] = &xm_usb3_0, 1210 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, 1211 [SLAVE_LPASS_SNOC] = &qns_lpass_snoc, 1212 [SLAVE_ANOC_PCIE_SNOC] = &qns_pcie_snoc, 1213 [SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc, 1214 }; 1215 1216 static const struct qcom_icc_desc qcs615_aggre1_noc = { 1217 .nodes = aggre1_noc_nodes, 1218 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 1219 .bcms = aggre1_noc_bcms, 1220 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 1221 }; 1222 1223 static struct qcom_icc_bcm * const camnoc_virt_bcms[] = { 1224 &bcm_mm1, 1225 }; 1226 1227 static struct qcom_icc_node * const camnoc_virt_nodes[] = { 1228 [MASTER_CAMNOC_HF0_UNCOMP] = &qxm_camnoc_hf0_uncomp, 1229 [MASTER_CAMNOC_HF1_UNCOMP] = &qxm_camnoc_hf1_uncomp, 1230 [MASTER_CAMNOC_SF_UNCOMP] = &qxm_camnoc_sf_uncomp, 1231 [SLAVE_CAMNOC_UNCOMP] = &qns_camnoc_uncomp, 1232 }; 1233 1234 static const struct qcom_icc_desc qcs615_camnoc_virt = { 1235 .nodes = camnoc_virt_nodes, 1236 .num_nodes = ARRAY_SIZE(camnoc_virt_nodes), 1237 .bcms = camnoc_virt_bcms, 1238 .num_bcms = ARRAY_SIZE(camnoc_virt_bcms), 1239 }; 1240 1241 static struct qcom_icc_bcm * const config_noc_bcms[] = { 1242 &bcm_cn0, 1243 &bcm_cn1, 1244 }; 1245 1246 static struct qcom_icc_node * const config_noc_nodes[] = { 1247 [MASTER_SPDM] = &qhm_spdm, 1248 [MASTER_SNOC_CNOC] = &qnm_snoc, 1249 [MASTER_QDSS_DAP] = &xm_qdss_dap, 1250 [SLAVE_A1NOC_CFG] = &qhs_a1_noc_cfg, 1251 [SLAVE_AHB2PHY_EAST] = &qhs_ahb2phy_east, 1252 [SLAVE_AHB2PHY_WEST] = &qhs_ahb2phy_west, 1253 [SLAVE_AOP] = &qhs_aop, 1254 [SLAVE_AOSS] = &qhs_aoss, 1255 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 1256 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1257 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx, 1258 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx, 1259 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1260 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg, 1261 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 1262 [SLAVE_EMAC_AVB_CFG] = &qhs_emac_avb_cfg, 1263 [SLAVE_GLM] = &qhs_glm, 1264 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, 1265 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1266 [SLAVE_IPA_CFG] = &qhs_ipa, 1267 [SLAVE_CNOC_MNOC_CFG] = &qhs_mnoc_cfg, 1268 [SLAVE_PCIE_CFG] = &qhs_pcie_config, 1269 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg, 1270 [SLAVE_PRNG] = &qhs_prng, 1271 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1272 [SLAVE_QSPI] = &qhs_qspi, 1273 [SLAVE_QUP_0] = &qhs_qup0, 1274 [SLAVE_QUP_1] = &qhs_qup1, 1275 [SLAVE_SDCC_1] = &qhs_sdc1, 1276 [SLAVE_SDCC_2] = &qhs_sdc2, 1277 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg, 1278 [SLAVE_SPDM_WRAPPER] = &qhs_spdm, 1279 [SLAVE_TCSR] = &qhs_tcsr, 1280 [SLAVE_TLMM_EAST] = &qhs_tlmm_east, 1281 [SLAVE_TLMM_SOUTH] = &qhs_tlmm_south, 1282 [SLAVE_TLMM_WEST] = &qhs_tlmm_west, 1283 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 1284 [SLAVE_USB2] = &qhs_usb2, 1285 [SLAVE_USB3] = &qhs_usb3, 1286 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1287 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 1288 [SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc, 1289 [SLAVE_SERVICE_CNOC] = &srvc_cnoc, 1290 }; 1291 1292 static const struct qcom_icc_desc qcs615_config_noc = { 1293 .nodes = config_noc_nodes, 1294 .num_nodes = ARRAY_SIZE(config_noc_nodes), 1295 .bcms = config_noc_bcms, 1296 .num_bcms = ARRAY_SIZE(config_noc_bcms), 1297 }; 1298 1299 static struct qcom_icc_node * const dc_noc_nodes[] = { 1300 [MASTER_CNOC_DC_NOC] = &qhm_cnoc, 1301 [SLAVE_DC_NOC_GEMNOC] = &qhs_dc_noc_gemnoc, 1302 [SLAVE_LLCC_CFG] = &qhs_llcc, 1303 }; 1304 1305 static const struct qcom_icc_desc qcs615_dc_noc = { 1306 .nodes = dc_noc_nodes, 1307 .num_nodes = ARRAY_SIZE(dc_noc_nodes), 1308 }; 1309 1310 static struct qcom_icc_bcm * const gem_noc_bcms[] = { 1311 &bcm_sh0, 1312 &bcm_sh2, 1313 &bcm_sh3, 1314 &bcm_mm1, 1315 }; 1316 1317 static struct qcom_icc_node * const gem_noc_nodes[] = { 1318 [MASTER_APPSS_PROC] = &acm_apps, 1319 [MASTER_GPU_TCU] = &acm_gpu_tcu, 1320 [MASTER_SYS_TCU] = &acm_sys_tcu, 1321 [MASTER_GEM_NOC_CFG] = &qhm_gemnoc_cfg, 1322 [MASTER_GFX3D] = &qnm_gpu, 1323 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 1324 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 1325 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc, 1326 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 1327 [SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg, 1328 [SLAVE_GEM_NOC_SNOC] = &qns_gem_noc_snoc, 1329 [SLAVE_LLCC] = &qns_llcc, 1330 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_sys_pcie, 1331 [SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc, 1332 }; 1333 1334 static const struct qcom_icc_desc qcs615_gem_noc = { 1335 .nodes = gem_noc_nodes, 1336 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 1337 .bcms = gem_noc_bcms, 1338 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 1339 }; 1340 1341 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 1342 &bcm_acv, 1343 &bcm_mc0, 1344 }; 1345 1346 static struct qcom_icc_node * const mc_virt_nodes[] = { 1347 [MASTER_LLCC] = &llcc_mc, 1348 [SLAVE_EBI1] = &ebi, 1349 }; 1350 1351 static const struct qcom_icc_desc qcs615_mc_virt = { 1352 .nodes = mc_virt_nodes, 1353 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 1354 .bcms = mc_virt_bcms, 1355 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 1356 }; 1357 1358 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 1359 &bcm_mm0, 1360 &bcm_mm1, 1361 &bcm_mm2, 1362 &bcm_mm3, 1363 }; 1364 1365 static struct qcom_icc_node * const mmss_noc_nodes[] = { 1366 [MASTER_CNOC_MNOC_CFG] = &qhm_mnoc_cfg, 1367 [MASTER_CAMNOC_HF0] = &qxm_camnoc_hf0, 1368 [MASTER_CAMNOC_HF1] = &qxm_camnoc_hf1, 1369 [MASTER_CAMNOC_SF] = &qxm_camnoc_sf, 1370 [MASTER_MDP0] = &qxm_mdp0, 1371 [MASTER_ROTATOR] = &qxm_rot, 1372 [MASTER_VIDEO_P0] = &qxm_venus0, 1373 [MASTER_VIDEO_PROC] = &qxm_venus_arm9, 1374 [SLAVE_MNOC_SF_MEM_NOC] = &qns2_mem_noc, 1375 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 1376 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 1377 }; 1378 1379 static const struct qcom_icc_desc qcs615_mmss_noc = { 1380 .nodes = mmss_noc_nodes, 1381 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 1382 .bcms = mmss_noc_bcms, 1383 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 1384 }; 1385 1386 static struct qcom_icc_bcm * const system_noc_bcms[] = { 1387 &bcm_sn0, 1388 &bcm_sn1, 1389 &bcm_sn2, 1390 &bcm_sn3, 1391 &bcm_sn4, 1392 &bcm_sn5, 1393 &bcm_sn8, 1394 &bcm_sn9, 1395 &bcm_sn12, 1396 &bcm_sn13, 1397 &bcm_sn15, 1398 }; 1399 1400 static struct qcom_icc_node * const system_noc_nodes[] = { 1401 [MASTER_SNOC_CFG] = &qhm_snoc_cfg, 1402 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, 1403 [MASTER_GEM_NOC_SNOC] = &qnm_gemnoc, 1404 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, 1405 [MASTER_LPASS_ANOC] = &qnm_lpass_anoc, 1406 [MASTER_ANOC_PCIE_SNOC] = &qnm_pcie_anoc, 1407 [MASTER_PIMEM] = &qxm_pimem, 1408 [MASTER_GIC] = &xm_gic, 1409 [SLAVE_APPSS] = &qhs_apss, 1410 [SLAVE_SNOC_CNOC] = &qns_cnoc, 1411 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 1412 [SLAVE_SNOC_MEM_NOC_GC] = &qns_memnoc_gc, 1413 [SLAVE_IMEM] = &qxs_imem, 1414 [SLAVE_PIMEM] = &qxs_pimem, 1415 [SLAVE_SERVICE_SNOC] = &srvc_snoc, 1416 [SLAVE_PCIE_0] = &xs_pcie, 1417 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1418 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1419 }; 1420 1421 static const struct qcom_icc_desc qcs615_system_noc = { 1422 .nodes = system_noc_nodes, 1423 .num_nodes = ARRAY_SIZE(system_noc_nodes), 1424 .bcms = system_noc_bcms, 1425 .num_bcms = ARRAY_SIZE(system_noc_bcms), 1426 }; 1427 1428 static const struct of_device_id qnoc_of_match[] = { 1429 { .compatible = "qcom,qcs615-aggre1-noc", 1430 .data = &qcs615_aggre1_noc}, 1431 { .compatible = "qcom,qcs615-camnoc-virt", 1432 .data = &qcs615_camnoc_virt}, 1433 { .compatible = "qcom,qcs615-config-noc", 1434 .data = &qcs615_config_noc}, 1435 { .compatible = "qcom,qcs615-dc-noc", 1436 .data = &qcs615_dc_noc}, 1437 { .compatible = "qcom,qcs615-gem-noc", 1438 .data = &qcs615_gem_noc}, 1439 { .compatible = "qcom,qcs615-mc-virt", 1440 .data = &qcs615_mc_virt}, 1441 { .compatible = "qcom,qcs615-mmss-noc", 1442 .data = &qcs615_mmss_noc}, 1443 { .compatible = "qcom,qcs615-system-noc", 1444 .data = &qcs615_system_noc}, 1445 { } 1446 }; 1447 MODULE_DEVICE_TABLE(of, qnoc_of_match); 1448 1449 static struct platform_driver qnoc_driver = { 1450 .probe = qcom_icc_rpmh_probe, 1451 .remove = qcom_icc_rpmh_remove, 1452 .driver = { 1453 .name = "qnoc-qcs615", 1454 .of_match_table = qnoc_of_match, 1455 .sync_state = icc_sync_state, 1456 }, 1457 }; 1458 1459 static int __init qnoc_driver_init(void) 1460 { 1461 return platform_driver_register(&qnoc_driver); 1462 } 1463 core_initcall(qnoc_driver_init); 1464 1465 static void __exit qnoc_driver_exit(void) 1466 { 1467 platform_driver_unregister(&qnoc_driver); 1468 } 1469 module_exit(qnoc_driver_exit); 1470 1471 MODULE_DESCRIPTION("qcs615 NoC driver"); 1472 MODULE_LICENSE("GPL"); 1473