1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2019 Linaro Ltd 4 */ 5 6 #include <dt-bindings/interconnect/qcom,qcs404.h> 7 #include <linux/clk.h> 8 #include <linux/device.h> 9 #include <linux/interconnect-provider.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/of_device.h> 14 15 16 #include "smd-rpm.h" 17 #include "icc-rpm.h" 18 19 enum { 20 QCS404_MASTER_AMPSS_M0 = 1, 21 QCS404_MASTER_GRAPHICS_3D, 22 QCS404_MASTER_MDP_PORT0, 23 QCS404_SNOC_BIMC_1_MAS, 24 QCS404_MASTER_TCU_0, 25 QCS404_MASTER_SPDM, 26 QCS404_MASTER_BLSP_1, 27 QCS404_MASTER_BLSP_2, 28 QCS404_MASTER_XM_USB_HS1, 29 QCS404_MASTER_CRYPTO_CORE0, 30 QCS404_MASTER_SDCC_1, 31 QCS404_MASTER_SDCC_2, 32 QCS404_SNOC_PNOC_MAS, 33 QCS404_MASTER_QPIC, 34 QCS404_MASTER_QDSS_BAM, 35 QCS404_BIMC_SNOC_MAS, 36 QCS404_PNOC_SNOC_MAS, 37 QCS404_MASTER_QDSS_ETR, 38 QCS404_MASTER_EMAC, 39 QCS404_MASTER_PCIE, 40 QCS404_MASTER_USB3, 41 QCS404_PNOC_INT_0, 42 QCS404_PNOC_INT_2, 43 QCS404_PNOC_INT_3, 44 QCS404_PNOC_SLV_0, 45 QCS404_PNOC_SLV_1, 46 QCS404_PNOC_SLV_2, 47 QCS404_PNOC_SLV_3, 48 QCS404_PNOC_SLV_4, 49 QCS404_PNOC_SLV_6, 50 QCS404_PNOC_SLV_7, 51 QCS404_PNOC_SLV_8, 52 QCS404_PNOC_SLV_9, 53 QCS404_PNOC_SLV_10, 54 QCS404_PNOC_SLV_11, 55 QCS404_SNOC_QDSS_INT, 56 QCS404_SNOC_INT_0, 57 QCS404_SNOC_INT_1, 58 QCS404_SNOC_INT_2, 59 QCS404_SLAVE_EBI_CH0, 60 QCS404_BIMC_SNOC_SLV, 61 QCS404_SLAVE_SPDM_WRAPPER, 62 QCS404_SLAVE_PDM, 63 QCS404_SLAVE_PRNG, 64 QCS404_SLAVE_TCSR, 65 QCS404_SLAVE_SNOC_CFG, 66 QCS404_SLAVE_MESSAGE_RAM, 67 QCS404_SLAVE_DISPLAY_CFG, 68 QCS404_SLAVE_GRAPHICS_3D_CFG, 69 QCS404_SLAVE_BLSP_1, 70 QCS404_SLAVE_TLMM_NORTH, 71 QCS404_SLAVE_PCIE_1, 72 QCS404_SLAVE_EMAC_CFG, 73 QCS404_SLAVE_BLSP_2, 74 QCS404_SLAVE_TLMM_EAST, 75 QCS404_SLAVE_TCU, 76 QCS404_SLAVE_PMIC_ARB, 77 QCS404_SLAVE_SDCC_1, 78 QCS404_SLAVE_SDCC_2, 79 QCS404_SLAVE_TLMM_SOUTH, 80 QCS404_SLAVE_USB_HS, 81 QCS404_SLAVE_USB3, 82 QCS404_SLAVE_CRYPTO_0_CFG, 83 QCS404_PNOC_SNOC_SLV, 84 QCS404_SLAVE_APPSS, 85 QCS404_SLAVE_WCSS, 86 QCS404_SNOC_BIMC_1_SLV, 87 QCS404_SLAVE_OCIMEM, 88 QCS404_SNOC_PNOC_SLV, 89 QCS404_SLAVE_QDSS_STM, 90 QCS404_SLAVE_CATS_128, 91 QCS404_SLAVE_OCMEM_64, 92 QCS404_SLAVE_LPASS, 93 }; 94 95 static const u16 mas_apps_proc_links[] = { 96 QCS404_SLAVE_EBI_CH0, 97 QCS404_BIMC_SNOC_SLV 98 }; 99 100 static struct qcom_icc_node mas_apps_proc = { 101 .name = "mas_apps_proc", 102 .id = QCS404_MASTER_AMPSS_M0, 103 .buswidth = 8, 104 .mas_rpm_id = 0, 105 .slv_rpm_id = -1, 106 .num_links = ARRAY_SIZE(mas_apps_proc_links), 107 .links = mas_apps_proc_links, 108 }; 109 110 static const u16 mas_oxili_links[] = { 111 QCS404_SLAVE_EBI_CH0, 112 QCS404_BIMC_SNOC_SLV 113 }; 114 115 static struct qcom_icc_node mas_oxili = { 116 .name = "mas_oxili", 117 .id = QCS404_MASTER_GRAPHICS_3D, 118 .buswidth = 8, 119 .mas_rpm_id = -1, 120 .slv_rpm_id = -1, 121 .num_links = ARRAY_SIZE(mas_oxili_links), 122 .links = mas_oxili_links, 123 }; 124 125 static const u16 mas_mdp_links[] = { 126 QCS404_SLAVE_EBI_CH0, 127 QCS404_BIMC_SNOC_SLV 128 }; 129 130 static struct qcom_icc_node mas_mdp = { 131 .name = "mas_mdp", 132 .id = QCS404_MASTER_MDP_PORT0, 133 .buswidth = 8, 134 .mas_rpm_id = -1, 135 .slv_rpm_id = -1, 136 .num_links = ARRAY_SIZE(mas_mdp_links), 137 .links = mas_mdp_links, 138 }; 139 140 static const u16 mas_snoc_bimc_1_links[] = { 141 QCS404_SLAVE_EBI_CH0 142 }; 143 144 static struct qcom_icc_node mas_snoc_bimc_1 = { 145 .name = "mas_snoc_bimc_1", 146 .id = QCS404_SNOC_BIMC_1_MAS, 147 .buswidth = 8, 148 .mas_rpm_id = 76, 149 .slv_rpm_id = -1, 150 .num_links = ARRAY_SIZE(mas_snoc_bimc_1_links), 151 .links = mas_snoc_bimc_1_links, 152 }; 153 154 static const u16 mas_tcu_0_links[] = { 155 QCS404_SLAVE_EBI_CH0, 156 QCS404_BIMC_SNOC_SLV 157 }; 158 159 static struct qcom_icc_node mas_tcu_0 = { 160 .name = "mas_tcu_0", 161 .id = QCS404_MASTER_TCU_0, 162 .buswidth = 8, 163 .mas_rpm_id = -1, 164 .slv_rpm_id = -1, 165 .num_links = ARRAY_SIZE(mas_tcu_0_links), 166 .links = mas_tcu_0_links, 167 }; 168 169 static const u16 mas_spdm_links[] = { 170 QCS404_PNOC_INT_3 171 }; 172 173 static struct qcom_icc_node mas_spdm = { 174 .name = "mas_spdm", 175 .id = QCS404_MASTER_SPDM, 176 .buswidth = 4, 177 .mas_rpm_id = -1, 178 .slv_rpm_id = -1, 179 .num_links = ARRAY_SIZE(mas_spdm_links), 180 .links = mas_spdm_links, 181 }; 182 183 static const u16 mas_blsp_1_links[] = { 184 QCS404_PNOC_INT_3 185 }; 186 187 static struct qcom_icc_node mas_blsp_1 = { 188 .name = "mas_blsp_1", 189 .id = QCS404_MASTER_BLSP_1, 190 .buswidth = 4, 191 .mas_rpm_id = 41, 192 .slv_rpm_id = -1, 193 .num_links = ARRAY_SIZE(mas_blsp_1_links), 194 .links = mas_blsp_1_links, 195 }; 196 197 static const u16 mas_blsp_2_links[] = { 198 QCS404_PNOC_INT_3 199 }; 200 201 static struct qcom_icc_node mas_blsp_2 = { 202 .name = "mas_blsp_2", 203 .id = QCS404_MASTER_BLSP_2, 204 .buswidth = 4, 205 .mas_rpm_id = 39, 206 .slv_rpm_id = -1, 207 .num_links = ARRAY_SIZE(mas_blsp_2_links), 208 .links = mas_blsp_2_links, 209 }; 210 211 static const u16 mas_xi_usb_hs1_links[] = { 212 QCS404_PNOC_INT_0 213 }; 214 215 static struct qcom_icc_node mas_xi_usb_hs1 = { 216 .name = "mas_xi_usb_hs1", 217 .id = QCS404_MASTER_XM_USB_HS1, 218 .buswidth = 8, 219 .mas_rpm_id = 138, 220 .slv_rpm_id = -1, 221 .num_links = ARRAY_SIZE(mas_xi_usb_hs1_links), 222 .links = mas_xi_usb_hs1_links, 223 }; 224 225 static const u16 mas_crypto_links[] = { 226 QCS404_PNOC_SNOC_SLV, 227 QCS404_PNOC_INT_2 228 }; 229 230 static struct qcom_icc_node mas_crypto = { 231 .name = "mas_crypto", 232 .id = QCS404_MASTER_CRYPTO_CORE0, 233 .buswidth = 8, 234 .mas_rpm_id = 23, 235 .slv_rpm_id = -1, 236 .num_links = ARRAY_SIZE(mas_crypto_links), 237 .links = mas_crypto_links, 238 }; 239 240 static const u16 mas_sdcc_1_links[] = { 241 QCS404_PNOC_INT_0 242 }; 243 244 static struct qcom_icc_node mas_sdcc_1 = { 245 .name = "mas_sdcc_1", 246 .id = QCS404_MASTER_SDCC_1, 247 .buswidth = 8, 248 .mas_rpm_id = 33, 249 .slv_rpm_id = -1, 250 .num_links = ARRAY_SIZE(mas_sdcc_1_links), 251 .links = mas_sdcc_1_links, 252 }; 253 254 static const u16 mas_sdcc_2_links[] = { 255 QCS404_PNOC_INT_0 256 }; 257 258 static struct qcom_icc_node mas_sdcc_2 = { 259 .name = "mas_sdcc_2", 260 .id = QCS404_MASTER_SDCC_2, 261 .buswidth = 8, 262 .mas_rpm_id = 35, 263 .slv_rpm_id = -1, 264 .num_links = ARRAY_SIZE(mas_sdcc_2_links), 265 .links = mas_sdcc_2_links, 266 }; 267 268 static const u16 mas_snoc_pcnoc_links[] = { 269 QCS404_PNOC_INT_2 270 }; 271 272 static struct qcom_icc_node mas_snoc_pcnoc = { 273 .name = "mas_snoc_pcnoc", 274 .id = QCS404_SNOC_PNOC_MAS, 275 .buswidth = 8, 276 .mas_rpm_id = 77, 277 .slv_rpm_id = -1, 278 .num_links = ARRAY_SIZE(mas_snoc_pcnoc_links), 279 .links = mas_snoc_pcnoc_links, 280 }; 281 282 static const u16 mas_qpic_links[] = { 283 QCS404_PNOC_INT_0 284 }; 285 286 static struct qcom_icc_node mas_qpic = { 287 .name = "mas_qpic", 288 .id = QCS404_MASTER_QPIC, 289 .buswidth = 4, 290 .mas_rpm_id = -1, 291 .slv_rpm_id = -1, 292 .num_links = ARRAY_SIZE(mas_qpic_links), 293 .links = mas_qpic_links, 294 }; 295 296 static const u16 mas_qdss_bam_links[] = { 297 QCS404_SNOC_QDSS_INT 298 }; 299 300 static struct qcom_icc_node mas_qdss_bam = { 301 .name = "mas_qdss_bam", 302 .id = QCS404_MASTER_QDSS_BAM, 303 .buswidth = 4, 304 .mas_rpm_id = -1, 305 .slv_rpm_id = -1, 306 .num_links = ARRAY_SIZE(mas_qdss_bam_links), 307 .links = mas_qdss_bam_links, 308 }; 309 310 static const u16 mas_bimc_snoc_links[] = { 311 QCS404_SLAVE_OCMEM_64, 312 QCS404_SLAVE_CATS_128, 313 QCS404_SNOC_INT_0, 314 QCS404_SNOC_INT_1 315 }; 316 317 static struct qcom_icc_node mas_bimc_snoc = { 318 .name = "mas_bimc_snoc", 319 .id = QCS404_BIMC_SNOC_MAS, 320 .buswidth = 8, 321 .mas_rpm_id = 21, 322 .slv_rpm_id = -1, 323 .num_links = ARRAY_SIZE(mas_bimc_snoc_links), 324 .links = mas_bimc_snoc_links, 325 }; 326 327 static const u16 mas_pcnoc_snoc_links[] = { 328 QCS404_SNOC_BIMC_1_SLV, 329 QCS404_SNOC_INT_2, 330 QCS404_SNOC_INT_0 331 }; 332 333 static struct qcom_icc_node mas_pcnoc_snoc = { 334 .name = "mas_pcnoc_snoc", 335 .id = QCS404_PNOC_SNOC_MAS, 336 .buswidth = 8, 337 .mas_rpm_id = 29, 338 .slv_rpm_id = -1, 339 .num_links = ARRAY_SIZE(mas_pcnoc_snoc_links), 340 .links = mas_pcnoc_snoc_links, 341 }; 342 343 static const u16 mas_qdss_etr_links[] = { 344 QCS404_SNOC_QDSS_INT 345 }; 346 347 static struct qcom_icc_node mas_qdss_etr = { 348 .name = "mas_qdss_etr", 349 .id = QCS404_MASTER_QDSS_ETR, 350 .buswidth = 8, 351 .mas_rpm_id = -1, 352 .slv_rpm_id = -1, 353 .num_links = ARRAY_SIZE(mas_qdss_etr_links), 354 .links = mas_qdss_etr_links, 355 }; 356 357 static const u16 mas_emac_links[] = { 358 QCS404_SNOC_BIMC_1_SLV, 359 QCS404_SNOC_INT_1 360 }; 361 362 static struct qcom_icc_node mas_emac = { 363 .name = "mas_emac", 364 .id = QCS404_MASTER_EMAC, 365 .buswidth = 8, 366 .mas_rpm_id = -1, 367 .slv_rpm_id = -1, 368 .num_links = ARRAY_SIZE(mas_emac_links), 369 .links = mas_emac_links, 370 }; 371 372 static const u16 mas_pcie_links[] = { 373 QCS404_SNOC_BIMC_1_SLV, 374 QCS404_SNOC_INT_1 375 }; 376 377 static struct qcom_icc_node mas_pcie = { 378 .name = "mas_pcie", 379 .id = QCS404_MASTER_PCIE, 380 .buswidth = 8, 381 .mas_rpm_id = -1, 382 .slv_rpm_id = -1, 383 .num_links = ARRAY_SIZE(mas_pcie_links), 384 .links = mas_pcie_links, 385 }; 386 387 static const u16 mas_usb3_links[] = { 388 QCS404_SNOC_BIMC_1_SLV, 389 QCS404_SNOC_INT_1 390 }; 391 392 static struct qcom_icc_node mas_usb3 = { 393 .name = "mas_usb3", 394 .id = QCS404_MASTER_USB3, 395 .buswidth = 8, 396 .mas_rpm_id = -1, 397 .slv_rpm_id = -1, 398 .num_links = ARRAY_SIZE(mas_usb3_links), 399 .links = mas_usb3_links, 400 }; 401 402 static const u16 pcnoc_int_0_links[] = { 403 QCS404_PNOC_SNOC_SLV, 404 QCS404_PNOC_INT_2 405 }; 406 407 static struct qcom_icc_node pcnoc_int_0 = { 408 .name = "pcnoc_int_0", 409 .id = QCS404_PNOC_INT_0, 410 .buswidth = 8, 411 .mas_rpm_id = 85, 412 .slv_rpm_id = 114, 413 .num_links = ARRAY_SIZE(pcnoc_int_0_links), 414 .links = pcnoc_int_0_links, 415 }; 416 417 static const u16 pcnoc_int_2_links[] = { 418 QCS404_PNOC_SLV_10, 419 QCS404_SLAVE_TCU, 420 QCS404_PNOC_SLV_11, 421 QCS404_PNOC_SLV_2, 422 QCS404_PNOC_SLV_3, 423 QCS404_PNOC_SLV_0, 424 QCS404_PNOC_SLV_1, 425 QCS404_PNOC_SLV_6, 426 QCS404_PNOC_SLV_7, 427 QCS404_PNOC_SLV_4, 428 QCS404_PNOC_SLV_8, 429 QCS404_PNOC_SLV_9 430 }; 431 432 static struct qcom_icc_node pcnoc_int_2 = { 433 .name = "pcnoc_int_2", 434 .id = QCS404_PNOC_INT_2, 435 .buswidth = 8, 436 .mas_rpm_id = 124, 437 .slv_rpm_id = 184, 438 .num_links = ARRAY_SIZE(pcnoc_int_2_links), 439 .links = pcnoc_int_2_links, 440 }; 441 442 static const u16 pcnoc_int_3_links[] = { 443 QCS404_PNOC_SNOC_SLV 444 }; 445 446 static struct qcom_icc_node pcnoc_int_3 = { 447 .name = "pcnoc_int_3", 448 .id = QCS404_PNOC_INT_3, 449 .buswidth = 8, 450 .mas_rpm_id = 125, 451 .slv_rpm_id = 185, 452 .num_links = ARRAY_SIZE(pcnoc_int_3_links), 453 .links = pcnoc_int_3_links, 454 }; 455 456 static const u16 pcnoc_s_0_links[] = { 457 QCS404_SLAVE_PRNG, 458 QCS404_SLAVE_SPDM_WRAPPER, 459 QCS404_SLAVE_PDM 460 }; 461 462 static struct qcom_icc_node pcnoc_s_0 = { 463 .name = "pcnoc_s_0", 464 .id = QCS404_PNOC_SLV_0, 465 .buswidth = 4, 466 .mas_rpm_id = 89, 467 .slv_rpm_id = 118, 468 .num_links = ARRAY_SIZE(pcnoc_s_0_links), 469 .links = pcnoc_s_0_links, 470 }; 471 472 static const u16 pcnoc_s_1_links[] = { 473 QCS404_SLAVE_TCSR 474 }; 475 476 static struct qcom_icc_node pcnoc_s_1 = { 477 .name = "pcnoc_s_1", 478 .id = QCS404_PNOC_SLV_1, 479 .buswidth = 4, 480 .mas_rpm_id = 90, 481 .slv_rpm_id = 119, 482 .num_links = ARRAY_SIZE(pcnoc_s_1_links), 483 .links = pcnoc_s_1_links, 484 }; 485 486 static const u16 pcnoc_s_2_links[] = { 487 QCS404_SLAVE_GRAPHICS_3D_CFG 488 }; 489 490 static struct qcom_icc_node pcnoc_s_2 = { 491 .name = "pcnoc_s_2", 492 .id = QCS404_PNOC_SLV_2, 493 .buswidth = 4, 494 .mas_rpm_id = -1, 495 .slv_rpm_id = -1, 496 .num_links = ARRAY_SIZE(pcnoc_s_2_links), 497 .links = pcnoc_s_2_links, 498 }; 499 500 static const u16 pcnoc_s_3_links[] = { 501 QCS404_SLAVE_MESSAGE_RAM 502 }; 503 504 static struct qcom_icc_node pcnoc_s_3 = { 505 .name = "pcnoc_s_3", 506 .id = QCS404_PNOC_SLV_3, 507 .buswidth = 4, 508 .mas_rpm_id = 92, 509 .slv_rpm_id = 121, 510 .num_links = ARRAY_SIZE(pcnoc_s_3_links), 511 .links = pcnoc_s_3_links, 512 }; 513 514 static const u16 pcnoc_s_4_links[] = { 515 QCS404_SLAVE_SNOC_CFG 516 }; 517 518 static struct qcom_icc_node pcnoc_s_4 = { 519 .name = "pcnoc_s_4", 520 .id = QCS404_PNOC_SLV_4, 521 .buswidth = 4, 522 .mas_rpm_id = 93, 523 .slv_rpm_id = 122, 524 .num_links = ARRAY_SIZE(pcnoc_s_4_links), 525 .links = pcnoc_s_4_links, 526 }; 527 528 static const u16 pcnoc_s_6_links[] = { 529 QCS404_SLAVE_BLSP_1, 530 QCS404_SLAVE_TLMM_NORTH, 531 QCS404_SLAVE_EMAC_CFG 532 }; 533 534 static struct qcom_icc_node pcnoc_s_6 = { 535 .name = "pcnoc_s_6", 536 .id = QCS404_PNOC_SLV_6, 537 .buswidth = 4, 538 .mas_rpm_id = 94, 539 .slv_rpm_id = 123, 540 .num_links = ARRAY_SIZE(pcnoc_s_6_links), 541 .links = pcnoc_s_6_links, 542 }; 543 544 static const u16 pcnoc_s_7_links[] = { 545 QCS404_SLAVE_TLMM_SOUTH, 546 QCS404_SLAVE_DISPLAY_CFG, 547 QCS404_SLAVE_SDCC_1, 548 QCS404_SLAVE_PCIE_1, 549 QCS404_SLAVE_SDCC_2 550 }; 551 552 static struct qcom_icc_node pcnoc_s_7 = { 553 .name = "pcnoc_s_7", 554 .id = QCS404_PNOC_SLV_7, 555 .buswidth = 4, 556 .mas_rpm_id = 95, 557 .slv_rpm_id = 124, 558 .num_links = ARRAY_SIZE(pcnoc_s_7_links), 559 .links = pcnoc_s_7_links, 560 }; 561 562 static const u16 pcnoc_s_8_links[] = { 563 QCS404_SLAVE_CRYPTO_0_CFG 564 }; 565 566 static struct qcom_icc_node pcnoc_s_8 = { 567 .name = "pcnoc_s_8", 568 .id = QCS404_PNOC_SLV_8, 569 .buswidth = 4, 570 .mas_rpm_id = 96, 571 .slv_rpm_id = 125, 572 .num_links = ARRAY_SIZE(pcnoc_s_8_links), 573 .links = pcnoc_s_8_links, 574 }; 575 576 static const u16 pcnoc_s_9_links[] = { 577 QCS404_SLAVE_BLSP_2, 578 QCS404_SLAVE_TLMM_EAST, 579 QCS404_SLAVE_PMIC_ARB 580 }; 581 582 static struct qcom_icc_node pcnoc_s_9 = { 583 .name = "pcnoc_s_9", 584 .id = QCS404_PNOC_SLV_9, 585 .buswidth = 4, 586 .mas_rpm_id = 97, 587 .slv_rpm_id = 126, 588 .num_links = ARRAY_SIZE(pcnoc_s_9_links), 589 .links = pcnoc_s_9_links, 590 }; 591 592 static const u16 pcnoc_s_10_links[] = { 593 QCS404_SLAVE_USB_HS 594 }; 595 596 static struct qcom_icc_node pcnoc_s_10 = { 597 .name = "pcnoc_s_10", 598 .id = QCS404_PNOC_SLV_10, 599 .buswidth = 4, 600 .mas_rpm_id = 157, 601 .slv_rpm_id = -1, 602 .num_links = ARRAY_SIZE(pcnoc_s_10_links), 603 .links = pcnoc_s_10_links, 604 }; 605 606 static const u16 pcnoc_s_11_links[] = { 607 QCS404_SLAVE_USB3 608 }; 609 610 static struct qcom_icc_node pcnoc_s_11 = { 611 .name = "pcnoc_s_11", 612 .id = QCS404_PNOC_SLV_11, 613 .buswidth = 4, 614 .mas_rpm_id = 158, 615 .slv_rpm_id = 246, 616 .num_links = ARRAY_SIZE(pcnoc_s_11_links), 617 .links = pcnoc_s_11_links, 618 }; 619 620 static const u16 qdss_int_links[] = { 621 QCS404_SNOC_BIMC_1_SLV, 622 QCS404_SNOC_INT_1 623 }; 624 625 static struct qcom_icc_node qdss_int = { 626 .name = "qdss_int", 627 .id = QCS404_SNOC_QDSS_INT, 628 .buswidth = 8, 629 .mas_rpm_id = -1, 630 .slv_rpm_id = -1, 631 .num_links = ARRAY_SIZE(qdss_int_links), 632 .links = qdss_int_links, 633 }; 634 635 static const u16 snoc_int_0_links[] = { 636 QCS404_SLAVE_LPASS, 637 QCS404_SLAVE_APPSS, 638 QCS404_SLAVE_WCSS 639 }; 640 641 static struct qcom_icc_node snoc_int_0 = { 642 .name = "snoc_int_0", 643 .id = QCS404_SNOC_INT_0, 644 .buswidth = 8, 645 .mas_rpm_id = 99, 646 .slv_rpm_id = 130, 647 .num_links = ARRAY_SIZE(snoc_int_0_links), 648 .links = snoc_int_0_links, 649 }; 650 651 static const u16 snoc_int_1_links[] = { 652 QCS404_SNOC_PNOC_SLV, 653 QCS404_SNOC_INT_2 654 }; 655 656 static struct qcom_icc_node snoc_int_1 = { 657 .name = "snoc_int_1", 658 .id = QCS404_SNOC_INT_1, 659 .buswidth = 8, 660 .mas_rpm_id = 100, 661 .slv_rpm_id = 131, 662 .num_links = ARRAY_SIZE(snoc_int_1_links), 663 .links = snoc_int_1_links, 664 }; 665 666 static const u16 snoc_int_2_links[] = { 667 QCS404_SLAVE_QDSS_STM, 668 QCS404_SLAVE_OCIMEM 669 }; 670 671 static struct qcom_icc_node snoc_int_2 = { 672 .name = "snoc_int_2", 673 .id = QCS404_SNOC_INT_2, 674 .buswidth = 8, 675 .mas_rpm_id = 134, 676 .slv_rpm_id = 197, 677 .num_links = ARRAY_SIZE(snoc_int_2_links), 678 .links = snoc_int_2_links, 679 }; 680 681 static struct qcom_icc_node slv_ebi = { 682 .name = "slv_ebi", 683 .id = QCS404_SLAVE_EBI_CH0, 684 .buswidth = 8, 685 .mas_rpm_id = -1, 686 .slv_rpm_id = 0, 687 }; 688 689 static const u16 slv_bimc_snoc_links[] = { 690 QCS404_BIMC_SNOC_MAS 691 }; 692 693 static struct qcom_icc_node slv_bimc_snoc = { 694 .name = "slv_bimc_snoc", 695 .id = QCS404_BIMC_SNOC_SLV, 696 .buswidth = 8, 697 .mas_rpm_id = -1, 698 .slv_rpm_id = 2, 699 .num_links = ARRAY_SIZE(slv_bimc_snoc_links), 700 .links = slv_bimc_snoc_links, 701 }; 702 703 static struct qcom_icc_node slv_spdm = { 704 .name = "slv_spdm", 705 .id = QCS404_SLAVE_SPDM_WRAPPER, 706 .buswidth = 4, 707 .mas_rpm_id = -1, 708 .slv_rpm_id = -1, 709 }; 710 711 static struct qcom_icc_node slv_pdm = { 712 .name = "slv_pdm", 713 .id = QCS404_SLAVE_PDM, 714 .buswidth = 4, 715 .mas_rpm_id = -1, 716 .slv_rpm_id = 41, 717 }; 718 719 static struct qcom_icc_node slv_prng = { 720 .name = "slv_prng", 721 .id = QCS404_SLAVE_PRNG, 722 .buswidth = 4, 723 .mas_rpm_id = -1, 724 .slv_rpm_id = 44, 725 }; 726 727 static struct qcom_icc_node slv_tcsr = { 728 .name = "slv_tcsr", 729 .id = QCS404_SLAVE_TCSR, 730 .buswidth = 4, 731 .mas_rpm_id = -1, 732 .slv_rpm_id = 50, 733 }; 734 735 static struct qcom_icc_node slv_snoc_cfg = { 736 .name = "slv_snoc_cfg", 737 .id = QCS404_SLAVE_SNOC_CFG, 738 .buswidth = 4, 739 .mas_rpm_id = -1, 740 .slv_rpm_id = 70, 741 }; 742 743 static struct qcom_icc_node slv_message_ram = { 744 .name = "slv_message_ram", 745 .id = QCS404_SLAVE_MESSAGE_RAM, 746 .buswidth = 4, 747 .mas_rpm_id = -1, 748 .slv_rpm_id = 55, 749 }; 750 751 static struct qcom_icc_node slv_disp_ss_cfg = { 752 .name = "slv_disp_ss_cfg", 753 .id = QCS404_SLAVE_DISPLAY_CFG, 754 .buswidth = 4, 755 .mas_rpm_id = -1, 756 .slv_rpm_id = -1, 757 }; 758 759 static struct qcom_icc_node slv_gpu_cfg = { 760 .name = "slv_gpu_cfg", 761 .id = QCS404_SLAVE_GRAPHICS_3D_CFG, 762 .buswidth = 4, 763 .mas_rpm_id = -1, 764 .slv_rpm_id = -1, 765 }; 766 767 static struct qcom_icc_node slv_blsp_1 = { 768 .name = "slv_blsp_1", 769 .id = QCS404_SLAVE_BLSP_1, 770 .buswidth = 4, 771 .mas_rpm_id = -1, 772 .slv_rpm_id = 39, 773 }; 774 775 static struct qcom_icc_node slv_tlmm_north = { 776 .name = "slv_tlmm_north", 777 .id = QCS404_SLAVE_TLMM_NORTH, 778 .buswidth = 4, 779 .mas_rpm_id = -1, 780 .slv_rpm_id = 214, 781 }; 782 783 static struct qcom_icc_node slv_pcie = { 784 .name = "slv_pcie", 785 .id = QCS404_SLAVE_PCIE_1, 786 .buswidth = 4, 787 .mas_rpm_id = -1, 788 .slv_rpm_id = -1, 789 }; 790 791 static struct qcom_icc_node slv_ethernet = { 792 .name = "slv_ethernet", 793 .id = QCS404_SLAVE_EMAC_CFG, 794 .buswidth = 4, 795 .mas_rpm_id = -1, 796 .slv_rpm_id = -1, 797 }; 798 799 static struct qcom_icc_node slv_blsp_2 = { 800 .name = "slv_blsp_2", 801 .id = QCS404_SLAVE_BLSP_2, 802 .buswidth = 4, 803 .mas_rpm_id = -1, 804 .slv_rpm_id = 37, 805 }; 806 807 static struct qcom_icc_node slv_tlmm_east = { 808 .name = "slv_tlmm_east", 809 .id = QCS404_SLAVE_TLMM_EAST, 810 .buswidth = 4, 811 .mas_rpm_id = -1, 812 .slv_rpm_id = 213, 813 }; 814 815 static struct qcom_icc_node slv_tcu = { 816 .name = "slv_tcu", 817 .id = QCS404_SLAVE_TCU, 818 .buswidth = 8, 819 .mas_rpm_id = -1, 820 .slv_rpm_id = -1, 821 }; 822 823 static struct qcom_icc_node slv_pmic_arb = { 824 .name = "slv_pmic_arb", 825 .id = QCS404_SLAVE_PMIC_ARB, 826 .buswidth = 4, 827 .mas_rpm_id = -1, 828 .slv_rpm_id = 59, 829 }; 830 831 static struct qcom_icc_node slv_sdcc_1 = { 832 .name = "slv_sdcc_1", 833 .id = QCS404_SLAVE_SDCC_1, 834 .buswidth = 4, 835 .mas_rpm_id = -1, 836 .slv_rpm_id = 31, 837 }; 838 839 static struct qcom_icc_node slv_sdcc_2 = { 840 .name = "slv_sdcc_2", 841 .id = QCS404_SLAVE_SDCC_2, 842 .buswidth = 4, 843 .mas_rpm_id = -1, 844 .slv_rpm_id = 33, 845 }; 846 847 static struct qcom_icc_node slv_tlmm_south = { 848 .name = "slv_tlmm_south", 849 .id = QCS404_SLAVE_TLMM_SOUTH, 850 .buswidth = 4, 851 .mas_rpm_id = -1, 852 .slv_rpm_id = -1, 853 }; 854 855 static struct qcom_icc_node slv_usb_hs = { 856 .name = "slv_usb_hs", 857 .id = QCS404_SLAVE_USB_HS, 858 .buswidth = 4, 859 .mas_rpm_id = -1, 860 .slv_rpm_id = 40, 861 }; 862 863 static struct qcom_icc_node slv_usb3 = { 864 .name = "slv_usb3", 865 .id = QCS404_SLAVE_USB3, 866 .buswidth = 4, 867 .mas_rpm_id = -1, 868 .slv_rpm_id = 22, 869 }; 870 871 static struct qcom_icc_node slv_crypto_0_cfg = { 872 .name = "slv_crypto_0_cfg", 873 .id = QCS404_SLAVE_CRYPTO_0_CFG, 874 .buswidth = 4, 875 .mas_rpm_id = -1, 876 .slv_rpm_id = 52, 877 }; 878 879 static const u16 slv_pcnoc_snoc_links[] = { 880 QCS404_PNOC_SNOC_MAS 881 }; 882 883 static struct qcom_icc_node slv_pcnoc_snoc = { 884 .name = "slv_pcnoc_snoc", 885 .id = QCS404_PNOC_SNOC_SLV, 886 .buswidth = 8, 887 .mas_rpm_id = -1, 888 .slv_rpm_id = 45, 889 .num_links = ARRAY_SIZE(slv_pcnoc_snoc_links), 890 .links = slv_pcnoc_snoc_links, 891 }; 892 893 static struct qcom_icc_node slv_kpss_ahb = { 894 .name = "slv_kpss_ahb", 895 .id = QCS404_SLAVE_APPSS, 896 .buswidth = 4, 897 .mas_rpm_id = -1, 898 .slv_rpm_id = -1, 899 }; 900 901 static struct qcom_icc_node slv_wcss = { 902 .name = "slv_wcss", 903 .id = QCS404_SLAVE_WCSS, 904 .buswidth = 4, 905 .mas_rpm_id = -1, 906 .slv_rpm_id = 23, 907 }; 908 909 static const u16 slv_snoc_bimc_1_links[] = { 910 QCS404_SNOC_BIMC_1_MAS 911 }; 912 913 static struct qcom_icc_node slv_snoc_bimc_1 = { 914 .name = "slv_snoc_bimc_1", 915 .id = QCS404_SNOC_BIMC_1_SLV, 916 .buswidth = 8, 917 .mas_rpm_id = -1, 918 .slv_rpm_id = 104, 919 .num_links = ARRAY_SIZE(slv_snoc_bimc_1_links), 920 .links = slv_snoc_bimc_1_links, 921 }; 922 923 static struct qcom_icc_node slv_imem = { 924 .name = "slv_imem", 925 .id = QCS404_SLAVE_OCIMEM, 926 .buswidth = 8, 927 .mas_rpm_id = -1, 928 .slv_rpm_id = 26, 929 }; 930 931 static const u16 slv_snoc_pcnoc_links[] = { 932 QCS404_SNOC_PNOC_MAS 933 }; 934 935 static struct qcom_icc_node slv_snoc_pcnoc = { 936 .name = "slv_snoc_pcnoc", 937 .id = QCS404_SNOC_PNOC_SLV, 938 .buswidth = 8, 939 .mas_rpm_id = -1, 940 .slv_rpm_id = 28, 941 .num_links = ARRAY_SIZE(slv_snoc_pcnoc_links), 942 .links = slv_snoc_pcnoc_links, 943 }; 944 945 static struct qcom_icc_node slv_qdss_stm = { 946 .name = "slv_qdss_stm", 947 .id = QCS404_SLAVE_QDSS_STM, 948 .buswidth = 4, 949 .mas_rpm_id = -1, 950 .slv_rpm_id = 30, 951 }; 952 953 static struct qcom_icc_node slv_cats_0 = { 954 .name = "slv_cats_0", 955 .id = QCS404_SLAVE_CATS_128, 956 .buswidth = 16, 957 .mas_rpm_id = -1, 958 .slv_rpm_id = -1, 959 }; 960 961 static struct qcom_icc_node slv_cats_1 = { 962 .name = "slv_cats_1", 963 .id = QCS404_SLAVE_OCMEM_64, 964 .buswidth = 8, 965 .mas_rpm_id = -1, 966 .slv_rpm_id = -1, 967 }; 968 969 static struct qcom_icc_node slv_lpass = { 970 .name = "slv_lpass", 971 .id = QCS404_SLAVE_LPASS, 972 .buswidth = 4, 973 .mas_rpm_id = -1, 974 .slv_rpm_id = -1, 975 }; 976 977 static struct qcom_icc_node * const qcs404_bimc_nodes[] = { 978 [MASTER_AMPSS_M0] = &mas_apps_proc, 979 [MASTER_OXILI] = &mas_oxili, 980 [MASTER_MDP_PORT0] = &mas_mdp, 981 [MASTER_SNOC_BIMC_1] = &mas_snoc_bimc_1, 982 [MASTER_TCU_0] = &mas_tcu_0, 983 [SLAVE_EBI_CH0] = &slv_ebi, 984 [SLAVE_BIMC_SNOC] = &slv_bimc_snoc, 985 }; 986 987 static const struct qcom_icc_desc qcs404_bimc = { 988 .nodes = qcs404_bimc_nodes, 989 .num_nodes = ARRAY_SIZE(qcs404_bimc_nodes), 990 }; 991 992 static struct qcom_icc_node * const qcs404_pcnoc_nodes[] = { 993 [MASTER_SPDM] = &mas_spdm, 994 [MASTER_BLSP_1] = &mas_blsp_1, 995 [MASTER_BLSP_2] = &mas_blsp_2, 996 [MASTER_XI_USB_HS1] = &mas_xi_usb_hs1, 997 [MASTER_CRYPT0] = &mas_crypto, 998 [MASTER_SDCC_1] = &mas_sdcc_1, 999 [MASTER_SDCC_2] = &mas_sdcc_2, 1000 [MASTER_SNOC_PCNOC] = &mas_snoc_pcnoc, 1001 [MASTER_QPIC] = &mas_qpic, 1002 [PCNOC_INT_0] = &pcnoc_int_0, 1003 [PCNOC_INT_2] = &pcnoc_int_2, 1004 [PCNOC_INT_3] = &pcnoc_int_3, 1005 [PCNOC_S_0] = &pcnoc_s_0, 1006 [PCNOC_S_1] = &pcnoc_s_1, 1007 [PCNOC_S_2] = &pcnoc_s_2, 1008 [PCNOC_S_3] = &pcnoc_s_3, 1009 [PCNOC_S_4] = &pcnoc_s_4, 1010 [PCNOC_S_6] = &pcnoc_s_6, 1011 [PCNOC_S_7] = &pcnoc_s_7, 1012 [PCNOC_S_8] = &pcnoc_s_8, 1013 [PCNOC_S_9] = &pcnoc_s_9, 1014 [PCNOC_S_10] = &pcnoc_s_10, 1015 [PCNOC_S_11] = &pcnoc_s_11, 1016 [SLAVE_SPDM] = &slv_spdm, 1017 [SLAVE_PDM] = &slv_pdm, 1018 [SLAVE_PRNG] = &slv_prng, 1019 [SLAVE_TCSR] = &slv_tcsr, 1020 [SLAVE_SNOC_CFG] = &slv_snoc_cfg, 1021 [SLAVE_MESSAGE_RAM] = &slv_message_ram, 1022 [SLAVE_DISP_SS_CFG] = &slv_disp_ss_cfg, 1023 [SLAVE_GPU_CFG] = &slv_gpu_cfg, 1024 [SLAVE_BLSP_1] = &slv_blsp_1, 1025 [SLAVE_BLSP_2] = &slv_blsp_2, 1026 [SLAVE_TLMM_NORTH] = &slv_tlmm_north, 1027 [SLAVE_PCIE] = &slv_pcie, 1028 [SLAVE_ETHERNET] = &slv_ethernet, 1029 [SLAVE_TLMM_EAST] = &slv_tlmm_east, 1030 [SLAVE_TCU] = &slv_tcu, 1031 [SLAVE_PMIC_ARB] = &slv_pmic_arb, 1032 [SLAVE_SDCC_1] = &slv_sdcc_1, 1033 [SLAVE_SDCC_2] = &slv_sdcc_2, 1034 [SLAVE_TLMM_SOUTH] = &slv_tlmm_south, 1035 [SLAVE_USB_HS] = &slv_usb_hs, 1036 [SLAVE_USB3] = &slv_usb3, 1037 [SLAVE_CRYPTO_0_CFG] = &slv_crypto_0_cfg, 1038 [SLAVE_PCNOC_SNOC] = &slv_pcnoc_snoc, 1039 }; 1040 1041 static const struct qcom_icc_desc qcs404_pcnoc = { 1042 .nodes = qcs404_pcnoc_nodes, 1043 .num_nodes = ARRAY_SIZE(qcs404_pcnoc_nodes), 1044 }; 1045 1046 static struct qcom_icc_node * const qcs404_snoc_nodes[] = { 1047 [MASTER_QDSS_BAM] = &mas_qdss_bam, 1048 [MASTER_BIMC_SNOC] = &mas_bimc_snoc, 1049 [MASTER_PCNOC_SNOC] = &mas_pcnoc_snoc, 1050 [MASTER_QDSS_ETR] = &mas_qdss_etr, 1051 [MASTER_EMAC] = &mas_emac, 1052 [MASTER_PCIE] = &mas_pcie, 1053 [MASTER_USB3] = &mas_usb3, 1054 [QDSS_INT] = &qdss_int, 1055 [SNOC_INT_0] = &snoc_int_0, 1056 [SNOC_INT_1] = &snoc_int_1, 1057 [SNOC_INT_2] = &snoc_int_2, 1058 [SLAVE_KPSS_AHB] = &slv_kpss_ahb, 1059 [SLAVE_WCSS] = &slv_wcss, 1060 [SLAVE_SNOC_BIMC_1] = &slv_snoc_bimc_1, 1061 [SLAVE_IMEM] = &slv_imem, 1062 [SLAVE_SNOC_PCNOC] = &slv_snoc_pcnoc, 1063 [SLAVE_QDSS_STM] = &slv_qdss_stm, 1064 [SLAVE_CATS_0] = &slv_cats_0, 1065 [SLAVE_CATS_1] = &slv_cats_1, 1066 [SLAVE_LPASS] = &slv_lpass, 1067 }; 1068 1069 static const struct qcom_icc_desc qcs404_snoc = { 1070 .nodes = qcs404_snoc_nodes, 1071 .num_nodes = ARRAY_SIZE(qcs404_snoc_nodes), 1072 }; 1073 1074 1075 static const struct of_device_id qcs404_noc_of_match[] = { 1076 { .compatible = "qcom,qcs404-bimc", .data = &qcs404_bimc }, 1077 { .compatible = "qcom,qcs404-pcnoc", .data = &qcs404_pcnoc }, 1078 { .compatible = "qcom,qcs404-snoc", .data = &qcs404_snoc }, 1079 { }, 1080 }; 1081 MODULE_DEVICE_TABLE(of, qcs404_noc_of_match); 1082 1083 static struct platform_driver qcs404_noc_driver = { 1084 .probe = qnoc_probe, 1085 .remove = qnoc_remove, 1086 .driver = { 1087 .name = "qnoc-qcs404", 1088 .of_match_table = qcs404_noc_of_match, 1089 }, 1090 }; 1091 module_platform_driver(qcs404_noc_driver); 1092 MODULE_DESCRIPTION("Qualcomm QCS404 NoC driver"); 1093 MODULE_LICENSE("GPL v2"); 1094