1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Qualcomm QCM2290 Network-on-Chip (NoC) QoS driver 4 * 5 * Copyright (c) 2021, Linaro Ltd. 6 * 7 */ 8 9 #include <dt-bindings/interconnect/qcom,qcm2290.h> 10 #include <linux/device.h> 11 #include <linux/interconnect-provider.h> 12 #include <linux/io.h> 13 #include <linux/module.h> 14 #include <linux/platform_device.h> 15 #include <linux/regmap.h> 16 #include <linux/slab.h> 17 18 #include "icc-rpm.h" 19 20 enum { 21 QCM2290_MASTER_APPSS_PROC = 1, 22 QCM2290_MASTER_SNOC_BIMC_RT, 23 QCM2290_MASTER_SNOC_BIMC_NRT, 24 QCM2290_MASTER_SNOC_BIMC, 25 QCM2290_MASTER_TCU_0, 26 QCM2290_MASTER_GFX3D, 27 QCM2290_MASTER_SNOC_CNOC, 28 QCM2290_MASTER_QDSS_DAP, 29 QCM2290_MASTER_CRYPTO_CORE0, 30 QCM2290_MASTER_SNOC_CFG, 31 QCM2290_MASTER_TIC, 32 QCM2290_MASTER_ANOC_SNOC, 33 QCM2290_MASTER_BIMC_SNOC, 34 QCM2290_MASTER_PIMEM, 35 QCM2290_MASTER_QDSS_BAM, 36 QCM2290_MASTER_QUP_0, 37 QCM2290_MASTER_IPA, 38 QCM2290_MASTER_QDSS_ETR, 39 QCM2290_MASTER_SDCC_1, 40 QCM2290_MASTER_SDCC_2, 41 QCM2290_MASTER_QPIC, 42 QCM2290_MASTER_USB3_0, 43 QCM2290_MASTER_QUP_CORE_0, 44 QCM2290_MASTER_CAMNOC_SF, 45 QCM2290_MASTER_VIDEO_P0, 46 QCM2290_MASTER_VIDEO_PROC, 47 QCM2290_MASTER_CAMNOC_HF, 48 QCM2290_MASTER_MDP0, 49 50 QCM2290_SLAVE_EBI1, 51 QCM2290_SLAVE_BIMC_SNOC, 52 QCM2290_SLAVE_BIMC_CFG, 53 QCM2290_SLAVE_CAMERA_NRT_THROTTLE_CFG, 54 QCM2290_SLAVE_CAMERA_RT_THROTTLE_CFG, 55 QCM2290_SLAVE_CAMERA_CFG, 56 QCM2290_SLAVE_CLK_CTL, 57 QCM2290_SLAVE_CRYPTO_0_CFG, 58 QCM2290_SLAVE_DISPLAY_CFG, 59 QCM2290_SLAVE_DISPLAY_THROTTLE_CFG, 60 QCM2290_SLAVE_GPU_CFG, 61 QCM2290_SLAVE_HWKM, 62 QCM2290_SLAVE_IMEM_CFG, 63 QCM2290_SLAVE_IPA_CFG, 64 QCM2290_SLAVE_LPASS, 65 QCM2290_SLAVE_MESSAGE_RAM, 66 QCM2290_SLAVE_PDM, 67 QCM2290_SLAVE_PIMEM_CFG, 68 QCM2290_SLAVE_PKA_WRAPPER, 69 QCM2290_SLAVE_PMIC_ARB, 70 QCM2290_SLAVE_PRNG, 71 QCM2290_SLAVE_QDSS_CFG, 72 QCM2290_SLAVE_QM_CFG, 73 QCM2290_SLAVE_QM_MPU_CFG, 74 QCM2290_SLAVE_QPIC, 75 QCM2290_SLAVE_QUP_0, 76 QCM2290_SLAVE_SDCC_1, 77 QCM2290_SLAVE_SDCC_2, 78 QCM2290_SLAVE_SNOC_CFG, 79 QCM2290_SLAVE_TCSR, 80 QCM2290_SLAVE_USB3, 81 QCM2290_SLAVE_VENUS_CFG, 82 QCM2290_SLAVE_VENUS_THROTTLE_CFG, 83 QCM2290_SLAVE_VSENSE_CTRL_CFG, 84 QCM2290_SLAVE_SERVICE_CNOC, 85 QCM2290_SLAVE_APPSS, 86 QCM2290_SLAVE_SNOC_CNOC, 87 QCM2290_SLAVE_IMEM, 88 QCM2290_SLAVE_PIMEM, 89 QCM2290_SLAVE_SNOC_BIMC, 90 QCM2290_SLAVE_SERVICE_SNOC, 91 QCM2290_SLAVE_QDSS_STM, 92 QCM2290_SLAVE_TCU, 93 QCM2290_SLAVE_ANOC_SNOC, 94 QCM2290_SLAVE_QUP_CORE_0, 95 QCM2290_SLAVE_SNOC_BIMC_NRT, 96 QCM2290_SLAVE_SNOC_BIMC_RT, 97 }; 98 99 /* Master nodes */ 100 static const u16 mas_appss_proc_links[] = { 101 QCM2290_SLAVE_EBI1, 102 QCM2290_SLAVE_BIMC_SNOC, 103 }; 104 105 static struct qcom_icc_node mas_appss_proc = { 106 .id = QCM2290_MASTER_APPSS_PROC, 107 .name = "mas_apps_proc", 108 .buswidth = 16, 109 .qos.ap_owned = true, 110 .qos.qos_port = 0, 111 .qos.qos_mode = NOC_QOS_MODE_FIXED, 112 .qos.prio_level = 0, 113 .qos.areq_prio = 0, 114 .bus_clk_desc = &mem_1_clk, 115 .ab_coeff = 159, 116 .ib_coeff = 96, 117 .mas_rpm_id = 0, 118 .slv_rpm_id = -1, 119 .num_links = ARRAY_SIZE(mas_appss_proc_links), 120 .links = mas_appss_proc_links, 121 }; 122 123 static const u16 mas_snoc_bimc_rt_links[] = { 124 QCM2290_SLAVE_EBI1, 125 }; 126 127 static struct qcom_icc_node mas_snoc_bimc_rt = { 128 .id = QCM2290_MASTER_SNOC_BIMC_RT, 129 .name = "mas_snoc_bimc_rt", 130 .buswidth = 16, 131 .qos.ap_owned = true, 132 .qos.qos_port = 2, 133 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 134 .mas_rpm_id = 163, 135 .slv_rpm_id = -1, 136 .num_links = ARRAY_SIZE(mas_snoc_bimc_rt_links), 137 .links = mas_snoc_bimc_rt_links, 138 }; 139 140 static const u16 mas_snoc_bimc_nrt_links[] = { 141 QCM2290_SLAVE_EBI1, 142 }; 143 144 static struct qcom_icc_node mas_snoc_bimc_nrt = { 145 .id = QCM2290_MASTER_SNOC_BIMC_NRT, 146 .name = "mas_snoc_bimc_nrt", 147 .buswidth = 16, 148 .qos.ap_owned = true, 149 .qos.qos_port = 3, 150 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 151 .mas_rpm_id = 164, 152 .slv_rpm_id = -1, 153 .num_links = ARRAY_SIZE(mas_snoc_bimc_nrt_links), 154 .links = mas_snoc_bimc_nrt_links, 155 }; 156 157 static const u16 mas_snoc_bimc_links[] = { 158 QCM2290_SLAVE_EBI1, 159 }; 160 161 static struct qcom_icc_node mas_snoc_bimc = { 162 .id = QCM2290_MASTER_SNOC_BIMC, 163 .name = "mas_snoc_bimc", 164 .buswidth = 16, 165 .qos.ap_owned = true, 166 .qos.qos_port = 6, 167 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 168 .mas_rpm_id = 3, 169 .slv_rpm_id = -1, 170 .num_links = ARRAY_SIZE(mas_snoc_bimc_links), 171 .links = mas_snoc_bimc_links, 172 }; 173 174 static const u16 mas_tcu_0_links[] = { 175 QCM2290_SLAVE_EBI1, 176 QCM2290_SLAVE_BIMC_SNOC, 177 }; 178 179 static struct qcom_icc_node mas_tcu_0 = { 180 .id = QCM2290_MASTER_TCU_0, 181 .name = "mas_tcu_0", 182 .buswidth = 8, 183 .qos.ap_owned = true, 184 .qos.qos_port = 4, 185 .qos.qos_mode = NOC_QOS_MODE_FIXED, 186 .qos.prio_level = 6, 187 .qos.areq_prio = 6, 188 .mas_rpm_id = 102, 189 .slv_rpm_id = -1, 190 .num_links = ARRAY_SIZE(mas_tcu_0_links), 191 .links = mas_tcu_0_links, 192 }; 193 194 static const u16 mas_snoc_cnoc_links[] = { 195 QCM2290_SLAVE_CAMERA_RT_THROTTLE_CFG, 196 QCM2290_SLAVE_SDCC_2, 197 QCM2290_SLAVE_SDCC_1, 198 QCM2290_SLAVE_QM_CFG, 199 QCM2290_SLAVE_BIMC_CFG, 200 QCM2290_SLAVE_USB3, 201 QCM2290_SLAVE_QM_MPU_CFG, 202 QCM2290_SLAVE_CAMERA_NRT_THROTTLE_CFG, 203 QCM2290_SLAVE_QDSS_CFG, 204 QCM2290_SLAVE_PDM, 205 QCM2290_SLAVE_IPA_CFG, 206 QCM2290_SLAVE_DISPLAY_THROTTLE_CFG, 207 QCM2290_SLAVE_TCSR, 208 QCM2290_SLAVE_MESSAGE_RAM, 209 QCM2290_SLAVE_PMIC_ARB, 210 QCM2290_SLAVE_LPASS, 211 QCM2290_SLAVE_DISPLAY_CFG, 212 QCM2290_SLAVE_VENUS_CFG, 213 QCM2290_SLAVE_GPU_CFG, 214 QCM2290_SLAVE_IMEM_CFG, 215 QCM2290_SLAVE_SNOC_CFG, 216 QCM2290_SLAVE_SERVICE_CNOC, 217 QCM2290_SLAVE_VENUS_THROTTLE_CFG, 218 QCM2290_SLAVE_PKA_WRAPPER, 219 QCM2290_SLAVE_HWKM, 220 QCM2290_SLAVE_PRNG, 221 QCM2290_SLAVE_VSENSE_CTRL_CFG, 222 QCM2290_SLAVE_CRYPTO_0_CFG, 223 QCM2290_SLAVE_PIMEM_CFG, 224 QCM2290_SLAVE_QUP_0, 225 QCM2290_SLAVE_CAMERA_CFG, 226 QCM2290_SLAVE_CLK_CTL, 227 QCM2290_SLAVE_QPIC, 228 }; 229 230 static struct qcom_icc_node mas_snoc_cnoc = { 231 .id = QCM2290_MASTER_SNOC_CNOC, 232 .name = "mas_snoc_cnoc", 233 .buswidth = 8, 234 .qos.ap_owned = true, 235 .qos.qos_mode = NOC_QOS_MODE_INVALID, 236 .mas_rpm_id = 52, 237 .slv_rpm_id = -1, 238 .num_links = ARRAY_SIZE(mas_snoc_cnoc_links), 239 .links = mas_snoc_cnoc_links, 240 }; 241 242 static const u16 mas_qdss_dap_links[] = { 243 QCM2290_SLAVE_CAMERA_RT_THROTTLE_CFG, 244 QCM2290_SLAVE_SDCC_2, 245 QCM2290_SLAVE_SDCC_1, 246 QCM2290_SLAVE_QM_CFG, 247 QCM2290_SLAVE_BIMC_CFG, 248 QCM2290_SLAVE_USB3, 249 QCM2290_SLAVE_QM_MPU_CFG, 250 QCM2290_SLAVE_CAMERA_NRT_THROTTLE_CFG, 251 QCM2290_SLAVE_QDSS_CFG, 252 QCM2290_SLAVE_PDM, 253 QCM2290_SLAVE_IPA_CFG, 254 QCM2290_SLAVE_DISPLAY_THROTTLE_CFG, 255 QCM2290_SLAVE_TCSR, 256 QCM2290_SLAVE_MESSAGE_RAM, 257 QCM2290_SLAVE_PMIC_ARB, 258 QCM2290_SLAVE_LPASS, 259 QCM2290_SLAVE_DISPLAY_CFG, 260 QCM2290_SLAVE_VENUS_CFG, 261 QCM2290_SLAVE_GPU_CFG, 262 QCM2290_SLAVE_IMEM_CFG, 263 QCM2290_SLAVE_SNOC_CFG, 264 QCM2290_SLAVE_SERVICE_CNOC, 265 QCM2290_SLAVE_VENUS_THROTTLE_CFG, 266 QCM2290_SLAVE_PKA_WRAPPER, 267 QCM2290_SLAVE_HWKM, 268 QCM2290_SLAVE_PRNG, 269 QCM2290_SLAVE_VSENSE_CTRL_CFG, 270 QCM2290_SLAVE_CRYPTO_0_CFG, 271 QCM2290_SLAVE_PIMEM_CFG, 272 QCM2290_SLAVE_QUP_0, 273 QCM2290_SLAVE_CAMERA_CFG, 274 QCM2290_SLAVE_CLK_CTL, 275 QCM2290_SLAVE_QPIC, 276 }; 277 278 static struct qcom_icc_node mas_qdss_dap = { 279 .id = QCM2290_MASTER_QDSS_DAP, 280 .name = "mas_qdss_dap", 281 .buswidth = 8, 282 .qos.ap_owned = true, 283 .qos.qos_mode = NOC_QOS_MODE_INVALID, 284 .mas_rpm_id = 49, 285 .slv_rpm_id = -1, 286 .num_links = ARRAY_SIZE(mas_qdss_dap_links), 287 .links = mas_qdss_dap_links, 288 }; 289 290 static const u16 mas_crypto_core0_links[] = { 291 QCM2290_SLAVE_ANOC_SNOC 292 }; 293 294 static struct qcom_icc_node mas_crypto_core0 = { 295 .id = QCM2290_MASTER_CRYPTO_CORE0, 296 .name = "mas_crypto_core0", 297 .buswidth = 8, 298 .qos.ap_owned = true, 299 .qos.qos_port = 22, 300 .qos.qos_mode = NOC_QOS_MODE_FIXED, 301 .qos.areq_prio = 2, 302 .mas_rpm_id = 23, 303 .slv_rpm_id = -1, 304 .num_links = ARRAY_SIZE(mas_crypto_core0_links), 305 .links = mas_crypto_core0_links, 306 }; 307 308 static const u16 mas_qup_core_0_links[] = { 309 QCM2290_SLAVE_QUP_CORE_0, 310 }; 311 312 static struct qcom_icc_node mas_qup_core_0 = { 313 .id = QCM2290_MASTER_QUP_CORE_0, 314 .name = "mas_qup_core_0", 315 .buswidth = 4, 316 .mas_rpm_id = 170, 317 .slv_rpm_id = -1, 318 .num_links = ARRAY_SIZE(mas_qup_core_0_links), 319 .links = mas_qup_core_0_links, 320 }; 321 322 static const u16 mas_camnoc_sf_links[] = { 323 QCM2290_SLAVE_SNOC_BIMC_NRT, 324 }; 325 326 static struct qcom_icc_node mas_camnoc_sf = { 327 .id = QCM2290_MASTER_CAMNOC_SF, 328 .name = "mas_camnoc_sf", 329 .buswidth = 32, 330 .qos.ap_owned = true, 331 .qos.qos_port = 4, 332 .qos.qos_mode = NOC_QOS_MODE_FIXED, 333 .qos.areq_prio = 3, 334 .mas_rpm_id = 172, 335 .slv_rpm_id = -1, 336 .num_links = ARRAY_SIZE(mas_camnoc_sf_links), 337 .links = mas_camnoc_sf_links, 338 }; 339 340 static const u16 mas_camnoc_hf_links[] = { 341 QCM2290_SLAVE_SNOC_BIMC_RT, 342 }; 343 344 static struct qcom_icc_node mas_camnoc_hf = { 345 .id = QCM2290_MASTER_CAMNOC_HF, 346 .name = "mas_camnoc_hf", 347 .buswidth = 32, 348 .qos.ap_owned = true, 349 .qos.qos_port = 10, 350 .qos.qos_mode = NOC_QOS_MODE_FIXED, 351 .qos.areq_prio = 3, 352 .qos.urg_fwd_en = true, 353 .mas_rpm_id = 173, 354 .slv_rpm_id = -1, 355 .num_links = ARRAY_SIZE(mas_camnoc_hf_links), 356 .links = mas_camnoc_hf_links, 357 }; 358 359 static const u16 mas_mdp0_links[] = { 360 QCM2290_SLAVE_SNOC_BIMC_RT, 361 }; 362 363 static struct qcom_icc_node mas_mdp0 = { 364 .id = QCM2290_MASTER_MDP0, 365 .name = "mas_mdp0", 366 .buswidth = 16, 367 .qos.ap_owned = true, 368 .qos.qos_port = 5, 369 .qos.qos_mode = NOC_QOS_MODE_FIXED, 370 .qos.areq_prio = 3, 371 .qos.urg_fwd_en = true, 372 .mas_rpm_id = 8, 373 .slv_rpm_id = -1, 374 .num_links = ARRAY_SIZE(mas_mdp0_links), 375 .links = mas_mdp0_links, 376 }; 377 378 static const u16 mas_video_p0_links[] = { 379 QCM2290_SLAVE_SNOC_BIMC_NRT, 380 }; 381 382 static struct qcom_icc_node mas_video_p0 = { 383 .id = QCM2290_MASTER_VIDEO_P0, 384 .name = "mas_video_p0", 385 .buswidth = 16, 386 .qos.ap_owned = true, 387 .qos.qos_port = 9, 388 .qos.qos_mode = NOC_QOS_MODE_FIXED, 389 .qos.areq_prio = 3, 390 .qos.urg_fwd_en = true, 391 .mas_rpm_id = 9, 392 .slv_rpm_id = -1, 393 .num_links = ARRAY_SIZE(mas_video_p0_links), 394 .links = mas_video_p0_links, 395 }; 396 397 static const u16 mas_video_proc_links[] = { 398 QCM2290_SLAVE_SNOC_BIMC_NRT, 399 }; 400 401 static struct qcom_icc_node mas_video_proc = { 402 .id = QCM2290_MASTER_VIDEO_PROC, 403 .name = "mas_video_proc", 404 .buswidth = 8, 405 .qos.ap_owned = true, 406 .qos.qos_port = 13, 407 .qos.qos_mode = NOC_QOS_MODE_FIXED, 408 .qos.areq_prio = 4, 409 .mas_rpm_id = 168, 410 .slv_rpm_id = -1, 411 .num_links = ARRAY_SIZE(mas_video_proc_links), 412 .links = mas_video_proc_links, 413 }; 414 415 static const u16 mas_snoc_cfg_links[] = { 416 QCM2290_SLAVE_SERVICE_SNOC, 417 }; 418 419 static struct qcom_icc_node mas_snoc_cfg = { 420 .id = QCM2290_MASTER_SNOC_CFG, 421 .name = "mas_snoc_cfg", 422 .buswidth = 4, 423 .qos.ap_owned = true, 424 .qos.qos_mode = NOC_QOS_MODE_INVALID, 425 .mas_rpm_id = 20, 426 .slv_rpm_id = -1, 427 .num_links = ARRAY_SIZE(mas_snoc_cfg_links), 428 .links = mas_snoc_cfg_links, 429 }; 430 431 static const u16 mas_tic_links[] = { 432 QCM2290_SLAVE_PIMEM, 433 QCM2290_SLAVE_IMEM, 434 QCM2290_SLAVE_APPSS, 435 QCM2290_SLAVE_SNOC_BIMC, 436 QCM2290_SLAVE_SNOC_CNOC, 437 QCM2290_SLAVE_TCU, 438 QCM2290_SLAVE_QDSS_STM, 439 }; 440 441 static struct qcom_icc_node mas_tic = { 442 .id = QCM2290_MASTER_TIC, 443 .name = "mas_tic", 444 .buswidth = 4, 445 .qos.ap_owned = true, 446 .qos.qos_port = 8, 447 .qos.qos_mode = NOC_QOS_MODE_FIXED, 448 .qos.areq_prio = 2, 449 .mas_rpm_id = 51, 450 .slv_rpm_id = -1, 451 .num_links = ARRAY_SIZE(mas_tic_links), 452 .links = mas_tic_links, 453 }; 454 455 static const u16 mas_anoc_snoc_links[] = { 456 QCM2290_SLAVE_PIMEM, 457 QCM2290_SLAVE_IMEM, 458 QCM2290_SLAVE_APPSS, 459 QCM2290_SLAVE_SNOC_BIMC, 460 QCM2290_SLAVE_SNOC_CNOC, 461 QCM2290_SLAVE_TCU, 462 QCM2290_SLAVE_QDSS_STM, 463 }; 464 465 static struct qcom_icc_node mas_anoc_snoc = { 466 .id = QCM2290_MASTER_ANOC_SNOC, 467 .name = "mas_anoc_snoc", 468 .buswidth = 16, 469 .mas_rpm_id = 110, 470 .slv_rpm_id = -1, 471 .num_links = ARRAY_SIZE(mas_anoc_snoc_links), 472 .links = mas_anoc_snoc_links, 473 }; 474 475 static const u16 mas_bimc_snoc_links[] = { 476 QCM2290_SLAVE_PIMEM, 477 QCM2290_SLAVE_IMEM, 478 QCM2290_SLAVE_APPSS, 479 QCM2290_SLAVE_SNOC_CNOC, 480 QCM2290_SLAVE_TCU, 481 QCM2290_SLAVE_QDSS_STM, 482 }; 483 484 static struct qcom_icc_node mas_bimc_snoc = { 485 .id = QCM2290_MASTER_BIMC_SNOC, 486 .name = "mas_bimc_snoc", 487 .buswidth = 8, 488 .mas_rpm_id = 21, 489 .slv_rpm_id = -1, 490 .num_links = ARRAY_SIZE(mas_bimc_snoc_links), 491 .links = mas_bimc_snoc_links, 492 }; 493 494 static const u16 mas_pimem_links[] = { 495 QCM2290_SLAVE_IMEM, 496 QCM2290_SLAVE_SNOC_BIMC, 497 }; 498 499 static struct qcom_icc_node mas_pimem = { 500 .id = QCM2290_MASTER_PIMEM, 501 .name = "mas_pimem", 502 .buswidth = 8, 503 .qos.ap_owned = true, 504 .qos.qos_port = 20, 505 .qos.qos_mode = NOC_QOS_MODE_FIXED, 506 .qos.areq_prio = 2, 507 .mas_rpm_id = 113, 508 .slv_rpm_id = -1, 509 .num_links = ARRAY_SIZE(mas_pimem_links), 510 .links = mas_pimem_links, 511 }; 512 513 static const u16 mas_qdss_bam_links[] = { 514 QCM2290_SLAVE_ANOC_SNOC, 515 }; 516 517 static struct qcom_icc_node mas_qdss_bam = { 518 .id = QCM2290_MASTER_QDSS_BAM, 519 .name = "mas_qdss_bam", 520 .buswidth = 4, 521 .qos.ap_owned = true, 522 .qos.qos_port = 2, 523 .qos.qos_mode = NOC_QOS_MODE_FIXED, 524 .qos.areq_prio = 2, 525 .mas_rpm_id = 19, 526 .slv_rpm_id = -1, 527 .num_links = ARRAY_SIZE(mas_qdss_bam_links), 528 .links = mas_qdss_bam_links, 529 }; 530 531 static const u16 mas_qup_0_links[] = { 532 QCM2290_SLAVE_ANOC_SNOC, 533 }; 534 535 static struct qcom_icc_node mas_qup_0 = { 536 .id = QCM2290_MASTER_QUP_0, 537 .name = "mas_qup_0", 538 .buswidth = 4, 539 .qos.ap_owned = true, 540 .qos.qos_port = 0, 541 .qos.qos_mode = NOC_QOS_MODE_FIXED, 542 .qos.areq_prio = 2, 543 .mas_rpm_id = 166, 544 .slv_rpm_id = -1, 545 .num_links = ARRAY_SIZE(mas_qup_0_links), 546 .links = mas_qup_0_links, 547 }; 548 549 static const u16 mas_ipa_links[] = { 550 QCM2290_SLAVE_ANOC_SNOC, 551 }; 552 553 static struct qcom_icc_node mas_ipa = { 554 .id = QCM2290_MASTER_IPA, 555 .name = "mas_ipa", 556 .buswidth = 8, 557 .qos.ap_owned = true, 558 .qos.qos_port = 3, 559 .qos.qos_mode = NOC_QOS_MODE_FIXED, 560 .qos.areq_prio = 2, 561 .mas_rpm_id = 59, 562 .slv_rpm_id = -1, 563 .num_links = ARRAY_SIZE(mas_ipa_links), 564 .links = mas_ipa_links, 565 }; 566 567 static const u16 mas_qdss_etr_links[] = { 568 QCM2290_SLAVE_ANOC_SNOC, 569 }; 570 571 static struct qcom_icc_node mas_qdss_etr = { 572 .id = QCM2290_MASTER_QDSS_ETR, 573 .name = "mas_qdss_etr", 574 .buswidth = 8, 575 .qos.ap_owned = true, 576 .qos.qos_port = 12, 577 .qos.qos_mode = NOC_QOS_MODE_FIXED, 578 .qos.areq_prio = 2, 579 .mas_rpm_id = 31, 580 .slv_rpm_id = -1, 581 .num_links = ARRAY_SIZE(mas_qdss_etr_links), 582 .links = mas_qdss_etr_links, 583 }; 584 585 static const u16 mas_sdcc_1_links[] = { 586 QCM2290_SLAVE_ANOC_SNOC, 587 }; 588 589 static struct qcom_icc_node mas_sdcc_1 = { 590 .id = QCM2290_MASTER_SDCC_1, 591 .name = "mas_sdcc_1", 592 .buswidth = 8, 593 .qos.ap_owned = true, 594 .qos.qos_port = 17, 595 .qos.qos_mode = NOC_QOS_MODE_FIXED, 596 .qos.areq_prio = 2, 597 .mas_rpm_id = 33, 598 .slv_rpm_id = -1, 599 .num_links = ARRAY_SIZE(mas_sdcc_1_links), 600 .links = mas_sdcc_1_links, 601 }; 602 603 static const u16 mas_sdcc_2_links[] = { 604 QCM2290_SLAVE_ANOC_SNOC, 605 }; 606 607 static struct qcom_icc_node mas_sdcc_2 = { 608 .id = QCM2290_MASTER_SDCC_2, 609 .name = "mas_sdcc_2", 610 .buswidth = 8, 611 .qos.ap_owned = true, 612 .qos.qos_port = 23, 613 .qos.qos_mode = NOC_QOS_MODE_FIXED, 614 .qos.areq_prio = 2, 615 .mas_rpm_id = 35, 616 .slv_rpm_id = -1, 617 .num_links = ARRAY_SIZE(mas_sdcc_2_links), 618 .links = mas_sdcc_2_links, 619 }; 620 621 static const u16 mas_qpic_links[] = { 622 QCM2290_SLAVE_ANOC_SNOC, 623 }; 624 625 static struct qcom_icc_node mas_qpic = { 626 .id = QCM2290_MASTER_QPIC, 627 .name = "mas_qpic", 628 .buswidth = 4, 629 .qos.ap_owned = true, 630 .qos.qos_port = 1, 631 .qos.qos_mode = NOC_QOS_MODE_FIXED, 632 .qos.areq_prio = 2, 633 .mas_rpm_id = 58, 634 .slv_rpm_id = -1, 635 .num_links = ARRAY_SIZE(mas_qpic_links), 636 .links = mas_qpic_links, 637 }; 638 639 static const u16 mas_usb3_0_links[] = { 640 QCM2290_SLAVE_ANOC_SNOC, 641 }; 642 643 static struct qcom_icc_node mas_usb3_0 = { 644 .id = QCM2290_MASTER_USB3_0, 645 .name = "mas_usb3_0", 646 .buswidth = 8, 647 .qos.ap_owned = true, 648 .qos.qos_port = 24, 649 .qos.qos_mode = NOC_QOS_MODE_FIXED, 650 .qos.areq_prio = 2, 651 .mas_rpm_id = 32, 652 .slv_rpm_id = -1, 653 .num_links = ARRAY_SIZE(mas_usb3_0_links), 654 .links = mas_usb3_0_links, 655 }; 656 657 static const u16 mas_gfx3d_links[] = { 658 QCM2290_SLAVE_EBI1, 659 }; 660 661 static struct qcom_icc_node mas_gfx3d = { 662 .id = QCM2290_MASTER_GFX3D, 663 .name = "mas_gfx3d", 664 .buswidth = 32, 665 .qos.ap_owned = true, 666 .qos.qos_port = 1, 667 .qos.qos_mode = NOC_QOS_MODE_FIXED, 668 .qos.prio_level = 0, 669 .qos.areq_prio = 0, 670 .mas_rpm_id = 6, 671 .slv_rpm_id = -1, 672 .num_links = ARRAY_SIZE(mas_gfx3d_links), 673 .links = mas_gfx3d_links, 674 }; 675 676 /* Slave nodes */ 677 static struct qcom_icc_node slv_ebi1 = { 678 .name = "slv_ebi1", 679 .id = QCM2290_SLAVE_EBI1, 680 .buswidth = 4, 681 .channels = 2, 682 .mas_rpm_id = -1, 683 .slv_rpm_id = 0, 684 }; 685 686 static const u16 slv_bimc_snoc_links[] = { 687 QCM2290_MASTER_BIMC_SNOC, 688 }; 689 690 static struct qcom_icc_node slv_bimc_snoc = { 691 .name = "slv_bimc_snoc", 692 .id = QCM2290_SLAVE_BIMC_SNOC, 693 .buswidth = 8, 694 .mas_rpm_id = -1, 695 .slv_rpm_id = 2, 696 .num_links = ARRAY_SIZE(slv_bimc_snoc_links), 697 .links = slv_bimc_snoc_links, 698 }; 699 700 static struct qcom_icc_node slv_bimc_cfg = { 701 .name = "slv_bimc_cfg", 702 .id = QCM2290_SLAVE_BIMC_CFG, 703 .buswidth = 4, 704 .qos.ap_owned = true, 705 .qos.qos_mode = NOC_QOS_MODE_INVALID, 706 .mas_rpm_id = -1, 707 .slv_rpm_id = 56, 708 }; 709 710 static struct qcom_icc_node slv_camera_nrt_throttle_cfg = { 711 .name = "slv_camera_nrt_throttle_cfg", 712 .id = QCM2290_SLAVE_CAMERA_NRT_THROTTLE_CFG, 713 .buswidth = 4, 714 .qos.ap_owned = true, 715 .qos.qos_mode = NOC_QOS_MODE_INVALID, 716 .mas_rpm_id = -1, 717 .slv_rpm_id = 271, 718 }; 719 720 static struct qcom_icc_node slv_camera_rt_throttle_cfg = { 721 .name = "slv_camera_rt_throttle_cfg", 722 .id = QCM2290_SLAVE_CAMERA_RT_THROTTLE_CFG, 723 .buswidth = 4, 724 .qos.ap_owned = true, 725 .qos.qos_mode = NOC_QOS_MODE_INVALID, 726 .mas_rpm_id = -1, 727 .slv_rpm_id = 279, 728 }; 729 730 static struct qcom_icc_node slv_camera_cfg = { 731 .name = "slv_camera_cfg", 732 .id = QCM2290_SLAVE_CAMERA_CFG, 733 .buswidth = 4, 734 .qos.ap_owned = true, 735 .qos.qos_mode = NOC_QOS_MODE_INVALID, 736 .mas_rpm_id = -1, 737 .slv_rpm_id = 3, 738 }; 739 740 static struct qcom_icc_node slv_clk_ctl = { 741 .name = "slv_clk_ctl", 742 .id = QCM2290_SLAVE_CLK_CTL, 743 .buswidth = 4, 744 .qos.ap_owned = true, 745 .qos.qos_mode = NOC_QOS_MODE_INVALID, 746 .mas_rpm_id = -1, 747 .slv_rpm_id = 47, 748 }; 749 750 static struct qcom_icc_node slv_crypto_0_cfg = { 751 .name = "slv_crypto_0_cfg", 752 .id = QCM2290_SLAVE_CRYPTO_0_CFG, 753 .buswidth = 4, 754 .qos.ap_owned = true, 755 .qos.qos_mode = NOC_QOS_MODE_INVALID, 756 .mas_rpm_id = -1, 757 .slv_rpm_id = 52, 758 }; 759 760 static struct qcom_icc_node slv_display_cfg = { 761 .name = "slv_display_cfg", 762 .id = QCM2290_SLAVE_DISPLAY_CFG, 763 .buswidth = 4, 764 .qos.ap_owned = true, 765 .qos.qos_mode = NOC_QOS_MODE_INVALID, 766 .mas_rpm_id = -1, 767 .slv_rpm_id = 4, 768 }; 769 770 static struct qcom_icc_node slv_display_throttle_cfg = { 771 .name = "slv_display_throttle_cfg", 772 .id = QCM2290_SLAVE_DISPLAY_THROTTLE_CFG, 773 .buswidth = 4, 774 .qos.ap_owned = true, 775 .qos.qos_mode = NOC_QOS_MODE_INVALID, 776 .mas_rpm_id = -1, 777 .slv_rpm_id = 156, 778 }; 779 780 static struct qcom_icc_node slv_gpu_cfg = { 781 .name = "slv_gpu_cfg", 782 .id = QCM2290_SLAVE_GPU_CFG, 783 .buswidth = 8, 784 .qos.ap_owned = true, 785 .qos.qos_mode = NOC_QOS_MODE_INVALID, 786 .mas_rpm_id = -1, 787 .slv_rpm_id = 275, 788 }; 789 790 static struct qcom_icc_node slv_hwkm = { 791 .name = "slv_hwkm", 792 .id = QCM2290_SLAVE_HWKM, 793 .buswidth = 4, 794 .qos.ap_owned = true, 795 .qos.qos_mode = NOC_QOS_MODE_INVALID, 796 .mas_rpm_id = -1, 797 .slv_rpm_id = 280, 798 }; 799 800 static struct qcom_icc_node slv_imem_cfg = { 801 .name = "slv_imem_cfg", 802 .id = QCM2290_SLAVE_IMEM_CFG, 803 .buswidth = 4, 804 .qos.ap_owned = true, 805 .qos.qos_mode = NOC_QOS_MODE_INVALID, 806 .mas_rpm_id = -1, 807 .slv_rpm_id = 54, 808 }; 809 810 static struct qcom_icc_node slv_ipa_cfg = { 811 .name = "slv_ipa_cfg", 812 .id = QCM2290_SLAVE_IPA_CFG, 813 .buswidth = 4, 814 .qos.ap_owned = true, 815 .qos.qos_mode = NOC_QOS_MODE_INVALID, 816 .mas_rpm_id = -1, 817 .slv_rpm_id = 183, 818 }; 819 820 static struct qcom_icc_node slv_lpass = { 821 .name = "slv_lpass", 822 .id = QCM2290_SLAVE_LPASS, 823 .buswidth = 4, 824 .qos.ap_owned = true, 825 .qos.qos_mode = NOC_QOS_MODE_INVALID, 826 .mas_rpm_id = -1, 827 .slv_rpm_id = 21, 828 }; 829 830 static struct qcom_icc_node slv_message_ram = { 831 .name = "slv_message_ram", 832 .id = QCM2290_SLAVE_MESSAGE_RAM, 833 .buswidth = 4, 834 .qos.ap_owned = true, 835 .qos.qos_mode = NOC_QOS_MODE_INVALID, 836 .mas_rpm_id = -1, 837 .slv_rpm_id = 55, 838 }; 839 840 static struct qcom_icc_node slv_pdm = { 841 .name = "slv_pdm", 842 .id = QCM2290_SLAVE_PDM, 843 .buswidth = 4, 844 .qos.ap_owned = true, 845 .qos.qos_mode = NOC_QOS_MODE_INVALID, 846 .mas_rpm_id = -1, 847 .slv_rpm_id = 41, 848 }; 849 850 static struct qcom_icc_node slv_pimem_cfg = { 851 .name = "slv_pimem_cfg", 852 .id = QCM2290_SLAVE_PIMEM_CFG, 853 .buswidth = 4, 854 .qos.ap_owned = true, 855 .qos.qos_mode = NOC_QOS_MODE_INVALID, 856 .mas_rpm_id = -1, 857 .slv_rpm_id = 167, 858 }; 859 860 static struct qcom_icc_node slv_pka_wrapper = { 861 .name = "slv_pka_wrapper", 862 .id = QCM2290_SLAVE_PKA_WRAPPER, 863 .buswidth = 4, 864 .qos.ap_owned = true, 865 .qos.qos_mode = NOC_QOS_MODE_INVALID, 866 .mas_rpm_id = -1, 867 .slv_rpm_id = 281, 868 }; 869 870 static struct qcom_icc_node slv_pmic_arb = { 871 .name = "slv_pmic_arb", 872 .id = QCM2290_SLAVE_PMIC_ARB, 873 .buswidth = 4, 874 .qos.ap_owned = true, 875 .qos.qos_mode = NOC_QOS_MODE_INVALID, 876 .mas_rpm_id = -1, 877 .slv_rpm_id = 59, 878 }; 879 880 static struct qcom_icc_node slv_prng = { 881 .name = "slv_prng", 882 .id = QCM2290_SLAVE_PRNG, 883 .buswidth = 4, 884 .qos.ap_owned = true, 885 .qos.qos_mode = NOC_QOS_MODE_INVALID, 886 .mas_rpm_id = -1, 887 .slv_rpm_id = 44, 888 }; 889 890 static struct qcom_icc_node slv_qdss_cfg = { 891 .name = "slv_qdss_cfg", 892 .id = QCM2290_SLAVE_QDSS_CFG, 893 .buswidth = 4, 894 .qos.ap_owned = true, 895 .qos.qos_mode = NOC_QOS_MODE_INVALID, 896 .mas_rpm_id = -1, 897 .slv_rpm_id = 63, 898 }; 899 900 static struct qcom_icc_node slv_qm_cfg = { 901 .name = "slv_qm_cfg", 902 .id = QCM2290_SLAVE_QM_CFG, 903 .buswidth = 4, 904 .qos.ap_owned = true, 905 .qos.qos_mode = NOC_QOS_MODE_INVALID, 906 .mas_rpm_id = -1, 907 .slv_rpm_id = 212, 908 }; 909 910 static struct qcom_icc_node slv_qm_mpu_cfg = { 911 .name = "slv_qm_mpu_cfg", 912 .id = QCM2290_SLAVE_QM_MPU_CFG, 913 .buswidth = 4, 914 .qos.ap_owned = true, 915 .qos.qos_mode = NOC_QOS_MODE_INVALID, 916 .mas_rpm_id = -1, 917 .slv_rpm_id = 231, 918 }; 919 920 static struct qcom_icc_node slv_qpic = { 921 .name = "slv_qpic", 922 .id = QCM2290_SLAVE_QPIC, 923 .buswidth = 4, 924 .qos.ap_owned = true, 925 .qos.qos_mode = NOC_QOS_MODE_INVALID, 926 .mas_rpm_id = -1, 927 .slv_rpm_id = 80, 928 }; 929 930 static struct qcom_icc_node slv_qup_0 = { 931 .name = "slv_qup_0", 932 .id = QCM2290_SLAVE_QUP_0, 933 .buswidth = 4, 934 .qos.ap_owned = true, 935 .qos.qos_mode = NOC_QOS_MODE_INVALID, 936 .mas_rpm_id = -1, 937 .slv_rpm_id = 261, 938 }; 939 940 static struct qcom_icc_node slv_sdcc_1 = { 941 .name = "slv_sdcc_1", 942 .id = QCM2290_SLAVE_SDCC_1, 943 .buswidth = 4, 944 .qos.ap_owned = true, 945 .qos.qos_mode = NOC_QOS_MODE_INVALID, 946 .mas_rpm_id = -1, 947 .slv_rpm_id = 31, 948 }; 949 950 static struct qcom_icc_node slv_sdcc_2 = { 951 .name = "slv_sdcc_2", 952 .id = QCM2290_SLAVE_SDCC_2, 953 .buswidth = 4, 954 .qos.ap_owned = true, 955 .qos.qos_mode = NOC_QOS_MODE_INVALID, 956 .mas_rpm_id = -1, 957 .slv_rpm_id = 33, 958 }; 959 960 static const u16 slv_snoc_cfg_links[] = { 961 QCM2290_MASTER_SNOC_CFG, 962 }; 963 964 static struct qcom_icc_node slv_snoc_cfg = { 965 .name = "slv_snoc_cfg", 966 .id = QCM2290_SLAVE_SNOC_CFG, 967 .buswidth = 4, 968 .qos.ap_owned = true, 969 .qos.qos_mode = NOC_QOS_MODE_INVALID, 970 .mas_rpm_id = -1, 971 .slv_rpm_id = 70, 972 .num_links = ARRAY_SIZE(slv_snoc_cfg_links), 973 .links = slv_snoc_cfg_links, 974 }; 975 976 static struct qcom_icc_node slv_tcsr = { 977 .name = "slv_tcsr", 978 .id = QCM2290_SLAVE_TCSR, 979 .buswidth = 4, 980 .qos.ap_owned = true, 981 .qos.qos_mode = NOC_QOS_MODE_INVALID, 982 .mas_rpm_id = -1, 983 .slv_rpm_id = 50, 984 }; 985 986 static struct qcom_icc_node slv_usb3 = { 987 .name = "slv_usb3", 988 .id = QCM2290_SLAVE_USB3, 989 .buswidth = 4, 990 .qos.ap_owned = true, 991 .qos.qos_mode = NOC_QOS_MODE_INVALID, 992 .mas_rpm_id = -1, 993 .slv_rpm_id = 22, 994 }; 995 996 static struct qcom_icc_node slv_venus_cfg = { 997 .name = "slv_venus_cfg", 998 .id = QCM2290_SLAVE_VENUS_CFG, 999 .buswidth = 4, 1000 .qos.ap_owned = true, 1001 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1002 .mas_rpm_id = -1, 1003 .slv_rpm_id = 10, 1004 }; 1005 1006 static struct qcom_icc_node slv_venus_throttle_cfg = { 1007 .name = "slv_venus_throttle_cfg", 1008 .id = QCM2290_SLAVE_VENUS_THROTTLE_CFG, 1009 .buswidth = 4, 1010 .qos.ap_owned = true, 1011 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1012 .mas_rpm_id = -1, 1013 .slv_rpm_id = 178, 1014 }; 1015 1016 static struct qcom_icc_node slv_vsense_ctrl_cfg = { 1017 .name = "slv_vsense_ctrl_cfg", 1018 .id = QCM2290_SLAVE_VSENSE_CTRL_CFG, 1019 .buswidth = 4, 1020 .qos.ap_owned = true, 1021 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1022 .mas_rpm_id = -1, 1023 .slv_rpm_id = 263, 1024 }; 1025 1026 static struct qcom_icc_node slv_service_cnoc = { 1027 .name = "slv_service_cnoc", 1028 .id = QCM2290_SLAVE_SERVICE_CNOC, 1029 .buswidth = 4, 1030 .qos.ap_owned = true, 1031 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1032 .mas_rpm_id = -1, 1033 .slv_rpm_id = 76, 1034 }; 1035 1036 static struct qcom_icc_node slv_qup_core_0 = { 1037 .name = "slv_qup_core_0", 1038 .id = QCM2290_SLAVE_QUP_CORE_0, 1039 .buswidth = 4, 1040 .qos.ap_owned = true, 1041 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1042 .mas_rpm_id = -1, 1043 .slv_rpm_id = 264, 1044 }; 1045 1046 static const u16 slv_snoc_bimc_nrt_links[] = { 1047 QCM2290_MASTER_SNOC_BIMC_NRT, 1048 }; 1049 1050 static struct qcom_icc_node slv_snoc_bimc_nrt = { 1051 .name = "slv_snoc_bimc_nrt", 1052 .id = QCM2290_SLAVE_SNOC_BIMC_NRT, 1053 .buswidth = 16, 1054 .qos.ap_owned = true, 1055 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1056 .mas_rpm_id = -1, 1057 .slv_rpm_id = 259, 1058 .num_links = ARRAY_SIZE(slv_snoc_bimc_nrt_links), 1059 .links = slv_snoc_bimc_nrt_links, 1060 }; 1061 1062 static const u16 slv_snoc_bimc_rt_links[] = { 1063 QCM2290_MASTER_SNOC_BIMC_RT, 1064 }; 1065 1066 static struct qcom_icc_node slv_snoc_bimc_rt = { 1067 .name = "slv_snoc_bimc_rt", 1068 .id = QCM2290_SLAVE_SNOC_BIMC_RT, 1069 .buswidth = 16, 1070 .qos.ap_owned = true, 1071 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1072 .mas_rpm_id = -1, 1073 .slv_rpm_id = 260, 1074 .num_links = ARRAY_SIZE(slv_snoc_bimc_rt_links), 1075 .links = slv_snoc_bimc_rt_links, 1076 }; 1077 1078 static struct qcom_icc_node slv_appss = { 1079 .name = "slv_appss", 1080 .id = QCM2290_SLAVE_APPSS, 1081 .buswidth = 8, 1082 .qos.ap_owned = true, 1083 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1084 .mas_rpm_id = -1, 1085 .slv_rpm_id = 20, 1086 }; 1087 1088 static const u16 slv_snoc_cnoc_links[] = { 1089 QCM2290_MASTER_SNOC_CNOC, 1090 }; 1091 1092 static struct qcom_icc_node slv_snoc_cnoc = { 1093 .name = "slv_snoc_cnoc", 1094 .id = QCM2290_SLAVE_SNOC_CNOC, 1095 .buswidth = 8, 1096 .mas_rpm_id = -1, 1097 .slv_rpm_id = 25, 1098 .num_links = ARRAY_SIZE(slv_snoc_cnoc_links), 1099 .links = slv_snoc_cnoc_links, 1100 }; 1101 1102 static struct qcom_icc_node slv_imem = { 1103 .name = "slv_imem", 1104 .id = QCM2290_SLAVE_IMEM, 1105 .buswidth = 8, 1106 .mas_rpm_id = -1, 1107 .slv_rpm_id = 26, 1108 }; 1109 1110 static struct qcom_icc_node slv_pimem = { 1111 .name = "slv_pimem", 1112 .id = QCM2290_SLAVE_PIMEM, 1113 .buswidth = 8, 1114 .qos.ap_owned = true, 1115 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1116 .mas_rpm_id = -1, 1117 .slv_rpm_id = 166, 1118 }; 1119 1120 static const u16 slv_snoc_bimc_links[] = { 1121 QCM2290_MASTER_SNOC_BIMC, 1122 }; 1123 1124 static struct qcom_icc_node slv_snoc_bimc = { 1125 .name = "slv_snoc_bimc", 1126 .id = QCM2290_SLAVE_SNOC_BIMC, 1127 .buswidth = 16, 1128 .mas_rpm_id = -1, 1129 .slv_rpm_id = 24, 1130 .num_links = ARRAY_SIZE(slv_snoc_bimc_links), 1131 .links = slv_snoc_bimc_links, 1132 }; 1133 1134 static struct qcom_icc_node slv_service_snoc = { 1135 .name = "slv_service_snoc", 1136 .id = QCM2290_SLAVE_SERVICE_SNOC, 1137 .buswidth = 4, 1138 .qos.ap_owned = true, 1139 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1140 .mas_rpm_id = -1, 1141 .slv_rpm_id = 29, 1142 }; 1143 1144 static struct qcom_icc_node slv_qdss_stm = { 1145 .name = "slv_qdss_stm", 1146 .id = QCM2290_SLAVE_QDSS_STM, 1147 .buswidth = 4, 1148 .mas_rpm_id = -1, 1149 .slv_rpm_id = 30, 1150 }; 1151 1152 static struct qcom_icc_node slv_tcu = { 1153 .name = "slv_tcu", 1154 .id = QCM2290_SLAVE_TCU, 1155 .buswidth = 8, 1156 .qos.ap_owned = true, 1157 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1158 .mas_rpm_id = -1, 1159 .slv_rpm_id = 133, 1160 }; 1161 1162 static const u16 slv_anoc_snoc_links[] = { 1163 QCM2290_MASTER_ANOC_SNOC, 1164 }; 1165 1166 static struct qcom_icc_node slv_anoc_snoc = { 1167 .name = "slv_anoc_snoc", 1168 .id = QCM2290_SLAVE_ANOC_SNOC, 1169 .buswidth = 16, 1170 .mas_rpm_id = -1, 1171 .slv_rpm_id = 141, 1172 .num_links = ARRAY_SIZE(slv_anoc_snoc_links), 1173 .links = slv_anoc_snoc_links, 1174 }; 1175 1176 /* NoC descriptors */ 1177 static struct qcom_icc_node * const qcm2290_bimc_nodes[] = { 1178 [MASTER_APPSS_PROC] = &mas_appss_proc, 1179 [MASTER_SNOC_BIMC_RT] = &mas_snoc_bimc_rt, 1180 [MASTER_SNOC_BIMC_NRT] = &mas_snoc_bimc_nrt, 1181 [MASTER_SNOC_BIMC] = &mas_snoc_bimc, 1182 [MASTER_TCU_0] = &mas_tcu_0, 1183 [MASTER_GFX3D] = &mas_gfx3d, 1184 [SLAVE_EBI1] = &slv_ebi1, 1185 [SLAVE_BIMC_SNOC] = &slv_bimc_snoc, 1186 }; 1187 1188 static const struct regmap_config qcm2290_bimc_regmap_config = { 1189 .reg_bits = 32, 1190 .reg_stride = 4, 1191 .val_bits = 32, 1192 .max_register = 0x80000, 1193 .fast_io = true, 1194 }; 1195 1196 static const struct qcom_icc_desc qcm2290_bimc = { 1197 .type = QCOM_ICC_BIMC, 1198 .nodes = qcm2290_bimc_nodes, 1199 .num_nodes = ARRAY_SIZE(qcm2290_bimc_nodes), 1200 .bus_clk_desc = &bimc_clk, 1201 .regmap_cfg = &qcm2290_bimc_regmap_config, 1202 .keep_alive = true, 1203 /* M_REG_BASE() in vendor msm_bus_bimc_adhoc driver */ 1204 .qos_offset = 0x8000, 1205 .ab_coeff = 153, 1206 }; 1207 1208 static struct qcom_icc_node * const qcm2290_cnoc_nodes[] = { 1209 [MASTER_SNOC_CNOC] = &mas_snoc_cnoc, 1210 [MASTER_QDSS_DAP] = &mas_qdss_dap, 1211 [SLAVE_BIMC_CFG] = &slv_bimc_cfg, 1212 [SLAVE_CAMERA_NRT_THROTTLE_CFG] = &slv_camera_nrt_throttle_cfg, 1213 [SLAVE_CAMERA_RT_THROTTLE_CFG] = &slv_camera_rt_throttle_cfg, 1214 [SLAVE_CAMERA_CFG] = &slv_camera_cfg, 1215 [SLAVE_CLK_CTL] = &slv_clk_ctl, 1216 [SLAVE_CRYPTO_0_CFG] = &slv_crypto_0_cfg, 1217 [SLAVE_DISPLAY_CFG] = &slv_display_cfg, 1218 [SLAVE_DISPLAY_THROTTLE_CFG] = &slv_display_throttle_cfg, 1219 [SLAVE_GPU_CFG] = &slv_gpu_cfg, 1220 [SLAVE_HWKM] = &slv_hwkm, 1221 [SLAVE_IMEM_CFG] = &slv_imem_cfg, 1222 [SLAVE_IPA_CFG] = &slv_ipa_cfg, 1223 [SLAVE_LPASS] = &slv_lpass, 1224 [SLAVE_MESSAGE_RAM] = &slv_message_ram, 1225 [SLAVE_PDM] = &slv_pdm, 1226 [SLAVE_PIMEM_CFG] = &slv_pimem_cfg, 1227 [SLAVE_PKA_WRAPPER] = &slv_pka_wrapper, 1228 [SLAVE_PMIC_ARB] = &slv_pmic_arb, 1229 [SLAVE_PRNG] = &slv_prng, 1230 [SLAVE_QDSS_CFG] = &slv_qdss_cfg, 1231 [SLAVE_QM_CFG] = &slv_qm_cfg, 1232 [SLAVE_QM_MPU_CFG] = &slv_qm_mpu_cfg, 1233 [SLAVE_QPIC] = &slv_qpic, 1234 [SLAVE_QUP_0] = &slv_qup_0, 1235 [SLAVE_SDCC_1] = &slv_sdcc_1, 1236 [SLAVE_SDCC_2] = &slv_sdcc_2, 1237 [SLAVE_SNOC_CFG] = &slv_snoc_cfg, 1238 [SLAVE_TCSR] = &slv_tcsr, 1239 [SLAVE_USB3] = &slv_usb3, 1240 [SLAVE_VENUS_CFG] = &slv_venus_cfg, 1241 [SLAVE_VENUS_THROTTLE_CFG] = &slv_venus_throttle_cfg, 1242 [SLAVE_VSENSE_CTRL_CFG] = &slv_vsense_ctrl_cfg, 1243 [SLAVE_SERVICE_CNOC] = &slv_service_cnoc, 1244 }; 1245 1246 static const struct regmap_config qcm2290_cnoc_regmap_config = { 1247 .reg_bits = 32, 1248 .reg_stride = 4, 1249 .val_bits = 32, 1250 .max_register = 0x8200, 1251 .fast_io = true, 1252 }; 1253 1254 static const struct qcom_icc_desc qcm2290_cnoc = { 1255 .type = QCOM_ICC_NOC, 1256 .nodes = qcm2290_cnoc_nodes, 1257 .num_nodes = ARRAY_SIZE(qcm2290_cnoc_nodes), 1258 .bus_clk_desc = &bus_1_clk, 1259 .regmap_cfg = &qcm2290_cnoc_regmap_config, 1260 .keep_alive = true, 1261 }; 1262 1263 static struct qcom_icc_node * const qcm2290_snoc_nodes[] = { 1264 [MASTER_CRYPTO_CORE0] = &mas_crypto_core0, 1265 [MASTER_SNOC_CFG] = &mas_snoc_cfg, 1266 [MASTER_TIC] = &mas_tic, 1267 [MASTER_ANOC_SNOC] = &mas_anoc_snoc, 1268 [MASTER_BIMC_SNOC] = &mas_bimc_snoc, 1269 [MASTER_PIMEM] = &mas_pimem, 1270 [MASTER_QDSS_BAM] = &mas_qdss_bam, 1271 [MASTER_QUP_0] = &mas_qup_0, 1272 [MASTER_IPA] = &mas_ipa, 1273 [MASTER_QDSS_ETR] = &mas_qdss_etr, 1274 [MASTER_SDCC_1] = &mas_sdcc_1, 1275 [MASTER_SDCC_2] = &mas_sdcc_2, 1276 [MASTER_QPIC] = &mas_qpic, 1277 [MASTER_USB3_0] = &mas_usb3_0, 1278 [SLAVE_APPSS] = &slv_appss, 1279 [SLAVE_SNOC_CNOC] = &slv_snoc_cnoc, 1280 [SLAVE_IMEM] = &slv_imem, 1281 [SLAVE_PIMEM] = &slv_pimem, 1282 [SLAVE_SNOC_BIMC] = &slv_snoc_bimc, 1283 [SLAVE_SERVICE_SNOC] = &slv_service_snoc, 1284 [SLAVE_QDSS_STM] = &slv_qdss_stm, 1285 [SLAVE_TCU] = &slv_tcu, 1286 [SLAVE_ANOC_SNOC] = &slv_anoc_snoc, 1287 }; 1288 1289 static const struct regmap_config qcm2290_snoc_regmap_config = { 1290 .reg_bits = 32, 1291 .reg_stride = 4, 1292 .val_bits = 32, 1293 .max_register = 0x60200, 1294 .fast_io = true, 1295 }; 1296 1297 static const struct qcom_icc_desc qcm2290_snoc = { 1298 .type = QCOM_ICC_QNOC, 1299 .nodes = qcm2290_snoc_nodes, 1300 .num_nodes = ARRAY_SIZE(qcm2290_snoc_nodes), 1301 .bus_clk_desc = &bus_2_clk, 1302 .regmap_cfg = &qcm2290_snoc_regmap_config, 1303 .keep_alive = true, 1304 /* Vendor DT node fab-sys_noc property 'qcom,base-offset' */ 1305 .qos_offset = 0x15000, 1306 }; 1307 1308 static struct qcom_icc_node * const qcm2290_qup_virt_nodes[] = { 1309 [MASTER_QUP_CORE_0] = &mas_qup_core_0, 1310 [SLAVE_QUP_CORE_0] = &slv_qup_core_0 1311 }; 1312 1313 static const struct qcom_icc_desc qcm2290_qup_virt = { 1314 .type = QCOM_ICC_QNOC, 1315 .nodes = qcm2290_qup_virt_nodes, 1316 .num_nodes = ARRAY_SIZE(qcm2290_qup_virt_nodes), 1317 .bus_clk_desc = &qup_clk, 1318 .keep_alive = true, 1319 }; 1320 1321 static struct qcom_icc_node * const qcm2290_mmnrt_virt_nodes[] = { 1322 [MASTER_CAMNOC_SF] = &mas_camnoc_sf, 1323 [MASTER_VIDEO_P0] = &mas_video_p0, 1324 [MASTER_VIDEO_PROC] = &mas_video_proc, 1325 [SLAVE_SNOC_BIMC_NRT] = &slv_snoc_bimc_nrt, 1326 }; 1327 1328 static const struct qcom_icc_desc qcm2290_mmnrt_virt = { 1329 .type = QCOM_ICC_QNOC, 1330 .nodes = qcm2290_mmnrt_virt_nodes, 1331 .num_nodes = ARRAY_SIZE(qcm2290_mmnrt_virt_nodes), 1332 .bus_clk_desc = &mmaxi_0_clk, 1333 .regmap_cfg = &qcm2290_snoc_regmap_config, 1334 .keep_alive = true, 1335 .qos_offset = 0x15000, 1336 .ab_coeff = 142, 1337 }; 1338 1339 static struct qcom_icc_node * const qcm2290_mmrt_virt_nodes[] = { 1340 [MASTER_CAMNOC_HF] = &mas_camnoc_hf, 1341 [MASTER_MDP0] = &mas_mdp0, 1342 [SLAVE_SNOC_BIMC_RT] = &slv_snoc_bimc_rt, 1343 }; 1344 1345 static const struct qcom_icc_desc qcm2290_mmrt_virt = { 1346 .type = QCOM_ICC_QNOC, 1347 .nodes = qcm2290_mmrt_virt_nodes, 1348 .num_nodes = ARRAY_SIZE(qcm2290_mmrt_virt_nodes), 1349 .bus_clk_desc = &mmaxi_1_clk, 1350 .regmap_cfg = &qcm2290_snoc_regmap_config, 1351 .keep_alive = true, 1352 .qos_offset = 0x15000, 1353 .ab_coeff = 139, 1354 }; 1355 1356 static const struct of_device_id qcm2290_noc_of_match[] = { 1357 { .compatible = "qcom,qcm2290-bimc", .data = &qcm2290_bimc }, 1358 { .compatible = "qcom,qcm2290-cnoc", .data = &qcm2290_cnoc }, 1359 { .compatible = "qcom,qcm2290-snoc", .data = &qcm2290_snoc }, 1360 { .compatible = "qcom,qcm2290-qup-virt", .data = &qcm2290_qup_virt }, 1361 { .compatible = "qcom,qcm2290-mmrt-virt", .data = &qcm2290_mmrt_virt }, 1362 { .compatible = "qcom,qcm2290-mmnrt-virt", .data = &qcm2290_mmnrt_virt }, 1363 { }, 1364 }; 1365 MODULE_DEVICE_TABLE(of, qcm2290_noc_of_match); 1366 1367 static struct platform_driver qcm2290_noc_driver = { 1368 .probe = qnoc_probe, 1369 .remove = qnoc_remove, 1370 .driver = { 1371 .name = "qnoc-qcm2290", 1372 .of_match_table = qcm2290_noc_of_match, 1373 .sync_state = icc_sync_state, 1374 }, 1375 }; 1376 module_platform_driver(qcm2290_noc_driver); 1377 1378 MODULE_DESCRIPTION("Qualcomm QCM2290 NoC driver"); 1379 MODULE_LICENSE("GPL v2"); 1380