1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/args.h> 8 #include <linux/bitfield.h> 9 #include <linux/clk.h> 10 #include <linux/interconnect-provider.h> 11 #include <linux/io.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/platform_device.h> 16 17 #include <dt-bindings/interconnect/qcom,osm-l3.h> 18 19 #define LUT_MAX_ENTRIES 40U 20 #define LUT_SRC GENMASK(31, 30) 21 #define LUT_L_VAL GENMASK(7, 0) 22 #define CLK_HW_DIV 2 23 24 /* OSM Register offsets */ 25 #define REG_ENABLE 0x0 26 #define OSM_LUT_ROW_SIZE 32 27 #define OSM_REG_FREQ_LUT 0x110 28 #define OSM_REG_PERF_STATE 0x920 29 30 /* EPSS Register offsets */ 31 #define EPSS_LUT_ROW_SIZE 4 32 #define EPSS_REG_L3_VOTE 0x90 33 #define EPSS_REG_FREQ_LUT 0x100 34 #define EPSS_REG_PERF_STATE 0x320 35 36 #define to_osm_l3_provider(_provider) \ 37 container_of(_provider, struct qcom_osm_l3_icc_provider, provider) 38 39 struct qcom_osm_l3_icc_provider { 40 void __iomem *base; 41 unsigned int max_state; 42 unsigned int reg_perf_state; 43 unsigned long lut_tables[LUT_MAX_ENTRIES]; 44 struct icc_provider provider; 45 }; 46 47 /** 48 * struct qcom_osm_l3_node - Qualcomm specific interconnect nodes 49 * @name: the node name used in debugfs 50 * @buswidth: width of the interconnect between a node and the bus 51 */ 52 struct qcom_osm_l3_node { 53 const char *name; 54 u16 buswidth; 55 }; 56 57 struct qcom_osm_l3_desc { 58 const struct qcom_osm_l3_node * const *nodes; 59 size_t num_nodes; 60 unsigned int lut_row_size; 61 unsigned int reg_freq_lut; 62 unsigned int reg_perf_state; 63 unsigned int lut_max_entries; 64 }; 65 66 #define DEFINE_QNODE(_name, _buswidth) \ 67 static const struct qcom_osm_l3_node _name = { \ 68 .name = #_name, \ 69 .buswidth = _buswidth, \ 70 } 71 72 DEFINE_QNODE(osm_l3_slave, 16); 73 DEFINE_QNODE(osm_l3_master, 16); 74 75 static const struct qcom_osm_l3_node * const osm_l3_nodes[] = { 76 [MASTER_OSM_L3_APPS] = &osm_l3_master, 77 [SLAVE_OSM_L3] = &osm_l3_slave, 78 }; 79 80 DEFINE_QNODE(epss_l3_slave, 32); 81 DEFINE_QNODE(epss_l3_master, 32); 82 83 static const struct qcom_osm_l3_node * const epss_l3_nodes[] = { 84 [MASTER_EPSS_L3_APPS] = &epss_l3_master, 85 [SLAVE_EPSS_L3_SHARED] = &epss_l3_slave, 86 }; 87 88 static const struct qcom_osm_l3_desc osm_l3 = { 89 .nodes = osm_l3_nodes, 90 .num_nodes = ARRAY_SIZE(osm_l3_nodes), 91 .lut_row_size = OSM_LUT_ROW_SIZE, 92 .reg_freq_lut = OSM_REG_FREQ_LUT, 93 .reg_perf_state = OSM_REG_PERF_STATE, 94 .lut_max_entries = LUT_MAX_ENTRIES, 95 }; 96 97 static const struct qcom_osm_l3_desc epss_l3_perf_state = { 98 .nodes = epss_l3_nodes, 99 .num_nodes = ARRAY_SIZE(epss_l3_nodes), 100 .lut_row_size = EPSS_LUT_ROW_SIZE, 101 .reg_freq_lut = EPSS_REG_FREQ_LUT, 102 .reg_perf_state = EPSS_REG_PERF_STATE, 103 .lut_max_entries = LUT_MAX_ENTRIES, 104 }; 105 106 static const struct qcom_osm_l3_desc shikra_epss_l3_perf_state = { 107 .nodes = epss_l3_nodes, 108 .num_nodes = ARRAY_SIZE(epss_l3_nodes), 109 .lut_row_size = EPSS_LUT_ROW_SIZE, 110 .reg_freq_lut = EPSS_REG_FREQ_LUT, 111 .reg_perf_state = EPSS_REG_PERF_STATE, 112 .lut_max_entries = 12, 113 }; 114 115 static const struct qcom_osm_l3_desc epss_l3_l3_vote = { 116 .nodes = epss_l3_nodes, 117 .num_nodes = ARRAY_SIZE(epss_l3_nodes), 118 .lut_row_size = EPSS_LUT_ROW_SIZE, 119 .reg_freq_lut = EPSS_REG_FREQ_LUT, 120 .reg_perf_state = EPSS_REG_L3_VOTE, 121 .lut_max_entries = LUT_MAX_ENTRIES, 122 }; 123 124 static int qcom_osm_l3_set(struct icc_node *src, struct icc_node *dst) 125 { 126 struct qcom_osm_l3_icc_provider *qp; 127 struct icc_provider *provider; 128 const struct qcom_osm_l3_node *qn; 129 unsigned int index; 130 u64 rate; 131 132 qn = src->data; 133 provider = src->provider; 134 qp = to_osm_l3_provider(provider); 135 136 rate = icc_units_to_bps(dst->peak_bw); 137 do_div(rate, qn->buswidth); 138 139 for (index = 0; index < qp->max_state - 1; index++) { 140 if (qp->lut_tables[index] >= rate) 141 break; 142 } 143 144 writel_relaxed(index, qp->base + qp->reg_perf_state); 145 146 return 0; 147 } 148 149 static void qcom_osm_l3_remove(struct platform_device *pdev) 150 { 151 struct qcom_osm_l3_icc_provider *qp = platform_get_drvdata(pdev); 152 153 icc_provider_deregister(&qp->provider); 154 icc_nodes_remove(&qp->provider); 155 } 156 157 static int qcom_osm_l3_probe(struct platform_device *pdev) 158 { 159 u32 info, src, lval, i, prev_freq = 0, freq; 160 static unsigned long hw_rate, xo_rate; 161 struct qcom_osm_l3_icc_provider *qp; 162 const struct qcom_osm_l3_desc *desc; 163 struct icc_onecell_data *data; 164 struct icc_provider *provider; 165 const struct qcom_osm_l3_node * const *qnodes; 166 struct icc_node *node; 167 size_t num_nodes; 168 struct clk *clk; 169 int ret; 170 171 clk = clk_get(&pdev->dev, "xo"); 172 if (IS_ERR(clk)) 173 return PTR_ERR(clk); 174 175 xo_rate = clk_get_rate(clk); 176 clk_put(clk); 177 178 clk = clk_get(&pdev->dev, "alternate"); 179 if (IS_ERR(clk)) 180 return PTR_ERR(clk); 181 182 hw_rate = clk_get_rate(clk) / CLK_HW_DIV; 183 clk_put(clk); 184 185 qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL); 186 if (!qp) 187 return -ENOMEM; 188 189 qp->base = devm_platform_ioremap_resource(pdev, 0); 190 if (IS_ERR(qp->base)) 191 return PTR_ERR(qp->base); 192 193 /* HW should be in enabled state to proceed */ 194 if (!(readl_relaxed(qp->base + REG_ENABLE) & 0x1)) { 195 dev_err(&pdev->dev, "error hardware not enabled\n"); 196 return -ENODEV; 197 } 198 199 desc = device_get_match_data(&pdev->dev); 200 if (!desc) 201 return -EINVAL; 202 203 qp->reg_perf_state = desc->reg_perf_state; 204 205 for (i = 0; i < desc->lut_max_entries; i++) { 206 info = readl_relaxed(qp->base + desc->reg_freq_lut + 207 i * desc->lut_row_size); 208 src = FIELD_GET(LUT_SRC, info); 209 lval = FIELD_GET(LUT_L_VAL, info); 210 if (src) 211 freq = xo_rate * lval; 212 else 213 freq = hw_rate; 214 215 /* Two of the same frequencies signify end of table */ 216 if (i > 0 && prev_freq == freq) 217 break; 218 219 dev_dbg(&pdev->dev, "index=%d freq=%d\n", i, freq); 220 221 qp->lut_tables[i] = freq; 222 prev_freq = freq; 223 } 224 qp->max_state = i; 225 226 qnodes = desc->nodes; 227 num_nodes = desc->num_nodes; 228 229 data = devm_kzalloc(&pdev->dev, struct_size(data, nodes, num_nodes), GFP_KERNEL); 230 if (!data) 231 return -ENOMEM; 232 data->num_nodes = num_nodes; 233 234 provider = &qp->provider; 235 provider->dev = &pdev->dev; 236 provider->set = qcom_osm_l3_set; 237 provider->aggregate = icc_std_aggregate; 238 provider->xlate = of_icc_xlate_onecell; 239 provider->data = data; 240 241 icc_provider_init(provider); 242 243 /* Create nodes */ 244 for (i = 0; i < num_nodes; i++) { 245 node = icc_node_create_dyn(); 246 247 if (IS_ERR(node)) { 248 ret = PTR_ERR(node); 249 goto err; 250 } 251 252 ret = icc_node_set_name(node, provider, qnodes[i]->name); 253 if (ret) { 254 icc_node_destroy(node->id); 255 goto err; 256 } 257 258 /* Cast away const and add it back in qcom_osm_l3_set() */ 259 node->data = (void *)qnodes[i]; 260 icc_node_add(node, provider); 261 262 data->nodes[i] = node; 263 } 264 265 /* Create link */ 266 icc_link_nodes(data->nodes[MASTER_OSM_L3_APPS], &data->nodes[SLAVE_OSM_L3]); 267 268 ret = icc_provider_register(provider); 269 if (ret) 270 goto err; 271 272 platform_set_drvdata(pdev, qp); 273 274 return 0; 275 err: 276 icc_nodes_remove(provider); 277 278 return ret; 279 } 280 281 static const struct of_device_id osm_l3_of_match[] = { 282 { .compatible = "qcom,epss-l3", .data = &epss_l3_l3_vote }, 283 { .compatible = "qcom,osm-l3", .data = &osm_l3 }, 284 { .compatible = "qcom,sa8775p-epss-l3", .data = &epss_l3_perf_state }, 285 { .compatible = "qcom,sc7180-osm-l3", .data = &osm_l3 }, 286 { .compatible = "qcom,sc7280-epss-l3", .data = &epss_l3_perf_state }, 287 { .compatible = "qcom,sdm845-osm-l3", .data = &osm_l3 }, 288 { .compatible = "qcom,shikra-epss-l3", .data = &shikra_epss_l3_perf_state }, 289 { .compatible = "qcom,sm8150-osm-l3", .data = &osm_l3 }, 290 { .compatible = "qcom,sc8180x-osm-l3", .data = &osm_l3 }, 291 { .compatible = "qcom,sm8250-epss-l3", .data = &epss_l3_perf_state }, 292 { } 293 }; 294 MODULE_DEVICE_TABLE(of, osm_l3_of_match); 295 296 static struct platform_driver osm_l3_driver = { 297 .probe = qcom_osm_l3_probe, 298 .remove = qcom_osm_l3_remove, 299 .driver = { 300 .name = "osm-l3", 301 .of_match_table = osm_l3_of_match, 302 .sync_state = icc_sync_state, 303 }, 304 }; 305 module_platform_driver(osm_l3_driver); 306 307 MODULE_DESCRIPTION("Qualcomm OSM L3 interconnect driver"); 308 MODULE_LICENSE("GPL v2"); 309