1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Qualcomm MSM8996 Network-on-Chip (NoC) QoS driver 4 * 5 * Copyright (c) 2021 Yassine Oudjana <y.oudjana@protonmail.com> 6 */ 7 8 #include <linux/device.h> 9 #include <linux/interconnect-provider.h> 10 #include <linux/io.h> 11 #include <linux/mod_devicetable.h> 12 #include <linux/module.h> 13 #include <linux/platform_device.h> 14 #include <linux/regmap.h> 15 16 #include <dt-bindings/interconnect/qcom,msm8996.h> 17 18 #include "icc-rpm.h" 19 #include "msm8996.h" 20 21 static const char * const mm_intf_clocks[] = { 22 "iface" 23 }; 24 25 static const char * const a0noc_intf_clocks[] = { 26 "aggre0_snoc_axi", 27 "aggre0_cnoc_ahb", 28 "aggre0_noc_mpu_cfg" 29 }; 30 31 static const char * const a2noc_intf_clocks[] = { 32 "aggre2_ufs_axi", 33 "ufs_axi" 34 }; 35 36 static const u16 mas_a0noc_common_links[] = { 37 MSM8996_SLAVE_A0NOC_SNOC 38 }; 39 40 static struct qcom_icc_node mas_pcie_0 = { 41 .name = "mas_pcie_0", 42 .id = MSM8996_MASTER_PCIE_0, 43 .buswidth = 8, 44 .mas_rpm_id = 65, 45 .slv_rpm_id = -1, 46 .qos.ap_owned = true, 47 .qos.qos_mode = NOC_QOS_MODE_FIXED, 48 .qos.areq_prio = 1, 49 .qos.prio_level = 1, 50 .qos.qos_port = 0, 51 .num_links = ARRAY_SIZE(mas_a0noc_common_links), 52 .links = mas_a0noc_common_links 53 }; 54 55 static struct qcom_icc_node mas_pcie_1 = { 56 .name = "mas_pcie_1", 57 .id = MSM8996_MASTER_PCIE_1, 58 .buswidth = 8, 59 .mas_rpm_id = 66, 60 .slv_rpm_id = -1, 61 .qos.ap_owned = true, 62 .qos.qos_mode = NOC_QOS_MODE_FIXED, 63 .qos.areq_prio = 1, 64 .qos.prio_level = 1, 65 .qos.qos_port = 1, 66 .num_links = ARRAY_SIZE(mas_a0noc_common_links), 67 .links = mas_a0noc_common_links 68 }; 69 70 static struct qcom_icc_node mas_pcie_2 = { 71 .name = "mas_pcie_2", 72 .id = MSM8996_MASTER_PCIE_2, 73 .buswidth = 8, 74 .mas_rpm_id = 119, 75 .slv_rpm_id = -1, 76 .qos.ap_owned = true, 77 .qos.qos_mode = NOC_QOS_MODE_FIXED, 78 .qos.areq_prio = 1, 79 .qos.prio_level = 1, 80 .qos.qos_port = 2, 81 .num_links = ARRAY_SIZE(mas_a0noc_common_links), 82 .links = mas_a0noc_common_links 83 }; 84 85 static const u16 mas_a1noc_common_links[] = { 86 MSM8996_SLAVE_A1NOC_SNOC 87 }; 88 89 static struct qcom_icc_node mas_cnoc_a1noc = { 90 .name = "mas_cnoc_a1noc", 91 .id = MSM8996_MASTER_CNOC_A1NOC, 92 .buswidth = 8, 93 .mas_rpm_id = 116, 94 .slv_rpm_id = -1, 95 .qos.ap_owned = true, 96 .qos.qos_mode = NOC_QOS_MODE_INVALID, 97 .num_links = ARRAY_SIZE(mas_a1noc_common_links), 98 .links = mas_a1noc_common_links 99 }; 100 101 static struct qcom_icc_node mas_crypto_c0 = { 102 .name = "mas_crypto_c0", 103 .id = MSM8996_MASTER_CRYPTO_CORE0, 104 .buswidth = 8, 105 .mas_rpm_id = 23, 106 .slv_rpm_id = -1, 107 .qos.ap_owned = true, 108 .qos.qos_mode = NOC_QOS_MODE_FIXED, 109 .qos.areq_prio = 1, 110 .qos.prio_level = 1, 111 .qos.qos_port = 0, 112 .num_links = ARRAY_SIZE(mas_a1noc_common_links), 113 .links = mas_a1noc_common_links 114 }; 115 116 static struct qcom_icc_node mas_pnoc_a1noc = { 117 .name = "mas_pnoc_a1noc", 118 .id = MSM8996_MASTER_PNOC_A1NOC, 119 .buswidth = 8, 120 .mas_rpm_id = 117, 121 .slv_rpm_id = -1, 122 .qos.ap_owned = false, 123 .qos.qos_mode = NOC_QOS_MODE_FIXED, 124 .qos.areq_prio = 0, 125 .qos.prio_level = 0, 126 .qos.qos_port = 1, 127 .num_links = ARRAY_SIZE(mas_a1noc_common_links), 128 .links = mas_a1noc_common_links 129 }; 130 131 static const u16 mas_a2noc_common_links[] = { 132 MSM8996_SLAVE_A2NOC_SNOC 133 }; 134 135 static struct qcom_icc_node mas_usb3 = { 136 .name = "mas_usb3", 137 .id = MSM8996_MASTER_USB3, 138 .buswidth = 8, 139 .mas_rpm_id = 32, 140 .slv_rpm_id = -1, 141 .qos.ap_owned = true, 142 .qos.qos_mode = NOC_QOS_MODE_FIXED, 143 .qos.areq_prio = 1, 144 .qos.prio_level = 1, 145 .qos.qos_port = 3, 146 .num_links = ARRAY_SIZE(mas_a2noc_common_links), 147 .links = mas_a2noc_common_links 148 }; 149 150 static struct qcom_icc_node mas_ipa = { 151 .name = "mas_ipa", 152 .id = MSM8996_MASTER_IPA, 153 .buswidth = 8, 154 .mas_rpm_id = 59, 155 .slv_rpm_id = -1, 156 .qos.ap_owned = true, 157 .qos.qos_mode = NOC_QOS_MODE_FIXED, 158 .qos.areq_prio = 0, 159 .qos.prio_level = 0, 160 .qos.qos_port = -1, 161 .num_links = ARRAY_SIZE(mas_a2noc_common_links), 162 .links = mas_a2noc_common_links 163 }; 164 165 static struct qcom_icc_node mas_ufs = { 166 .name = "mas_ufs", 167 .id = MSM8996_MASTER_UFS, 168 .buswidth = 8, 169 .mas_rpm_id = 68, 170 .slv_rpm_id = -1, 171 .qos.ap_owned = true, 172 .qos.qos_mode = NOC_QOS_MODE_FIXED, 173 .qos.areq_prio = 1, 174 .qos.prio_level = 1, 175 .qos.qos_port = 2, 176 .num_links = ARRAY_SIZE(mas_a2noc_common_links), 177 .links = mas_a2noc_common_links 178 }; 179 180 static const u16 mas_apps_proc_links[] = { 181 MSM8996_SLAVE_BIMC_SNOC_1, 182 MSM8996_SLAVE_EBI_CH0, 183 MSM8996_SLAVE_BIMC_SNOC_0 184 }; 185 186 static struct qcom_icc_node mas_apps_proc = { 187 .name = "mas_apps_proc", 188 .id = MSM8996_MASTER_AMPSS_M0, 189 .buswidth = 8, 190 .mas_rpm_id = 0, 191 .slv_rpm_id = -1, 192 .qos.ap_owned = true, 193 .qos.qos_mode = NOC_QOS_MODE_FIXED, 194 .qos.areq_prio = 0, 195 .qos.prio_level = 0, 196 .qos.qos_port = 0, 197 .num_links = ARRAY_SIZE(mas_apps_proc_links), 198 .links = mas_apps_proc_links 199 }; 200 201 static const u16 mas_oxili_common_links[] = { 202 MSM8996_SLAVE_BIMC_SNOC_1, 203 MSM8996_SLAVE_HMSS_L3, 204 MSM8996_SLAVE_EBI_CH0, 205 MSM8996_SLAVE_BIMC_SNOC_0 206 }; 207 208 static struct qcom_icc_node mas_oxili = { 209 .name = "mas_oxili", 210 .id = MSM8996_MASTER_GRAPHICS_3D, 211 .buswidth = 8, 212 .mas_rpm_id = 6, 213 .slv_rpm_id = -1, 214 .qos.ap_owned = true, 215 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 216 .qos.areq_prio = 0, 217 .qos.prio_level = 0, 218 .qos.qos_port = 1, 219 .num_links = ARRAY_SIZE(mas_oxili_common_links), 220 .links = mas_oxili_common_links 221 }; 222 223 static struct qcom_icc_node mas_mnoc_bimc = { 224 .name = "mas_mnoc_bimc", 225 .id = MSM8996_MASTER_MNOC_BIMC, 226 .buswidth = 8, 227 .mas_rpm_id = 2, 228 .slv_rpm_id = -1, 229 .qos.ap_owned = true, 230 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 231 .qos.areq_prio = 0, 232 .qos.prio_level = 0, 233 .qos.qos_port = 2, 234 .num_links = ARRAY_SIZE(mas_oxili_common_links), 235 .links = mas_oxili_common_links 236 }; 237 238 static const u16 mas_snoc_bimc_links[] = { 239 MSM8996_SLAVE_HMSS_L3, 240 MSM8996_SLAVE_EBI_CH0 241 }; 242 243 static struct qcom_icc_node mas_snoc_bimc = { 244 .name = "mas_snoc_bimc", 245 .id = MSM8996_MASTER_SNOC_BIMC, 246 .buswidth = 8, 247 .mas_rpm_id = 3, 248 .slv_rpm_id = -1, 249 .qos.ap_owned = false, 250 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 251 .qos.areq_prio = 0, 252 .qos.prio_level = 0, 253 .qos.qos_port = -1, 254 .num_links = ARRAY_SIZE(mas_snoc_bimc_links), 255 .links = mas_snoc_bimc_links 256 }; 257 258 static const u16 mas_snoc_cnoc_links[] = { 259 MSM8996_SLAVE_CLK_CTL, 260 MSM8996_SLAVE_RBCPR_CX, 261 MSM8996_SLAVE_A2NOC_SMMU_CFG, 262 MSM8996_SLAVE_A0NOC_MPU_CFG, 263 MSM8996_SLAVE_MESSAGE_RAM, 264 MSM8996_SLAVE_CNOC_MNOC_MMSS_CFG, 265 MSM8996_SLAVE_PCIE_0_CFG, 266 MSM8996_SLAVE_TLMM, 267 MSM8996_SLAVE_MPM, 268 MSM8996_SLAVE_A0NOC_SMMU_CFG, 269 MSM8996_SLAVE_EBI1_PHY_CFG, 270 MSM8996_SLAVE_BIMC_CFG, 271 MSM8996_SLAVE_PIMEM_CFG, 272 MSM8996_SLAVE_RBCPR_MX, 273 MSM8996_SLAVE_PRNG, 274 MSM8996_SLAVE_PCIE20_AHB2PHY, 275 MSM8996_SLAVE_A2NOC_MPU_CFG, 276 MSM8996_SLAVE_QDSS_CFG, 277 MSM8996_SLAVE_A2NOC_CFG, 278 MSM8996_SLAVE_A0NOC_CFG, 279 MSM8996_SLAVE_UFS_CFG, 280 MSM8996_SLAVE_CRYPTO_0_CFG, 281 MSM8996_SLAVE_PCIE_1_CFG, 282 MSM8996_SLAVE_SNOC_CFG, 283 MSM8996_SLAVE_SNOC_MPU_CFG, 284 MSM8996_SLAVE_A1NOC_MPU_CFG, 285 MSM8996_SLAVE_A1NOC_SMMU_CFG, 286 MSM8996_SLAVE_PCIE_2_CFG, 287 MSM8996_SLAVE_CNOC_MNOC_CFG, 288 MSM8996_SLAVE_QDSS_RBCPR_APU_CFG, 289 MSM8996_SLAVE_PMIC_ARB, 290 MSM8996_SLAVE_IMEM_CFG, 291 MSM8996_SLAVE_A1NOC_CFG, 292 MSM8996_SLAVE_SSC_CFG, 293 MSM8996_SLAVE_TCSR, 294 MSM8996_SLAVE_LPASS_SMMU_CFG, 295 MSM8996_SLAVE_DCC_CFG 296 }; 297 298 static struct qcom_icc_node mas_snoc_cnoc = { 299 .name = "mas_snoc_cnoc", 300 .id = MSM8996_MASTER_SNOC_CNOC, 301 .buswidth = 8, 302 .mas_rpm_id = 52, 303 .slv_rpm_id = -1, 304 .num_links = ARRAY_SIZE(mas_snoc_cnoc_links), 305 .links = mas_snoc_cnoc_links 306 }; 307 308 static const u16 mas_qdss_dap_links[] = { 309 MSM8996_SLAVE_QDSS_RBCPR_APU_CFG, 310 MSM8996_SLAVE_RBCPR_CX, 311 MSM8996_SLAVE_A2NOC_SMMU_CFG, 312 MSM8996_SLAVE_A0NOC_MPU_CFG, 313 MSM8996_SLAVE_MESSAGE_RAM, 314 MSM8996_SLAVE_PCIE_0_CFG, 315 MSM8996_SLAVE_TLMM, 316 MSM8996_SLAVE_MPM, 317 MSM8996_SLAVE_A0NOC_SMMU_CFG, 318 MSM8996_SLAVE_EBI1_PHY_CFG, 319 MSM8996_SLAVE_BIMC_CFG, 320 MSM8996_SLAVE_PIMEM_CFG, 321 MSM8996_SLAVE_RBCPR_MX, 322 MSM8996_SLAVE_CLK_CTL, 323 MSM8996_SLAVE_PRNG, 324 MSM8996_SLAVE_PCIE20_AHB2PHY, 325 MSM8996_SLAVE_A2NOC_MPU_CFG, 326 MSM8996_SLAVE_QDSS_CFG, 327 MSM8996_SLAVE_A2NOC_CFG, 328 MSM8996_SLAVE_A0NOC_CFG, 329 MSM8996_SLAVE_UFS_CFG, 330 MSM8996_SLAVE_CRYPTO_0_CFG, 331 MSM8996_SLAVE_CNOC_A1NOC, 332 MSM8996_SLAVE_PCIE_1_CFG, 333 MSM8996_SLAVE_SNOC_CFG, 334 MSM8996_SLAVE_SNOC_MPU_CFG, 335 MSM8996_SLAVE_A1NOC_MPU_CFG, 336 MSM8996_SLAVE_A1NOC_SMMU_CFG, 337 MSM8996_SLAVE_PCIE_2_CFG, 338 MSM8996_SLAVE_CNOC_MNOC_CFG, 339 MSM8996_SLAVE_CNOC_MNOC_MMSS_CFG, 340 MSM8996_SLAVE_PMIC_ARB, 341 MSM8996_SLAVE_IMEM_CFG, 342 MSM8996_SLAVE_A1NOC_CFG, 343 MSM8996_SLAVE_SSC_CFG, 344 MSM8996_SLAVE_TCSR, 345 MSM8996_SLAVE_LPASS_SMMU_CFG, 346 MSM8996_SLAVE_DCC_CFG 347 }; 348 349 static struct qcom_icc_node mas_qdss_dap = { 350 .name = "mas_qdss_dap", 351 .id = MSM8996_MASTER_QDSS_DAP, 352 .buswidth = 8, 353 .mas_rpm_id = 49, 354 .slv_rpm_id = -1, 355 .qos.ap_owned = true, 356 .qos.qos_mode = NOC_QOS_MODE_INVALID, 357 .num_links = ARRAY_SIZE(mas_qdss_dap_links), 358 .links = mas_qdss_dap_links 359 }; 360 361 static const u16 mas_cnoc_mnoc_mmss_cfg_links[] = { 362 MSM8996_SLAVE_MMAGIC_CFG, 363 MSM8996_SLAVE_DSA_MPU_CFG, 364 MSM8996_SLAVE_MMSS_CLK_CFG, 365 MSM8996_SLAVE_CAMERA_THROTTLE_CFG, 366 MSM8996_SLAVE_VENUS_CFG, 367 MSM8996_SLAVE_SMMU_VFE_CFG, 368 MSM8996_SLAVE_MISC_CFG, 369 MSM8996_SLAVE_SMMU_CPP_CFG, 370 MSM8996_SLAVE_GRAPHICS_3D_CFG, 371 MSM8996_SLAVE_DISPLAY_THROTTLE_CFG, 372 MSM8996_SLAVE_VENUS_THROTTLE_CFG, 373 MSM8996_SLAVE_CAMERA_CFG, 374 MSM8996_SLAVE_DISPLAY_CFG, 375 MSM8996_SLAVE_CPR_CFG, 376 MSM8996_SLAVE_SMMU_ROTATOR_CFG, 377 MSM8996_SLAVE_DSA_CFG, 378 MSM8996_SLAVE_SMMU_VENUS_CFG, 379 MSM8996_SLAVE_VMEM_CFG, 380 MSM8996_SLAVE_SMMU_JPEG_CFG, 381 MSM8996_SLAVE_SMMU_MDP_CFG, 382 MSM8996_SLAVE_MNOC_MPU_CFG 383 }; 384 385 static struct qcom_icc_node mas_cnoc_mnoc_mmss_cfg = { 386 .name = "mas_cnoc_mnoc_mmss_cfg", 387 .id = MSM8996_MASTER_CNOC_MNOC_MMSS_CFG, 388 .buswidth = 8, 389 .mas_rpm_id = 4, 390 .slv_rpm_id = -1, 391 .qos.ap_owned = true, 392 .qos.qos_mode = NOC_QOS_MODE_INVALID, 393 .num_links = ARRAY_SIZE(mas_cnoc_mnoc_mmss_cfg_links), 394 .links = mas_cnoc_mnoc_mmss_cfg_links 395 }; 396 397 static const u16 mas_cnoc_mnoc_cfg_links[] = { 398 MSM8996_SLAVE_SERVICE_MNOC 399 }; 400 401 static struct qcom_icc_node mas_cnoc_mnoc_cfg = { 402 .name = "mas_cnoc_mnoc_cfg", 403 .id = MSM8996_MASTER_CNOC_MNOC_CFG, 404 .buswidth = 8, 405 .mas_rpm_id = 5, 406 .slv_rpm_id = -1, 407 .qos.ap_owned = true, 408 .qos.qos_mode = NOC_QOS_MODE_INVALID, 409 .num_links = ARRAY_SIZE(mas_cnoc_mnoc_cfg_links), 410 .links = mas_cnoc_mnoc_cfg_links 411 }; 412 413 static const u16 mas_mnoc_bimc_common_links[] = { 414 MSM8996_SLAVE_MNOC_BIMC 415 }; 416 417 static struct qcom_icc_node mas_cpp = { 418 .name = "mas_cpp", 419 .id = MSM8996_MASTER_CPP, 420 .buswidth = 32, 421 .mas_rpm_id = 115, 422 .slv_rpm_id = -1, 423 .qos.ap_owned = true, 424 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 425 .qos.areq_prio = 0, 426 .qos.prio_level = 0, 427 .qos.qos_port = 5, 428 .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links), 429 .links = mas_mnoc_bimc_common_links 430 }; 431 432 static struct qcom_icc_node mas_jpeg = { 433 .name = "mas_jpeg", 434 .id = MSM8996_MASTER_JPEG, 435 .buswidth = 32, 436 .mas_rpm_id = 7, 437 .slv_rpm_id = -1, 438 .qos.ap_owned = true, 439 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 440 .qos.areq_prio = 0, 441 .qos.prio_level = 0, 442 .qos.qos_port = 7, 443 .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links), 444 .links = mas_mnoc_bimc_common_links 445 }; 446 447 static struct qcom_icc_node mas_mdp_p0 = { 448 .name = "mas_mdp_p0", 449 .id = MSM8996_MASTER_MDP_PORT0, 450 .buswidth = 32, 451 .ib_coeff = 25, 452 .mas_rpm_id = 8, 453 .slv_rpm_id = -1, 454 .qos.ap_owned = true, 455 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 456 .qos.areq_prio = 0, 457 .qos.prio_level = 0, 458 .qos.qos_port = 1, 459 .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links), 460 .links = mas_mnoc_bimc_common_links 461 }; 462 463 static struct qcom_icc_node mas_mdp_p1 = { 464 .name = "mas_mdp_p1", 465 .id = MSM8996_MASTER_MDP_PORT1, 466 .buswidth = 32, 467 .ib_coeff = 25, 468 .mas_rpm_id = 61, 469 .slv_rpm_id = -1, 470 .qos.ap_owned = true, 471 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 472 .qos.areq_prio = 0, 473 .qos.prio_level = 0, 474 .qos.qos_port = 2, 475 .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links), 476 .links = mas_mnoc_bimc_common_links 477 }; 478 479 static struct qcom_icc_node mas_rotator = { 480 .name = "mas_rotator", 481 .id = MSM8996_MASTER_ROTATOR, 482 .buswidth = 32, 483 .mas_rpm_id = 120, 484 .slv_rpm_id = -1, 485 .qos.ap_owned = true, 486 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 487 .qos.areq_prio = 0, 488 .qos.prio_level = 0, 489 .qos.qos_port = 0, 490 .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links), 491 .links = mas_mnoc_bimc_common_links 492 }; 493 494 static struct qcom_icc_node mas_venus = { 495 .name = "mas_venus", 496 .id = MSM8996_MASTER_VIDEO_P0, 497 .buswidth = 32, 498 .mas_rpm_id = 9, 499 .slv_rpm_id = -1, 500 .qos.ap_owned = true, 501 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 502 .qos.areq_prio = 0, 503 .qos.prio_level = 0, 504 .qos.qos_port = 3, 505 .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links), 506 .links = mas_mnoc_bimc_common_links 507 }; 508 509 static struct qcom_icc_node mas_vfe = { 510 .name = "mas_vfe", 511 .id = MSM8996_MASTER_VFE, 512 .buswidth = 32, 513 .mas_rpm_id = 11, 514 .slv_rpm_id = -1, 515 .qos.ap_owned = true, 516 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 517 .qos.areq_prio = 0, 518 .qos.prio_level = 0, 519 .qos.qos_port = 6, 520 .num_links = ARRAY_SIZE(mas_mnoc_bimc_common_links), 521 .links = mas_mnoc_bimc_common_links 522 }; 523 524 static const u16 mas_vmem_common_links[] = { 525 MSM8996_SLAVE_VMEM 526 }; 527 528 static struct qcom_icc_node mas_snoc_vmem = { 529 .name = "mas_snoc_vmem", 530 .id = MSM8996_MASTER_SNOC_VMEM, 531 .buswidth = 32, 532 .mas_rpm_id = 114, 533 .slv_rpm_id = -1, 534 .qos.ap_owned = true, 535 .qos.qos_mode = NOC_QOS_MODE_INVALID, 536 .num_links = ARRAY_SIZE(mas_vmem_common_links), 537 .links = mas_vmem_common_links 538 }; 539 540 static struct qcom_icc_node mas_venus_vmem = { 541 .name = "mas_venus_vmem", 542 .id = MSM8996_MASTER_VIDEO_P0_OCMEM, 543 .buswidth = 32, 544 .mas_rpm_id = 121, 545 .slv_rpm_id = -1, 546 .qos.ap_owned = true, 547 .qos.qos_mode = NOC_QOS_MODE_INVALID, 548 .num_links = ARRAY_SIZE(mas_vmem_common_links), 549 .links = mas_vmem_common_links 550 }; 551 552 static const u16 mas_snoc_pnoc_links[] = { 553 MSM8996_SLAVE_BLSP_1, 554 MSM8996_SLAVE_BLSP_2, 555 MSM8996_SLAVE_USB_HS, 556 MSM8996_SLAVE_SDCC_1, 557 MSM8996_SLAVE_SDCC_2, 558 MSM8996_SLAVE_SDCC_4, 559 MSM8996_SLAVE_TSIF, 560 MSM8996_SLAVE_PDM, 561 MSM8996_SLAVE_AHB2PHY 562 }; 563 564 static struct qcom_icc_node mas_snoc_pnoc = { 565 .name = "mas_snoc_pnoc", 566 .id = MSM8996_MASTER_SNOC_PNOC, 567 .buswidth = 8, 568 .mas_rpm_id = 44, 569 .slv_rpm_id = -1, 570 .num_links = ARRAY_SIZE(mas_snoc_pnoc_links), 571 .links = mas_snoc_pnoc_links 572 }; 573 574 static const u16 mas_pnoc_a1noc_common_links[] = { 575 MSM8996_SLAVE_PNOC_A1NOC 576 }; 577 578 static struct qcom_icc_node mas_sdcc_1 = { 579 .name = "mas_sdcc_1", 580 .id = MSM8996_MASTER_SDCC_1, 581 .buswidth = 8, 582 .mas_rpm_id = 33, 583 .slv_rpm_id = -1, 584 .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links), 585 .links = mas_pnoc_a1noc_common_links 586 }; 587 588 static struct qcom_icc_node mas_sdcc_2 = { 589 .name = "mas_sdcc_2", 590 .id = MSM8996_MASTER_SDCC_2, 591 .buswidth = 8, 592 .mas_rpm_id = 35, 593 .slv_rpm_id = -1, 594 .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links), 595 .links = mas_pnoc_a1noc_common_links 596 }; 597 598 static struct qcom_icc_node mas_sdcc_4 = { 599 .name = "mas_sdcc_4", 600 .id = MSM8996_MASTER_SDCC_4, 601 .buswidth = 8, 602 .mas_rpm_id = 36, 603 .slv_rpm_id = -1, 604 .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links), 605 .links = mas_pnoc_a1noc_common_links 606 }; 607 608 static struct qcom_icc_node mas_usb_hs = { 609 .name = "mas_usb_hs", 610 .id = MSM8996_MASTER_USB_HS, 611 .buswidth = 8, 612 .mas_rpm_id = 42, 613 .slv_rpm_id = -1, 614 .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links), 615 .links = mas_pnoc_a1noc_common_links 616 }; 617 618 static struct qcom_icc_node mas_blsp_1 = { 619 .name = "mas_blsp_1", 620 .id = MSM8996_MASTER_BLSP_1, 621 .buswidth = 4, 622 .mas_rpm_id = 41, 623 .slv_rpm_id = -1, 624 .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links), 625 .links = mas_pnoc_a1noc_common_links 626 }; 627 628 static struct qcom_icc_node mas_blsp_2 = { 629 .name = "mas_blsp_2", 630 .id = MSM8996_MASTER_BLSP_2, 631 .buswidth = 4, 632 .mas_rpm_id = 39, 633 .slv_rpm_id = -1, 634 .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links), 635 .links = mas_pnoc_a1noc_common_links 636 }; 637 638 static struct qcom_icc_node mas_tsif = { 639 .name = "mas_tsif", 640 .id = MSM8996_MASTER_TSIF, 641 .buswidth = 4, 642 .mas_rpm_id = 37, 643 .slv_rpm_id = -1, 644 .num_links = ARRAY_SIZE(mas_pnoc_a1noc_common_links), 645 .links = mas_pnoc_a1noc_common_links 646 }; 647 648 static const u16 mas_hmss_links[] = { 649 MSM8996_SLAVE_PIMEM, 650 MSM8996_SLAVE_OCIMEM, 651 MSM8996_SLAVE_SNOC_BIMC 652 }; 653 654 static struct qcom_icc_node mas_hmss = { 655 .name = "mas_hmss", 656 .id = MSM8996_MASTER_HMSS, 657 .buswidth = 8, 658 .mas_rpm_id = 118, 659 .slv_rpm_id = -1, 660 .qos.ap_owned = true, 661 .qos.qos_mode = NOC_QOS_MODE_FIXED, 662 .qos.areq_prio = 1, 663 .qos.prio_level = 1, 664 .qos.qos_port = 4, 665 .num_links = ARRAY_SIZE(mas_hmss_links), 666 .links = mas_hmss_links 667 }; 668 669 static const u16 mas_qdss_common_links[] = { 670 MSM8996_SLAVE_PIMEM, 671 MSM8996_SLAVE_USB3, 672 MSM8996_SLAVE_OCIMEM, 673 MSM8996_SLAVE_SNOC_BIMC, 674 MSM8996_SLAVE_SNOC_PNOC 675 }; 676 677 static struct qcom_icc_node mas_qdss_bam = { 678 .name = "mas_qdss_bam", 679 .id = MSM8996_MASTER_QDSS_BAM, 680 .buswidth = 16, 681 .mas_rpm_id = 19, 682 .slv_rpm_id = -1, 683 .qos.ap_owned = true, 684 .qos.qos_mode = NOC_QOS_MODE_FIXED, 685 .qos.areq_prio = 1, 686 .qos.prio_level = 1, 687 .qos.qos_port = 2, 688 .num_links = ARRAY_SIZE(mas_qdss_common_links), 689 .links = mas_qdss_common_links 690 }; 691 692 static const u16 mas_snoc_cfg_links[] = { 693 MSM8996_SLAVE_SERVICE_SNOC 694 }; 695 696 static struct qcom_icc_node mas_snoc_cfg = { 697 .name = "mas_snoc_cfg", 698 .id = MSM8996_MASTER_SNOC_CFG, 699 .buswidth = 16, 700 .mas_rpm_id = 20, 701 .slv_rpm_id = -1, 702 .qos.ap_owned = true, 703 .qos.qos_mode = NOC_QOS_MODE_INVALID, 704 .num_links = ARRAY_SIZE(mas_snoc_cfg_links), 705 .links = mas_snoc_cfg_links 706 }; 707 708 static const u16 mas_bimc_snoc_0_links[] = { 709 MSM8996_SLAVE_SNOC_VMEM, 710 MSM8996_SLAVE_USB3, 711 MSM8996_SLAVE_PIMEM, 712 MSM8996_SLAVE_LPASS, 713 MSM8996_SLAVE_APPSS, 714 MSM8996_SLAVE_SNOC_CNOC, 715 MSM8996_SLAVE_SNOC_PNOC, 716 MSM8996_SLAVE_OCIMEM, 717 MSM8996_SLAVE_QDSS_STM 718 }; 719 720 static struct qcom_icc_node mas_bimc_snoc_0 = { 721 .name = "mas_bimc_snoc_0", 722 .id = MSM8996_MASTER_BIMC_SNOC_0, 723 .buswidth = 16, 724 .mas_rpm_id = 21, 725 .slv_rpm_id = -1, 726 .qos.ap_owned = true, 727 .qos.qos_mode = NOC_QOS_MODE_INVALID, 728 .num_links = ARRAY_SIZE(mas_bimc_snoc_0_links), 729 .links = mas_bimc_snoc_0_links 730 }; 731 732 static const u16 mas_bimc_snoc_1_links[] = { 733 MSM8996_SLAVE_PCIE_2, 734 MSM8996_SLAVE_PCIE_1, 735 MSM8996_SLAVE_PCIE_0 736 }; 737 738 static struct qcom_icc_node mas_bimc_snoc_1 = { 739 .name = "mas_bimc_snoc_1", 740 .id = MSM8996_MASTER_BIMC_SNOC_1, 741 .buswidth = 16, 742 .mas_rpm_id = 109, 743 .slv_rpm_id = -1, 744 .qos.ap_owned = true, 745 .qos.qos_mode = NOC_QOS_MODE_INVALID, 746 .num_links = ARRAY_SIZE(mas_bimc_snoc_1_links), 747 .links = mas_bimc_snoc_1_links 748 }; 749 750 static const u16 mas_a0noc_snoc_links[] = { 751 MSM8996_SLAVE_SNOC_PNOC, 752 MSM8996_SLAVE_OCIMEM, 753 MSM8996_SLAVE_APPSS, 754 MSM8996_SLAVE_SNOC_BIMC, 755 MSM8996_SLAVE_PIMEM 756 }; 757 758 static struct qcom_icc_node mas_a0noc_snoc = { 759 .name = "mas_a0noc_snoc", 760 .id = MSM8996_MASTER_A0NOC_SNOC, 761 .buswidth = 16, 762 .mas_rpm_id = 110, 763 .slv_rpm_id = -1, 764 .qos.ap_owned = true, 765 .qos.qos_mode = NOC_QOS_MODE_INVALID, 766 .num_links = ARRAY_SIZE(mas_a0noc_snoc_links), 767 .links = mas_a0noc_snoc_links 768 }; 769 770 static const u16 mas_a1noc_snoc_links[] = { 771 MSM8996_SLAVE_SNOC_VMEM, 772 MSM8996_SLAVE_USB3, 773 MSM8996_SLAVE_PCIE_0, 774 MSM8996_SLAVE_PIMEM, 775 MSM8996_SLAVE_PCIE_2, 776 MSM8996_SLAVE_LPASS, 777 MSM8996_SLAVE_PCIE_1, 778 MSM8996_SLAVE_APPSS, 779 MSM8996_SLAVE_SNOC_BIMC, 780 MSM8996_SLAVE_SNOC_CNOC, 781 MSM8996_SLAVE_SNOC_PNOC, 782 MSM8996_SLAVE_OCIMEM, 783 MSM8996_SLAVE_QDSS_STM 784 }; 785 786 static struct qcom_icc_node mas_a1noc_snoc = { 787 .name = "mas_a1noc_snoc", 788 .id = MSM8996_MASTER_A1NOC_SNOC, 789 .buswidth = 16, 790 .mas_rpm_id = 111, 791 .slv_rpm_id = -1, 792 .num_links = ARRAY_SIZE(mas_a1noc_snoc_links), 793 .links = mas_a1noc_snoc_links 794 }; 795 796 static const u16 mas_a2noc_snoc_links[] = { 797 MSM8996_SLAVE_SNOC_VMEM, 798 MSM8996_SLAVE_USB3, 799 MSM8996_SLAVE_PCIE_1, 800 MSM8996_SLAVE_PIMEM, 801 MSM8996_SLAVE_PCIE_2, 802 MSM8996_SLAVE_QDSS_STM, 803 MSM8996_SLAVE_LPASS, 804 MSM8996_SLAVE_SNOC_BIMC, 805 MSM8996_SLAVE_SNOC_CNOC, 806 MSM8996_SLAVE_SNOC_PNOC, 807 MSM8996_SLAVE_OCIMEM, 808 MSM8996_SLAVE_PCIE_0 809 }; 810 811 static struct qcom_icc_node mas_a2noc_snoc = { 812 .name = "mas_a2noc_snoc", 813 .id = MSM8996_MASTER_A2NOC_SNOC, 814 .buswidth = 16, 815 .mas_rpm_id = 112, 816 .slv_rpm_id = -1, 817 .num_links = ARRAY_SIZE(mas_a2noc_snoc_links), 818 .links = mas_a2noc_snoc_links 819 }; 820 821 static struct qcom_icc_node mas_qdss_etr = { 822 .name = "mas_qdss_etr", 823 .id = MSM8996_MASTER_QDSS_ETR, 824 .buswidth = 16, 825 .mas_rpm_id = 31, 826 .slv_rpm_id = -1, 827 .qos.ap_owned = true, 828 .qos.qos_mode = NOC_QOS_MODE_FIXED, 829 .qos.areq_prio = 1, 830 .qos.prio_level = 1, 831 .qos.qos_port = 3, 832 .num_links = ARRAY_SIZE(mas_qdss_common_links), 833 .links = mas_qdss_common_links 834 }; 835 836 static const u16 slv_a0noc_snoc_links[] = { 837 MSM8996_MASTER_A0NOC_SNOC 838 }; 839 840 static struct qcom_icc_node slv_a0noc_snoc = { 841 .name = "slv_a0noc_snoc", 842 .id = MSM8996_SLAVE_A0NOC_SNOC, 843 .buswidth = 8, 844 .mas_rpm_id = -1, 845 .slv_rpm_id = 141, 846 .qos.ap_owned = true, 847 .qos.qos_mode = NOC_QOS_MODE_INVALID, 848 .num_links = ARRAY_SIZE(slv_a0noc_snoc_links), 849 .links = slv_a0noc_snoc_links 850 }; 851 852 static const u16 slv_a1noc_snoc_links[] = { 853 MSM8996_MASTER_A1NOC_SNOC 854 }; 855 856 static struct qcom_icc_node slv_a1noc_snoc = { 857 .name = "slv_a1noc_snoc", 858 .id = MSM8996_SLAVE_A1NOC_SNOC, 859 .buswidth = 8, 860 .mas_rpm_id = -1, 861 .slv_rpm_id = 142, 862 .num_links = ARRAY_SIZE(slv_a1noc_snoc_links), 863 .links = slv_a1noc_snoc_links 864 }; 865 866 static const u16 slv_a2noc_snoc_links[] = { 867 MSM8996_MASTER_A2NOC_SNOC 868 }; 869 870 static struct qcom_icc_node slv_a2noc_snoc = { 871 .name = "slv_a2noc_snoc", 872 .id = MSM8996_SLAVE_A2NOC_SNOC, 873 .buswidth = 8, 874 .mas_rpm_id = -1, 875 .slv_rpm_id = 143, 876 .num_links = ARRAY_SIZE(slv_a2noc_snoc_links), 877 .links = slv_a2noc_snoc_links 878 }; 879 880 static struct qcom_icc_node slv_ebi = { 881 .name = "slv_ebi", 882 .id = MSM8996_SLAVE_EBI_CH0, 883 .buswidth = 8, 884 .mas_rpm_id = -1, 885 .slv_rpm_id = 0 886 }; 887 888 static struct qcom_icc_node slv_hmss_l3 = { 889 .name = "slv_hmss_l3", 890 .id = MSM8996_SLAVE_HMSS_L3, 891 .buswidth = 8, 892 .mas_rpm_id = -1, 893 .slv_rpm_id = 160 894 }; 895 896 static const u16 slv_bimc_snoc_0_links[] = { 897 MSM8996_MASTER_BIMC_SNOC_0 898 }; 899 900 static struct qcom_icc_node slv_bimc_snoc_0 = { 901 .name = "slv_bimc_snoc_0", 902 .id = MSM8996_SLAVE_BIMC_SNOC_0, 903 .buswidth = 8, 904 .mas_rpm_id = -1, 905 .slv_rpm_id = 2, 906 .qos.ap_owned = true, 907 .qos.qos_mode = NOC_QOS_MODE_INVALID, 908 .num_links = ARRAY_SIZE(slv_bimc_snoc_0_links), 909 .links = slv_bimc_snoc_0_links 910 }; 911 912 static const u16 slv_bimc_snoc_1_links[] = { 913 MSM8996_MASTER_BIMC_SNOC_1 914 }; 915 916 static struct qcom_icc_node slv_bimc_snoc_1 = { 917 .name = "slv_bimc_snoc_1", 918 .id = MSM8996_SLAVE_BIMC_SNOC_1, 919 .buswidth = 8, 920 .mas_rpm_id = -1, 921 .slv_rpm_id = 138, 922 .qos.ap_owned = true, 923 .qos.qos_mode = NOC_QOS_MODE_INVALID, 924 .num_links = ARRAY_SIZE(slv_bimc_snoc_1_links), 925 .links = slv_bimc_snoc_1_links 926 }; 927 928 static const u16 slv_cnoc_a1noc_links[] = { 929 MSM8996_MASTER_CNOC_A1NOC 930 }; 931 932 static struct qcom_icc_node slv_cnoc_a1noc = { 933 .name = "slv_cnoc_a1noc", 934 .id = MSM8996_SLAVE_CNOC_A1NOC, 935 .buswidth = 4, 936 .mas_rpm_id = -1, 937 .slv_rpm_id = 75, 938 .qos.ap_owned = true, 939 .qos.qos_mode = NOC_QOS_MODE_INVALID, 940 .num_links = ARRAY_SIZE(slv_cnoc_a1noc_links), 941 .links = slv_cnoc_a1noc_links 942 }; 943 944 static struct qcom_icc_node slv_clk_ctl = { 945 .name = "slv_clk_ctl", 946 .id = MSM8996_SLAVE_CLK_CTL, 947 .buswidth = 4, 948 .mas_rpm_id = -1, 949 .slv_rpm_id = 47 950 }; 951 952 static struct qcom_icc_node slv_tcsr = { 953 .name = "slv_tcsr", 954 .id = MSM8996_SLAVE_TCSR, 955 .buswidth = 4, 956 .mas_rpm_id = -1, 957 .slv_rpm_id = 50 958 }; 959 960 static struct qcom_icc_node slv_tlmm = { 961 .name = "slv_tlmm", 962 .id = MSM8996_SLAVE_TLMM, 963 .buswidth = 4, 964 .mas_rpm_id = -1, 965 .slv_rpm_id = 51 966 }; 967 968 static struct qcom_icc_node slv_crypto0_cfg = { 969 .name = "slv_crypto0_cfg", 970 .id = MSM8996_SLAVE_CRYPTO_0_CFG, 971 .buswidth = 4, 972 .mas_rpm_id = -1, 973 .slv_rpm_id = 52, 974 .qos.ap_owned = true, 975 .qos.qos_mode = NOC_QOS_MODE_INVALID 976 }; 977 978 static struct qcom_icc_node slv_mpm = { 979 .name = "slv_mpm", 980 .id = MSM8996_SLAVE_MPM, 981 .buswidth = 4, 982 .mas_rpm_id = -1, 983 .slv_rpm_id = 62, 984 .qos.ap_owned = true, 985 .qos.qos_mode = NOC_QOS_MODE_INVALID 986 }; 987 988 static struct qcom_icc_node slv_pimem_cfg = { 989 .name = "slv_pimem_cfg", 990 .id = MSM8996_SLAVE_PIMEM_CFG, 991 .buswidth = 4, 992 .mas_rpm_id = -1, 993 .slv_rpm_id = 167, 994 .qos.ap_owned = true, 995 .qos.qos_mode = NOC_QOS_MODE_INVALID 996 }; 997 998 static struct qcom_icc_node slv_imem_cfg = { 999 .name = "slv_imem_cfg", 1000 .id = MSM8996_SLAVE_IMEM_CFG, 1001 .buswidth = 4, 1002 .mas_rpm_id = -1, 1003 .slv_rpm_id = 54, 1004 .qos.ap_owned = true, 1005 .qos.qos_mode = NOC_QOS_MODE_INVALID 1006 }; 1007 1008 static struct qcom_icc_node slv_message_ram = { 1009 .name = "slv_message_ram", 1010 .id = MSM8996_SLAVE_MESSAGE_RAM, 1011 .buswidth = 4, 1012 .mas_rpm_id = -1, 1013 .slv_rpm_id = 55 1014 }; 1015 1016 static struct qcom_icc_node slv_bimc_cfg = { 1017 .name = "slv_bimc_cfg", 1018 .id = MSM8996_SLAVE_BIMC_CFG, 1019 .buswidth = 4, 1020 .mas_rpm_id = -1, 1021 .slv_rpm_id = 56, 1022 .qos.ap_owned = true, 1023 .qos.qos_mode = NOC_QOS_MODE_INVALID 1024 }; 1025 1026 static struct qcom_icc_node slv_pmic_arb = { 1027 .name = "slv_pmic_arb", 1028 .id = MSM8996_SLAVE_PMIC_ARB, 1029 .buswidth = 4, 1030 .mas_rpm_id = -1, 1031 .slv_rpm_id = 59 1032 }; 1033 1034 static struct qcom_icc_node slv_prng = { 1035 .name = "slv_prng", 1036 .id = MSM8996_SLAVE_PRNG, 1037 .buswidth = 4, 1038 .mas_rpm_id = -1, 1039 .slv_rpm_id = 127, 1040 .qos.ap_owned = true, 1041 .qos.qos_mode = NOC_QOS_MODE_INVALID 1042 }; 1043 1044 static struct qcom_icc_node slv_dcc_cfg = { 1045 .name = "slv_dcc_cfg", 1046 .id = MSM8996_SLAVE_DCC_CFG, 1047 .buswidth = 4, 1048 .mas_rpm_id = -1, 1049 .slv_rpm_id = 155, 1050 .qos.ap_owned = true, 1051 .qos.qos_mode = NOC_QOS_MODE_INVALID 1052 }; 1053 1054 static struct qcom_icc_node slv_rbcpr_mx = { 1055 .name = "slv_rbcpr_mx", 1056 .id = MSM8996_SLAVE_RBCPR_MX, 1057 .buswidth = 4, 1058 .mas_rpm_id = -1, 1059 .slv_rpm_id = 170, 1060 .qos.ap_owned = true, 1061 .qos.qos_mode = NOC_QOS_MODE_INVALID 1062 }; 1063 1064 static struct qcom_icc_node slv_qdss_cfg = { 1065 .name = "slv_qdss_cfg", 1066 .id = MSM8996_SLAVE_QDSS_CFG, 1067 .buswidth = 4, 1068 .mas_rpm_id = -1, 1069 .slv_rpm_id = 63, 1070 .qos.ap_owned = true, 1071 .qos.qos_mode = NOC_QOS_MODE_INVALID 1072 }; 1073 1074 static struct qcom_icc_node slv_rbcpr_cx = { 1075 .name = "slv_rbcpr_cx", 1076 .id = MSM8996_SLAVE_RBCPR_CX, 1077 .buswidth = 4, 1078 .mas_rpm_id = -1, 1079 .slv_rpm_id = 169, 1080 .qos.ap_owned = true, 1081 .qos.qos_mode = NOC_QOS_MODE_INVALID 1082 }; 1083 1084 static struct qcom_icc_node slv_cpu_apu_cfg = { 1085 .name = "slv_cpu_apu_cfg", 1086 .id = MSM8996_SLAVE_QDSS_RBCPR_APU_CFG, 1087 .buswidth = 4, 1088 .mas_rpm_id = -1, 1089 .slv_rpm_id = 168, 1090 .qos.ap_owned = true, 1091 .qos.qos_mode = NOC_QOS_MODE_INVALID 1092 }; 1093 1094 static const u16 slv_cnoc_mnoc_cfg_links[] = { 1095 MSM8996_MASTER_CNOC_MNOC_CFG 1096 }; 1097 1098 static struct qcom_icc_node slv_cnoc_mnoc_cfg = { 1099 .name = "slv_cnoc_mnoc_cfg", 1100 .id = MSM8996_SLAVE_CNOC_MNOC_CFG, 1101 .buswidth = 4, 1102 .mas_rpm_id = -1, 1103 .slv_rpm_id = 66, 1104 .qos.ap_owned = true, 1105 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1106 .num_links = ARRAY_SIZE(slv_cnoc_mnoc_cfg_links), 1107 .links = slv_cnoc_mnoc_cfg_links 1108 }; 1109 1110 static struct qcom_icc_node slv_snoc_cfg = { 1111 .name = "slv_snoc_cfg", 1112 .id = MSM8996_SLAVE_SNOC_CFG, 1113 .buswidth = 4, 1114 .mas_rpm_id = -1, 1115 .slv_rpm_id = 70, 1116 .qos.ap_owned = true, 1117 .qos.qos_mode = NOC_QOS_MODE_INVALID 1118 }; 1119 1120 static struct qcom_icc_node slv_snoc_mpu_cfg = { 1121 .name = "slv_snoc_mpu_cfg", 1122 .id = MSM8996_SLAVE_SNOC_MPU_CFG, 1123 .buswidth = 4, 1124 .mas_rpm_id = -1, 1125 .slv_rpm_id = 67, 1126 .qos.ap_owned = true, 1127 .qos.qos_mode = NOC_QOS_MODE_INVALID 1128 }; 1129 1130 static struct qcom_icc_node slv_ebi1_phy_cfg = { 1131 .name = "slv_ebi1_phy_cfg", 1132 .id = MSM8996_SLAVE_EBI1_PHY_CFG, 1133 .buswidth = 4, 1134 .mas_rpm_id = -1, 1135 .slv_rpm_id = 73, 1136 .qos.ap_owned = true, 1137 .qos.qos_mode = NOC_QOS_MODE_INVALID 1138 }; 1139 1140 static struct qcom_icc_node slv_a0noc_cfg = { 1141 .name = "slv_a0noc_cfg", 1142 .id = MSM8996_SLAVE_A0NOC_CFG, 1143 .buswidth = 4, 1144 .mas_rpm_id = -1, 1145 .slv_rpm_id = 144, 1146 .qos.ap_owned = true, 1147 .qos.qos_mode = NOC_QOS_MODE_INVALID 1148 }; 1149 1150 static struct qcom_icc_node slv_pcie_1_cfg = { 1151 .name = "slv_pcie_1_cfg", 1152 .id = MSM8996_SLAVE_PCIE_1_CFG, 1153 .buswidth = 4, 1154 .mas_rpm_id = -1, 1155 .slv_rpm_id = 89, 1156 .qos.ap_owned = true, 1157 .qos.qos_mode = NOC_QOS_MODE_INVALID 1158 }; 1159 1160 static struct qcom_icc_node slv_pcie_2_cfg = { 1161 .name = "slv_pcie_2_cfg", 1162 .id = MSM8996_SLAVE_PCIE_2_CFG, 1163 .buswidth = 4, 1164 .mas_rpm_id = -1, 1165 .slv_rpm_id = 165, 1166 .qos.ap_owned = true, 1167 .qos.qos_mode = NOC_QOS_MODE_INVALID 1168 }; 1169 1170 static struct qcom_icc_node slv_pcie_0_cfg = { 1171 .name = "slv_pcie_0_cfg", 1172 .id = MSM8996_SLAVE_PCIE_0_CFG, 1173 .buswidth = 4, 1174 .mas_rpm_id = -1, 1175 .slv_rpm_id = 88, 1176 .qos.ap_owned = true, 1177 .qos.qos_mode = NOC_QOS_MODE_INVALID 1178 }; 1179 1180 static struct qcom_icc_node slv_pcie20_ahb2phy = { 1181 .name = "slv_pcie20_ahb2phy", 1182 .id = MSM8996_SLAVE_PCIE20_AHB2PHY, 1183 .buswidth = 4, 1184 .mas_rpm_id = -1, 1185 .slv_rpm_id = 163, 1186 .qos.ap_owned = true, 1187 .qos.qos_mode = NOC_QOS_MODE_INVALID 1188 }; 1189 1190 static struct qcom_icc_node slv_a0noc_mpu_cfg = { 1191 .name = "slv_a0noc_mpu_cfg", 1192 .id = MSM8996_SLAVE_A0NOC_MPU_CFG, 1193 .buswidth = 4, 1194 .mas_rpm_id = -1, 1195 .slv_rpm_id = 145, 1196 .qos.ap_owned = true, 1197 .qos.qos_mode = NOC_QOS_MODE_INVALID 1198 }; 1199 1200 static struct qcom_icc_node slv_ufs_cfg = { 1201 .name = "slv_ufs_cfg", 1202 .id = MSM8996_SLAVE_UFS_CFG, 1203 .buswidth = 4, 1204 .mas_rpm_id = -1, 1205 .slv_rpm_id = 92, 1206 .qos.ap_owned = true, 1207 .qos.qos_mode = NOC_QOS_MODE_INVALID 1208 }; 1209 1210 static struct qcom_icc_node slv_a1noc_cfg = { 1211 .name = "slv_a1noc_cfg", 1212 .id = MSM8996_SLAVE_A1NOC_CFG, 1213 .buswidth = 4, 1214 .mas_rpm_id = -1, 1215 .slv_rpm_id = 147, 1216 .qos.ap_owned = true, 1217 .qos.qos_mode = NOC_QOS_MODE_INVALID 1218 }; 1219 1220 static struct qcom_icc_node slv_a1noc_mpu_cfg = { 1221 .name = "slv_a1noc_mpu_cfg", 1222 .id = MSM8996_SLAVE_A1NOC_MPU_CFG, 1223 .buswidth = 4, 1224 .mas_rpm_id = -1, 1225 .slv_rpm_id = 148, 1226 .qos.ap_owned = true, 1227 .qos.qos_mode = NOC_QOS_MODE_INVALID 1228 }; 1229 1230 static struct qcom_icc_node slv_a2noc_cfg = { 1231 .name = "slv_a2noc_cfg", 1232 .id = MSM8996_SLAVE_A2NOC_CFG, 1233 .buswidth = 4, 1234 .mas_rpm_id = -1, 1235 .slv_rpm_id = 150, 1236 .qos.ap_owned = true, 1237 .qos.qos_mode = NOC_QOS_MODE_INVALID 1238 }; 1239 1240 static struct qcom_icc_node slv_a2noc_mpu_cfg = { 1241 .name = "slv_a2noc_mpu_cfg", 1242 .id = MSM8996_SLAVE_A2NOC_MPU_CFG, 1243 .buswidth = 4, 1244 .mas_rpm_id = -1, 1245 .slv_rpm_id = 151, 1246 .qos.ap_owned = true, 1247 .qos.qos_mode = NOC_QOS_MODE_INVALID 1248 }; 1249 1250 static struct qcom_icc_node slv_ssc_cfg = { 1251 .name = "slv_ssc_cfg", 1252 .id = MSM8996_SLAVE_SSC_CFG, 1253 .buswidth = 4, 1254 .mas_rpm_id = -1, 1255 .slv_rpm_id = 177, 1256 .qos.ap_owned = true, 1257 .qos.qos_mode = NOC_QOS_MODE_INVALID 1258 }; 1259 1260 static struct qcom_icc_node slv_a0noc_smmu_cfg = { 1261 .name = "slv_a0noc_smmu_cfg", 1262 .id = MSM8996_SLAVE_A0NOC_SMMU_CFG, 1263 .buswidth = 8, 1264 .mas_rpm_id = -1, 1265 .slv_rpm_id = 146, 1266 .qos.ap_owned = true, 1267 .qos.qos_mode = NOC_QOS_MODE_INVALID 1268 }; 1269 1270 static struct qcom_icc_node slv_a1noc_smmu_cfg = { 1271 .name = "slv_a1noc_smmu_cfg", 1272 .id = MSM8996_SLAVE_A1NOC_SMMU_CFG, 1273 .buswidth = 8, 1274 .mas_rpm_id = -1, 1275 .slv_rpm_id = 149, 1276 .qos.ap_owned = true, 1277 .qos.qos_mode = NOC_QOS_MODE_INVALID 1278 }; 1279 1280 static struct qcom_icc_node slv_a2noc_smmu_cfg = { 1281 .name = "slv_a2noc_smmu_cfg", 1282 .id = MSM8996_SLAVE_A2NOC_SMMU_CFG, 1283 .buswidth = 8, 1284 .mas_rpm_id = -1, 1285 .slv_rpm_id = 152, 1286 .qos.ap_owned = true, 1287 .qos.qos_mode = NOC_QOS_MODE_INVALID 1288 }; 1289 1290 static struct qcom_icc_node slv_lpass_smmu_cfg = { 1291 .name = "slv_lpass_smmu_cfg", 1292 .id = MSM8996_SLAVE_LPASS_SMMU_CFG, 1293 .buswidth = 8, 1294 .mas_rpm_id = -1, 1295 .slv_rpm_id = 161, 1296 .qos.ap_owned = true, 1297 .qos.qos_mode = NOC_QOS_MODE_INVALID 1298 }; 1299 1300 static const u16 slv_cnoc_mnoc_mmss_cfg_links[] = { 1301 MSM8996_MASTER_CNOC_MNOC_MMSS_CFG 1302 }; 1303 1304 static struct qcom_icc_node slv_cnoc_mnoc_mmss_cfg = { 1305 .name = "slv_cnoc_mnoc_mmss_cfg", 1306 .id = MSM8996_SLAVE_CNOC_MNOC_MMSS_CFG, 1307 .buswidth = 8, 1308 .mas_rpm_id = -1, 1309 .slv_rpm_id = 58, 1310 .qos.ap_owned = true, 1311 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1312 .num_links = ARRAY_SIZE(slv_cnoc_mnoc_mmss_cfg_links), 1313 .links = slv_cnoc_mnoc_mmss_cfg_links 1314 }; 1315 1316 static struct qcom_icc_node slv_mmagic_cfg = { 1317 .name = "slv_mmagic_cfg", 1318 .id = MSM8996_SLAVE_MMAGIC_CFG, 1319 .buswidth = 8, 1320 .mas_rpm_id = -1, 1321 .slv_rpm_id = 162, 1322 .qos.ap_owned = true, 1323 .qos.qos_mode = NOC_QOS_MODE_INVALID 1324 }; 1325 1326 static struct qcom_icc_node slv_cpr_cfg = { 1327 .name = "slv_cpr_cfg", 1328 .id = MSM8996_SLAVE_CPR_CFG, 1329 .buswidth = 8, 1330 .mas_rpm_id = -1, 1331 .slv_rpm_id = 6, 1332 .qos.ap_owned = true, 1333 .qos.qos_mode = NOC_QOS_MODE_INVALID 1334 }; 1335 1336 static struct qcom_icc_node slv_misc_cfg = { 1337 .name = "slv_misc_cfg", 1338 .id = MSM8996_SLAVE_MISC_CFG, 1339 .buswidth = 8, 1340 .mas_rpm_id = -1, 1341 .slv_rpm_id = 8, 1342 .qos.ap_owned = true, 1343 .qos.qos_mode = NOC_QOS_MODE_INVALID 1344 }; 1345 1346 static struct qcom_icc_node slv_venus_throttle_cfg = { 1347 .name = "slv_venus_throttle_cfg", 1348 .id = MSM8996_SLAVE_VENUS_THROTTLE_CFG, 1349 .buswidth = 8, 1350 .mas_rpm_id = -1, 1351 .slv_rpm_id = 178, 1352 .qos.ap_owned = true, 1353 .qos.qos_mode = NOC_QOS_MODE_INVALID 1354 }; 1355 1356 static struct qcom_icc_node slv_venus_cfg = { 1357 .name = "slv_venus_cfg", 1358 .id = MSM8996_SLAVE_VENUS_CFG, 1359 .buswidth = 8, 1360 .mas_rpm_id = -1, 1361 .slv_rpm_id = 10, 1362 .qos.ap_owned = true, 1363 .qos.qos_mode = NOC_QOS_MODE_INVALID 1364 }; 1365 1366 static struct qcom_icc_node slv_vmem_cfg = { 1367 .name = "slv_vmem_cfg", 1368 .id = MSM8996_SLAVE_VMEM_CFG, 1369 .buswidth = 8, 1370 .mas_rpm_id = -1, 1371 .slv_rpm_id = 180, 1372 .qos.ap_owned = true, 1373 .qos.qos_mode = NOC_QOS_MODE_INVALID 1374 }; 1375 1376 static struct qcom_icc_node slv_dsa_cfg = { 1377 .name = "slv_dsa_cfg", 1378 .id = MSM8996_SLAVE_DSA_CFG, 1379 .buswidth = 8, 1380 .mas_rpm_id = -1, 1381 .slv_rpm_id = 157, 1382 .qos.ap_owned = true, 1383 .qos.qos_mode = NOC_QOS_MODE_INVALID 1384 }; 1385 1386 static struct qcom_icc_node slv_mnoc_clocks_cfg = { 1387 .name = "slv_mnoc_clocks_cfg", 1388 .id = MSM8996_SLAVE_MMSS_CLK_CFG, 1389 .buswidth = 8, 1390 .mas_rpm_id = -1, 1391 .slv_rpm_id = 12, 1392 .qos.ap_owned = true, 1393 .qos.qos_mode = NOC_QOS_MODE_INVALID 1394 }; 1395 1396 static struct qcom_icc_node slv_dsa_mpu_cfg = { 1397 .name = "slv_dsa_mpu_cfg", 1398 .id = MSM8996_SLAVE_DSA_MPU_CFG, 1399 .buswidth = 8, 1400 .mas_rpm_id = -1, 1401 .slv_rpm_id = 158, 1402 .qos.ap_owned = true, 1403 .qos.qos_mode = NOC_QOS_MODE_INVALID 1404 }; 1405 1406 static struct qcom_icc_node slv_mnoc_mpu_cfg = { 1407 .name = "slv_mnoc_mpu_cfg", 1408 .id = MSM8996_SLAVE_MNOC_MPU_CFG, 1409 .buswidth = 8, 1410 .mas_rpm_id = -1, 1411 .slv_rpm_id = 14, 1412 .qos.ap_owned = true, 1413 .qos.qos_mode = NOC_QOS_MODE_INVALID 1414 }; 1415 1416 static struct qcom_icc_node slv_display_cfg = { 1417 .name = "slv_display_cfg", 1418 .id = MSM8996_SLAVE_DISPLAY_CFG, 1419 .buswidth = 8, 1420 .mas_rpm_id = -1, 1421 .slv_rpm_id = 4, 1422 .qos.ap_owned = true, 1423 .qos.qos_mode = NOC_QOS_MODE_INVALID 1424 }; 1425 1426 static struct qcom_icc_node slv_display_throttle_cfg = { 1427 .name = "slv_display_throttle_cfg", 1428 .id = MSM8996_SLAVE_DISPLAY_THROTTLE_CFG, 1429 .buswidth = 8, 1430 .mas_rpm_id = -1, 1431 .slv_rpm_id = 156, 1432 .qos.ap_owned = true, 1433 .qos.qos_mode = NOC_QOS_MODE_INVALID 1434 }; 1435 1436 static struct qcom_icc_node slv_camera_cfg = { 1437 .name = "slv_camera_cfg", 1438 .id = MSM8996_SLAVE_CAMERA_CFG, 1439 .buswidth = 8, 1440 .mas_rpm_id = -1, 1441 .slv_rpm_id = 3, 1442 .qos.ap_owned = true, 1443 .qos.qos_mode = NOC_QOS_MODE_INVALID 1444 }; 1445 1446 static struct qcom_icc_node slv_camera_throttle_cfg = { 1447 .name = "slv_camera_throttle_cfg", 1448 .id = MSM8996_SLAVE_CAMERA_THROTTLE_CFG, 1449 .buswidth = 8, 1450 .mas_rpm_id = -1, 1451 .slv_rpm_id = 154, 1452 .qos.ap_owned = true, 1453 .qos.qos_mode = NOC_QOS_MODE_INVALID 1454 }; 1455 1456 static struct qcom_icc_node slv_oxili_cfg = { 1457 .name = "slv_oxili_cfg", 1458 .id = MSM8996_SLAVE_GRAPHICS_3D_CFG, 1459 .buswidth = 8, 1460 .mas_rpm_id = -1, 1461 .slv_rpm_id = 11, 1462 .qos.ap_owned = true, 1463 .qos.qos_mode = NOC_QOS_MODE_INVALID 1464 }; 1465 1466 static struct qcom_icc_node slv_smmu_mdp_cfg = { 1467 .name = "slv_smmu_mdp_cfg", 1468 .id = MSM8996_SLAVE_SMMU_MDP_CFG, 1469 .buswidth = 8, 1470 .mas_rpm_id = -1, 1471 .slv_rpm_id = 173, 1472 .qos.ap_owned = true, 1473 .qos.qos_mode = NOC_QOS_MODE_INVALID 1474 }; 1475 1476 static struct qcom_icc_node slv_smmu_rot_cfg = { 1477 .name = "slv_smmu_rot_cfg", 1478 .id = MSM8996_SLAVE_SMMU_ROTATOR_CFG, 1479 .buswidth = 8, 1480 .mas_rpm_id = -1, 1481 .slv_rpm_id = 174, 1482 .qos.ap_owned = true, 1483 .qos.qos_mode = NOC_QOS_MODE_INVALID 1484 }; 1485 1486 static struct qcom_icc_node slv_smmu_venus_cfg = { 1487 .name = "slv_smmu_venus_cfg", 1488 .id = MSM8996_SLAVE_SMMU_VENUS_CFG, 1489 .buswidth = 8, 1490 .mas_rpm_id = -1, 1491 .slv_rpm_id = 175, 1492 .qos.ap_owned = true, 1493 .qos.qos_mode = NOC_QOS_MODE_INVALID 1494 }; 1495 1496 static struct qcom_icc_node slv_smmu_cpp_cfg = { 1497 .name = "slv_smmu_cpp_cfg", 1498 .id = MSM8996_SLAVE_SMMU_CPP_CFG, 1499 .buswidth = 8, 1500 .mas_rpm_id = -1, 1501 .slv_rpm_id = 171, 1502 .qos.ap_owned = true, 1503 .qos.qos_mode = NOC_QOS_MODE_INVALID 1504 }; 1505 1506 static struct qcom_icc_node slv_smmu_jpeg_cfg = { 1507 .name = "slv_smmu_jpeg_cfg", 1508 .id = MSM8996_SLAVE_SMMU_JPEG_CFG, 1509 .buswidth = 8, 1510 .mas_rpm_id = -1, 1511 .slv_rpm_id = 172, 1512 .qos.ap_owned = true, 1513 .qos.qos_mode = NOC_QOS_MODE_INVALID 1514 }; 1515 1516 static struct qcom_icc_node slv_smmu_vfe_cfg = { 1517 .name = "slv_smmu_vfe_cfg", 1518 .id = MSM8996_SLAVE_SMMU_VFE_CFG, 1519 .buswidth = 8, 1520 .mas_rpm_id = -1, 1521 .slv_rpm_id = 176, 1522 .qos.ap_owned = true, 1523 .qos.qos_mode = NOC_QOS_MODE_INVALID 1524 }; 1525 1526 static const u16 slv_mnoc_bimc_links[] = { 1527 MSM8996_MASTER_MNOC_BIMC 1528 }; 1529 1530 static struct qcom_icc_node slv_mnoc_bimc = { 1531 .name = "slv_mnoc_bimc", 1532 .id = MSM8996_SLAVE_MNOC_BIMC, 1533 .buswidth = 32, 1534 .mas_rpm_id = -1, 1535 .slv_rpm_id = 16, 1536 .qos.ap_owned = true, 1537 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1538 .num_links = ARRAY_SIZE(slv_mnoc_bimc_links), 1539 .links = slv_mnoc_bimc_links 1540 }; 1541 1542 static struct qcom_icc_node slv_vmem = { 1543 .name = "slv_vmem", 1544 .id = MSM8996_SLAVE_VMEM, 1545 .buswidth = 32, 1546 .mas_rpm_id = -1, 1547 .slv_rpm_id = 179, 1548 .qos.ap_owned = true, 1549 .qos.qos_mode = NOC_QOS_MODE_INVALID 1550 }; 1551 1552 static struct qcom_icc_node slv_srvc_mnoc = { 1553 .name = "slv_srvc_mnoc", 1554 .id = MSM8996_SLAVE_SERVICE_MNOC, 1555 .buswidth = 8, 1556 .mas_rpm_id = -1, 1557 .slv_rpm_id = 17, 1558 .qos.ap_owned = true, 1559 .qos.qos_mode = NOC_QOS_MODE_INVALID 1560 }; 1561 1562 static const u16 slv_pnoc_a1noc_links[] = { 1563 MSM8996_MASTER_PNOC_A1NOC 1564 }; 1565 1566 static struct qcom_icc_node slv_pnoc_a1noc = { 1567 .name = "slv_pnoc_a1noc", 1568 .id = MSM8996_SLAVE_PNOC_A1NOC, 1569 .buswidth = 8, 1570 .mas_rpm_id = -1, 1571 .slv_rpm_id = 139, 1572 .num_links = ARRAY_SIZE(slv_pnoc_a1noc_links), 1573 .links = slv_pnoc_a1noc_links 1574 }; 1575 1576 static struct qcom_icc_node slv_usb_hs = { 1577 .name = "slv_usb_hs", 1578 .id = MSM8996_SLAVE_USB_HS, 1579 .buswidth = 4, 1580 .mas_rpm_id = -1, 1581 .slv_rpm_id = 40 1582 }; 1583 1584 static struct qcom_icc_node slv_sdcc_2 = { 1585 .name = "slv_sdcc_2", 1586 .id = MSM8996_SLAVE_SDCC_2, 1587 .buswidth = 4, 1588 .mas_rpm_id = -1, 1589 .slv_rpm_id = 33 1590 }; 1591 1592 static struct qcom_icc_node slv_sdcc_4 = { 1593 .name = "slv_sdcc_4", 1594 .id = MSM8996_SLAVE_SDCC_4, 1595 .buswidth = 4, 1596 .mas_rpm_id = -1, 1597 .slv_rpm_id = 34 1598 }; 1599 1600 static struct qcom_icc_node slv_tsif = { 1601 .name = "slv_tsif", 1602 .id = MSM8996_SLAVE_TSIF, 1603 .buswidth = 4, 1604 .mas_rpm_id = -1, 1605 .slv_rpm_id = 35 1606 }; 1607 1608 static struct qcom_icc_node slv_blsp_2 = { 1609 .name = "slv_blsp_2", 1610 .id = MSM8996_SLAVE_BLSP_2, 1611 .buswidth = 4, 1612 .mas_rpm_id = -1, 1613 .slv_rpm_id = 37 1614 }; 1615 1616 static struct qcom_icc_node slv_sdcc_1 = { 1617 .name = "slv_sdcc_1", 1618 .id = MSM8996_SLAVE_SDCC_1, 1619 .buswidth = 4, 1620 .mas_rpm_id = -1, 1621 .slv_rpm_id = 31 1622 }; 1623 1624 static struct qcom_icc_node slv_blsp_1 = { 1625 .name = "slv_blsp_1", 1626 .id = MSM8996_SLAVE_BLSP_1, 1627 .buswidth = 4, 1628 .mas_rpm_id = -1, 1629 .slv_rpm_id = 39 1630 }; 1631 1632 static struct qcom_icc_node slv_pdm = { 1633 .name = "slv_pdm", 1634 .id = MSM8996_SLAVE_PDM, 1635 .buswidth = 4, 1636 .mas_rpm_id = -1, 1637 .slv_rpm_id = 41 1638 }; 1639 1640 static struct qcom_icc_node slv_ahb2phy = { 1641 .name = "slv_ahb2phy", 1642 .id = MSM8996_SLAVE_AHB2PHY, 1643 .buswidth = 4, 1644 .mas_rpm_id = -1, 1645 .slv_rpm_id = 153, 1646 .qos.ap_owned = true, 1647 .qos.qos_mode = NOC_QOS_MODE_INVALID 1648 }; 1649 1650 static struct qcom_icc_node slv_hmss = { 1651 .name = "slv_hmss", 1652 .id = MSM8996_SLAVE_APPSS, 1653 .buswidth = 16, 1654 .mas_rpm_id = -1, 1655 .slv_rpm_id = 20, 1656 .qos.ap_owned = true, 1657 .qos.qos_mode = NOC_QOS_MODE_INVALID 1658 }; 1659 1660 static struct qcom_icc_node slv_lpass = { 1661 .name = "slv_lpass", 1662 .id = MSM8996_SLAVE_LPASS, 1663 .buswidth = 16, 1664 .mas_rpm_id = -1, 1665 .slv_rpm_id = 21, 1666 .qos.ap_owned = true, 1667 .qos.qos_mode = NOC_QOS_MODE_INVALID 1668 }; 1669 1670 static struct qcom_icc_node slv_usb3 = { 1671 .name = "slv_usb3", 1672 .id = MSM8996_SLAVE_USB3, 1673 .buswidth = 16, 1674 .mas_rpm_id = -1, 1675 .slv_rpm_id = 22, 1676 .qos.ap_owned = true, 1677 .qos.qos_mode = NOC_QOS_MODE_INVALID 1678 }; 1679 1680 static const u16 slv_snoc_bimc_links[] = { 1681 MSM8996_MASTER_SNOC_BIMC 1682 }; 1683 1684 static struct qcom_icc_node slv_snoc_bimc = { 1685 .name = "slv_snoc_bimc", 1686 .id = MSM8996_SLAVE_SNOC_BIMC, 1687 .buswidth = 32, 1688 .mas_rpm_id = -1, 1689 .slv_rpm_id = 24, 1690 .num_links = ARRAY_SIZE(slv_snoc_bimc_links), 1691 .links = slv_snoc_bimc_links 1692 }; 1693 1694 static const u16 slv_snoc_cnoc_links[] = { 1695 MSM8996_MASTER_SNOC_CNOC 1696 }; 1697 1698 static struct qcom_icc_node slv_snoc_cnoc = { 1699 .name = "slv_snoc_cnoc", 1700 .id = MSM8996_SLAVE_SNOC_CNOC, 1701 .buswidth = 16, 1702 .mas_rpm_id = -1, 1703 .slv_rpm_id = 25, 1704 .num_links = ARRAY_SIZE(slv_snoc_cnoc_links), 1705 .links = slv_snoc_cnoc_links 1706 }; 1707 1708 static struct qcom_icc_node slv_imem = { 1709 .name = "slv_imem", 1710 .id = MSM8996_SLAVE_OCIMEM, 1711 .buswidth = 16, 1712 .mas_rpm_id = -1, 1713 .slv_rpm_id = 26 1714 }; 1715 1716 static struct qcom_icc_node slv_pimem = { 1717 .name = "slv_pimem", 1718 .id = MSM8996_SLAVE_PIMEM, 1719 .buswidth = 16, 1720 .mas_rpm_id = -1, 1721 .slv_rpm_id = 166 1722 }; 1723 1724 static const u16 slv_snoc_vmem_links[] = { 1725 MSM8996_MASTER_SNOC_VMEM 1726 }; 1727 1728 static struct qcom_icc_node slv_snoc_vmem = { 1729 .name = "slv_snoc_vmem", 1730 .id = MSM8996_SLAVE_SNOC_VMEM, 1731 .buswidth = 16, 1732 .mas_rpm_id = -1, 1733 .slv_rpm_id = 140, 1734 .qos.ap_owned = true, 1735 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1736 .num_links = ARRAY_SIZE(slv_snoc_vmem_links), 1737 .links = slv_snoc_vmem_links 1738 }; 1739 1740 static const u16 slv_snoc_pnoc_links[] = { 1741 MSM8996_MASTER_SNOC_PNOC 1742 }; 1743 1744 static struct qcom_icc_node slv_snoc_pnoc = { 1745 .name = "slv_snoc_pnoc", 1746 .id = MSM8996_SLAVE_SNOC_PNOC, 1747 .buswidth = 16, 1748 .mas_rpm_id = -1, 1749 .slv_rpm_id = 28, 1750 .num_links = ARRAY_SIZE(slv_snoc_pnoc_links), 1751 .links = slv_snoc_pnoc_links 1752 }; 1753 1754 static struct qcom_icc_node slv_qdss_stm = { 1755 .name = "slv_qdss_stm", 1756 .id = MSM8996_SLAVE_QDSS_STM, 1757 .buswidth = 16, 1758 .mas_rpm_id = -1, 1759 .slv_rpm_id = 30 1760 }; 1761 1762 static struct qcom_icc_node slv_pcie_0 = { 1763 .name = "slv_pcie_0", 1764 .id = MSM8996_SLAVE_PCIE_0, 1765 .buswidth = 16, 1766 .mas_rpm_id = -1, 1767 .slv_rpm_id = 84, 1768 .qos.ap_owned = true, 1769 .qos.qos_mode = NOC_QOS_MODE_INVALID 1770 }; 1771 1772 static struct qcom_icc_node slv_pcie_1 = { 1773 .name = "slv_pcie_1", 1774 .id = MSM8996_SLAVE_PCIE_1, 1775 .buswidth = 16, 1776 .mas_rpm_id = -1, 1777 .slv_rpm_id = 85, 1778 .qos.ap_owned = true, 1779 .qos.qos_mode = NOC_QOS_MODE_INVALID 1780 }; 1781 1782 static struct qcom_icc_node slv_pcie_2 = { 1783 .name = "slv_pcie_2", 1784 .id = MSM8996_SLAVE_PCIE_2, 1785 .buswidth = 16, 1786 .mas_rpm_id = -1, 1787 .slv_rpm_id = 164, 1788 .qos.ap_owned = true, 1789 .qos.qos_mode = NOC_QOS_MODE_INVALID 1790 }; 1791 1792 static struct qcom_icc_node slv_srvc_snoc = { 1793 .name = "slv_srvc_snoc", 1794 .id = MSM8996_SLAVE_SERVICE_SNOC, 1795 .buswidth = 16, 1796 .mas_rpm_id = -1, 1797 .slv_rpm_id = 29, 1798 .qos.ap_owned = true, 1799 .qos.qos_mode = NOC_QOS_MODE_INVALID 1800 }; 1801 1802 static struct qcom_icc_node * const a0noc_nodes[] = { 1803 [MASTER_PCIE_0] = &mas_pcie_0, 1804 [MASTER_PCIE_1] = &mas_pcie_1, 1805 [MASTER_PCIE_2] = &mas_pcie_2 1806 }; 1807 1808 static const struct regmap_config msm8996_a0noc_regmap_config = { 1809 .reg_bits = 32, 1810 .reg_stride = 4, 1811 .val_bits = 32, 1812 .max_register = 0x6000, 1813 .fast_io = true 1814 }; 1815 1816 static const struct qcom_icc_desc msm8996_a0noc = { 1817 .type = QCOM_ICC_NOC, 1818 .nodes = a0noc_nodes, 1819 .num_nodes = ARRAY_SIZE(a0noc_nodes), 1820 .intf_clocks = a0noc_intf_clocks, 1821 .num_intf_clocks = ARRAY_SIZE(a0noc_intf_clocks), 1822 .regmap_cfg = &msm8996_a0noc_regmap_config 1823 }; 1824 1825 static struct qcom_icc_node * const a1noc_nodes[] = { 1826 [MASTER_CNOC_A1NOC] = &mas_cnoc_a1noc, 1827 [MASTER_CRYPTO_CORE0] = &mas_crypto_c0, 1828 [MASTER_PNOC_A1NOC] = &mas_pnoc_a1noc 1829 }; 1830 1831 static const struct regmap_config msm8996_a1noc_regmap_config = { 1832 .reg_bits = 32, 1833 .reg_stride = 4, 1834 .val_bits = 32, 1835 .max_register = 0x5000, 1836 .fast_io = true 1837 }; 1838 1839 static const struct qcom_icc_desc msm8996_a1noc = { 1840 .type = QCOM_ICC_NOC, 1841 .nodes = a1noc_nodes, 1842 .num_nodes = ARRAY_SIZE(a1noc_nodes), 1843 .bus_clk_desc = &aggre1_branch_clk, 1844 .regmap_cfg = &msm8996_a1noc_regmap_config 1845 }; 1846 1847 static struct qcom_icc_node * const a2noc_nodes[] = { 1848 [MASTER_USB3] = &mas_usb3, 1849 [MASTER_IPA] = &mas_ipa, 1850 [MASTER_UFS] = &mas_ufs 1851 }; 1852 1853 static const struct regmap_config msm8996_a2noc_regmap_config = { 1854 .reg_bits = 32, 1855 .reg_stride = 4, 1856 .val_bits = 32, 1857 .max_register = 0x7000, 1858 .fast_io = true 1859 }; 1860 1861 static const struct qcom_icc_desc msm8996_a2noc = { 1862 .type = QCOM_ICC_NOC, 1863 .nodes = a2noc_nodes, 1864 .num_nodes = ARRAY_SIZE(a2noc_nodes), 1865 .bus_clk_desc = &aggre2_branch_clk, 1866 .intf_clocks = a2noc_intf_clocks, 1867 .num_intf_clocks = ARRAY_SIZE(a2noc_intf_clocks), 1868 .regmap_cfg = &msm8996_a2noc_regmap_config 1869 }; 1870 1871 static struct qcom_icc_node * const bimc_nodes[] = { 1872 [MASTER_AMPSS_M0] = &mas_apps_proc, 1873 [MASTER_GRAPHICS_3D] = &mas_oxili, 1874 [MASTER_MNOC_BIMC] = &mas_mnoc_bimc, 1875 [MASTER_SNOC_BIMC] = &mas_snoc_bimc, 1876 [SLAVE_EBI_CH0] = &slv_ebi, 1877 [SLAVE_HMSS_L3] = &slv_hmss_l3, 1878 [SLAVE_BIMC_SNOC_0] = &slv_bimc_snoc_0, 1879 [SLAVE_BIMC_SNOC_1] = &slv_bimc_snoc_1 1880 }; 1881 1882 static const struct regmap_config msm8996_bimc_regmap_config = { 1883 .reg_bits = 32, 1884 .reg_stride = 4, 1885 .val_bits = 32, 1886 .max_register = 0x5a000, 1887 .fast_io = true 1888 }; 1889 1890 static const struct qcom_icc_desc msm8996_bimc = { 1891 .type = QCOM_ICC_BIMC, 1892 .nodes = bimc_nodes, 1893 .num_nodes = ARRAY_SIZE(bimc_nodes), 1894 .bus_clk_desc = &bimc_clk, 1895 .regmap_cfg = &msm8996_bimc_regmap_config, 1896 .ab_coeff = 154, 1897 }; 1898 1899 static struct qcom_icc_node * const cnoc_nodes[] = { 1900 [MASTER_SNOC_CNOC] = &mas_snoc_cnoc, 1901 [MASTER_QDSS_DAP] = &mas_qdss_dap, 1902 [SLAVE_CNOC_A1NOC] = &slv_cnoc_a1noc, 1903 [SLAVE_CLK_CTL] = &slv_clk_ctl, 1904 [SLAVE_TCSR] = &slv_tcsr, 1905 [SLAVE_TLMM] = &slv_tlmm, 1906 [SLAVE_CRYPTO_0_CFG] = &slv_crypto0_cfg, 1907 [SLAVE_MPM] = &slv_mpm, 1908 [SLAVE_PIMEM_CFG] = &slv_pimem_cfg, 1909 [SLAVE_IMEM_CFG] = &slv_imem_cfg, 1910 [SLAVE_MESSAGE_RAM] = &slv_message_ram, 1911 [SLAVE_BIMC_CFG] = &slv_bimc_cfg, 1912 [SLAVE_PMIC_ARB] = &slv_pmic_arb, 1913 [SLAVE_PRNG] = &slv_prng, 1914 [SLAVE_DCC_CFG] = &slv_dcc_cfg, 1915 [SLAVE_RBCPR_MX] = &slv_rbcpr_mx, 1916 [SLAVE_QDSS_CFG] = &slv_qdss_cfg, 1917 [SLAVE_RBCPR_CX] = &slv_rbcpr_cx, 1918 [SLAVE_QDSS_RBCPR_APU] = &slv_cpu_apu_cfg, 1919 [SLAVE_CNOC_MNOC_CFG] = &slv_cnoc_mnoc_cfg, 1920 [SLAVE_SNOC_CFG] = &slv_snoc_cfg, 1921 [SLAVE_SNOC_MPU_CFG] = &slv_snoc_mpu_cfg, 1922 [SLAVE_EBI1_PHY_CFG] = &slv_ebi1_phy_cfg, 1923 [SLAVE_A0NOC_CFG] = &slv_a0noc_cfg, 1924 [SLAVE_PCIE_1_CFG] = &slv_pcie_1_cfg, 1925 [SLAVE_PCIE_2_CFG] = &slv_pcie_2_cfg, 1926 [SLAVE_PCIE_0_CFG] = &slv_pcie_0_cfg, 1927 [SLAVE_PCIE20_AHB2PHY] = &slv_pcie20_ahb2phy, 1928 [SLAVE_A0NOC_MPU_CFG] = &slv_a0noc_mpu_cfg, 1929 [SLAVE_UFS_CFG] = &slv_ufs_cfg, 1930 [SLAVE_A1NOC_CFG] = &slv_a1noc_cfg, 1931 [SLAVE_A1NOC_MPU_CFG] = &slv_a1noc_mpu_cfg, 1932 [SLAVE_A2NOC_CFG] = &slv_a2noc_cfg, 1933 [SLAVE_A2NOC_MPU_CFG] = &slv_a2noc_mpu_cfg, 1934 [SLAVE_SSC_CFG] = &slv_ssc_cfg, 1935 [SLAVE_A0NOC_SMMU_CFG] = &slv_a0noc_smmu_cfg, 1936 [SLAVE_A1NOC_SMMU_CFG] = &slv_a1noc_smmu_cfg, 1937 [SLAVE_A2NOC_SMMU_CFG] = &slv_a2noc_smmu_cfg, 1938 [SLAVE_LPASS_SMMU_CFG] = &slv_lpass_smmu_cfg, 1939 [SLAVE_CNOC_MNOC_MMSS_CFG] = &slv_cnoc_mnoc_mmss_cfg 1940 }; 1941 1942 static const struct regmap_config msm8996_cnoc_regmap_config = { 1943 .reg_bits = 32, 1944 .reg_stride = 4, 1945 .val_bits = 32, 1946 .max_register = 0x1000, 1947 .fast_io = true 1948 }; 1949 1950 static const struct qcom_icc_desc msm8996_cnoc = { 1951 .type = QCOM_ICC_NOC, 1952 .nodes = cnoc_nodes, 1953 .num_nodes = ARRAY_SIZE(cnoc_nodes), 1954 .bus_clk_desc = &bus_2_clk, 1955 .regmap_cfg = &msm8996_cnoc_regmap_config 1956 }; 1957 1958 static struct qcom_icc_node * const mnoc_nodes[] = { 1959 [MASTER_CNOC_MNOC_CFG] = &mas_cnoc_mnoc_cfg, 1960 [MASTER_CPP] = &mas_cpp, 1961 [MASTER_JPEG] = &mas_jpeg, 1962 [MASTER_MDP_PORT0] = &mas_mdp_p0, 1963 [MASTER_MDP_PORT1] = &mas_mdp_p1, 1964 [MASTER_ROTATOR] = &mas_rotator, 1965 [MASTER_VIDEO_P0] = &mas_venus, 1966 [MASTER_VFE] = &mas_vfe, 1967 [MASTER_SNOC_VMEM] = &mas_snoc_vmem, 1968 [MASTER_VIDEO_P0_OCMEM] = &mas_venus_vmem, 1969 [MASTER_CNOC_MNOC_MMSS_CFG] = &mas_cnoc_mnoc_mmss_cfg, 1970 [SLAVE_MNOC_BIMC] = &slv_mnoc_bimc, 1971 [SLAVE_VMEM] = &slv_vmem, 1972 [SLAVE_SERVICE_MNOC] = &slv_srvc_mnoc, 1973 [SLAVE_MMAGIC_CFG] = &slv_mmagic_cfg, 1974 [SLAVE_CPR_CFG] = &slv_cpr_cfg, 1975 [SLAVE_MISC_CFG] = &slv_misc_cfg, 1976 [SLAVE_VENUS_THROTTLE_CFG] = &slv_venus_throttle_cfg, 1977 [SLAVE_VENUS_CFG] = &slv_venus_cfg, 1978 [SLAVE_VMEM_CFG] = &slv_vmem_cfg, 1979 [SLAVE_DSA_CFG] = &slv_dsa_cfg, 1980 [SLAVE_MMSS_CLK_CFG] = &slv_mnoc_clocks_cfg, 1981 [SLAVE_DSA_MPU_CFG] = &slv_dsa_mpu_cfg, 1982 [SLAVE_MNOC_MPU_CFG] = &slv_mnoc_mpu_cfg, 1983 [SLAVE_DISPLAY_CFG] = &slv_display_cfg, 1984 [SLAVE_DISPLAY_THROTTLE_CFG] = &slv_display_throttle_cfg, 1985 [SLAVE_CAMERA_CFG] = &slv_camera_cfg, 1986 [SLAVE_CAMERA_THROTTLE_CFG] = &slv_camera_throttle_cfg, 1987 [SLAVE_GRAPHICS_3D_CFG] = &slv_oxili_cfg, 1988 [SLAVE_SMMU_MDP_CFG] = &slv_smmu_mdp_cfg, 1989 [SLAVE_SMMU_ROT_CFG] = &slv_smmu_rot_cfg, 1990 [SLAVE_SMMU_VENUS_CFG] = &slv_smmu_venus_cfg, 1991 [SLAVE_SMMU_CPP_CFG] = &slv_smmu_cpp_cfg, 1992 [SLAVE_SMMU_JPEG_CFG] = &slv_smmu_jpeg_cfg, 1993 [SLAVE_SMMU_VFE_CFG] = &slv_smmu_vfe_cfg 1994 }; 1995 1996 static const struct regmap_config msm8996_mnoc_regmap_config = { 1997 .reg_bits = 32, 1998 .reg_stride = 4, 1999 .val_bits = 32, 2000 .max_register = 0x1c000, 2001 .fast_io = true 2002 }; 2003 2004 static const struct qcom_icc_desc msm8996_mnoc = { 2005 .type = QCOM_ICC_NOC, 2006 .nodes = mnoc_nodes, 2007 .num_nodes = ARRAY_SIZE(mnoc_nodes), 2008 .bus_clk_desc = &mmaxi_0_clk, 2009 .intf_clocks = mm_intf_clocks, 2010 .num_intf_clocks = ARRAY_SIZE(mm_intf_clocks), 2011 .regmap_cfg = &msm8996_mnoc_regmap_config, 2012 .ab_coeff = 154, 2013 }; 2014 2015 static struct qcom_icc_node * const pnoc_nodes[] = { 2016 [MASTER_SNOC_PNOC] = &mas_snoc_pnoc, 2017 [MASTER_SDCC_1] = &mas_sdcc_1, 2018 [MASTER_SDCC_2] = &mas_sdcc_2, 2019 [MASTER_SDCC_4] = &mas_sdcc_4, 2020 [MASTER_USB_HS] = &mas_usb_hs, 2021 [MASTER_BLSP_1] = &mas_blsp_1, 2022 [MASTER_BLSP_2] = &mas_blsp_2, 2023 [MASTER_TSIF] = &mas_tsif, 2024 [SLAVE_PNOC_A1NOC] = &slv_pnoc_a1noc, 2025 [SLAVE_USB_HS] = &slv_usb_hs, 2026 [SLAVE_SDCC_2] = &slv_sdcc_2, 2027 [SLAVE_SDCC_4] = &slv_sdcc_4, 2028 [SLAVE_TSIF] = &slv_tsif, 2029 [SLAVE_BLSP_2] = &slv_blsp_2, 2030 [SLAVE_SDCC_1] = &slv_sdcc_1, 2031 [SLAVE_BLSP_1] = &slv_blsp_1, 2032 [SLAVE_PDM] = &slv_pdm, 2033 [SLAVE_AHB2PHY] = &slv_ahb2phy 2034 }; 2035 2036 static const struct regmap_config msm8996_pnoc_regmap_config = { 2037 .reg_bits = 32, 2038 .reg_stride = 4, 2039 .val_bits = 32, 2040 .max_register = 0x3000, 2041 .fast_io = true 2042 }; 2043 2044 static const struct qcom_icc_desc msm8996_pnoc = { 2045 .type = QCOM_ICC_NOC, 2046 .nodes = pnoc_nodes, 2047 .num_nodes = ARRAY_SIZE(pnoc_nodes), 2048 .bus_clk_desc = &bus_0_clk, 2049 .regmap_cfg = &msm8996_pnoc_regmap_config 2050 }; 2051 2052 static struct qcom_icc_node * const snoc_nodes[] = { 2053 [MASTER_HMSS] = &mas_hmss, 2054 [MASTER_QDSS_BAM] = &mas_qdss_bam, 2055 [MASTER_SNOC_CFG] = &mas_snoc_cfg, 2056 [MASTER_BIMC_SNOC_0] = &mas_bimc_snoc_0, 2057 [MASTER_BIMC_SNOC_1] = &mas_bimc_snoc_1, 2058 [MASTER_A0NOC_SNOC] = &mas_a0noc_snoc, 2059 [MASTER_A1NOC_SNOC] = &mas_a1noc_snoc, 2060 [MASTER_A2NOC_SNOC] = &mas_a2noc_snoc, 2061 [MASTER_QDSS_ETR] = &mas_qdss_etr, 2062 [SLAVE_A0NOC_SNOC] = &slv_a0noc_snoc, 2063 [SLAVE_A1NOC_SNOC] = &slv_a1noc_snoc, 2064 [SLAVE_A2NOC_SNOC] = &slv_a2noc_snoc, 2065 [SLAVE_HMSS] = &slv_hmss, 2066 [SLAVE_LPASS] = &slv_lpass, 2067 [SLAVE_USB3] = &slv_usb3, 2068 [SLAVE_SNOC_BIMC] = &slv_snoc_bimc, 2069 [SLAVE_SNOC_CNOC] = &slv_snoc_cnoc, 2070 [SLAVE_IMEM] = &slv_imem, 2071 [SLAVE_PIMEM] = &slv_pimem, 2072 [SLAVE_SNOC_VMEM] = &slv_snoc_vmem, 2073 [SLAVE_SNOC_PNOC] = &slv_snoc_pnoc, 2074 [SLAVE_QDSS_STM] = &slv_qdss_stm, 2075 [SLAVE_PCIE_0] = &slv_pcie_0, 2076 [SLAVE_PCIE_1] = &slv_pcie_1, 2077 [SLAVE_PCIE_2] = &slv_pcie_2, 2078 [SLAVE_SERVICE_SNOC] = &slv_srvc_snoc 2079 }; 2080 2081 static const struct regmap_config msm8996_snoc_regmap_config = { 2082 .reg_bits = 32, 2083 .reg_stride = 4, 2084 .val_bits = 32, 2085 .max_register = 0x20000, 2086 .fast_io = true 2087 }; 2088 2089 static const struct qcom_icc_desc msm8996_snoc = { 2090 .type = QCOM_ICC_NOC, 2091 .nodes = snoc_nodes, 2092 .num_nodes = ARRAY_SIZE(snoc_nodes), 2093 .bus_clk_desc = &bus_1_clk, 2094 .regmap_cfg = &msm8996_snoc_regmap_config 2095 }; 2096 2097 static const struct of_device_id qnoc_of_match[] = { 2098 { .compatible = "qcom,msm8996-a0noc", .data = &msm8996_a0noc}, 2099 { .compatible = "qcom,msm8996-a1noc", .data = &msm8996_a1noc}, 2100 { .compatible = "qcom,msm8996-a2noc", .data = &msm8996_a2noc}, 2101 { .compatible = "qcom,msm8996-bimc", .data = &msm8996_bimc}, 2102 { .compatible = "qcom,msm8996-cnoc", .data = &msm8996_cnoc}, 2103 { .compatible = "qcom,msm8996-mnoc", .data = &msm8996_mnoc}, 2104 { .compatible = "qcom,msm8996-pnoc", .data = &msm8996_pnoc}, 2105 { .compatible = "qcom,msm8996-snoc", .data = &msm8996_snoc}, 2106 { } 2107 }; 2108 MODULE_DEVICE_TABLE(of, qnoc_of_match); 2109 2110 static struct platform_driver qnoc_driver = { 2111 .probe = qnoc_probe, 2112 .remove = qnoc_remove, 2113 .driver = { 2114 .name = "qnoc-msm8996", 2115 .of_match_table = qnoc_of_match, 2116 .sync_state = icc_sync_state, 2117 } 2118 }; 2119 static int __init qnoc_driver_init(void) 2120 { 2121 return platform_driver_register(&qnoc_driver); 2122 } 2123 core_initcall(qnoc_driver_init); 2124 2125 static void __exit qnoc_driver_exit(void) 2126 { 2127 platform_driver_unregister(&qnoc_driver); 2128 } 2129 module_exit(qnoc_driver_exit); 2130 2131 MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>"); 2132 MODULE_DESCRIPTION("Qualcomm MSM8996 NoC driver"); 2133 MODULE_LICENSE("GPL v2"); 2134