1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Based on data from msm8976-bus.dtsi in Qualcomm's msm-3.10 release: 4 * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. 5 */ 6 7 #include <linux/device.h> 8 #include <linux/interconnect-provider.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 #include <linux/regmap.h> 12 13 #include <dt-bindings/interconnect/qcom,msm8976.h> 14 15 #include "icc-rpm.h" 16 17 enum { 18 QNOC_MASTER_AMPSS_M0 = 1, 19 QNOC_MNOC_BIMC_MAS, 20 QNOC_SNOC_BIMC_MAS, 21 QNOC_MASTER_TCU_0, 22 QNOC_MASTER_USB_HS2, 23 QNOC_MASTER_BLSP_1, 24 QNOC_MASTER_USB_HS, 25 QNOC_MASTER_BLSP_2, 26 QNOC_MASTER_CRYPTO_CORE0, 27 QNOC_MASTER_SDCC_1, 28 QNOC_MASTER_SDCC_2, 29 QNOC_MASTER_SDCC_3, 30 QNOC_SNOC_PNOC_MAS, 31 QNOC_MASTER_LPASS_AHB, 32 QNOC_MASTER_SPDM, 33 QNOC_MASTER_DEHR, 34 QNOC_MASTER_XM_USB_HS1, 35 QNOC_MASTER_QDSS_BAM, 36 QNOC_BIMC_SNOC_MAS, 37 QNOC_MASTER_JPEG, 38 QNOC_MASTER_GRAPHICS_3D, 39 QNOC_MASTER_MDP_PORT0, 40 QNOC_MASTER_MDP_PORT1, 41 QNOC_PNOC_SNOC_MAS, 42 QNOC_MASTER_VIDEO_P0, 43 QNOC_MASTER_VIDEO_P1, 44 QNOC_MASTER_VFE0, 45 QNOC_MASTER_VFE1, 46 QNOC_MASTER_CPP, 47 QNOC_MASTER_QDSS_ETR, 48 QNOC_MASTER_LPASS_PROC, 49 QNOC_MASTER_IPA, 50 QNOC_PNOC_M_0, 51 QNOC_PNOC_M_1, 52 QNOC_PNOC_INT_0, 53 QNOC_PNOC_INT_1, 54 QNOC_PNOC_INT_2, 55 QNOC_PNOC_SLV_1, 56 QNOC_PNOC_SLV_2, 57 QNOC_PNOC_SLV_3, 58 QNOC_PNOC_SLV_4, 59 QNOC_PNOC_SLV_8, 60 QNOC_PNOC_SLV_9, 61 QNOC_SNOC_MM_INT_0, 62 QNOC_SNOC_QDSS_INT, 63 QNOC_SNOC_INT_0, 64 QNOC_SNOC_INT_1, 65 QNOC_SNOC_INT_2, 66 QNOC_SLAVE_EBI_CH0, 67 QNOC_BIMC_SNOC_SLV, 68 QNOC_SLAVE_TCSR, 69 QNOC_SLAVE_TLMM, 70 QNOC_SLAVE_CRYPTO_0_CFG, 71 QNOC_SLAVE_MESSAGE_RAM, 72 QNOC_SLAVE_PDM, 73 QNOC_SLAVE_PRNG, 74 QNOC_SLAVE_PMIC_ARB, 75 QNOC_SLAVE_SNOC_CFG, 76 QNOC_SLAVE_DCC_CFG, 77 QNOC_SLAVE_CAMERA_CFG, 78 QNOC_SLAVE_DISPLAY_CFG, 79 QNOC_SLAVE_VENUS_CFG, 80 QNOC_SLAVE_SDCC_1, 81 QNOC_SLAVE_BLSP_1, 82 QNOC_SLAVE_USB_HS, 83 QNOC_SLAVE_SDCC_3, 84 QNOC_SLAVE_SDCC_2, 85 QNOC_SLAVE_GRAPHICS_3D_CFG, 86 QNOC_SLAVE_USB_HS2, 87 QNOC_SLAVE_BLSP_2, 88 QNOC_PNOC_SNOC_SLV, 89 QNOC_SLAVE_APPSS, 90 QNOC_MNOC_BIMC_SLV, 91 QNOC_SNOC_BIMC_SLV, 92 QNOC_SLAVE_SYSTEM_IMEM, 93 QNOC_SNOC_PNOC_SLV, 94 QNOC_SLAVE_QDSS_STM, 95 QNOC_SLAVE_CATS_128, 96 QNOC_SLAVE_OCMEM_64, 97 QNOC_SLAVE_LPASS, 98 }; 99 100 static const u16 mas_apps_proc_links[] = { 101 QNOC_SLAVE_EBI_CH0, 102 QNOC_BIMC_SNOC_SLV 103 }; 104 105 static struct qcom_icc_node mas_apps_proc = { 106 .name = "mas_apps_proc", 107 .id = QNOC_MASTER_AMPSS_M0, 108 .buswidth = 16, 109 .mas_rpm_id = 0, 110 .slv_rpm_id = -1, 111 .qos.ap_owned = true, 112 .qos.qos_mode = NOC_QOS_MODE_FIXED, 113 .qos.areq_prio = 0, 114 .qos.prio_level = 0, 115 .qos.qos_port = 0, 116 .num_links = ARRAY_SIZE(mas_apps_proc_links), 117 .links = mas_apps_proc_links, 118 }; 119 120 static const u16 mas_smmnoc_bimc_links[] = { 121 QNOC_SLAVE_EBI_CH0 122 }; 123 124 static struct qcom_icc_node mas_smmnoc_bimc = { 125 .name = "mas_smmnoc_bimc", 126 .id = QNOC_MNOC_BIMC_MAS, 127 .channels = 2, 128 .buswidth = 16, 129 .mas_rpm_id = 135, 130 .slv_rpm_id = -1, 131 .qos.ap_owned = true, 132 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 133 .qos.areq_prio = 0, 134 .qos.prio_level = 0, 135 .qos.qos_port = 2, 136 .num_links = ARRAY_SIZE(mas_smmnoc_bimc_links), 137 .links = mas_smmnoc_bimc_links, 138 }; 139 140 static const u16 mas_snoc_bimc_links[] = { 141 QNOC_SLAVE_EBI_CH0 142 }; 143 144 static struct qcom_icc_node mas_snoc_bimc = { 145 .name = "mas_snoc_bimc", 146 .id = QNOC_SNOC_BIMC_MAS, 147 .channels = 2, 148 .buswidth = 16, 149 .mas_rpm_id = 3, 150 .slv_rpm_id = -1, 151 .qos.ap_owned = true, 152 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 153 .qos.areq_prio = 0, 154 .qos.prio_level = 0, 155 .qos.qos_port = 3, 156 .num_links = ARRAY_SIZE(mas_snoc_bimc_links), 157 .links = mas_snoc_bimc_links, 158 }; 159 160 static const u16 mas_tcu_0_links[] = { 161 QNOC_SLAVE_EBI_CH0, 162 QNOC_BIMC_SNOC_SLV 163 }; 164 165 static struct qcom_icc_node mas_tcu_0 = { 166 .name = "mas_tcu_0", 167 .id = QNOC_MASTER_TCU_0, 168 .buswidth = 16, 169 .mas_rpm_id = 102, 170 .slv_rpm_id = -1, 171 .qos.ap_owned = true, 172 .qos.qos_mode = NOC_QOS_MODE_FIXED, 173 .qos.areq_prio = 0, 174 .qos.prio_level = 2, 175 .qos.qos_port = 4, 176 .num_links = ARRAY_SIZE(mas_tcu_0_links), 177 .links = mas_tcu_0_links, 178 }; 179 180 static const u16 mas_usb_hs2_links[] = { 181 QNOC_PNOC_M_0 182 }; 183 184 static struct qcom_icc_node mas_usb_hs2 = { 185 .name = "mas_usb_hs2", 186 .id = QNOC_MASTER_USB_HS2, 187 .buswidth = 4, 188 .mas_rpm_id = 57, 189 .slv_rpm_id = -1, 190 .num_links = ARRAY_SIZE(mas_usb_hs2_links), 191 .links = mas_usb_hs2_links, 192 }; 193 194 static const u16 mas_blsp_1_links[] = { 195 QNOC_PNOC_M_1 196 }; 197 198 static struct qcom_icc_node mas_blsp_1 = { 199 .name = "mas_blsp_1", 200 .id = QNOC_MASTER_BLSP_1, 201 .buswidth = 4, 202 .mas_rpm_id = 41, 203 .slv_rpm_id = -1, 204 .num_links = ARRAY_SIZE(mas_blsp_1_links), 205 .links = mas_blsp_1_links, 206 }; 207 208 static const u16 mas_usb_hs1_links[] = { 209 QNOC_PNOC_M_1 210 }; 211 212 static struct qcom_icc_node mas_usb_hs1 = { 213 .name = "mas_usb_hs1", 214 .id = QNOC_MASTER_USB_HS, 215 .buswidth = 4, 216 .mas_rpm_id = 42, 217 .slv_rpm_id = -1, 218 .num_links = ARRAY_SIZE(mas_usb_hs1_links), 219 .links = mas_usb_hs1_links, 220 }; 221 222 static const u16 mas_blsp_2_links[] = { 223 QNOC_PNOC_M_1 224 }; 225 226 static struct qcom_icc_node mas_blsp_2 = { 227 .name = "mas_blsp_2", 228 .id = QNOC_MASTER_BLSP_2, 229 .buswidth = 4, 230 .mas_rpm_id = 39, 231 .slv_rpm_id = -1, 232 .num_links = ARRAY_SIZE(mas_blsp_2_links), 233 .links = mas_blsp_2_links, 234 }; 235 236 static const u16 mas_crypto_links[] = { 237 QNOC_PNOC_INT_1 238 }; 239 240 static struct qcom_icc_node mas_crypto = { 241 .name = "mas_crypto", 242 .id = QNOC_MASTER_CRYPTO_CORE0, 243 .buswidth = 8, 244 .mas_rpm_id = 23, 245 .slv_rpm_id = -1, 246 .qos.ap_owned = true, 247 .qos.qos_mode = NOC_QOS_MODE_FIXED, 248 .qos.areq_prio = 0, 249 .qos.prio_level = 0, 250 .qos.qos_port = 0, 251 .num_links = ARRAY_SIZE(mas_crypto_links), 252 .links = mas_crypto_links, 253 }; 254 255 static const u16 mas_sdcc_1_links[] = { 256 QNOC_PNOC_INT_1 257 }; 258 259 static struct qcom_icc_node mas_sdcc_1 = { 260 .name = "mas_sdcc_1", 261 .id = QNOC_MASTER_SDCC_1, 262 .buswidth = 8, 263 .mas_rpm_id = 33, 264 .slv_rpm_id = -1, 265 .qos.qos_mode = NOC_QOS_MODE_FIXED, 266 .qos.areq_prio = 0, 267 .qos.prio_level = 0, 268 .qos.qos_port = 7, 269 .num_links = ARRAY_SIZE(mas_sdcc_1_links), 270 .links = mas_sdcc_1_links, 271 }; 272 273 static const u16 mas_sdcc_2_links[] = { 274 QNOC_PNOC_INT_1 275 }; 276 277 static struct qcom_icc_node mas_sdcc_2 = { 278 .name = "mas_sdcc_2", 279 .id = QNOC_MASTER_SDCC_2, 280 .buswidth = 8, 281 .mas_rpm_id = 35, 282 .slv_rpm_id = -1, 283 .qos.qos_mode = NOC_QOS_MODE_FIXED, 284 .qos.areq_prio = 0, 285 .qos.prio_level = 0, 286 .qos.qos_port = 8, 287 .num_links = ARRAY_SIZE(mas_sdcc_2_links), 288 .links = mas_sdcc_2_links, 289 }; 290 291 static const u16 mas_sdcc_3_links[] = { 292 QNOC_PNOC_INT_1 293 }; 294 295 static struct qcom_icc_node mas_sdcc_3 = { 296 .name = "mas_sdcc_3", 297 .id = QNOC_MASTER_SDCC_3, 298 .buswidth = 8, 299 .mas_rpm_id = 34, 300 .slv_rpm_id = -1, 301 .qos.qos_mode = NOC_QOS_MODE_FIXED, 302 .qos.areq_prio = 0, 303 .qos.prio_level = 0, 304 .qos.qos_port = 10, 305 .num_links = ARRAY_SIZE(mas_sdcc_3_links), 306 .links = mas_sdcc_3_links, 307 }; 308 309 static const u16 mas_snoc_pcnoc_links[] = { 310 QNOC_PNOC_INT_2 311 }; 312 313 static struct qcom_icc_node mas_snoc_pcnoc = { 314 .name = "mas_snoc_pcnoc", 315 .id = QNOC_SNOC_PNOC_MAS, 316 .buswidth = 8, 317 .mas_rpm_id = 77, 318 .slv_rpm_id = -1, 319 .qos.qos_mode = NOC_QOS_MODE_FIXED, 320 .qos.areq_prio = 0, 321 .qos.prio_level = 0, 322 .qos.qos_port = 9, 323 .num_links = ARRAY_SIZE(mas_snoc_pcnoc_links), 324 .links = mas_snoc_pcnoc_links, 325 }; 326 327 static const u16 mas_lpass_ahb_links[] = { 328 QNOC_PNOC_SNOC_SLV 329 }; 330 331 static struct qcom_icc_node mas_lpass_ahb = { 332 .name = "mas_lpass_ahb", 333 .id = QNOC_MASTER_LPASS_AHB, 334 .buswidth = 8, 335 .mas_rpm_id = 18, 336 .slv_rpm_id = -1, 337 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 338 .qos.areq_prio = 0, 339 .qos.prio_level = 0, 340 .qos.qos_port = 12, 341 .num_links = ARRAY_SIZE(mas_lpass_ahb_links), 342 .links = mas_lpass_ahb_links, 343 }; 344 345 static const u16 mas_spdm_links[] = { 346 QNOC_PNOC_M_0 347 }; 348 349 static struct qcom_icc_node mas_spdm = { 350 .name = "mas_spdm", 351 .id = QNOC_MASTER_SPDM, 352 .buswidth = 4, 353 .mas_rpm_id = -1, 354 .slv_rpm_id = -1, 355 .num_links = ARRAY_SIZE(mas_spdm_links), 356 .links = mas_spdm_links, 357 }; 358 359 static const u16 mas_dehr_links[] = { 360 QNOC_PNOC_M_0 361 }; 362 363 static struct qcom_icc_node mas_dehr = { 364 .name = "mas_dehr", 365 .id = QNOC_MASTER_DEHR, 366 .buswidth = 4, 367 .mas_rpm_id = -1, 368 .slv_rpm_id = -1, 369 .num_links = ARRAY_SIZE(mas_dehr_links), 370 .links = mas_dehr_links, 371 }; 372 373 static const u16 mas_xm_usb_hs1_links[] = { 374 QNOC_PNOC_INT_0 375 }; 376 377 static struct qcom_icc_node mas_xm_usb_hs1 = { 378 .name = "mas_xm_usb_hs1", 379 .id = QNOC_MASTER_XM_USB_HS1, 380 .buswidth = 8, 381 .mas_rpm_id = -1, 382 .slv_rpm_id = -1, 383 .num_links = ARRAY_SIZE(mas_xm_usb_hs1_links), 384 .links = mas_xm_usb_hs1_links, 385 }; 386 387 static const u16 mas_qdss_bam_links[] = { 388 QNOC_SNOC_QDSS_INT 389 }; 390 391 static struct qcom_icc_node mas_qdss_bam = { 392 .name = "mas_qdss_bam", 393 .id = QNOC_MASTER_QDSS_BAM, 394 .buswidth = 4, 395 .mas_rpm_id = 19, 396 .slv_rpm_id = -1, 397 .qos.ap_owned = true, 398 .qos.qos_mode = NOC_QOS_MODE_FIXED, 399 .qos.areq_prio = 1, 400 .qos.prio_level = 1, 401 .qos.qos_port = 11, 402 .num_links = ARRAY_SIZE(mas_qdss_bam_links), 403 .links = mas_qdss_bam_links, 404 }; 405 406 static const u16 mas_bimc_snoc_links[] = { 407 QNOC_SNOC_INT_2 408 }; 409 410 static struct qcom_icc_node mas_bimc_snoc = { 411 .name = "mas_bimc_snoc", 412 .id = QNOC_BIMC_SNOC_MAS, 413 .buswidth = 8, 414 .mas_rpm_id = 21, 415 .slv_rpm_id = -1, 416 .num_links = ARRAY_SIZE(mas_bimc_snoc_links), 417 .links = mas_bimc_snoc_links, 418 }; 419 420 static const u16 mas_jpeg_links[] = { 421 QNOC_SNOC_MM_INT_0, 422 QNOC_MNOC_BIMC_SLV 423 }; 424 425 static struct qcom_icc_node mas_jpeg = { 426 .name = "mas_jpeg", 427 .id = QNOC_MASTER_JPEG, 428 .buswidth = 16, 429 .mas_rpm_id = 7, 430 .slv_rpm_id = -1, 431 .qos.ap_owned = true, 432 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 433 .qos.areq_prio = 0, 434 .qos.prio_level = 0, 435 .qos.qos_port = 6, 436 .num_links = ARRAY_SIZE(mas_jpeg_links), 437 .links = mas_jpeg_links, 438 }; 439 440 static const u16 mas_oxili_links[] = { 441 QNOC_MNOC_BIMC_SLV, 442 QNOC_SNOC_MM_INT_0 443 }; 444 445 static struct qcom_icc_node mas_oxili = { 446 .name = "mas_oxili", 447 .id = QNOC_MASTER_GRAPHICS_3D, 448 .channels = 2, 449 .buswidth = 16, 450 .ib_coeff = 200, 451 .mas_rpm_id = 6, 452 .slv_rpm_id = -1, 453 .qos.ap_owned = true, 454 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 455 .qos.areq_prio = 0, 456 .qos.prio_level = 0, 457 .qos.qos_port = 16, /* [16, 17] */ 458 .num_links = ARRAY_SIZE(mas_oxili_links), 459 .links = mas_oxili_links, 460 }; 461 462 static const u16 mas_mdp0_links[] = { 463 QNOC_SNOC_MM_INT_0, 464 QNOC_MNOC_BIMC_SLV 465 }; 466 467 static struct qcom_icc_node mas_mdp0 = { 468 .name = "mas_mdp0", 469 .id = QNOC_MASTER_MDP_PORT0, 470 .buswidth = 16, 471 .ib_coeff = 50, 472 .mas_rpm_id = 8, 473 .slv_rpm_id = -1, 474 .qos.ap_owned = true, 475 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 476 .qos.areq_prio = 0, 477 .qos.prio_level = 0, 478 .qos.qos_port = 7, 479 .num_links = ARRAY_SIZE(mas_mdp0_links), 480 .links = mas_mdp0_links, 481 }; 482 483 static const u16 mas_mdp1_links[] = { 484 QNOC_SNOC_MM_INT_0, 485 QNOC_MNOC_BIMC_SLV 486 }; 487 488 static struct qcom_icc_node mas_mdp1 = { 489 .name = "mas_mdp1", 490 .id = QNOC_MASTER_MDP_PORT1, 491 .buswidth = 16, 492 .ib_coeff = 50, 493 .mas_rpm_id = 61, 494 .slv_rpm_id = -1, 495 .qos.ap_owned = true, 496 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 497 .qos.areq_prio = 0, 498 .qos.prio_level = 0, 499 .qos.qos_port = 13, 500 .num_links = ARRAY_SIZE(mas_mdp1_links), 501 .links = mas_mdp1_links, 502 }; 503 504 static const u16 mas_pcnoc_snoc_links[] = { 505 QNOC_SNOC_INT_2 506 }; 507 508 static struct qcom_icc_node mas_pcnoc_snoc = { 509 .name = "mas_pcnoc_snoc", 510 .id = QNOC_PNOC_SNOC_MAS, 511 .buswidth = 8, 512 .mas_rpm_id = 29, 513 .slv_rpm_id = -1, 514 .qos.qos_mode = NOC_QOS_MODE_FIXED, 515 .qos.areq_prio = 0, 516 .qos.prio_level = 0, 517 .qos.qos_port = 5, 518 .num_links = ARRAY_SIZE(mas_pcnoc_snoc_links), 519 .links = mas_pcnoc_snoc_links, 520 }; 521 522 static const u16 mas_venus_0_links[] = { 523 QNOC_SNOC_MM_INT_0, 524 QNOC_MNOC_BIMC_SLV 525 }; 526 527 static struct qcom_icc_node mas_venus_0 = { 528 .name = "mas_venus_0", 529 .id = QNOC_MASTER_VIDEO_P0, 530 .buswidth = 16, 531 .mas_rpm_id = 9, 532 .slv_rpm_id = -1, 533 .qos.ap_owned = true, 534 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 535 .qos.areq_prio = 0, 536 .qos.prio_level = 0, 537 .qos.qos_port = 8, 538 .num_links = ARRAY_SIZE(mas_venus_0_links), 539 .links = mas_venus_0_links, 540 }; 541 542 static const u16 mas_venus_1_links[] = { 543 QNOC_SNOC_MM_INT_0, 544 QNOC_MNOC_BIMC_SLV 545 }; 546 547 static struct qcom_icc_node mas_venus_1 = { 548 .name = "mas_venus_1", 549 .id = QNOC_MASTER_VIDEO_P1, 550 .buswidth = 16, 551 .mas_rpm_id = 10, 552 .slv_rpm_id = -1, 553 .qos.ap_owned = true, 554 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 555 .qos.areq_prio = 0, 556 .qos.prio_level = 0, 557 .qos.qos_port = 14, 558 .num_links = ARRAY_SIZE(mas_venus_1_links), 559 .links = mas_venus_1_links, 560 }; 561 562 static const u16 mas_vfe_0_links[] = { 563 QNOC_SNOC_MM_INT_0, 564 QNOC_MNOC_BIMC_SLV 565 }; 566 567 static struct qcom_icc_node mas_vfe_0 = { 568 .name = "mas_vfe_0", 569 .id = QNOC_MASTER_VFE0, 570 .buswidth = 16, 571 .mas_rpm_id = 11, 572 .slv_rpm_id = -1, 573 .qos.ap_owned = true, 574 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 575 .qos.areq_prio = 0, 576 .qos.prio_level = 0, 577 .qos.qos_port = 9, 578 .num_links = ARRAY_SIZE(mas_vfe_0_links), 579 .links = mas_vfe_0_links, 580 }; 581 582 static const u16 mas_vfe_1_links[] = { 583 QNOC_SNOC_MM_INT_0, 584 QNOC_MNOC_BIMC_SLV 585 }; 586 587 static struct qcom_icc_node mas_vfe_1 = { 588 .name = "mas_vfe_1", 589 .id = QNOC_MASTER_VFE1, 590 .buswidth = 16, 591 .mas_rpm_id = 133, 592 .slv_rpm_id = -1, 593 .qos.ap_owned = true, 594 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 595 .qos.areq_prio = 0, 596 .qos.prio_level = 0, 597 .qos.qos_port = 15, 598 .num_links = ARRAY_SIZE(mas_vfe_1_links), 599 .links = mas_vfe_1_links, 600 }; 601 602 static const u16 mas_cpp_links[] = { 603 QNOC_SNOC_MM_INT_0, 604 QNOC_MNOC_BIMC_SLV 605 }; 606 607 static struct qcom_icc_node mas_cpp = { 608 .name = "mas_cpp", 609 .id = QNOC_MASTER_CPP, 610 .buswidth = 16, 611 .mas_rpm_id = 115, 612 .slv_rpm_id = -1, 613 .qos.ap_owned = true, 614 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 615 .qos.areq_prio = 0, 616 .qos.prio_level = 0, 617 .qos.qos_port = 12, 618 .num_links = ARRAY_SIZE(mas_cpp_links), 619 .links = mas_cpp_links, 620 }; 621 622 static const u16 mas_qdss_etr_links[] = { 623 QNOC_SNOC_QDSS_INT 624 }; 625 626 static struct qcom_icc_node mas_qdss_etr = { 627 .name = "mas_qdss_etr", 628 .id = QNOC_MASTER_QDSS_ETR, 629 .buswidth = 8, 630 .mas_rpm_id = 31, 631 .slv_rpm_id = -1, 632 .qos.ap_owned = true, 633 .qos.qos_mode = NOC_QOS_MODE_FIXED, 634 .qos.areq_prio = 1, 635 .qos.prio_level = 1, 636 .qos.qos_port = 10, 637 .num_links = ARRAY_SIZE(mas_qdss_etr_links), 638 .links = mas_qdss_etr_links, 639 }; 640 641 static const u16 mas_lpass_proc_links[] = { 642 QNOC_SNOC_INT_0, 643 QNOC_SNOC_INT_1, 644 QNOC_SNOC_BIMC_SLV 645 }; 646 647 static struct qcom_icc_node mas_lpass_proc = { 648 .name = "mas_lpass_proc", 649 .id = QNOC_MASTER_LPASS_PROC, 650 .buswidth = 8, 651 .mas_rpm_id = -1, 652 .slv_rpm_id = -1, 653 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 654 .qos.areq_prio = 0, 655 .qos.prio_level = 0, 656 .qos.qos_port = 19, 657 .num_links = ARRAY_SIZE(mas_lpass_proc_links), 658 .links = mas_lpass_proc_links, 659 }; 660 661 static const u16 mas_ipa_links[] = { 662 QNOC_SNOC_INT_2 663 }; 664 665 static struct qcom_icc_node mas_ipa = { 666 .name = "mas_ipa", 667 .id = QNOC_MASTER_IPA, 668 .buswidth = 8, 669 .mas_rpm_id = 59, 670 .slv_rpm_id = -1, 671 .qos.ap_owned = true, 672 .qos.qos_mode = NOC_QOS_MODE_FIXED, 673 .qos.areq_prio = 1, 674 .qos.prio_level = 1, 675 .qos.qos_port = 18, 676 .num_links = ARRAY_SIZE(mas_ipa_links), 677 .links = mas_ipa_links, 678 }; 679 680 static const u16 pcnoc_m_0_links[] = { 681 QNOC_PNOC_SNOC_SLV 682 }; 683 684 static struct qcom_icc_node pcnoc_m_0 = { 685 .name = "pcnoc_m_0", 686 .id = QNOC_PNOC_M_0, 687 .buswidth = 4, 688 .mas_rpm_id = 87, 689 .slv_rpm_id = 116, 690 .qos.qos_mode = NOC_QOS_MODE_FIXED, 691 .qos.areq_prio = 0, 692 .qos.prio_level = 0, 693 .qos.qos_port = 5, 694 .num_links = ARRAY_SIZE(pcnoc_m_0_links), 695 .links = pcnoc_m_0_links, 696 }; 697 698 static const u16 pcnoc_m_1_links[] = { 699 QNOC_PNOC_SNOC_SLV 700 }; 701 702 static struct qcom_icc_node pcnoc_m_1 = { 703 .name = "pcnoc_m_1", 704 .id = QNOC_PNOC_M_1, 705 .buswidth = 4, 706 .mas_rpm_id = 88, 707 .slv_rpm_id = 117, 708 .qos.qos_mode = NOC_QOS_MODE_FIXED, 709 .qos.areq_prio = 0, 710 .qos.prio_level = 0, 711 .qos.qos_port = 6, 712 .num_links = ARRAY_SIZE(pcnoc_m_1_links), 713 .links = pcnoc_m_1_links, 714 }; 715 716 static const u16 pcnoc_int_0_links[] = { 717 QNOC_PNOC_SNOC_SLV, 718 QNOC_PNOC_INT_2 719 }; 720 721 static struct qcom_icc_node pcnoc_int_0 = { 722 .name = "pcnoc_int_0", 723 .id = QNOC_PNOC_INT_0, 724 .buswidth = 4, 725 .mas_rpm_id = -1, 726 .slv_rpm_id = -1, 727 .num_links = ARRAY_SIZE(pcnoc_int_0_links), 728 .links = pcnoc_int_0_links, 729 }; 730 731 static const u16 pcnoc_int_1_links[] = { 732 QNOC_PNOC_SNOC_SLV, 733 QNOC_PNOC_INT_2 734 }; 735 736 static struct qcom_icc_node pcnoc_int_1 = { 737 .name = "pcnoc_int_1", 738 .id = QNOC_PNOC_INT_1, 739 .buswidth = 8, 740 .mas_rpm_id = 86, 741 .slv_rpm_id = 115, 742 .num_links = ARRAY_SIZE(pcnoc_int_1_links), 743 .links = pcnoc_int_1_links, 744 }; 745 746 static const u16 pcnoc_int_2_links[] = { 747 QNOC_PNOC_SLV_1, 748 QNOC_PNOC_SLV_2, 749 QNOC_PNOC_SLV_4, 750 QNOC_PNOC_SLV_8, 751 QNOC_PNOC_SLV_9, 752 QNOC_PNOC_SLV_3 753 }; 754 755 static struct qcom_icc_node pcnoc_int_2 = { 756 .name = "pcnoc_int_2", 757 .id = QNOC_PNOC_INT_2, 758 .buswidth = 8, 759 .mas_rpm_id = 124, 760 .slv_rpm_id = 184, 761 .num_links = ARRAY_SIZE(pcnoc_int_2_links), 762 .links = pcnoc_int_2_links, 763 }; 764 765 static const u16 pcnoc_s_1_links[] = { 766 QNOC_SLAVE_CRYPTO_0_CFG, 767 QNOC_SLAVE_PRNG, 768 QNOC_SLAVE_PDM, 769 QNOC_SLAVE_MESSAGE_RAM 770 }; 771 772 static struct qcom_icc_node pcnoc_s_1 = { 773 .name = "pcnoc_s_1", 774 .id = QNOC_PNOC_SLV_1, 775 .buswidth = 4, 776 .mas_rpm_id = 90, 777 .slv_rpm_id = 119, 778 .num_links = ARRAY_SIZE(pcnoc_s_1_links), 779 .links = pcnoc_s_1_links, 780 }; 781 782 static const u16 pcnoc_s_2_links[] = { 783 QNOC_SLAVE_PMIC_ARB 784 }; 785 786 static struct qcom_icc_node pcnoc_s_2 = { 787 .name = "pcnoc_s_2", 788 .id = QNOC_PNOC_SLV_2, 789 .buswidth = 4, 790 .mas_rpm_id = 91, 791 .slv_rpm_id = 120, 792 .num_links = ARRAY_SIZE(pcnoc_s_2_links), 793 .links = pcnoc_s_2_links, 794 }; 795 796 static const u16 pcnoc_s_3_links[] = { 797 QNOC_SLAVE_SNOC_CFG, 798 QNOC_SLAVE_DCC_CFG 799 }; 800 801 static struct qcom_icc_node pcnoc_s_3 = { 802 .name = "pcnoc_s_3", 803 .id = QNOC_PNOC_SLV_3, 804 .buswidth = 4, 805 .mas_rpm_id = 92, 806 .slv_rpm_id = 121, 807 .num_links = ARRAY_SIZE(pcnoc_s_3_links), 808 .links = pcnoc_s_3_links, 809 }; 810 811 static const u16 pcnoc_s_4_links[] = { 812 QNOC_SLAVE_CAMERA_CFG, 813 QNOC_SLAVE_DISPLAY_CFG, 814 QNOC_SLAVE_VENUS_CFG 815 }; 816 817 static struct qcom_icc_node pcnoc_s_4 = { 818 .name = "pcnoc_s_4", 819 .id = QNOC_PNOC_SLV_4, 820 .buswidth = 4, 821 .mas_rpm_id = 93, 822 .slv_rpm_id = 122, 823 .qos.ap_owned = true, 824 .qos.qos_mode = NOC_QOS_MODE_INVALID, 825 .num_links = ARRAY_SIZE(pcnoc_s_4_links), 826 .links = pcnoc_s_4_links, 827 }; 828 829 static const u16 pcnoc_s_8_links[] = { 830 QNOC_SLAVE_USB_HS, 831 QNOC_SLAVE_SDCC_3, 832 QNOC_SLAVE_BLSP_1, 833 QNOC_SLAVE_SDCC_1 834 }; 835 836 static struct qcom_icc_node pcnoc_s_8 = { 837 .name = "pcnoc_s_8", 838 .id = QNOC_PNOC_SLV_8, 839 .buswidth = 4, 840 .mas_rpm_id = 96, 841 .slv_rpm_id = 125, 842 .num_links = ARRAY_SIZE(pcnoc_s_8_links), 843 .links = pcnoc_s_8_links, 844 }; 845 846 static const u16 pcnoc_s_9_links[] = { 847 QNOC_SLAVE_GRAPHICS_3D_CFG, 848 QNOC_SLAVE_USB_HS2, 849 QNOC_SLAVE_SDCC_2, 850 QNOC_SLAVE_BLSP_2 851 }; 852 853 static struct qcom_icc_node pcnoc_s_9 = { 854 .name = "pcnoc_s_9", 855 .id = QNOC_PNOC_SLV_9, 856 .buswidth = 4, 857 .mas_rpm_id = 97, 858 .slv_rpm_id = 126, 859 .num_links = ARRAY_SIZE(pcnoc_s_9_links), 860 .links = pcnoc_s_9_links, 861 }; 862 863 static const u16 mm_int_0_links[] = { 864 QNOC_SNOC_INT_0 865 }; 866 867 static struct qcom_icc_node mm_int_0 = { 868 .name = "mm_int_0", 869 .id = QNOC_SNOC_MM_INT_0, 870 .buswidth = 16, 871 .ib_coeff = 200, 872 .mas_rpm_id = 79, 873 .slv_rpm_id = 108, 874 .qos.ap_owned = true, 875 .qos.qos_mode = NOC_QOS_MODE_INVALID, 876 .num_links = ARRAY_SIZE(mm_int_0_links), 877 .links = mm_int_0_links, 878 }; 879 880 static const u16 qdss_int_links[] = { 881 QNOC_SNOC_INT_2 882 }; 883 884 static struct qcom_icc_node qdss_int = { 885 .name = "qdss_int", 886 .id = QNOC_SNOC_QDSS_INT, 887 .buswidth = 8, 888 .mas_rpm_id = 98, 889 .slv_rpm_id = 128, 890 .qos.ap_owned = true, 891 .qos.qos_mode = NOC_QOS_MODE_INVALID, 892 .num_links = ARRAY_SIZE(qdss_int_links), 893 .links = qdss_int_links, 894 }; 895 896 static const u16 snoc_int_0_links[] = { 897 QNOC_SLAVE_QDSS_STM, 898 QNOC_SLAVE_SYSTEM_IMEM, 899 QNOC_SNOC_PNOC_SLV 900 }; 901 902 static struct qcom_icc_node snoc_int_0 = { 903 .name = "snoc_int_0", 904 .id = QNOC_SNOC_INT_0, 905 .buswidth = 8, 906 .mas_rpm_id = 99, 907 .slv_rpm_id = 130, 908 .num_links = ARRAY_SIZE(snoc_int_0_links), 909 .links = snoc_int_0_links, 910 }; 911 912 static const u16 snoc_int_1_links[] = { 913 QNOC_SLAVE_LPASS, 914 QNOC_SLAVE_CATS_128, 915 QNOC_SLAVE_OCMEM_64, 916 QNOC_SLAVE_APPSS 917 }; 918 919 static struct qcom_icc_node snoc_int_1 = { 920 .name = "snoc_int_1", 921 .id = QNOC_SNOC_INT_1, 922 .buswidth = 8, 923 .mas_rpm_id = 100, 924 .slv_rpm_id = 131, 925 .qos.ap_owned = true, 926 .qos.qos_mode = NOC_QOS_MODE_INVALID, 927 .num_links = ARRAY_SIZE(snoc_int_1_links), 928 .links = snoc_int_1_links, 929 }; 930 931 static const u16 snoc_int_2_links[] = { 932 QNOC_SNOC_INT_0, 933 QNOC_SNOC_INT_1, 934 QNOC_SNOC_BIMC_SLV 935 }; 936 937 static struct qcom_icc_node snoc_int_2 = { 938 .name = "snoc_int_2", 939 .id = QNOC_SNOC_INT_2, 940 .buswidth = 8, 941 .mas_rpm_id = 134, 942 .slv_rpm_id = 197, 943 .num_links = ARRAY_SIZE(snoc_int_2_links), 944 .links = snoc_int_2_links, 945 }; 946 947 static struct qcom_icc_node slv_ebi = { 948 .name = "slv_ebi", 949 .id = QNOC_SLAVE_EBI_CH0, 950 .channels = 2, 951 .buswidth = 16, 952 .mas_rpm_id = -1, 953 .slv_rpm_id = 0, 954 }; 955 956 static const u16 slv_bimc_snoc_links[] = { 957 QNOC_BIMC_SNOC_MAS 958 }; 959 960 static struct qcom_icc_node slv_bimc_snoc = { 961 .name = "slv_bimc_snoc", 962 .id = QNOC_BIMC_SNOC_SLV, 963 .buswidth = 16, 964 .mas_rpm_id = -1, 965 .slv_rpm_id = 2, 966 .num_links = ARRAY_SIZE(slv_bimc_snoc_links), 967 .links = slv_bimc_snoc_links, 968 }; 969 970 static struct qcom_icc_node slv_tcsr = { 971 .name = "slv_tcsr", 972 .id = QNOC_SLAVE_TCSR, 973 .buswidth = 4, 974 .mas_rpm_id = -1, 975 .slv_rpm_id = 50, 976 }; 977 978 static struct qcom_icc_node slv_tlmm = { 979 .name = "slv_tlmm", 980 .id = QNOC_SLAVE_TLMM, 981 .buswidth = 4, 982 .mas_rpm_id = -1, 983 .slv_rpm_id = 51, 984 }; 985 986 static struct qcom_icc_node slv_crypto_0_cfg = { 987 .name = "slv_crypto_0_cfg", 988 .id = QNOC_SLAVE_CRYPTO_0_CFG, 989 .buswidth = 4, 990 .mas_rpm_id = -1, 991 .slv_rpm_id = 52, 992 .qos.ap_owned = true, 993 .qos.qos_mode = NOC_QOS_MODE_INVALID, 994 }; 995 996 static struct qcom_icc_node slv_message_ram = { 997 .name = "slv_message_ram", 998 .id = QNOC_SLAVE_MESSAGE_RAM, 999 .buswidth = 4, 1000 .mas_rpm_id = -1, 1001 .slv_rpm_id = 55, 1002 }; 1003 1004 static struct qcom_icc_node slv_pdm = { 1005 .name = "slv_pdm", 1006 .id = QNOC_SLAVE_PDM, 1007 .buswidth = 4, 1008 .mas_rpm_id = -1, 1009 .slv_rpm_id = 41, 1010 }; 1011 1012 static struct qcom_icc_node slv_prng = { 1013 .name = "slv_prng", 1014 .id = QNOC_SLAVE_PRNG, 1015 .buswidth = 4, 1016 .mas_rpm_id = -1, 1017 .slv_rpm_id = 44, 1018 .qos.ap_owned = true, 1019 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1020 }; 1021 1022 static struct qcom_icc_node slv_pmic_arb = { 1023 .name = "slv_pmic_arb", 1024 .id = QNOC_SLAVE_PMIC_ARB, 1025 .buswidth = 4, 1026 .mas_rpm_id = -1, 1027 .slv_rpm_id = 59, 1028 }; 1029 1030 static struct qcom_icc_node slv_snoc_cfg = { 1031 .name = "slv_snoc_cfg", 1032 .id = QNOC_SLAVE_SNOC_CFG, 1033 .buswidth = 4, 1034 .mas_rpm_id = -1, 1035 .slv_rpm_id = 70, 1036 }; 1037 1038 static struct qcom_icc_node slv_dcc_cfg = { 1039 .name = "slv_dcc_cfg", 1040 .id = QNOC_SLAVE_DCC_CFG, 1041 .buswidth = 4, 1042 .mas_rpm_id = -1, 1043 .slv_rpm_id = 155, 1044 .qos.ap_owned = true, 1045 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1046 }; 1047 1048 static struct qcom_icc_node slv_camera_ss_cfg = { 1049 .name = "slv_camera_ss_cfg", 1050 .id = QNOC_SLAVE_CAMERA_CFG, 1051 .buswidth = 4, 1052 .mas_rpm_id = -1, 1053 .slv_rpm_id = 3, 1054 .qos.ap_owned = true, 1055 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1056 }; 1057 1058 static struct qcom_icc_node slv_disp_ss_cfg = { 1059 .name = "slv_disp_ss_cfg", 1060 .id = QNOC_SLAVE_DISPLAY_CFG, 1061 .buswidth = 4, 1062 .mas_rpm_id = -1, 1063 .slv_rpm_id = 4, 1064 .qos.ap_owned = true, 1065 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1066 }; 1067 1068 static struct qcom_icc_node slv_venus_cfg = { 1069 .name = "slv_venus_cfg", 1070 .id = QNOC_SLAVE_VENUS_CFG, 1071 .buswidth = 4, 1072 .mas_rpm_id = -1, 1073 .slv_rpm_id = 10, 1074 .qos.ap_owned = true, 1075 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1076 }; 1077 1078 static struct qcom_icc_node slv_sdcc_1 = { 1079 .name = "slv_sdcc_1", 1080 .id = QNOC_SLAVE_SDCC_1, 1081 .buswidth = 4, 1082 .mas_rpm_id = -1, 1083 .slv_rpm_id = 31, 1084 }; 1085 1086 static struct qcom_icc_node slv_blsp_1 = { 1087 .name = "slv_blsp_1", 1088 .id = QNOC_SLAVE_BLSP_1, 1089 .buswidth = 4, 1090 .mas_rpm_id = -1, 1091 .slv_rpm_id = 39, 1092 }; 1093 1094 static struct qcom_icc_node slv_usb_hs = { 1095 .name = "slv_usb_hs", 1096 .id = QNOC_SLAVE_USB_HS, 1097 .buswidth = 4, 1098 .mas_rpm_id = -1, 1099 .slv_rpm_id = 40, 1100 }; 1101 1102 static struct qcom_icc_node slv_sdcc_3 = { 1103 .name = "slv_sdcc_3", 1104 .id = QNOC_SLAVE_SDCC_3, 1105 .buswidth = 4, 1106 .mas_rpm_id = -1, 1107 .slv_rpm_id = 32, 1108 }; 1109 1110 static struct qcom_icc_node slv_sdcc_2 = { 1111 .name = "slv_sdcc_2", 1112 .id = QNOC_SLAVE_SDCC_2, 1113 .buswidth = 4, 1114 .mas_rpm_id = -1, 1115 .slv_rpm_id = 33, 1116 }; 1117 1118 static struct qcom_icc_node slv_gpu_cfg = { 1119 .name = "slv_gpu_cfg", 1120 .id = QNOC_SLAVE_GRAPHICS_3D_CFG, 1121 .buswidth = 4, 1122 .mas_rpm_id = -1, 1123 .slv_rpm_id = 11, 1124 .qos.ap_owned = true, 1125 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1126 }; 1127 1128 static struct qcom_icc_node slv_usb_hs2 = { 1129 .name = "slv_usb_hs2", 1130 .id = QNOC_SLAVE_USB_HS2, 1131 .buswidth = 4, 1132 .mas_rpm_id = -1, 1133 .slv_rpm_id = 79, 1134 }; 1135 1136 static struct qcom_icc_node slv_blsp_2 = { 1137 .name = "slv_blsp_2", 1138 .id = QNOC_SLAVE_BLSP_2, 1139 .buswidth = 4, 1140 .mas_rpm_id = -1, 1141 .slv_rpm_id = 37, 1142 }; 1143 1144 static const u16 slv_pcnoc_snoc_links[] = { 1145 QNOC_PNOC_SNOC_MAS 1146 }; 1147 1148 static struct qcom_icc_node slv_pcnoc_snoc = { 1149 .name = "slv_pcnoc_snoc", 1150 .id = QNOC_PNOC_SNOC_SLV, 1151 .buswidth = 8, 1152 .mas_rpm_id = -1, 1153 .slv_rpm_id = 45, 1154 .num_links = ARRAY_SIZE(slv_pcnoc_snoc_links), 1155 .links = slv_pcnoc_snoc_links, 1156 }; 1157 1158 static struct qcom_icc_node slv_kpss_ahb = { 1159 .name = "slv_kpss_ahb", 1160 .id = QNOC_SLAVE_APPSS, 1161 .buswidth = 4, 1162 .mas_rpm_id = -1, 1163 .slv_rpm_id = 20, 1164 .qos.ap_owned = true, 1165 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1166 }; 1167 1168 static const u16 slv_smmnoc_bimc_links[] = { 1169 QNOC_MNOC_BIMC_MAS 1170 }; 1171 1172 static struct qcom_icc_node slv_smmnoc_bimc = { 1173 .name = "slv_smmnoc_bimc", 1174 .id = QNOC_MNOC_BIMC_SLV, 1175 .channels = 2, 1176 .buswidth = 16, 1177 .ib_coeff = 200, 1178 .mas_rpm_id = -1, 1179 .slv_rpm_id = 198, 1180 .qos.ap_owned = true, 1181 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1182 .num_links = ARRAY_SIZE(slv_smmnoc_bimc_links), 1183 .links = slv_smmnoc_bimc_links, 1184 }; 1185 1186 static const u16 slv_snoc_bimc_links[] = { 1187 QNOC_SNOC_BIMC_MAS 1188 }; 1189 1190 static struct qcom_icc_node slv_snoc_bimc = { 1191 .name = "slv_snoc_bimc", 1192 .id = QNOC_SNOC_BIMC_SLV, 1193 .channels = 2, 1194 .buswidth = 8, 1195 .mas_rpm_id = -1, 1196 .slv_rpm_id = 24, 1197 .qos.ap_owned = true, 1198 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1199 .num_links = ARRAY_SIZE(slv_snoc_bimc_links), 1200 .links = slv_snoc_bimc_links, 1201 }; 1202 1203 static struct qcom_icc_node slv_imem = { 1204 .name = "slv_imem", 1205 .id = QNOC_SLAVE_SYSTEM_IMEM, 1206 .buswidth = 8, 1207 .mas_rpm_id = -1, 1208 .slv_rpm_id = 26, 1209 }; 1210 1211 static const u16 slv_snoc_pcnoc_links[] = { 1212 QNOC_SNOC_PNOC_MAS 1213 }; 1214 1215 static struct qcom_icc_node slv_snoc_pcnoc = { 1216 .name = "slv_snoc_pcnoc", 1217 .id = QNOC_SNOC_PNOC_SLV, 1218 .buswidth = 8, 1219 .mas_rpm_id = -1, 1220 .slv_rpm_id = 28, 1221 .num_links = ARRAY_SIZE(slv_snoc_pcnoc_links), 1222 .links = slv_snoc_pcnoc_links, 1223 }; 1224 1225 static struct qcom_icc_node slv_qdss_stm = { 1226 .name = "slv_qdss_stm", 1227 .id = QNOC_SLAVE_QDSS_STM, 1228 .buswidth = 4, 1229 .mas_rpm_id = -1, 1230 .slv_rpm_id = 30, 1231 }; 1232 1233 static struct qcom_icc_node slv_cats_0 = { 1234 .name = "slv_cats_0", 1235 .id = QNOC_SLAVE_CATS_128, 1236 .buswidth = 16, 1237 .mas_rpm_id = -1, 1238 .slv_rpm_id = 106, 1239 .qos.ap_owned = true, 1240 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1241 }; 1242 1243 static struct qcom_icc_node slv_cats_1 = { 1244 .name = "slv_cats_1", 1245 .id = QNOC_SLAVE_OCMEM_64, 1246 .buswidth = 8, 1247 .mas_rpm_id = -1, 1248 .slv_rpm_id = 107, 1249 .qos.ap_owned = true, 1250 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1251 }; 1252 1253 static struct qcom_icc_node slv_lpass = { 1254 .name = "slv_lpass", 1255 .id = QNOC_SLAVE_LPASS, 1256 .buswidth = 8, 1257 .mas_rpm_id = -1, 1258 .slv_rpm_id = 21, 1259 .qos.ap_owned = true, 1260 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1261 }; 1262 1263 static struct qcom_icc_node * const msm8976_bimc_nodes[] = { 1264 [MAS_APPS_PROC] = &mas_apps_proc, 1265 [MAS_SMMNOC_BIMC] = &mas_smmnoc_bimc, 1266 [MAS_SNOC_BIMC] = &mas_snoc_bimc, 1267 [MAS_TCU_0] = &mas_tcu_0, 1268 [SLV_EBI] = &slv_ebi, 1269 [SLV_BIMC_SNOC] = &slv_bimc_snoc, 1270 }; 1271 1272 static const struct regmap_config msm8976_bimc_regmap_config = { 1273 .reg_bits = 32, 1274 .reg_stride = 4, 1275 .val_bits = 32, 1276 .max_register = 0x62000, 1277 .fast_io = true, 1278 }; 1279 1280 static const struct qcom_icc_desc msm8976_bimc = { 1281 .type = QCOM_ICC_BIMC, 1282 .nodes = msm8976_bimc_nodes, 1283 .num_nodes = ARRAY_SIZE(msm8976_bimc_nodes), 1284 .bus_clk_desc = &bimc_clk, 1285 .regmap_cfg = &msm8976_bimc_regmap_config, 1286 .qos_offset = 0x8000, 1287 .ab_coeff = 154, 1288 }; 1289 1290 static struct qcom_icc_node * const msm8976_pcnoc_nodes[] = { 1291 [MAS_USB_HS2] = &mas_usb_hs2, 1292 [MAS_BLSP_1] = &mas_blsp_1, 1293 [MAS_USB_HS1] = &mas_usb_hs1, 1294 [MAS_BLSP_2] = &mas_blsp_2, 1295 [MAS_CRYPTO] = &mas_crypto, 1296 [MAS_SDCC_1] = &mas_sdcc_1, 1297 [MAS_SDCC_2] = &mas_sdcc_2, 1298 [MAS_SDCC_3] = &mas_sdcc_3, 1299 [MAS_SNOC_PCNOC] = &mas_snoc_pcnoc, 1300 [MAS_LPASS_AHB] = &mas_lpass_ahb, 1301 [MAS_SPDM] = &mas_spdm, 1302 [MAS_DEHR] = &mas_dehr, 1303 [MAS_XM_USB_HS1] = &mas_xm_usb_hs1, 1304 [PCNOC_M_0] = &pcnoc_m_0, 1305 [PCNOC_M_1] = &pcnoc_m_1, 1306 [PCNOC_INT_0] = &pcnoc_int_0, 1307 [PCNOC_INT_1] = &pcnoc_int_1, 1308 [PCNOC_INT_2] = &pcnoc_int_2, 1309 [PCNOC_S_1] = &pcnoc_s_1, 1310 [PCNOC_S_2] = &pcnoc_s_2, 1311 [PCNOC_S_3] = &pcnoc_s_3, 1312 [PCNOC_S_4] = &pcnoc_s_4, 1313 [PCNOC_S_8] = &pcnoc_s_8, 1314 [PCNOC_S_9] = &pcnoc_s_9, 1315 [SLV_TCSR] = &slv_tcsr, 1316 [SLV_TLMM] = &slv_tlmm, 1317 [SLV_CRYPTO_0_CFG] = &slv_crypto_0_cfg, 1318 [SLV_MESSAGE_RAM] = &slv_message_ram, 1319 [SLV_PDM] = &slv_pdm, 1320 [SLV_PRNG] = &slv_prng, 1321 [SLV_PMIC_ARB] = &slv_pmic_arb, 1322 [SLV_SNOC_CFG] = &slv_snoc_cfg, 1323 [SLV_DCC_CFG] = &slv_dcc_cfg, 1324 [SLV_CAMERA_SS_CFG] = &slv_camera_ss_cfg, 1325 [SLV_DISP_SS_CFG] = &slv_disp_ss_cfg, 1326 [SLV_VENUS_CFG] = &slv_venus_cfg, 1327 [SLV_SDCC_1] = &slv_sdcc_1, 1328 [SLV_BLSP_1] = &slv_blsp_1, 1329 [SLV_USB_HS] = &slv_usb_hs, 1330 [SLV_SDCC_3] = &slv_sdcc_3, 1331 [SLV_SDCC_2] = &slv_sdcc_2, 1332 [SLV_GPU_CFG] = &slv_gpu_cfg, 1333 [SLV_USB_HS2] = &slv_usb_hs2, 1334 [SLV_BLSP_2] = &slv_blsp_2, 1335 [SLV_PCNOC_SNOC] = &slv_pcnoc_snoc, 1336 }; 1337 1338 static const struct regmap_config msm8976_pcnoc_regmap_config = { 1339 .reg_bits = 32, 1340 .reg_stride = 4, 1341 .val_bits = 32, 1342 .max_register = 0x14000, 1343 .fast_io = true, 1344 }; 1345 1346 static const struct qcom_icc_desc msm8976_pcnoc = { 1347 .type = QCOM_ICC_NOC, 1348 .nodes = msm8976_pcnoc_nodes, 1349 .num_nodes = ARRAY_SIZE(msm8976_pcnoc_nodes), 1350 .bus_clk_desc = &bus_0_clk, 1351 .qos_offset = 0x7000, 1352 .keep_alive = true, 1353 .regmap_cfg = &msm8976_pcnoc_regmap_config, 1354 }; 1355 1356 static struct qcom_icc_node * const msm8976_snoc_nodes[] = { 1357 [MAS_QDSS_BAM] = &mas_qdss_bam, 1358 [MAS_BIMC_SNOC] = &mas_bimc_snoc, 1359 [MAS_PCNOC_SNOC] = &mas_pcnoc_snoc, 1360 [MAS_QDSS_ETR] = &mas_qdss_etr, 1361 [MAS_LPASS_PROC] = &mas_lpass_proc, 1362 [MAS_IPA] = &mas_ipa, 1363 [QDSS_INT] = &qdss_int, 1364 [SNOC_INT_0] = &snoc_int_0, 1365 [SNOC_INT_1] = &snoc_int_1, 1366 [SNOC_INT_2] = &snoc_int_2, 1367 [SLV_KPSS_AHB] = &slv_kpss_ahb, 1368 [SLV_SNOC_BIMC] = &slv_snoc_bimc, 1369 [SLV_IMEM] = &slv_imem, 1370 [SLV_SNOC_PCNOC] = &slv_snoc_pcnoc, 1371 [SLV_QDSS_STM] = &slv_qdss_stm, 1372 [SLV_CATS_0] = &slv_cats_0, 1373 [SLV_CATS_1] = &slv_cats_1, 1374 [SLV_LPASS] = &slv_lpass, 1375 }; 1376 1377 static const struct regmap_config msm8976_snoc_regmap_config = { 1378 .reg_bits = 32, 1379 .reg_stride = 4, 1380 .val_bits = 32, 1381 .max_register = 0x1A000, 1382 .fast_io = true, 1383 }; 1384 1385 static const struct qcom_icc_desc msm8976_snoc = { 1386 .type = QCOM_ICC_NOC, 1387 .nodes = msm8976_snoc_nodes, 1388 .num_nodes = ARRAY_SIZE(msm8976_snoc_nodes), 1389 .bus_clk_desc = &bus_1_clk, 1390 .regmap_cfg = &msm8976_snoc_regmap_config, 1391 .qos_offset = 0x7000, 1392 }; 1393 1394 static struct qcom_icc_node * const msm8976_snoc_mm_nodes[] = { 1395 [MAS_JPEG] = &mas_jpeg, 1396 [MAS_OXILI] = &mas_oxili, 1397 [MAS_MDP0] = &mas_mdp0, 1398 [MAS_MDP1] = &mas_mdp1, 1399 [MAS_VENUS_0] = &mas_venus_0, 1400 [MAS_VENUS_1] = &mas_venus_1, 1401 [MAS_VFE_0] = &mas_vfe_0, 1402 [MAS_VFE_1] = &mas_vfe_1, 1403 [MAS_CPP] = &mas_cpp, 1404 [MM_INT_0] = &mm_int_0, 1405 [SLV_SMMNOC_BIMC] = &slv_smmnoc_bimc, 1406 }; 1407 1408 static const struct qcom_icc_desc msm8976_snoc_mm = { 1409 .type = QCOM_ICC_NOC, 1410 .nodes = msm8976_snoc_mm_nodes, 1411 .num_nodes = ARRAY_SIZE(msm8976_snoc_mm_nodes), 1412 .bus_clk_desc = &bus_2_clk, 1413 .regmap_cfg = &msm8976_snoc_regmap_config, 1414 .qos_offset = 0x7000, 1415 .ab_coeff = 154, 1416 }; 1417 1418 static const struct of_device_id msm8976_noc_of_match[] = { 1419 { .compatible = "qcom,msm8976-bimc", .data = &msm8976_bimc }, 1420 { .compatible = "qcom,msm8976-pcnoc", .data = &msm8976_pcnoc }, 1421 { .compatible = "qcom,msm8976-snoc", .data = &msm8976_snoc }, 1422 { .compatible = "qcom,msm8976-snoc-mm", .data = &msm8976_snoc_mm }, 1423 { } 1424 }; 1425 MODULE_DEVICE_TABLE(of, msm8976_noc_of_match); 1426 1427 static struct platform_driver msm8976_noc_driver = { 1428 .probe = qnoc_probe, 1429 .remove = qnoc_remove, 1430 .driver = { 1431 .name = "qnoc-msm8976", 1432 .of_match_table = msm8976_noc_of_match, 1433 .sync_state = icc_sync_state, 1434 }, 1435 }; 1436 module_platform_driver(msm8976_noc_driver); 1437 1438 MODULE_DESCRIPTION("Qualcomm MSM8976 NoC driver"); 1439 MODULE_LICENSE("GPL"); 1440