1 // SPDX-License-Identifier: GPL-2.0 2 3 #include <linux/clk.h> 4 #include <linux/interconnect-provider.h> 5 #include <linux/module.h> 6 #include <linux/of_device.h> 7 #include <linux/platform_device.h> 8 #include <linux/regmap.h> 9 10 #include <dt-bindings/interconnect/qcom,msm8953.h> 11 12 #include "icc-rpm.h" 13 14 enum { 15 MSM8953_MASTER_AMPSS_M0 = 1, 16 MSM8953_MASTER_GRAPHICS_3D, 17 MSM8953_SNOC_BIMC_0_MAS, 18 MSM8953_SNOC_BIMC_2_MAS, 19 MSM8953_SNOC_BIMC_1_MAS, 20 MSM8953_MASTER_TCU_0, 21 MSM8953_SLAVE_EBI_CH0, 22 MSM8953_BIMC_SNOC_SLV, 23 MSM8953_MASTER_SPDM, 24 MSM8953_MASTER_BLSP_1, 25 MSM8953_MASTER_BLSP_2, 26 MSM8953_MASTER_USB3, 27 MSM8953_MASTER_CRYPTO_CORE0, 28 MSM8953_MASTER_SDCC_1, 29 MSM8953_MASTER_SDCC_2, 30 MSM8953_SNOC_PNOC_MAS, 31 MSM8953_PNOC_M_0, 32 MSM8953_PNOC_M_1, 33 MSM8953_PNOC_INT_1, 34 MSM8953_PNOC_INT_2, 35 MSM8953_PNOC_SLV_0, 36 MSM8953_PNOC_SLV_1, 37 MSM8953_PNOC_SLV_2, 38 MSM8953_PNOC_SLV_3, 39 MSM8953_PNOC_SLV_4, 40 MSM8953_PNOC_SLV_6, 41 MSM8953_PNOC_SLV_7, 42 MSM8953_PNOC_SLV_8, 43 MSM8953_PNOC_SLV_9, 44 MSM8953_SLAVE_SPDM_WRAPPER, 45 MSM8953_SLAVE_PDM, 46 MSM8953_SLAVE_TCSR, 47 MSM8953_SLAVE_SNOC_CFG, 48 MSM8953_SLAVE_TLMM, 49 MSM8953_SLAVE_MESSAGE_RAM, 50 MSM8953_SLAVE_BLSP_1, 51 MSM8953_SLAVE_BLSP_2, 52 MSM8953_SLAVE_PRNG, 53 MSM8953_SLAVE_CAMERA_CFG, 54 MSM8953_SLAVE_DISPLAY_CFG, 55 MSM8953_SLAVE_VENUS_CFG, 56 MSM8953_SLAVE_GRAPHICS_3D_CFG, 57 MSM8953_SLAVE_SDCC_1, 58 MSM8953_SLAVE_SDCC_2, 59 MSM8953_SLAVE_CRYPTO_0_CFG, 60 MSM8953_SLAVE_PMIC_ARB, 61 MSM8953_SLAVE_USB3, 62 MSM8953_SLAVE_IPA_CFG, 63 MSM8953_SLAVE_TCU, 64 MSM8953_PNOC_SNOC_SLV, 65 MSM8953_MASTER_QDSS_BAM, 66 MSM8953_BIMC_SNOC_MAS, 67 MSM8953_PNOC_SNOC_MAS, 68 MSM8953_MASTER_IPA, 69 MSM8953_MASTER_QDSS_ETR, 70 MSM8953_SNOC_QDSS_INT, 71 MSM8953_SNOC_INT_0, 72 MSM8953_SNOC_INT_1, 73 MSM8953_SNOC_INT_2, 74 MSM8953_SLAVE_APPSS, 75 MSM8953_SLAVE_WCSS, 76 MSM8953_SNOC_BIMC_1_SLV, 77 MSM8953_SLAVE_OCIMEM, 78 MSM8953_SNOC_PNOC_SLV, 79 MSM8953_SLAVE_QDSS_STM, 80 MSM8953_SLAVE_OCMEM_64, 81 MSM8953_SLAVE_LPASS, 82 MSM8953_MASTER_JPEG, 83 MSM8953_MASTER_MDP_PORT0, 84 MSM8953_MASTER_VIDEO_P0, 85 MSM8953_MASTER_VFE, 86 MSM8953_MASTER_VFE1, 87 MSM8953_MASTER_CPP, 88 MSM8953_SNOC_BIMC_0_SLV, 89 MSM8953_SNOC_BIMC_2_SLV, 90 MSM8953_SLAVE_CATS_128, 91 }; 92 93 static const u16 mas_apps_proc_links[] = { 94 MSM8953_SLAVE_EBI_CH0, 95 MSM8953_BIMC_SNOC_SLV 96 }; 97 98 static struct qcom_icc_node mas_apps_proc = { 99 .name = "mas_apps_proc", 100 .id = MSM8953_MASTER_AMPSS_M0, 101 .buswidth = 8, 102 .qos.ap_owned = true, 103 .qos.qos_mode = NOC_QOS_MODE_FIXED, 104 .qos.prio_level = 0, 105 .qos.areq_prio = 0, 106 .qos.qos_port = 0, 107 .num_links = ARRAY_SIZE(mas_apps_proc_links), 108 .links = mas_apps_proc_links, 109 }; 110 111 static const u16 mas_oxili_links[] = { 112 MSM8953_SLAVE_EBI_CH0, 113 MSM8953_BIMC_SNOC_SLV 114 }; 115 116 static struct qcom_icc_node mas_oxili = { 117 .name = "mas_oxili", 118 .id = MSM8953_MASTER_GRAPHICS_3D, 119 .buswidth = 8, 120 .qos.ap_owned = true, 121 .qos.qos_mode = NOC_QOS_MODE_FIXED, 122 .qos.prio_level = 0, 123 .qos.areq_prio = 0, 124 .qos.qos_port = 2, 125 .num_links = ARRAY_SIZE(mas_oxili_links), 126 .links = mas_oxili_links, 127 }; 128 129 static const u16 mas_snoc_bimc_0_links[] = { 130 MSM8953_SLAVE_EBI_CH0, 131 MSM8953_BIMC_SNOC_SLV 132 }; 133 134 static struct qcom_icc_node mas_snoc_bimc_0 = { 135 .name = "mas_snoc_bimc_0", 136 .id = MSM8953_SNOC_BIMC_0_MAS, 137 .buswidth = 8, 138 .qos.ap_owned = true, 139 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 140 .qos.prio_level = 0, 141 .qos.areq_prio = 0, 142 .qos.qos_port = 3, 143 .num_links = ARRAY_SIZE(mas_snoc_bimc_0_links), 144 .links = mas_snoc_bimc_0_links, 145 }; 146 147 static const u16 mas_snoc_bimc_2_links[] = { 148 MSM8953_SLAVE_EBI_CH0, 149 MSM8953_BIMC_SNOC_SLV 150 }; 151 152 static struct qcom_icc_node mas_snoc_bimc_2 = { 153 .name = "mas_snoc_bimc_2", 154 .id = MSM8953_SNOC_BIMC_2_MAS, 155 .buswidth = 8, 156 .qos.ap_owned = true, 157 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 158 .qos.prio_level = 0, 159 .qos.areq_prio = 0, 160 .qos.qos_port = 4, 161 .num_links = ARRAY_SIZE(mas_snoc_bimc_2_links), 162 .links = mas_snoc_bimc_2_links, 163 }; 164 165 static const u16 mas_snoc_bimc_1_links[] = { 166 MSM8953_SLAVE_EBI_CH0 167 }; 168 169 static struct qcom_icc_node mas_snoc_bimc_1 = { 170 .name = "mas_snoc_bimc_1", 171 .id = MSM8953_SNOC_BIMC_1_MAS, 172 .buswidth = 8, 173 .mas_rpm_id = 76, 174 .slv_rpm_id = -1, 175 .num_links = ARRAY_SIZE(mas_snoc_bimc_1_links), 176 .links = mas_snoc_bimc_1_links, 177 }; 178 179 static const u16 mas_tcu_0_links[] = { 180 MSM8953_SLAVE_EBI_CH0, 181 MSM8953_BIMC_SNOC_SLV 182 }; 183 184 static struct qcom_icc_node mas_tcu_0 = { 185 .name = "mas_tcu_0", 186 .id = MSM8953_MASTER_TCU_0, 187 .buswidth = 8, 188 .qos.ap_owned = true, 189 .qos.qos_mode = NOC_QOS_MODE_FIXED, 190 .qos.prio_level = 2, 191 .qos.areq_prio = 2, 192 .qos.qos_port = 6, 193 .num_links = ARRAY_SIZE(mas_tcu_0_links), 194 .links = mas_tcu_0_links, 195 }; 196 197 static struct qcom_icc_node slv_ebi = { 198 .name = "slv_ebi", 199 .id = MSM8953_SLAVE_EBI_CH0, 200 .buswidth = 8, 201 .mas_rpm_id = -1, 202 .slv_rpm_id = 0, 203 }; 204 205 static const u16 slv_bimc_snoc_links[] = { 206 MSM8953_BIMC_SNOC_MAS 207 }; 208 209 static struct qcom_icc_node slv_bimc_snoc = { 210 .name = "slv_bimc_snoc", 211 .id = MSM8953_BIMC_SNOC_SLV, 212 .buswidth = 8, 213 .mas_rpm_id = -1, 214 .slv_rpm_id = 2, 215 .num_links = ARRAY_SIZE(slv_bimc_snoc_links), 216 .links = slv_bimc_snoc_links, 217 }; 218 219 static const u16 mas_spdm_links[] = { 220 MSM8953_PNOC_M_0 221 }; 222 223 static struct qcom_icc_node mas_spdm = { 224 .name = "mas_spdm", 225 .id = MSM8953_MASTER_SPDM, 226 .buswidth = 4, 227 .qos.ap_owned = true, 228 .qos.qos_mode = NOC_QOS_MODE_INVALID, 229 .qos.prio_level = 0, 230 .qos.areq_prio = 0, 231 .qos.qos_port = -1, 232 .num_links = ARRAY_SIZE(mas_spdm_links), 233 .links = mas_spdm_links, 234 }; 235 236 static const u16 mas_blsp_1_links[] = { 237 MSM8953_PNOC_M_1 238 }; 239 240 static struct qcom_icc_node mas_blsp_1 = { 241 .name = "mas_blsp_1", 242 .id = MSM8953_MASTER_BLSP_1, 243 .buswidth = 4, 244 .mas_rpm_id = 41, 245 .slv_rpm_id = -1, 246 .num_links = ARRAY_SIZE(mas_blsp_1_links), 247 .links = mas_blsp_1_links, 248 }; 249 250 static const u16 mas_blsp_2_links[] = { 251 MSM8953_PNOC_M_1 252 }; 253 254 static struct qcom_icc_node mas_blsp_2 = { 255 .name = "mas_blsp_2", 256 .id = MSM8953_MASTER_BLSP_2, 257 .buswidth = 4, 258 .mas_rpm_id = 39, 259 .slv_rpm_id = -1, 260 .num_links = ARRAY_SIZE(mas_blsp_2_links), 261 .links = mas_blsp_2_links, 262 }; 263 264 static const u16 mas_usb3_links[] = { 265 MSM8953_PNOC_INT_1 266 }; 267 268 static struct qcom_icc_node mas_usb3 = { 269 .name = "mas_usb3", 270 .id = MSM8953_MASTER_USB3, 271 .buswidth = 8, 272 .qos.ap_owned = true, 273 .qos.qos_mode = NOC_QOS_MODE_FIXED, 274 .qos.prio_level = 1, 275 .qos.areq_prio = 1, 276 .qos.qos_port = 11, 277 .num_links = ARRAY_SIZE(mas_usb3_links), 278 .links = mas_usb3_links, 279 }; 280 281 static const u16 mas_crypto_links[] = { 282 MSM8953_PNOC_INT_1 283 }; 284 285 static struct qcom_icc_node mas_crypto = { 286 .name = "mas_crypto", 287 .id = MSM8953_MASTER_CRYPTO_CORE0, 288 .buswidth = 8, 289 .qos.ap_owned = true, 290 .qos.qos_mode = NOC_QOS_MODE_FIXED, 291 .qos.prio_level = 1, 292 .qos.areq_prio = 1, 293 .qos.qos_port = 0, 294 .num_links = ARRAY_SIZE(mas_crypto_links), 295 .links = mas_crypto_links, 296 }; 297 298 static const u16 mas_sdcc_1_links[] = { 299 MSM8953_PNOC_INT_1 300 }; 301 302 static struct qcom_icc_node mas_sdcc_1 = { 303 .name = "mas_sdcc_1", 304 .id = MSM8953_MASTER_SDCC_1, 305 .buswidth = 8, 306 .mas_rpm_id = 33, 307 .slv_rpm_id = -1, 308 .num_links = ARRAY_SIZE(mas_sdcc_1_links), 309 .links = mas_sdcc_1_links, 310 }; 311 312 static const u16 mas_sdcc_2_links[] = { 313 MSM8953_PNOC_INT_1 314 }; 315 316 static struct qcom_icc_node mas_sdcc_2 = { 317 .name = "mas_sdcc_2", 318 .id = MSM8953_MASTER_SDCC_2, 319 .buswidth = 8, 320 .mas_rpm_id = 35, 321 .slv_rpm_id = -1, 322 .num_links = ARRAY_SIZE(mas_sdcc_2_links), 323 .links = mas_sdcc_2_links, 324 }; 325 326 static const u16 mas_snoc_pcnoc_links[] = { 327 MSM8953_PNOC_INT_2 328 }; 329 330 static struct qcom_icc_node mas_snoc_pcnoc = { 331 .name = "mas_snoc_pcnoc", 332 .id = MSM8953_SNOC_PNOC_MAS, 333 .buswidth = 8, 334 .mas_rpm_id = 77, 335 .slv_rpm_id = -1, 336 .num_links = ARRAY_SIZE(mas_snoc_pcnoc_links), 337 .links = mas_snoc_pcnoc_links, 338 }; 339 340 static const u16 pcnoc_m_0_links[] = { 341 MSM8953_PNOC_INT_1 342 }; 343 344 static struct qcom_icc_node pcnoc_m_0 = { 345 .name = "pcnoc_m_0", 346 .id = MSM8953_PNOC_M_0, 347 .buswidth = 4, 348 .qos.ap_owned = true, 349 .qos.qos_mode = NOC_QOS_MODE_FIXED, 350 .qos.prio_level = 1, 351 .qos.areq_prio = 1, 352 .qos.qos_port = 5, 353 .num_links = ARRAY_SIZE(pcnoc_m_0_links), 354 .links = pcnoc_m_0_links, 355 }; 356 357 static const u16 pcnoc_m_1_links[] = { 358 MSM8953_PNOC_INT_1 359 }; 360 361 static struct qcom_icc_node pcnoc_m_1 = { 362 .name = "pcnoc_m_1", 363 .id = MSM8953_PNOC_M_1, 364 .buswidth = 4, 365 .mas_rpm_id = 88, 366 .slv_rpm_id = 117, 367 .num_links = ARRAY_SIZE(pcnoc_m_1_links), 368 .links = pcnoc_m_1_links, 369 }; 370 371 static const u16 pcnoc_int_1_links[] = { 372 MSM8953_PNOC_INT_2, 373 MSM8953_PNOC_SNOC_SLV 374 }; 375 376 static struct qcom_icc_node pcnoc_int_1 = { 377 .name = "pcnoc_int_1", 378 .id = MSM8953_PNOC_INT_1, 379 .buswidth = 8, 380 .mas_rpm_id = 86, 381 .slv_rpm_id = 115, 382 .num_links = ARRAY_SIZE(pcnoc_int_1_links), 383 .links = pcnoc_int_1_links, 384 }; 385 386 static const u16 pcnoc_int_2_links[] = { 387 MSM8953_PNOC_SLV_1, 388 MSM8953_PNOC_SLV_2, 389 MSM8953_PNOC_SLV_0, 390 MSM8953_PNOC_SLV_4, 391 MSM8953_PNOC_SLV_6, 392 MSM8953_PNOC_SLV_7, 393 MSM8953_PNOC_SLV_8, 394 MSM8953_PNOC_SLV_9, 395 MSM8953_SLAVE_TCU, 396 MSM8953_SLAVE_GRAPHICS_3D_CFG, 397 MSM8953_PNOC_SLV_3 398 }; 399 400 static struct qcom_icc_node pcnoc_int_2 = { 401 .name = "pcnoc_int_2", 402 .id = MSM8953_PNOC_INT_2, 403 .buswidth = 8, 404 .mas_rpm_id = 124, 405 .slv_rpm_id = 184, 406 .num_links = ARRAY_SIZE(pcnoc_int_2_links), 407 .links = pcnoc_int_2_links, 408 }; 409 410 static const u16 pcnoc_s_0_links[] = { 411 MSM8953_SLAVE_PDM, 412 MSM8953_SLAVE_SPDM_WRAPPER 413 }; 414 415 static struct qcom_icc_node pcnoc_s_0 = { 416 .name = "pcnoc_s_0", 417 .id = MSM8953_PNOC_SLV_0, 418 .buswidth = 4, 419 .mas_rpm_id = 89, 420 .slv_rpm_id = 118, 421 .num_links = ARRAY_SIZE(pcnoc_s_0_links), 422 .links = pcnoc_s_0_links, 423 }; 424 425 static const u16 pcnoc_s_1_links[] = { 426 MSM8953_SLAVE_TCSR 427 }; 428 429 static struct qcom_icc_node pcnoc_s_1 = { 430 .name = "pcnoc_s_1", 431 .id = MSM8953_PNOC_SLV_1, 432 .buswidth = 4, 433 .mas_rpm_id = 90, 434 .slv_rpm_id = 119, 435 .num_links = ARRAY_SIZE(pcnoc_s_1_links), 436 .links = pcnoc_s_1_links, 437 }; 438 439 static const u16 pcnoc_s_2_links[] = { 440 MSM8953_SLAVE_SNOC_CFG 441 }; 442 443 static struct qcom_icc_node pcnoc_s_2 = { 444 .name = "pcnoc_s_2", 445 .id = MSM8953_PNOC_SLV_2, 446 .buswidth = 4, 447 .mas_rpm_id = 91, 448 .slv_rpm_id = 120, 449 .num_links = ARRAY_SIZE(pcnoc_s_2_links), 450 .links = pcnoc_s_2_links, 451 }; 452 453 static const u16 pcnoc_s_3_links[] = { 454 MSM8953_SLAVE_TLMM, 455 MSM8953_SLAVE_PRNG, 456 MSM8953_SLAVE_BLSP_1, 457 MSM8953_SLAVE_BLSP_2, 458 MSM8953_SLAVE_MESSAGE_RAM 459 }; 460 461 static struct qcom_icc_node pcnoc_s_3 = { 462 .name = "pcnoc_s_3", 463 .id = MSM8953_PNOC_SLV_3, 464 .buswidth = 4, 465 .mas_rpm_id = 92, 466 .slv_rpm_id = 121, 467 .num_links = ARRAY_SIZE(pcnoc_s_3_links), 468 .links = pcnoc_s_3_links, 469 }; 470 471 static const u16 pcnoc_s_4_links[] = { 472 MSM8953_SLAVE_CAMERA_CFG, 473 MSM8953_SLAVE_DISPLAY_CFG, 474 MSM8953_SLAVE_VENUS_CFG 475 }; 476 477 static struct qcom_icc_node pcnoc_s_4 = { 478 .name = "pcnoc_s_4", 479 .id = MSM8953_PNOC_SLV_4, 480 .buswidth = 4, 481 .qos.ap_owned = true, 482 .qos.qos_mode = NOC_QOS_MODE_INVALID, 483 .qos.prio_level = 0, 484 .qos.areq_prio = 0, 485 .qos.qos_port = -1, 486 .num_links = ARRAY_SIZE(pcnoc_s_4_links), 487 .links = pcnoc_s_4_links, 488 }; 489 490 static const u16 pcnoc_s_6_links[] = { 491 MSM8953_SLAVE_CRYPTO_0_CFG, 492 MSM8953_SLAVE_SDCC_2, 493 MSM8953_SLAVE_SDCC_1 494 }; 495 496 static struct qcom_icc_node pcnoc_s_6 = { 497 .name = "pcnoc_s_6", 498 .id = MSM8953_PNOC_SLV_6, 499 .buswidth = 4, 500 .mas_rpm_id = 94, 501 .slv_rpm_id = 123, 502 .num_links = ARRAY_SIZE(pcnoc_s_6_links), 503 .links = pcnoc_s_6_links, 504 }; 505 506 static const u16 pcnoc_s_7_links[] = { 507 MSM8953_SLAVE_PMIC_ARB 508 }; 509 510 static struct qcom_icc_node pcnoc_s_7 = { 511 .name = "pcnoc_s_7", 512 .id = MSM8953_PNOC_SLV_7, 513 .buswidth = 4, 514 .mas_rpm_id = 95, 515 .slv_rpm_id = 124, 516 .num_links = ARRAY_SIZE(pcnoc_s_7_links), 517 .links = pcnoc_s_7_links, 518 }; 519 520 static const u16 pcnoc_s_8_links[] = { 521 MSM8953_SLAVE_USB3 522 }; 523 524 static struct qcom_icc_node pcnoc_s_8 = { 525 .name = "pcnoc_s_8", 526 .id = MSM8953_PNOC_SLV_8, 527 .buswidth = 4, 528 .qos.ap_owned = true, 529 .qos.qos_mode = NOC_QOS_MODE_INVALID, 530 .qos.prio_level = 0, 531 .qos.areq_prio = 0, 532 .qos.qos_port = -1, 533 .num_links = ARRAY_SIZE(pcnoc_s_8_links), 534 .links = pcnoc_s_8_links, 535 }; 536 537 static const u16 pcnoc_s_9_links[] = { 538 MSM8953_SLAVE_IPA_CFG 539 }; 540 541 static struct qcom_icc_node pcnoc_s_9 = { 542 .name = "pcnoc_s_9", 543 .id = MSM8953_PNOC_SLV_9, 544 .buswidth = 4, 545 .qos.ap_owned = true, 546 .qos.qos_mode = NOC_QOS_MODE_INVALID, 547 .qos.prio_level = 0, 548 .qos.areq_prio = 0, 549 .qos.qos_port = -1, 550 .num_links = ARRAY_SIZE(pcnoc_s_9_links), 551 .links = pcnoc_s_9_links, 552 }; 553 554 static struct qcom_icc_node slv_spdm = { 555 .name = "slv_spdm", 556 .id = MSM8953_SLAVE_SPDM_WRAPPER, 557 .buswidth = 4, 558 .qos.ap_owned = true, 559 .qos.qos_mode = NOC_QOS_MODE_INVALID, 560 .qos.prio_level = 0, 561 .qos.areq_prio = 0, 562 .qos.qos_port = -1, 563 }; 564 565 static struct qcom_icc_node slv_pdm = { 566 .name = "slv_pdm", 567 .id = MSM8953_SLAVE_PDM, 568 .buswidth = 4, 569 .mas_rpm_id = -1, 570 .slv_rpm_id = 41, 571 }; 572 573 static struct qcom_icc_node slv_tcsr = { 574 .name = "slv_tcsr", 575 .id = MSM8953_SLAVE_TCSR, 576 .buswidth = 4, 577 .mas_rpm_id = -1, 578 .slv_rpm_id = 50, 579 }; 580 581 static struct qcom_icc_node slv_snoc_cfg = { 582 .name = "slv_snoc_cfg", 583 .id = MSM8953_SLAVE_SNOC_CFG, 584 .buswidth = 4, 585 .mas_rpm_id = -1, 586 .slv_rpm_id = 70, 587 }; 588 589 static struct qcom_icc_node slv_tlmm = { 590 .name = "slv_tlmm", 591 .id = MSM8953_SLAVE_TLMM, 592 .buswidth = 4, 593 .mas_rpm_id = -1, 594 .slv_rpm_id = 51, 595 }; 596 597 static struct qcom_icc_node slv_message_ram = { 598 .name = "slv_message_ram", 599 .id = MSM8953_SLAVE_MESSAGE_RAM, 600 .buswidth = 4, 601 .mas_rpm_id = -1, 602 .slv_rpm_id = 55, 603 }; 604 605 static struct qcom_icc_node slv_blsp_1 = { 606 .name = "slv_blsp_1", 607 .id = MSM8953_SLAVE_BLSP_1, 608 .buswidth = 4, 609 .mas_rpm_id = -1, 610 .slv_rpm_id = 39, 611 }; 612 613 static struct qcom_icc_node slv_blsp_2 = { 614 .name = "slv_blsp_2", 615 .id = MSM8953_SLAVE_BLSP_2, 616 .buswidth = 4, 617 .mas_rpm_id = -1, 618 .slv_rpm_id = 37, 619 }; 620 621 static struct qcom_icc_node slv_prng = { 622 .name = "slv_prng", 623 .id = MSM8953_SLAVE_PRNG, 624 .buswidth = 4, 625 .mas_rpm_id = -1, 626 .slv_rpm_id = 44, 627 }; 628 629 static struct qcom_icc_node slv_camera_ss_cfg = { 630 .name = "slv_camera_ss_cfg", 631 .id = MSM8953_SLAVE_CAMERA_CFG, 632 .buswidth = 4, 633 .qos.ap_owned = true, 634 .qos.qos_mode = NOC_QOS_MODE_INVALID, 635 .qos.prio_level = 0, 636 .qos.areq_prio = 0, 637 .qos.qos_port = -1, 638 }; 639 640 static struct qcom_icc_node slv_disp_ss_cfg = { 641 .name = "slv_disp_ss_cfg", 642 .id = MSM8953_SLAVE_DISPLAY_CFG, 643 .buswidth = 4, 644 .qos.ap_owned = true, 645 .qos.qos_mode = NOC_QOS_MODE_INVALID, 646 .qos.prio_level = 0, 647 .qos.areq_prio = 0, 648 .qos.qos_port = -1, 649 }; 650 651 static struct qcom_icc_node slv_venus_cfg = { 652 .name = "slv_venus_cfg", 653 .id = MSM8953_SLAVE_VENUS_CFG, 654 .buswidth = 4, 655 .qos.ap_owned = true, 656 .qos.qos_mode = NOC_QOS_MODE_INVALID, 657 .qos.prio_level = 0, 658 .qos.areq_prio = 0, 659 .qos.qos_port = -1, 660 }; 661 662 static struct qcom_icc_node slv_gpu_cfg = { 663 .name = "slv_gpu_cfg", 664 .id = MSM8953_SLAVE_GRAPHICS_3D_CFG, 665 .buswidth = 8, 666 .qos.ap_owned = true, 667 .qos.qos_mode = NOC_QOS_MODE_INVALID, 668 .qos.prio_level = 0, 669 .qos.areq_prio = 0, 670 .qos.qos_port = -1, 671 }; 672 673 static struct qcom_icc_node slv_sdcc_1 = { 674 .name = "slv_sdcc_1", 675 .id = MSM8953_SLAVE_SDCC_1, 676 .buswidth = 4, 677 .mas_rpm_id = -1, 678 .slv_rpm_id = 31, 679 }; 680 681 static struct qcom_icc_node slv_sdcc_2 = { 682 .name = "slv_sdcc_2", 683 .id = MSM8953_SLAVE_SDCC_2, 684 .buswidth = 4, 685 .mas_rpm_id = -1, 686 .slv_rpm_id = 33, 687 }; 688 689 static struct qcom_icc_node slv_crypto_0_cfg = { 690 .name = "slv_crypto_0_cfg", 691 .id = MSM8953_SLAVE_CRYPTO_0_CFG, 692 .buswidth = 4, 693 .qos.ap_owned = true, 694 .qos.qos_mode = NOC_QOS_MODE_INVALID, 695 .qos.prio_level = 0, 696 .qos.areq_prio = 0, 697 .qos.qos_port = -1, 698 }; 699 700 static struct qcom_icc_node slv_pmic_arb = { 701 .name = "slv_pmic_arb", 702 .id = MSM8953_SLAVE_PMIC_ARB, 703 .buswidth = 4, 704 .mas_rpm_id = -1, 705 .slv_rpm_id = 59, 706 }; 707 708 static struct qcom_icc_node slv_usb3 = { 709 .name = "slv_usb3", 710 .id = MSM8953_SLAVE_USB3, 711 .buswidth = 4, 712 .qos.ap_owned = true, 713 .qos.qos_mode = NOC_QOS_MODE_INVALID, 714 .qos.prio_level = 0, 715 .qos.areq_prio = 0, 716 .qos.qos_port = -1, 717 }; 718 719 static struct qcom_icc_node slv_ipa_cfg = { 720 .name = "slv_ipa_cfg", 721 .id = MSM8953_SLAVE_IPA_CFG, 722 .buswidth = 4, 723 .qos.ap_owned = true, 724 .qos.qos_mode = NOC_QOS_MODE_INVALID, 725 .qos.prio_level = 0, 726 .qos.areq_prio = 0, 727 .qos.qos_port = -1, 728 }; 729 730 static struct qcom_icc_node slv_tcu = { 731 .name = "slv_tcu", 732 .id = MSM8953_SLAVE_TCU, 733 .buswidth = 8, 734 .qos.ap_owned = true, 735 .qos.qos_mode = NOC_QOS_MODE_INVALID, 736 .qos.prio_level = 0, 737 .qos.areq_prio = 0, 738 .qos.qos_port = -1, 739 }; 740 741 static const u16 slv_pcnoc_snoc_links[] = { 742 MSM8953_PNOC_SNOC_MAS 743 }; 744 745 static struct qcom_icc_node slv_pcnoc_snoc = { 746 .name = "slv_pcnoc_snoc", 747 .id = MSM8953_PNOC_SNOC_SLV, 748 .buswidth = 8, 749 .mas_rpm_id = -1, 750 .slv_rpm_id = 45, 751 .num_links = ARRAY_SIZE(slv_pcnoc_snoc_links), 752 .links = slv_pcnoc_snoc_links, 753 }; 754 755 static const u16 mas_qdss_bam_links[] = { 756 MSM8953_SNOC_QDSS_INT 757 }; 758 759 static struct qcom_icc_node mas_qdss_bam = { 760 .name = "mas_qdss_bam", 761 .id = MSM8953_MASTER_QDSS_BAM, 762 .buswidth = 4, 763 .qos.ap_owned = true, 764 .qos.qos_mode = NOC_QOS_MODE_FIXED, 765 .qos.prio_level = 1, 766 .qos.areq_prio = 1, 767 .qos.qos_port = 11, 768 .num_links = ARRAY_SIZE(mas_qdss_bam_links), 769 .links = mas_qdss_bam_links, 770 }; 771 772 static const u16 mas_bimc_snoc_links[] = { 773 MSM8953_SNOC_INT_0, 774 MSM8953_SNOC_INT_1, 775 MSM8953_SNOC_INT_2 776 }; 777 778 static struct qcom_icc_node mas_bimc_snoc = { 779 .name = "mas_bimc_snoc", 780 .id = MSM8953_BIMC_SNOC_MAS, 781 .buswidth = 8, 782 .mas_rpm_id = 21, 783 .slv_rpm_id = -1, 784 .num_links = ARRAY_SIZE(mas_bimc_snoc_links), 785 .links = mas_bimc_snoc_links, 786 }; 787 788 static const u16 mas_pcnoc_snoc_links[] = { 789 MSM8953_SNOC_INT_0, 790 MSM8953_SNOC_INT_1, 791 MSM8953_SNOC_BIMC_1_SLV 792 }; 793 794 static struct qcom_icc_node mas_pcnoc_snoc = { 795 .name = "mas_pcnoc_snoc", 796 .id = MSM8953_PNOC_SNOC_MAS, 797 .buswidth = 8, 798 .mas_rpm_id = 29, 799 .slv_rpm_id = -1, 800 .num_links = ARRAY_SIZE(mas_pcnoc_snoc_links), 801 .links = mas_pcnoc_snoc_links, 802 }; 803 804 static const u16 mas_ipa_links[] = { 805 MSM8953_SNOC_INT_0, 806 MSM8953_SNOC_INT_1, 807 MSM8953_SNOC_BIMC_1_SLV 808 }; 809 810 static struct qcom_icc_node mas_ipa = { 811 .name = "mas_ipa", 812 .id = MSM8953_MASTER_IPA, 813 .buswidth = 8, 814 .qos.ap_owned = true, 815 .qos.qos_mode = NOC_QOS_MODE_FIXED, 816 .qos.prio_level = 0, 817 .qos.areq_prio = 0, 818 .qos.qos_port = 14, 819 .num_links = ARRAY_SIZE(mas_ipa_links), 820 .links = mas_ipa_links, 821 }; 822 823 static const u16 mas_qdss_etr_links[] = { 824 MSM8953_SNOC_QDSS_INT 825 }; 826 827 static struct qcom_icc_node mas_qdss_etr = { 828 .name = "mas_qdss_etr", 829 .id = MSM8953_MASTER_QDSS_ETR, 830 .buswidth = 8, 831 .qos.ap_owned = true, 832 .qos.qos_mode = NOC_QOS_MODE_FIXED, 833 .qos.prio_level = 1, 834 .qos.areq_prio = 1, 835 .qos.qos_port = 10, 836 .num_links = ARRAY_SIZE(mas_qdss_etr_links), 837 .links = mas_qdss_etr_links, 838 }; 839 840 static const u16 qdss_int_links[] = { 841 MSM8953_SNOC_INT_1, 842 MSM8953_SNOC_BIMC_1_SLV 843 }; 844 845 static struct qcom_icc_node qdss_int = { 846 .name = "qdss_int", 847 .id = MSM8953_SNOC_QDSS_INT, 848 .buswidth = 8, 849 .qos.ap_owned = true, 850 .qos.qos_mode = NOC_QOS_MODE_INVALID, 851 .qos.prio_level = 0, 852 .qos.areq_prio = 0, 853 .qos.qos_port = -1, 854 .num_links = ARRAY_SIZE(qdss_int_links), 855 .links = qdss_int_links, 856 }; 857 858 static const u16 snoc_int_0_links[] = { 859 MSM8953_SLAVE_LPASS, 860 MSM8953_SLAVE_WCSS, 861 MSM8953_SLAVE_APPSS 862 }; 863 864 static struct qcom_icc_node snoc_int_0 = { 865 .name = "snoc_int_0", 866 .id = MSM8953_SNOC_INT_0, 867 .buswidth = 8, 868 .qos.ap_owned = true, 869 .qos.qos_mode = NOC_QOS_MODE_INVALID, 870 .qos.prio_level = 0, 871 .qos.areq_prio = 0, 872 .qos.qos_port = -1, 873 .num_links = ARRAY_SIZE(snoc_int_0_links), 874 .links = snoc_int_0_links, 875 }; 876 877 static const u16 snoc_int_1_links[] = { 878 MSM8953_SLAVE_QDSS_STM, 879 MSM8953_SLAVE_OCIMEM, 880 MSM8953_SNOC_PNOC_SLV 881 }; 882 883 static struct qcom_icc_node snoc_int_1 = { 884 .name = "snoc_int_1", 885 .id = MSM8953_SNOC_INT_1, 886 .buswidth = 8, 887 .mas_rpm_id = 100, 888 .slv_rpm_id = 131, 889 .num_links = ARRAY_SIZE(snoc_int_1_links), 890 .links = snoc_int_1_links, 891 }; 892 893 static const u16 snoc_int_2_links[] = { 894 MSM8953_SLAVE_CATS_128, 895 MSM8953_SLAVE_OCMEM_64 896 }; 897 898 static struct qcom_icc_node snoc_int_2 = { 899 .name = "snoc_int_2", 900 .id = MSM8953_SNOC_INT_2, 901 .buswidth = 8, 902 .qos.ap_owned = true, 903 .qos.qos_mode = NOC_QOS_MODE_INVALID, 904 .qos.prio_level = 0, 905 .qos.areq_prio = 0, 906 .qos.qos_port = -1, 907 .num_links = ARRAY_SIZE(snoc_int_2_links), 908 .links = snoc_int_2_links, 909 }; 910 911 static struct qcom_icc_node slv_kpss_ahb = { 912 .name = "slv_kpss_ahb", 913 .id = MSM8953_SLAVE_APPSS, 914 .buswidth = 4, 915 .qos.ap_owned = true, 916 .qos.qos_mode = NOC_QOS_MODE_INVALID, 917 .qos.prio_level = 0, 918 .qos.areq_prio = 0, 919 .qos.qos_port = -1, 920 }; 921 922 static struct qcom_icc_node slv_wcss = { 923 .name = "slv_wcss", 924 .id = MSM8953_SLAVE_WCSS, 925 .buswidth = 4, 926 .qos.ap_owned = true, 927 .qos.qos_mode = NOC_QOS_MODE_INVALID, 928 .qos.prio_level = 0, 929 .qos.areq_prio = 0, 930 .qos.qos_port = -1, 931 }; 932 933 static const u16 slv_snoc_bimc_1_links[] = { 934 MSM8953_SNOC_BIMC_1_MAS 935 }; 936 937 static struct qcom_icc_node slv_snoc_bimc_1 = { 938 .name = "slv_snoc_bimc_1", 939 .id = MSM8953_SNOC_BIMC_1_SLV, 940 .buswidth = 8, 941 .mas_rpm_id = -1, 942 .slv_rpm_id = 104, 943 .num_links = ARRAY_SIZE(slv_snoc_bimc_1_links), 944 .links = slv_snoc_bimc_1_links, 945 }; 946 947 static struct qcom_icc_node slv_imem = { 948 .name = "slv_imem", 949 .id = MSM8953_SLAVE_OCIMEM, 950 .buswidth = 8, 951 .mas_rpm_id = -1, 952 .slv_rpm_id = 26, 953 }; 954 955 static const u16 slv_snoc_pcnoc_links[] = { 956 MSM8953_SNOC_PNOC_MAS 957 }; 958 959 static struct qcom_icc_node slv_snoc_pcnoc = { 960 .name = "slv_snoc_pcnoc", 961 .id = MSM8953_SNOC_PNOC_SLV, 962 .buswidth = 8, 963 .mas_rpm_id = -1, 964 .slv_rpm_id = 28, 965 .num_links = ARRAY_SIZE(slv_snoc_pcnoc_links), 966 .links = slv_snoc_pcnoc_links, 967 }; 968 969 static struct qcom_icc_node slv_qdss_stm = { 970 .name = "slv_qdss_stm", 971 .id = MSM8953_SLAVE_QDSS_STM, 972 .buswidth = 4, 973 .mas_rpm_id = -1, 974 .slv_rpm_id = 30, 975 }; 976 977 static struct qcom_icc_node slv_cats_1 = { 978 .name = "slv_cats_1", 979 .id = MSM8953_SLAVE_OCMEM_64, 980 .buswidth = 8, 981 .qos.ap_owned = true, 982 .qos.qos_mode = NOC_QOS_MODE_INVALID, 983 .qos.prio_level = 0, 984 .qos.areq_prio = 0, 985 .qos.qos_port = -1, 986 }; 987 988 static struct qcom_icc_node slv_lpass = { 989 .name = "slv_lpass", 990 .id = MSM8953_SLAVE_LPASS, 991 .buswidth = 4, 992 .qos.ap_owned = true, 993 .qos.qos_mode = NOC_QOS_MODE_INVALID, 994 .qos.prio_level = 0, 995 .qos.areq_prio = 0, 996 .qos.qos_port = -1, 997 }; 998 999 static const u16 mas_jpeg_links[] = { 1000 MSM8953_SNOC_BIMC_2_SLV 1001 }; 1002 1003 static struct qcom_icc_node mas_jpeg = { 1004 .name = "mas_jpeg", 1005 .id = MSM8953_MASTER_JPEG, 1006 .buswidth = 16, 1007 .qos.ap_owned = true, 1008 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 1009 .qos.prio_level = 0, 1010 .qos.areq_prio = 0, 1011 .qos.qos_port = 6, 1012 .num_links = ARRAY_SIZE(mas_jpeg_links), 1013 .links = mas_jpeg_links, 1014 }; 1015 1016 static const u16 mas_mdp_links[] = { 1017 MSM8953_SNOC_BIMC_0_SLV 1018 }; 1019 1020 static struct qcom_icc_node mas_mdp = { 1021 .name = "mas_mdp", 1022 .id = MSM8953_MASTER_MDP_PORT0, 1023 .buswidth = 16, 1024 .qos.ap_owned = true, 1025 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 1026 .qos.prio_level = 0, 1027 .qos.areq_prio = 0, 1028 .qos.qos_port = 7, 1029 .num_links = ARRAY_SIZE(mas_mdp_links), 1030 .links = mas_mdp_links, 1031 }; 1032 1033 static const u16 mas_venus_links[] = { 1034 MSM8953_SNOC_BIMC_2_SLV 1035 }; 1036 1037 static struct qcom_icc_node mas_venus = { 1038 .name = "mas_venus", 1039 .id = MSM8953_MASTER_VIDEO_P0, 1040 .buswidth = 16, 1041 .qos.ap_owned = true, 1042 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 1043 .qos.prio_level = 0, 1044 .qos.areq_prio = 0, 1045 .qos.qos_port = 8, 1046 .num_links = ARRAY_SIZE(mas_venus_links), 1047 .links = mas_venus_links, 1048 }; 1049 1050 static const u16 mas_vfe0_links[] = { 1051 MSM8953_SNOC_BIMC_0_SLV 1052 }; 1053 1054 static struct qcom_icc_node mas_vfe0 = { 1055 .name = "mas_vfe0", 1056 .id = MSM8953_MASTER_VFE, 1057 .buswidth = 16, 1058 .qos.ap_owned = true, 1059 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 1060 .qos.prio_level = 0, 1061 .qos.areq_prio = 0, 1062 .qos.qos_port = 9, 1063 .num_links = ARRAY_SIZE(mas_vfe0_links), 1064 .links = mas_vfe0_links, 1065 }; 1066 1067 static const u16 mas_vfe1_links[] = { 1068 MSM8953_SNOC_BIMC_0_SLV 1069 }; 1070 1071 static struct qcom_icc_node mas_vfe1 = { 1072 .name = "mas_vfe1", 1073 .id = MSM8953_MASTER_VFE1, 1074 .buswidth = 16, 1075 .qos.ap_owned = true, 1076 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 1077 .qos.prio_level = 0, 1078 .qos.areq_prio = 0, 1079 .qos.qos_port = 13, 1080 .num_links = ARRAY_SIZE(mas_vfe1_links), 1081 .links = mas_vfe1_links, 1082 }; 1083 1084 static const u16 mas_cpp_links[] = { 1085 MSM8953_SNOC_BIMC_2_SLV 1086 }; 1087 1088 static struct qcom_icc_node mas_cpp = { 1089 .name = "mas_cpp", 1090 .id = MSM8953_MASTER_CPP, 1091 .buswidth = 16, 1092 .qos.ap_owned = true, 1093 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 1094 .qos.prio_level = 0, 1095 .qos.areq_prio = 0, 1096 .qos.qos_port = 12, 1097 .num_links = ARRAY_SIZE(mas_cpp_links), 1098 .links = mas_cpp_links, 1099 }; 1100 1101 static const u16 slv_snoc_bimc_0_links[] = { 1102 MSM8953_SNOC_BIMC_0_MAS 1103 }; 1104 1105 static struct qcom_icc_node slv_snoc_bimc_0 = { 1106 .name = "slv_snoc_bimc_0", 1107 .id = MSM8953_SNOC_BIMC_0_SLV, 1108 .buswidth = 16, 1109 .qos.ap_owned = true, 1110 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1111 .qos.prio_level = 0, 1112 .qos.areq_prio = 0, 1113 .qos.qos_port = -1, 1114 .num_links = ARRAY_SIZE(slv_snoc_bimc_0_links), 1115 .links = slv_snoc_bimc_0_links, 1116 }; 1117 1118 static const u16 slv_snoc_bimc_2_links[] = { 1119 MSM8953_SNOC_BIMC_2_MAS 1120 }; 1121 1122 static struct qcom_icc_node slv_snoc_bimc_2 = { 1123 .name = "slv_snoc_bimc_2", 1124 .id = MSM8953_SNOC_BIMC_2_SLV, 1125 .buswidth = 16, 1126 .qos.ap_owned = true, 1127 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1128 .qos.prio_level = 0, 1129 .qos.areq_prio = 0, 1130 .qos.qos_port = -1, 1131 .num_links = ARRAY_SIZE(slv_snoc_bimc_2_links), 1132 .links = slv_snoc_bimc_2_links, 1133 }; 1134 1135 static struct qcom_icc_node slv_cats_0 = { 1136 .name = "slv_cats_0", 1137 .id = MSM8953_SLAVE_CATS_128, 1138 .buswidth = 16, 1139 .qos.ap_owned = true, 1140 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1141 .qos.prio_level = 0, 1142 .qos.areq_prio = 0, 1143 .qos.qos_port = -1, 1144 }; 1145 1146 static struct qcom_icc_node * const msm8953_bimc_nodes[] = { 1147 [MAS_APPS_PROC] = &mas_apps_proc, 1148 [MAS_OXILI] = &mas_oxili, 1149 [MAS_SNOC_BIMC_0] = &mas_snoc_bimc_0, 1150 [MAS_SNOC_BIMC_2] = &mas_snoc_bimc_2, 1151 [MAS_SNOC_BIMC_1] = &mas_snoc_bimc_1, 1152 [MAS_TCU_0] = &mas_tcu_0, 1153 [SLV_EBI] = &slv_ebi, 1154 [SLV_BIMC_SNOC] = &slv_bimc_snoc, 1155 }; 1156 1157 static const struct regmap_config msm8953_bimc_regmap_config = { 1158 .fast_io = true, 1159 .max_register = 0x5a000, 1160 .reg_bits = 32, 1161 .reg_stride = 4, 1162 .val_bits = 32, 1163 }; 1164 1165 static const struct qcom_icc_desc msm8953_bimc = { 1166 .type = QCOM_ICC_BIMC, 1167 .bus_clk_desc = &bimc_clk, 1168 .nodes = msm8953_bimc_nodes, 1169 .num_nodes = ARRAY_SIZE(msm8953_bimc_nodes), 1170 .qos_offset = 0x8000, 1171 .ab_coeff = 153, 1172 .regmap_cfg = &msm8953_bimc_regmap_config 1173 }; 1174 1175 static struct qcom_icc_node * const msm8953_pcnoc_nodes[] = { 1176 [MAS_SPDM] = &mas_spdm, 1177 [MAS_BLSP_1] = &mas_blsp_1, 1178 [MAS_BLSP_2] = &mas_blsp_2, 1179 [MAS_USB3] = &mas_usb3, 1180 [MAS_CRYPTO] = &mas_crypto, 1181 [MAS_SDCC_1] = &mas_sdcc_1, 1182 [MAS_SDCC_2] = &mas_sdcc_2, 1183 [MAS_SNOC_PCNOC] = &mas_snoc_pcnoc, 1184 [PCNOC_M_0] = &pcnoc_m_0, 1185 [PCNOC_M_1] = &pcnoc_m_1, 1186 [PCNOC_INT_1] = &pcnoc_int_1, 1187 [PCNOC_INT_2] = &pcnoc_int_2, 1188 [PCNOC_S_0] = &pcnoc_s_0, 1189 [PCNOC_S_1] = &pcnoc_s_1, 1190 [PCNOC_S_2] = &pcnoc_s_2, 1191 [PCNOC_S_3] = &pcnoc_s_3, 1192 [PCNOC_S_4] = &pcnoc_s_4, 1193 [PCNOC_S_6] = &pcnoc_s_6, 1194 [PCNOC_S_7] = &pcnoc_s_7, 1195 [PCNOC_S_8] = &pcnoc_s_8, 1196 [PCNOC_S_9] = &pcnoc_s_9, 1197 [SLV_SPDM] = &slv_spdm, 1198 [SLV_PDM] = &slv_pdm, 1199 [SLV_TCSR] = &slv_tcsr, 1200 [SLV_SNOC_CFG] = &slv_snoc_cfg, 1201 [SLV_TLMM] = &slv_tlmm, 1202 [SLV_MESSAGE_RAM] = &slv_message_ram, 1203 [SLV_BLSP_1] = &slv_blsp_1, 1204 [SLV_BLSP_2] = &slv_blsp_2, 1205 [SLV_PRNG] = &slv_prng, 1206 [SLV_CAMERA_SS_CFG] = &slv_camera_ss_cfg, 1207 [SLV_DISP_SS_CFG] = &slv_disp_ss_cfg, 1208 [SLV_VENUS_CFG] = &slv_venus_cfg, 1209 [SLV_GPU_CFG] = &slv_gpu_cfg, 1210 [SLV_SDCC_1] = &slv_sdcc_1, 1211 [SLV_SDCC_2] = &slv_sdcc_2, 1212 [SLV_CRYPTO_0_CFG] = &slv_crypto_0_cfg, 1213 [SLV_PMIC_ARB] = &slv_pmic_arb, 1214 [SLV_USB3] = &slv_usb3, 1215 [SLV_IPA_CFG] = &slv_ipa_cfg, 1216 [SLV_TCU] = &slv_tcu, 1217 [SLV_PCNOC_SNOC] = &slv_pcnoc_snoc, 1218 }; 1219 1220 static const char * const msm8953_pcnoc_intf_clocks[] = { 1221 "pcnoc_usb3_axi" 1222 }; 1223 1224 static const struct regmap_config msm8953_pcnoc_regmap_config = { 1225 .fast_io = true, 1226 .max_register = 0x12080, 1227 .reg_bits = 32, 1228 .reg_stride = 4, 1229 .val_bits = 32, 1230 }; 1231 1232 static const struct qcom_icc_desc msm8953_pcnoc = { 1233 .type = QCOM_ICC_NOC, 1234 .bus_clk_desc = &bus_0_clk, 1235 .intf_clocks = msm8953_pcnoc_intf_clocks, 1236 .num_intf_clocks = ARRAY_SIZE(msm8953_pcnoc_intf_clocks), 1237 .nodes = msm8953_pcnoc_nodes, 1238 .num_nodes = ARRAY_SIZE(msm8953_pcnoc_nodes), 1239 .qos_offset = 0x7000, 1240 .regmap_cfg = &msm8953_pcnoc_regmap_config, 1241 }; 1242 1243 static struct qcom_icc_node * const msm8953_snoc_nodes[] = { 1244 [MAS_QDSS_BAM] = &mas_qdss_bam, 1245 [MAS_BIMC_SNOC] = &mas_bimc_snoc, 1246 [MAS_PCNOC_SNOC] = &mas_pcnoc_snoc, 1247 [MAS_IPA] = &mas_ipa, 1248 [MAS_QDSS_ETR] = &mas_qdss_etr, 1249 [QDSS_INT] = &qdss_int, 1250 [SNOC_INT_0] = &snoc_int_0, 1251 [SNOC_INT_1] = &snoc_int_1, 1252 [SNOC_INT_2] = &snoc_int_2, 1253 [SLV_KPSS_AHB] = &slv_kpss_ahb, 1254 [SLV_WCSS] = &slv_wcss, 1255 [SLV_SNOC_BIMC_1] = &slv_snoc_bimc_1, 1256 [SLV_IMEM] = &slv_imem, 1257 [SLV_SNOC_PCNOC] = &slv_snoc_pcnoc, 1258 [SLV_QDSS_STM] = &slv_qdss_stm, 1259 [SLV_CATS_1] = &slv_cats_1, 1260 [SLV_LPASS] = &slv_lpass, 1261 }; 1262 1263 static const struct regmap_config msm8953_snoc_regmap_config = { 1264 .fast_io = true, 1265 .max_register = 0x16080, 1266 .reg_bits = 32, 1267 .reg_stride = 4, 1268 .val_bits = 32, 1269 }; 1270 1271 static const struct qcom_icc_desc msm8953_snoc = { 1272 .type = QCOM_ICC_NOC, 1273 .bus_clk_desc = &bus_1_clk, 1274 .nodes = msm8953_snoc_nodes, 1275 .num_nodes = ARRAY_SIZE(msm8953_snoc_nodes), 1276 .qos_offset = 0x7000, 1277 .regmap_cfg = &msm8953_snoc_regmap_config, 1278 }; 1279 1280 static struct qcom_icc_node * const msm8953_snoc_mm_nodes[] = { 1281 [MAS_JPEG] = &mas_jpeg, 1282 [MAS_MDP] = &mas_mdp, 1283 [MAS_VENUS] = &mas_venus, 1284 [MAS_VFE0] = &mas_vfe0, 1285 [MAS_VFE1] = &mas_vfe1, 1286 [MAS_CPP] = &mas_cpp, 1287 [SLV_SNOC_BIMC_0] = &slv_snoc_bimc_0, 1288 [SLV_SNOC_BIMC_2] = &slv_snoc_bimc_2, 1289 [SLV_CATS_0] = &slv_cats_0, 1290 }; 1291 1292 static const struct qcom_icc_desc msm8953_snoc_mm = { 1293 .type = QCOM_ICC_NOC, 1294 .bus_clk_desc = &bus_2_clk, 1295 .nodes = msm8953_snoc_mm_nodes, 1296 .num_nodes = ARRAY_SIZE(msm8953_snoc_mm_nodes), 1297 .qos_offset = 0x7000, 1298 .ab_coeff = 153, 1299 .regmap_cfg = &msm8953_snoc_regmap_config, 1300 }; 1301 1302 static const struct of_device_id msm8953_noc_of_match[] = { 1303 { .compatible = "qcom,msm8953-bimc", .data = &msm8953_bimc }, 1304 { .compatible = "qcom,msm8953-pcnoc", .data = &msm8953_pcnoc }, 1305 { .compatible = "qcom,msm8953-snoc", .data = &msm8953_snoc }, 1306 { .compatible = "qcom,msm8953-snoc-mm", .data = &msm8953_snoc_mm }, 1307 { } 1308 }; 1309 MODULE_DEVICE_TABLE(of, msm8953_noc_of_match); 1310 1311 static struct platform_driver msm8953_noc_driver = { 1312 .probe = qnoc_probe, 1313 .remove = qnoc_remove, 1314 .driver = { 1315 .name = "qnoc-msm8953", 1316 .of_match_table = msm8953_noc_of_match, 1317 }, 1318 }; 1319 1320 module_platform_driver(msm8953_noc_driver); 1321 MODULE_DESCRIPTION("Qualcomm MSM8953 NoC driver"); 1322 MODULE_LICENSE("GPL"); 1323