1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Based on data from msm8937-bus.dtsi in Qualcomm's msm-3.18 release: 4 * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. 5 */ 6 7 #include <linux/device.h> 8 #include <linux/interconnect-provider.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 #include <linux/regmap.h> 12 13 #include <dt-bindings/interconnect/qcom,msm8937.h> 14 15 #include "icc-rpm.h" 16 17 enum { 18 QNOC_MASTER_AMPSS_M0 = 1, 19 QNOC_MASTER_GRAPHICS_3D, 20 QNOC_SNOC_BIMC_0_MAS, 21 QNOC_SNOC_BIMC_2_MAS, 22 QNOC_SNOC_BIMC_1_MAS, 23 QNOC_MASTER_TCU_0, 24 QNOC_MASTER_SPDM, 25 QNOC_MASTER_BLSP_1, 26 QNOC_MASTER_BLSP_2, 27 QNOC_MASTER_USB_HS, 28 QNOC_MASTER_XM_USB_HS1, 29 QNOC_MASTER_CRYPTO_CORE0, 30 QNOC_MASTER_SDCC_1, 31 QNOC_MASTER_SDCC_2, 32 QNOC_SNOC_PNOC_MAS, 33 QNOC_MASTER_QDSS_BAM, 34 QNOC_BIMC_SNOC_MAS, 35 QNOC_MASTER_JPEG, 36 QNOC_MASTER_MDP_PORT0, 37 QNOC_PNOC_SNOC_MAS, 38 QNOC_MASTER_VIDEO_P0, 39 QNOC_MASTER_VFE, 40 QNOC_MASTER_VFE1, 41 QNOC_MASTER_CPP, 42 QNOC_MASTER_QDSS_ETR, 43 QNOC_PNOC_M_0, 44 QNOC_PNOC_M_1, 45 QNOC_PNOC_INT_0, 46 QNOC_PNOC_INT_1, 47 QNOC_PNOC_INT_2, 48 QNOC_PNOC_INT_3, 49 QNOC_PNOC_SLV_0, 50 QNOC_PNOC_SLV_1, 51 QNOC_PNOC_SLV_2, 52 QNOC_PNOC_SLV_3, 53 QNOC_PNOC_SLV_4, 54 QNOC_PNOC_SLV_6, 55 QNOC_PNOC_SLV_7, 56 QNOC_PNOC_SLV_8, 57 QNOC_SNOC_QDSS_INT, 58 QNOC_SNOC_INT_0, 59 QNOC_SNOC_INT_1, 60 QNOC_SNOC_INT_2, 61 QNOC_SLAVE_EBI_CH0, 62 QNOC_BIMC_SNOC_SLV, 63 QNOC_SLAVE_SDCC_2, 64 QNOC_SLAVE_SPDM_WRAPPER, 65 QNOC_SLAVE_PDM, 66 QNOC_SLAVE_PRNG, 67 QNOC_SLAVE_TCSR, 68 QNOC_SLAVE_SNOC_CFG, 69 QNOC_SLAVE_MESSAGE_RAM, 70 QNOC_SLAVE_CAMERA_CFG, 71 QNOC_SLAVE_DISPLAY_CFG, 72 QNOC_SLAVE_VENUS_CFG, 73 QNOC_SLAVE_GRAPHICS_3D_CFG, 74 QNOC_SLAVE_TLMM, 75 QNOC_SLAVE_BLSP_1, 76 QNOC_SLAVE_BLSP_2, 77 QNOC_SLAVE_PMIC_ARB, 78 QNOC_SLAVE_SDCC_1, 79 QNOC_SLAVE_CRYPTO_0_CFG, 80 QNOC_SLAVE_USB_HS, 81 QNOC_SLAVE_TCU, 82 QNOC_PNOC_SNOC_SLV, 83 QNOC_SLAVE_APPSS, 84 QNOC_SLAVE_WCSS, 85 QNOC_SNOC_BIMC_0_SLV, 86 QNOC_SNOC_BIMC_1_SLV, 87 QNOC_SNOC_BIMC_2_SLV, 88 QNOC_SLAVE_OCIMEM, 89 QNOC_SNOC_PNOC_SLV, 90 QNOC_SLAVE_QDSS_STM, 91 QNOC_SLAVE_CATS_128, 92 QNOC_SLAVE_OCMEM_64, 93 QNOC_SLAVE_LPASS, 94 }; 95 96 static const u16 mas_apps_proc_links[] = { 97 QNOC_SLAVE_EBI_CH0, 98 QNOC_BIMC_SNOC_SLV 99 }; 100 101 static struct qcom_icc_node mas_apps_proc = { 102 .name = "mas_apps_proc", 103 .id = QNOC_MASTER_AMPSS_M0, 104 .buswidth = 8, 105 .mas_rpm_id = 0, 106 .slv_rpm_id = -1, 107 .qos.ap_owned = true, 108 .qos.qos_mode = NOC_QOS_MODE_FIXED, 109 .qos.areq_prio = 0, 110 .qos.prio_level = 0, 111 .qos.qos_port = 0, 112 .num_links = ARRAY_SIZE(mas_apps_proc_links), 113 .links = mas_apps_proc_links, 114 }; 115 116 static const u16 mas_oxili_links[] = { 117 QNOC_SLAVE_EBI_CH0, 118 QNOC_BIMC_SNOC_SLV 119 }; 120 121 static struct qcom_icc_node mas_oxili = { 122 .name = "mas_oxili", 123 .id = QNOC_MASTER_GRAPHICS_3D, 124 .buswidth = 8, 125 .mas_rpm_id = 6, 126 .slv_rpm_id = -1, 127 .qos.ap_owned = true, 128 .qos.qos_mode = NOC_QOS_MODE_FIXED, 129 .qos.areq_prio = 0, 130 .qos.prio_level = 0, 131 .qos.qos_port = 2, 132 .num_links = ARRAY_SIZE(mas_oxili_links), 133 .links = mas_oxili_links, 134 }; 135 136 static const u16 mas_snoc_bimc_0_links[] = { 137 QNOC_SLAVE_EBI_CH0, 138 QNOC_BIMC_SNOC_SLV 139 }; 140 141 static struct qcom_icc_node mas_snoc_bimc_0 = { 142 .name = "mas_snoc_bimc_0", 143 .id = QNOC_SNOC_BIMC_0_MAS, 144 .buswidth = 8, 145 .mas_rpm_id = 3, 146 .slv_rpm_id = -1, 147 .qos.ap_owned = true, 148 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 149 .qos.areq_prio = 0, 150 .qos.prio_level = 0, 151 .qos.qos_port = 3, 152 .num_links = ARRAY_SIZE(mas_snoc_bimc_0_links), 153 .links = mas_snoc_bimc_0_links, 154 }; 155 156 static const u16 mas_snoc_bimc_2_links[] = { 157 QNOC_SLAVE_EBI_CH0, 158 QNOC_BIMC_SNOC_SLV 159 }; 160 161 static struct qcom_icc_node mas_snoc_bimc_2 = { 162 .name = "mas_snoc_bimc_2", 163 .id = QNOC_SNOC_BIMC_2_MAS, 164 .buswidth = 8, 165 .mas_rpm_id = 108, 166 .slv_rpm_id = -1, 167 .qos.ap_owned = true, 168 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 169 .qos.areq_prio = 0, 170 .qos.prio_level = 0, 171 .qos.qos_port = 4, 172 .num_links = ARRAY_SIZE(mas_snoc_bimc_2_links), 173 .links = mas_snoc_bimc_2_links, 174 }; 175 176 static const u16 mas_snoc_bimc_1_links[] = { 177 QNOC_SLAVE_EBI_CH0 178 }; 179 180 static struct qcom_icc_node mas_snoc_bimc_1 = { 181 .name = "mas_snoc_bimc_1", 182 .id = QNOC_SNOC_BIMC_1_MAS, 183 .buswidth = 8, 184 .mas_rpm_id = 76, 185 .slv_rpm_id = -1, 186 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 187 .qos.areq_prio = 0, 188 .qos.prio_level = 0, 189 .qos.qos_port = 5, 190 .num_links = ARRAY_SIZE(mas_snoc_bimc_1_links), 191 .links = mas_snoc_bimc_1_links, 192 }; 193 194 static const u16 mas_tcu_0_links[] = { 195 QNOC_SLAVE_EBI_CH0, 196 QNOC_BIMC_SNOC_SLV 197 }; 198 199 static struct qcom_icc_node mas_tcu_0 = { 200 .name = "mas_tcu_0", 201 .id = QNOC_MASTER_TCU_0, 202 .buswidth = 8, 203 .mas_rpm_id = 102, 204 .slv_rpm_id = -1, 205 .qos.ap_owned = true, 206 .qos.qos_mode = NOC_QOS_MODE_FIXED, 207 .qos.areq_prio = 0, 208 .qos.prio_level = 2, 209 .qos.qos_port = 6, 210 .num_links = ARRAY_SIZE(mas_tcu_0_links), 211 .links = mas_tcu_0_links, 212 }; 213 214 static const u16 mas_spdm_links[] = { 215 QNOC_PNOC_M_0 216 }; 217 218 static struct qcom_icc_node mas_spdm = { 219 .name = "mas_spdm", 220 .id = QNOC_MASTER_SPDM, 221 .buswidth = 4, 222 .mas_rpm_id = 50, 223 .slv_rpm_id = -1, 224 .qos.ap_owned = true, 225 .qos.qos_mode = NOC_QOS_MODE_INVALID, 226 .num_links = ARRAY_SIZE(mas_spdm_links), 227 .links = mas_spdm_links, 228 }; 229 230 static const u16 mas_blsp_1_links[] = { 231 QNOC_PNOC_M_1 232 }; 233 234 static struct qcom_icc_node mas_blsp_1 = { 235 .name = "mas_blsp_1", 236 .id = QNOC_MASTER_BLSP_1, 237 .buswidth = 4, 238 .mas_rpm_id = 41, 239 .slv_rpm_id = -1, 240 .num_links = ARRAY_SIZE(mas_blsp_1_links), 241 .links = mas_blsp_1_links, 242 }; 243 244 static const u16 mas_blsp_2_links[] = { 245 QNOC_PNOC_M_1 246 }; 247 248 static struct qcom_icc_node mas_blsp_2 = { 249 .name = "mas_blsp_2", 250 .id = QNOC_MASTER_BLSP_2, 251 .buswidth = 4, 252 .mas_rpm_id = 39, 253 .slv_rpm_id = -1, 254 .num_links = ARRAY_SIZE(mas_blsp_2_links), 255 .links = mas_blsp_2_links, 256 }; 257 258 static const u16 mas_usb_hs1_links[] = { 259 QNOC_PNOC_INT_0 260 }; 261 262 static struct qcom_icc_node mas_usb_hs1 = { 263 .name = "mas_usb_hs1", 264 .id = QNOC_MASTER_USB_HS, 265 .buswidth = 4, 266 .mas_rpm_id = 42, 267 .slv_rpm_id = -1, 268 .qos.ap_owned = true, 269 .qos.qos_mode = NOC_QOS_MODE_FIXED, 270 .qos.areq_prio = 1, 271 .qos.prio_level = 1, 272 .qos.qos_port = 12, 273 .num_links = ARRAY_SIZE(mas_usb_hs1_links), 274 .links = mas_usb_hs1_links, 275 }; 276 277 static const u16 mas_xi_usb_hs1_links[] = { 278 QNOC_PNOC_INT_0 279 }; 280 281 static struct qcom_icc_node mas_xi_usb_hs1 = { 282 .name = "mas_xi_usb_hs1", 283 .id = QNOC_MASTER_XM_USB_HS1, 284 .buswidth = 8, 285 .mas_rpm_id = 138, 286 .slv_rpm_id = -1, 287 .qos.qos_mode = NOC_QOS_MODE_FIXED, 288 .qos.areq_prio = 0, 289 .qos.prio_level = 0, 290 .qos.qos_port = 11, 291 .num_links = ARRAY_SIZE(mas_xi_usb_hs1_links), 292 .links = mas_xi_usb_hs1_links, 293 }; 294 295 static const u16 mas_crypto_links[] = { 296 QNOC_PNOC_INT_0 297 }; 298 299 static struct qcom_icc_node mas_crypto = { 300 .name = "mas_crypto", 301 .id = QNOC_MASTER_CRYPTO_CORE0, 302 .buswidth = 8, 303 .mas_rpm_id = 23, 304 .slv_rpm_id = -1, 305 .qos.ap_owned = true, 306 .qos.qos_mode = NOC_QOS_MODE_FIXED, 307 .qos.areq_prio = 1, 308 .qos.prio_level = 1, 309 .qos.qos_port = 0, 310 .num_links = ARRAY_SIZE(mas_crypto_links), 311 .links = mas_crypto_links, 312 }; 313 314 static const u16 mas_sdcc_1_links[] = { 315 QNOC_PNOC_INT_0 316 }; 317 318 static struct qcom_icc_node mas_sdcc_1 = { 319 .name = "mas_sdcc_1", 320 .id = QNOC_MASTER_SDCC_1, 321 .buswidth = 8, 322 .mas_rpm_id = 33, 323 .slv_rpm_id = -1, 324 .qos.qos_mode = NOC_QOS_MODE_FIXED, 325 .qos.areq_prio = 0, 326 .qos.prio_level = 0, 327 .qos.qos_port = 7, 328 .num_links = ARRAY_SIZE(mas_sdcc_1_links), 329 .links = mas_sdcc_1_links, 330 }; 331 332 static const u16 mas_sdcc_2_links[] = { 333 QNOC_PNOC_INT_0 334 }; 335 336 static struct qcom_icc_node mas_sdcc_2 = { 337 .name = "mas_sdcc_2", 338 .id = QNOC_MASTER_SDCC_2, 339 .buswidth = 8, 340 .mas_rpm_id = 35, 341 .slv_rpm_id = -1, 342 .qos.qos_mode = NOC_QOS_MODE_FIXED, 343 .qos.areq_prio = 0, 344 .qos.prio_level = 0, 345 .qos.qos_port = 8, 346 .num_links = ARRAY_SIZE(mas_sdcc_2_links), 347 .links = mas_sdcc_2_links, 348 }; 349 350 static const u16 mas_snoc_pcnoc_links[] = { 351 QNOC_PNOC_SLV_7, 352 QNOC_PNOC_INT_2, 353 QNOC_PNOC_INT_3 354 }; 355 356 static struct qcom_icc_node mas_snoc_pcnoc = { 357 .name = "mas_snoc_pcnoc", 358 .id = QNOC_SNOC_PNOC_MAS, 359 .buswidth = 8, 360 .mas_rpm_id = 77, 361 .slv_rpm_id = -1, 362 .qos.qos_mode = NOC_QOS_MODE_FIXED, 363 .qos.areq_prio = 0, 364 .qos.prio_level = 0, 365 .qos.qos_port = 9, 366 .num_links = ARRAY_SIZE(mas_snoc_pcnoc_links), 367 .links = mas_snoc_pcnoc_links, 368 }; 369 370 static const u16 mas_qdss_bam_links[] = { 371 QNOC_SNOC_QDSS_INT 372 }; 373 374 static struct qcom_icc_node mas_qdss_bam = { 375 .name = "mas_qdss_bam", 376 .id = QNOC_MASTER_QDSS_BAM, 377 .buswidth = 4, 378 .mas_rpm_id = 19, 379 .slv_rpm_id = -1, 380 .qos.ap_owned = true, 381 .qos.qos_mode = NOC_QOS_MODE_FIXED, 382 .qos.areq_prio = 1, 383 .qos.prio_level = 1, 384 .qos.qos_port = 11, 385 .num_links = ARRAY_SIZE(mas_qdss_bam_links), 386 .links = mas_qdss_bam_links, 387 }; 388 389 static const u16 mas_bimc_snoc_links[] = { 390 QNOC_SNOC_INT_0, 391 QNOC_SNOC_INT_1, 392 QNOC_SNOC_INT_2 393 }; 394 395 static struct qcom_icc_node mas_bimc_snoc = { 396 .name = "mas_bimc_snoc", 397 .id = QNOC_BIMC_SNOC_MAS, 398 .buswidth = 8, 399 .mas_rpm_id = 21, 400 .slv_rpm_id = -1, 401 .num_links = ARRAY_SIZE(mas_bimc_snoc_links), 402 .links = mas_bimc_snoc_links, 403 }; 404 405 static const u16 mas_jpeg_links[] = { 406 QNOC_SNOC_BIMC_2_SLV 407 }; 408 409 static struct qcom_icc_node mas_jpeg = { 410 .name = "mas_jpeg", 411 .id = QNOC_MASTER_JPEG, 412 .buswidth = 16, 413 .mas_rpm_id = 7, 414 .slv_rpm_id = -1, 415 .qos.ap_owned = true, 416 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 417 .qos.areq_prio = 0, 418 .qos.prio_level = 0, 419 .qos.qos_port = 6, 420 .num_links = ARRAY_SIZE(mas_jpeg_links), 421 .links = mas_jpeg_links, 422 }; 423 424 static const u16 mas_mdp_links[] = { 425 QNOC_SNOC_BIMC_0_SLV 426 }; 427 428 static struct qcom_icc_node mas_mdp = { 429 .name = "mas_mdp", 430 .id = QNOC_MASTER_MDP_PORT0, 431 .buswidth = 16, 432 .mas_rpm_id = 8, 433 .slv_rpm_id = -1, 434 .qos.ap_owned = true, 435 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 436 .qos.areq_prio = 0, 437 .qos.prio_level = 0, 438 .qos.qos_port = 7, 439 .num_links = ARRAY_SIZE(mas_mdp_links), 440 .links = mas_mdp_links, 441 }; 442 443 static const u16 mas_pcnoc_snoc_links[] = { 444 QNOC_SNOC_INT_0, 445 QNOC_SNOC_INT_1, 446 QNOC_SNOC_BIMC_1_SLV 447 }; 448 449 static struct qcom_icc_node mas_pcnoc_snoc = { 450 .name = "mas_pcnoc_snoc", 451 .id = QNOC_PNOC_SNOC_MAS, 452 .buswidth = 8, 453 .mas_rpm_id = 29, 454 .slv_rpm_id = -1, 455 .qos.qos_mode = NOC_QOS_MODE_FIXED, 456 .qos.areq_prio = 0, 457 .qos.prio_level = 0, 458 .qos.qos_port = 5, 459 .num_links = ARRAY_SIZE(mas_pcnoc_snoc_links), 460 .links = mas_pcnoc_snoc_links, 461 }; 462 463 static const u16 mas_venus_links[] = { 464 QNOC_SNOC_BIMC_2_SLV 465 }; 466 467 static struct qcom_icc_node mas_venus = { 468 .name = "mas_venus", 469 .id = QNOC_MASTER_VIDEO_P0, 470 .buswidth = 16, 471 .mas_rpm_id = 9, 472 .slv_rpm_id = -1, 473 .qos.ap_owned = true, 474 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 475 .qos.areq_prio = 0, 476 .qos.prio_level = 0, 477 .qos.qos_port = 8, 478 .num_links = ARRAY_SIZE(mas_venus_links), 479 .links = mas_venus_links, 480 }; 481 482 static const u16 mas_vfe0_links[] = { 483 QNOC_SNOC_BIMC_0_SLV 484 }; 485 486 static struct qcom_icc_node mas_vfe0 = { 487 .name = "mas_vfe0", 488 .id = QNOC_MASTER_VFE, 489 .buswidth = 16, 490 .mas_rpm_id = 11, 491 .slv_rpm_id = -1, 492 .qos.ap_owned = true, 493 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 494 .qos.areq_prio = 0, 495 .qos.prio_level = 0, 496 .qos.qos_port = 9, 497 .num_links = ARRAY_SIZE(mas_vfe0_links), 498 .links = mas_vfe0_links, 499 }; 500 501 static const u16 mas_vfe1_links[] = { 502 QNOC_SNOC_BIMC_0_SLV 503 }; 504 505 static struct qcom_icc_node mas_vfe1 = { 506 .name = "mas_vfe1", 507 .id = QNOC_MASTER_VFE1, 508 .buswidth = 16, 509 .mas_rpm_id = 133, 510 .slv_rpm_id = -1, 511 .qos.ap_owned = true, 512 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 513 .qos.areq_prio = 0, 514 .qos.prio_level = 0, 515 .qos.qos_port = 13, 516 .num_links = ARRAY_SIZE(mas_vfe1_links), 517 .links = mas_vfe1_links, 518 }; 519 520 static const u16 mas_cpp_links[] = { 521 QNOC_SNOC_BIMC_2_SLV 522 }; 523 524 static struct qcom_icc_node mas_cpp = { 525 .name = "mas_cpp", 526 .id = QNOC_MASTER_CPP, 527 .buswidth = 16, 528 .mas_rpm_id = 115, 529 .slv_rpm_id = -1, 530 .qos.ap_owned = true, 531 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 532 .qos.areq_prio = 0, 533 .qos.prio_level = 0, 534 .qos.qos_port = 12, 535 .num_links = ARRAY_SIZE(mas_cpp_links), 536 .links = mas_cpp_links, 537 }; 538 539 static const u16 mas_qdss_etr_links[] = { 540 QNOC_SNOC_QDSS_INT 541 }; 542 543 static struct qcom_icc_node mas_qdss_etr = { 544 .name = "mas_qdss_etr", 545 .id = QNOC_MASTER_QDSS_ETR, 546 .buswidth = 8, 547 .mas_rpm_id = 31, 548 .slv_rpm_id = -1, 549 .qos.ap_owned = true, 550 .qos.qos_mode = NOC_QOS_MODE_FIXED, 551 .qos.areq_prio = 1, 552 .qos.prio_level = 1, 553 .qos.qos_port = 10, 554 .num_links = ARRAY_SIZE(mas_qdss_etr_links), 555 .links = mas_qdss_etr_links, 556 }; 557 558 static const u16 pcnoc_m_0_links[] = { 559 QNOC_PNOC_INT_0 560 }; 561 562 static struct qcom_icc_node pcnoc_m_0 = { 563 .name = "pcnoc_m_0", 564 .id = QNOC_PNOC_M_0, 565 .buswidth = 4, 566 .mas_rpm_id = 87, 567 .slv_rpm_id = 116, 568 .qos.ap_owned = true, 569 .qos.qos_mode = NOC_QOS_MODE_FIXED, 570 .qos.areq_prio = 1, 571 .qos.prio_level = 1, 572 .qos.qos_port = 5, 573 .num_links = ARRAY_SIZE(pcnoc_m_0_links), 574 .links = pcnoc_m_0_links, 575 }; 576 577 static const u16 pcnoc_m_1_links[] = { 578 QNOC_PNOC_INT_0 579 }; 580 581 static struct qcom_icc_node pcnoc_m_1 = { 582 .name = "pcnoc_m_1", 583 .id = QNOC_PNOC_M_1, 584 .buswidth = 4, 585 .mas_rpm_id = 88, 586 .slv_rpm_id = 117, 587 .num_links = ARRAY_SIZE(pcnoc_m_1_links), 588 .links = pcnoc_m_1_links, 589 }; 590 591 static const u16 pcnoc_int_0_links[] = { 592 QNOC_PNOC_SNOC_SLV, 593 QNOC_PNOC_SLV_7, 594 QNOC_PNOC_INT_3, 595 QNOC_PNOC_INT_2 596 }; 597 598 static struct qcom_icc_node pcnoc_int_0 = { 599 .name = "pcnoc_int_0", 600 .id = QNOC_PNOC_INT_0, 601 .buswidth = 8, 602 .mas_rpm_id = 85, 603 .slv_rpm_id = 114, 604 .num_links = ARRAY_SIZE(pcnoc_int_0_links), 605 .links = pcnoc_int_0_links, 606 }; 607 608 static const u16 pcnoc_int_1_links[] = { 609 QNOC_PNOC_SNOC_SLV, 610 QNOC_PNOC_SLV_7, 611 QNOC_PNOC_INT_3, 612 QNOC_PNOC_INT_2 613 }; 614 615 static struct qcom_icc_node pcnoc_int_1 = { 616 .name = "pcnoc_int_1", 617 .id = QNOC_PNOC_INT_1, 618 .buswidth = 8, 619 .mas_rpm_id = -1, 620 .slv_rpm_id = -1, 621 .num_links = ARRAY_SIZE(pcnoc_int_1_links), 622 .links = pcnoc_int_1_links, 623 }; 624 625 static const u16 pcnoc_int_2_links[] = { 626 QNOC_PNOC_SLV_2, 627 QNOC_PNOC_SLV_3, 628 QNOC_PNOC_SLV_6, 629 QNOC_PNOC_SLV_8 630 }; 631 632 static struct qcom_icc_node pcnoc_int_2 = { 633 .name = "pcnoc_int_2", 634 .id = QNOC_PNOC_INT_2, 635 .buswidth = 8, 636 .mas_rpm_id = 124, 637 .slv_rpm_id = 184, 638 .num_links = ARRAY_SIZE(pcnoc_int_2_links), 639 .links = pcnoc_int_2_links, 640 }; 641 642 static const u16 pcnoc_int_3_links[] = { 643 QNOC_PNOC_SLV_1, 644 QNOC_PNOC_SLV_0, 645 QNOC_PNOC_SLV_4, 646 QNOC_SLAVE_GRAPHICS_3D_CFG, 647 QNOC_SLAVE_TCU 648 }; 649 650 static struct qcom_icc_node pcnoc_int_3 = { 651 .name = "pcnoc_int_3", 652 .id = QNOC_PNOC_INT_3, 653 .buswidth = 8, 654 .mas_rpm_id = 125, 655 .slv_rpm_id = 185, 656 .num_links = ARRAY_SIZE(pcnoc_int_3_links), 657 .links = pcnoc_int_3_links, 658 }; 659 660 static const u16 pcnoc_s_0_links[] = { 661 QNOC_SLAVE_SPDM_WRAPPER, 662 QNOC_SLAVE_PDM, 663 QNOC_SLAVE_PRNG, 664 QNOC_SLAVE_SDCC_2 665 }; 666 667 static struct qcom_icc_node pcnoc_s_0 = { 668 .name = "pcnoc_s_0", 669 .id = QNOC_PNOC_SLV_0, 670 .buswidth = 4, 671 .mas_rpm_id = 89, 672 .slv_rpm_id = 118, 673 .num_links = ARRAY_SIZE(pcnoc_s_0_links), 674 .links = pcnoc_s_0_links, 675 }; 676 677 static const u16 pcnoc_s_1_links[] = { 678 QNOC_SLAVE_TCSR 679 }; 680 681 static struct qcom_icc_node pcnoc_s_1 = { 682 .name = "pcnoc_s_1", 683 .id = QNOC_PNOC_SLV_1, 684 .buswidth = 4, 685 .mas_rpm_id = 90, 686 .slv_rpm_id = 119, 687 .num_links = ARRAY_SIZE(pcnoc_s_1_links), 688 .links = pcnoc_s_1_links, 689 }; 690 691 static const u16 pcnoc_s_2_links[] = { 692 QNOC_SLAVE_SNOC_CFG 693 }; 694 695 static struct qcom_icc_node pcnoc_s_2 = { 696 .name = "pcnoc_s_2", 697 .id = QNOC_PNOC_SLV_2, 698 .buswidth = 4, 699 .mas_rpm_id = 91, 700 .slv_rpm_id = 120, 701 .num_links = ARRAY_SIZE(pcnoc_s_2_links), 702 .links = pcnoc_s_2_links, 703 }; 704 705 static const u16 pcnoc_s_3_links[] = { 706 QNOC_SLAVE_MESSAGE_RAM 707 }; 708 709 static struct qcom_icc_node pcnoc_s_3 = { 710 .name = "pcnoc_s_3", 711 .id = QNOC_PNOC_SLV_3, 712 .buswidth = 4, 713 .mas_rpm_id = 92, 714 .slv_rpm_id = 121, 715 .num_links = ARRAY_SIZE(pcnoc_s_3_links), 716 .links = pcnoc_s_3_links, 717 }; 718 719 static const u16 pcnoc_s_4_links[] = { 720 QNOC_SLAVE_CAMERA_CFG, 721 QNOC_SLAVE_DISPLAY_CFG, 722 QNOC_SLAVE_VENUS_CFG 723 }; 724 725 static struct qcom_icc_node pcnoc_s_4 = { 726 .name = "pcnoc_s_4", 727 .id = QNOC_PNOC_SLV_4, 728 .buswidth = 4, 729 .mas_rpm_id = 93, 730 .slv_rpm_id = 122, 731 .qos.ap_owned = true, 732 .qos.qos_mode = NOC_QOS_MODE_INVALID, 733 .num_links = ARRAY_SIZE(pcnoc_s_4_links), 734 .links = pcnoc_s_4_links, 735 }; 736 737 static const u16 pcnoc_s_6_links[] = { 738 QNOC_SLAVE_TLMM, 739 QNOC_SLAVE_BLSP_1, 740 QNOC_SLAVE_BLSP_2 741 }; 742 743 static struct qcom_icc_node pcnoc_s_6 = { 744 .name = "pcnoc_s_6", 745 .id = QNOC_PNOC_SLV_6, 746 .buswidth = 4, 747 .mas_rpm_id = 94, 748 .slv_rpm_id = 123, 749 .num_links = ARRAY_SIZE(pcnoc_s_6_links), 750 .links = pcnoc_s_6_links, 751 }; 752 753 static const u16 pcnoc_s_7_links[] = { 754 QNOC_SLAVE_SDCC_1, 755 QNOC_SLAVE_PMIC_ARB 756 }; 757 758 static struct qcom_icc_node pcnoc_s_7 = { 759 .name = "pcnoc_s_7", 760 .id = QNOC_PNOC_SLV_7, 761 .buswidth = 4, 762 .mas_rpm_id = 95, 763 .slv_rpm_id = 124, 764 .num_links = ARRAY_SIZE(pcnoc_s_7_links), 765 .links = pcnoc_s_7_links, 766 }; 767 768 static const u16 pcnoc_s_8_links[] = { 769 QNOC_SLAVE_USB_HS, 770 QNOC_SLAVE_CRYPTO_0_CFG 771 }; 772 773 static struct qcom_icc_node pcnoc_s_8 = { 774 .name = "pcnoc_s_8", 775 .id = QNOC_PNOC_SLV_8, 776 .buswidth = 4, 777 .mas_rpm_id = 96, 778 .slv_rpm_id = 125, 779 .num_links = ARRAY_SIZE(pcnoc_s_8_links), 780 .links = pcnoc_s_8_links, 781 }; 782 783 static const u16 qdss_int_links[] = { 784 QNOC_SNOC_INT_1, 785 QNOC_SNOC_BIMC_1_SLV 786 }; 787 788 static struct qcom_icc_node qdss_int = { 789 .name = "qdss_int", 790 .id = QNOC_SNOC_QDSS_INT, 791 .buswidth = 8, 792 .mas_rpm_id = 98, 793 .slv_rpm_id = 128, 794 .qos.ap_owned = true, 795 .qos.qos_mode = NOC_QOS_MODE_INVALID, 796 .num_links = ARRAY_SIZE(qdss_int_links), 797 .links = qdss_int_links, 798 }; 799 800 static const u16 snoc_int_0_links[] = { 801 QNOC_SLAVE_LPASS, 802 QNOC_SLAVE_WCSS, 803 QNOC_SLAVE_APPSS 804 }; 805 806 static struct qcom_icc_node snoc_int_0 = { 807 .name = "snoc_int_0", 808 .id = QNOC_SNOC_INT_0, 809 .buswidth = 8, 810 .mas_rpm_id = 99, 811 .slv_rpm_id = 130, 812 .qos.ap_owned = true, 813 .qos.qos_mode = NOC_QOS_MODE_INVALID, 814 .num_links = ARRAY_SIZE(snoc_int_0_links), 815 .links = snoc_int_0_links, 816 }; 817 818 static const u16 snoc_int_1_links[] = { 819 QNOC_SLAVE_QDSS_STM, 820 QNOC_SLAVE_OCIMEM, 821 QNOC_SNOC_PNOC_SLV 822 }; 823 824 static struct qcom_icc_node snoc_int_1 = { 825 .name = "snoc_int_1", 826 .id = QNOC_SNOC_INT_1, 827 .buswidth = 8, 828 .mas_rpm_id = 100, 829 .slv_rpm_id = 131, 830 .num_links = ARRAY_SIZE(snoc_int_1_links), 831 .links = snoc_int_1_links, 832 }; 833 834 static const u16 snoc_int_2_links[] = { 835 QNOC_SLAVE_CATS_128, 836 QNOC_SLAVE_OCMEM_64 837 }; 838 839 static struct qcom_icc_node snoc_int_2 = { 840 .name = "snoc_int_2", 841 .id = QNOC_SNOC_INT_2, 842 .buswidth = 8, 843 .mas_rpm_id = 134, 844 .slv_rpm_id = 197, 845 .qos.ap_owned = true, 846 .qos.qos_mode = NOC_QOS_MODE_INVALID, 847 .num_links = ARRAY_SIZE(snoc_int_2_links), 848 .links = snoc_int_2_links, 849 }; 850 851 static struct qcom_icc_node slv_ebi = { 852 .name = "slv_ebi", 853 .id = QNOC_SLAVE_EBI_CH0, 854 .buswidth = 8, 855 .mas_rpm_id = -1, 856 .slv_rpm_id = 0, 857 }; 858 859 static const u16 slv_bimc_snoc_links[] = { 860 QNOC_BIMC_SNOC_MAS 861 }; 862 863 static struct qcom_icc_node slv_bimc_snoc = { 864 .name = "slv_bimc_snoc", 865 .id = QNOC_BIMC_SNOC_SLV, 866 .buswidth = 8, 867 .mas_rpm_id = -1, 868 .slv_rpm_id = 2, 869 .num_links = ARRAY_SIZE(slv_bimc_snoc_links), 870 .links = slv_bimc_snoc_links, 871 }; 872 873 static struct qcom_icc_node slv_sdcc_2 = { 874 .name = "slv_sdcc_2", 875 .id = QNOC_SLAVE_SDCC_2, 876 .buswidth = 4, 877 .mas_rpm_id = -1, 878 .slv_rpm_id = 33, 879 }; 880 881 static struct qcom_icc_node slv_spdm = { 882 .name = "slv_spdm", 883 .id = QNOC_SLAVE_SPDM_WRAPPER, 884 .buswidth = 4, 885 .mas_rpm_id = -1, 886 .slv_rpm_id = 60, 887 .qos.ap_owned = true, 888 .qos.qos_mode = NOC_QOS_MODE_INVALID, 889 }; 890 891 static struct qcom_icc_node slv_pdm = { 892 .name = "slv_pdm", 893 .id = QNOC_SLAVE_PDM, 894 .buswidth = 4, 895 .mas_rpm_id = -1, 896 .slv_rpm_id = 41, 897 }; 898 899 static struct qcom_icc_node slv_prng = { 900 .name = "slv_prng", 901 .id = QNOC_SLAVE_PRNG, 902 .buswidth = 4, 903 .mas_rpm_id = -1, 904 .slv_rpm_id = 44, 905 }; 906 907 static struct qcom_icc_node slv_tcsr = { 908 .name = "slv_tcsr", 909 .id = QNOC_SLAVE_TCSR, 910 .buswidth = 4, 911 .mas_rpm_id = -1, 912 .slv_rpm_id = 50, 913 }; 914 915 static struct qcom_icc_node slv_snoc_cfg = { 916 .name = "slv_snoc_cfg", 917 .id = QNOC_SLAVE_SNOC_CFG, 918 .buswidth = 4, 919 .mas_rpm_id = -1, 920 .slv_rpm_id = 70, 921 }; 922 923 static struct qcom_icc_node slv_message_ram = { 924 .name = "slv_message_ram", 925 .id = QNOC_SLAVE_MESSAGE_RAM, 926 .buswidth = 4, 927 .mas_rpm_id = -1, 928 .slv_rpm_id = 55, 929 }; 930 931 static struct qcom_icc_node slv_camera_ss_cfg = { 932 .name = "slv_camera_ss_cfg", 933 .id = QNOC_SLAVE_CAMERA_CFG, 934 .buswidth = 4, 935 .mas_rpm_id = -1, 936 .slv_rpm_id = 3, 937 .qos.ap_owned = true, 938 .qos.qos_mode = NOC_QOS_MODE_INVALID, 939 }; 940 941 static struct qcom_icc_node slv_disp_ss_cfg = { 942 .name = "slv_disp_ss_cfg", 943 .id = QNOC_SLAVE_DISPLAY_CFG, 944 .buswidth = 4, 945 .mas_rpm_id = -1, 946 .slv_rpm_id = 4, 947 .qos.ap_owned = true, 948 .qos.qos_mode = NOC_QOS_MODE_INVALID, 949 }; 950 951 static struct qcom_icc_node slv_venus_cfg = { 952 .name = "slv_venus_cfg", 953 .id = QNOC_SLAVE_VENUS_CFG, 954 .buswidth = 4, 955 .mas_rpm_id = -1, 956 .slv_rpm_id = 10, 957 .qos.ap_owned = true, 958 .qos.qos_mode = NOC_QOS_MODE_INVALID, 959 }; 960 961 static struct qcom_icc_node slv_gpu_cfg = { 962 .name = "slv_gpu_cfg", 963 .id = QNOC_SLAVE_GRAPHICS_3D_CFG, 964 .buswidth = 8, 965 .mas_rpm_id = -1, 966 .slv_rpm_id = 11, 967 .qos.ap_owned = true, 968 .qos.qos_mode = NOC_QOS_MODE_INVALID, 969 }; 970 971 static struct qcom_icc_node slv_tlmm = { 972 .name = "slv_tlmm", 973 .id = QNOC_SLAVE_TLMM, 974 .buswidth = 4, 975 .mas_rpm_id = -1, 976 .slv_rpm_id = 51, 977 }; 978 979 static struct qcom_icc_node slv_blsp_1 = { 980 .name = "slv_blsp_1", 981 .id = QNOC_SLAVE_BLSP_1, 982 .buswidth = 4, 983 .mas_rpm_id = -1, 984 .slv_rpm_id = 39, 985 }; 986 987 static struct qcom_icc_node slv_blsp_2 = { 988 .name = "slv_blsp_2", 989 .id = QNOC_SLAVE_BLSP_2, 990 .buswidth = 4, 991 .mas_rpm_id = -1, 992 .slv_rpm_id = 37, 993 }; 994 995 static struct qcom_icc_node slv_pmic_arb = { 996 .name = "slv_pmic_arb", 997 .id = QNOC_SLAVE_PMIC_ARB, 998 .buswidth = 4, 999 .mas_rpm_id = -1, 1000 .slv_rpm_id = 59, 1001 }; 1002 1003 static struct qcom_icc_node slv_sdcc_1 = { 1004 .name = "slv_sdcc_1", 1005 .id = QNOC_SLAVE_SDCC_1, 1006 .buswidth = 4, 1007 .mas_rpm_id = -1, 1008 .slv_rpm_id = 31, 1009 }; 1010 1011 static struct qcom_icc_node slv_crypto_0_cfg = { 1012 .name = "slv_crypto_0_cfg", 1013 .id = QNOC_SLAVE_CRYPTO_0_CFG, 1014 .buswidth = 4, 1015 .mas_rpm_id = -1, 1016 .slv_rpm_id = 52, 1017 }; 1018 1019 static struct qcom_icc_node slv_usb_hs = { 1020 .name = "slv_usb_hs", 1021 .id = QNOC_SLAVE_USB_HS, 1022 .buswidth = 4, 1023 .mas_rpm_id = -1, 1024 .slv_rpm_id = 40, 1025 }; 1026 1027 static struct qcom_icc_node slv_tcu = { 1028 .name = "slv_tcu", 1029 .id = QNOC_SLAVE_TCU, 1030 .buswidth = 8, 1031 .mas_rpm_id = -1, 1032 .slv_rpm_id = 133, 1033 .qos.ap_owned = true, 1034 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1035 }; 1036 1037 static const u16 slv_pcnoc_snoc_links[] = { 1038 QNOC_PNOC_SNOC_MAS 1039 }; 1040 1041 static struct qcom_icc_node slv_pcnoc_snoc = { 1042 .name = "slv_pcnoc_snoc", 1043 .id = QNOC_PNOC_SNOC_SLV, 1044 .buswidth = 8, 1045 .mas_rpm_id = -1, 1046 .slv_rpm_id = 45, 1047 .num_links = ARRAY_SIZE(slv_pcnoc_snoc_links), 1048 .links = slv_pcnoc_snoc_links, 1049 }; 1050 1051 static struct qcom_icc_node slv_kpss_ahb = { 1052 .name = "slv_kpss_ahb", 1053 .id = QNOC_SLAVE_APPSS, 1054 .buswidth = 4, 1055 .mas_rpm_id = -1, 1056 .slv_rpm_id = 20, 1057 .qos.ap_owned = true, 1058 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1059 }; 1060 1061 static struct qcom_icc_node slv_wcss = { 1062 .name = "slv_wcss", 1063 .id = QNOC_SLAVE_WCSS, 1064 .buswidth = 4, 1065 .mas_rpm_id = -1, 1066 .slv_rpm_id = 23, 1067 .qos.ap_owned = true, 1068 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1069 }; 1070 1071 static const u16 slv_snoc_bimc_0_links[] = { 1072 QNOC_SNOC_BIMC_0_MAS 1073 }; 1074 1075 static struct qcom_icc_node slv_snoc_bimc_0 = { 1076 .name = "slv_snoc_bimc_0", 1077 .id = QNOC_SNOC_BIMC_0_SLV, 1078 .buswidth = 16, 1079 .mas_rpm_id = -1, 1080 .slv_rpm_id = 24, 1081 .qos.ap_owned = true, 1082 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1083 .num_links = ARRAY_SIZE(slv_snoc_bimc_0_links), 1084 .links = slv_snoc_bimc_0_links, 1085 }; 1086 1087 static const u16 slv_snoc_bimc_1_links[] = { 1088 QNOC_SNOC_BIMC_1_MAS 1089 }; 1090 1091 static struct qcom_icc_node slv_snoc_bimc_1 = { 1092 .name = "slv_snoc_bimc_1", 1093 .id = QNOC_SNOC_BIMC_1_SLV, 1094 .buswidth = 8, 1095 .mas_rpm_id = -1, 1096 .slv_rpm_id = 104, 1097 .num_links = ARRAY_SIZE(slv_snoc_bimc_1_links), 1098 .links = slv_snoc_bimc_1_links, 1099 }; 1100 1101 static const u16 slv_snoc_bimc_2_links[] = { 1102 QNOC_SNOC_BIMC_2_MAS 1103 }; 1104 1105 static struct qcom_icc_node slv_snoc_bimc_2 = { 1106 .name = "slv_snoc_bimc_2", 1107 .id = QNOC_SNOC_BIMC_2_SLV, 1108 .buswidth = 16, 1109 .mas_rpm_id = -1, 1110 .slv_rpm_id = 137, 1111 .qos.ap_owned = true, 1112 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1113 .num_links = ARRAY_SIZE(slv_snoc_bimc_2_links), 1114 .links = slv_snoc_bimc_2_links, 1115 }; 1116 1117 static struct qcom_icc_node slv_imem = { 1118 .name = "slv_imem", 1119 .id = QNOC_SLAVE_OCIMEM, 1120 .buswidth = 8, 1121 .mas_rpm_id = -1, 1122 .slv_rpm_id = 26, 1123 }; 1124 1125 static const u16 slv_snoc_pcnoc_links[] = { 1126 QNOC_SNOC_PNOC_MAS 1127 }; 1128 1129 static struct qcom_icc_node slv_snoc_pcnoc = { 1130 .name = "slv_snoc_pcnoc", 1131 .id = QNOC_SNOC_PNOC_SLV, 1132 .buswidth = 8, 1133 .mas_rpm_id = -1, 1134 .slv_rpm_id = 28, 1135 .num_links = ARRAY_SIZE(slv_snoc_pcnoc_links), 1136 .links = slv_snoc_pcnoc_links, 1137 }; 1138 1139 static struct qcom_icc_node slv_qdss_stm = { 1140 .name = "slv_qdss_stm", 1141 .id = QNOC_SLAVE_QDSS_STM, 1142 .buswidth = 4, 1143 .mas_rpm_id = -1, 1144 .slv_rpm_id = 30, 1145 }; 1146 1147 static struct qcom_icc_node slv_cats_0 = { 1148 .name = "slv_cats_0", 1149 .id = QNOC_SLAVE_CATS_128, 1150 .buswidth = 16, 1151 .mas_rpm_id = -1, 1152 .slv_rpm_id = 106, 1153 .qos.ap_owned = true, 1154 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1155 }; 1156 1157 static struct qcom_icc_node slv_cats_1 = { 1158 .name = "slv_cats_1", 1159 .id = QNOC_SLAVE_OCMEM_64, 1160 .buswidth = 8, 1161 .mas_rpm_id = -1, 1162 .slv_rpm_id = 107, 1163 .qos.ap_owned = true, 1164 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1165 }; 1166 1167 static struct qcom_icc_node slv_lpass = { 1168 .name = "slv_lpass", 1169 .id = QNOC_SLAVE_LPASS, 1170 .buswidth = 8, 1171 .mas_rpm_id = -1, 1172 .slv_rpm_id = 21, 1173 .qos.ap_owned = true, 1174 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1175 }; 1176 1177 static struct qcom_icc_node * const msm8937_bimc_nodes[] = { 1178 [MAS_APPS_PROC] = &mas_apps_proc, 1179 [MAS_OXILI] = &mas_oxili, 1180 [MAS_SNOC_BIMC_0] = &mas_snoc_bimc_0, 1181 [MAS_SNOC_BIMC_2] = &mas_snoc_bimc_2, 1182 [MAS_SNOC_BIMC_1] = &mas_snoc_bimc_1, 1183 [MAS_TCU_0] = &mas_tcu_0, 1184 [SLV_EBI] = &slv_ebi, 1185 [SLV_BIMC_SNOC] = &slv_bimc_snoc, 1186 }; 1187 1188 static const struct regmap_config msm8937_bimc_regmap_config = { 1189 .reg_bits = 32, 1190 .reg_stride = 4, 1191 .val_bits = 32, 1192 .max_register = 0x5A000, 1193 .fast_io = true, 1194 }; 1195 1196 static const struct qcom_icc_desc msm8937_bimc = { 1197 .type = QCOM_ICC_BIMC, 1198 .nodes = msm8937_bimc_nodes, 1199 .num_nodes = ARRAY_SIZE(msm8937_bimc_nodes), 1200 .bus_clk_desc = &bimc_clk, 1201 .regmap_cfg = &msm8937_bimc_regmap_config, 1202 .qos_offset = 0x8000, 1203 .ab_coeff = 154, 1204 }; 1205 1206 static struct qcom_icc_node * const msm8937_pcnoc_nodes[] = { 1207 [MAS_SPDM] = &mas_spdm, 1208 [MAS_BLSP_1] = &mas_blsp_1, 1209 [MAS_BLSP_2] = &mas_blsp_2, 1210 [MAS_USB_HS1] = &mas_usb_hs1, 1211 [MAS_XI_USB_HS1] = &mas_xi_usb_hs1, 1212 [MAS_CRYPTO] = &mas_crypto, 1213 [MAS_SDCC_1] = &mas_sdcc_1, 1214 [MAS_SDCC_2] = &mas_sdcc_2, 1215 [MAS_SNOC_PCNOC] = &mas_snoc_pcnoc, 1216 [PCNOC_M_0] = &pcnoc_m_0, 1217 [PCNOC_M_1] = &pcnoc_m_1, 1218 [PCNOC_INT_0] = &pcnoc_int_0, 1219 [PCNOC_INT_1] = &pcnoc_int_1, 1220 [PCNOC_INT_2] = &pcnoc_int_2, 1221 [PCNOC_INT_3] = &pcnoc_int_3, 1222 [PCNOC_S_0] = &pcnoc_s_0, 1223 [PCNOC_S_1] = &pcnoc_s_1, 1224 [PCNOC_S_2] = &pcnoc_s_2, 1225 [PCNOC_S_3] = &pcnoc_s_3, 1226 [PCNOC_S_4] = &pcnoc_s_4, 1227 [PCNOC_S_6] = &pcnoc_s_6, 1228 [PCNOC_S_7] = &pcnoc_s_7, 1229 [PCNOC_S_8] = &pcnoc_s_8, 1230 [SLV_SDCC_2] = &slv_sdcc_2, 1231 [SLV_SPDM] = &slv_spdm, 1232 [SLV_PDM] = &slv_pdm, 1233 [SLV_PRNG] = &slv_prng, 1234 [SLV_TCSR] = &slv_tcsr, 1235 [SLV_SNOC_CFG] = &slv_snoc_cfg, 1236 [SLV_MESSAGE_RAM] = &slv_message_ram, 1237 [SLV_CAMERA_SS_CFG] = &slv_camera_ss_cfg, 1238 [SLV_DISP_SS_CFG] = &slv_disp_ss_cfg, 1239 [SLV_VENUS_CFG] = &slv_venus_cfg, 1240 [SLV_GPU_CFG] = &slv_gpu_cfg, 1241 [SLV_TLMM] = &slv_tlmm, 1242 [SLV_BLSP_1] = &slv_blsp_1, 1243 [SLV_BLSP_2] = &slv_blsp_2, 1244 [SLV_PMIC_ARB] = &slv_pmic_arb, 1245 [SLV_SDCC_1] = &slv_sdcc_1, 1246 [SLV_CRYPTO_0_CFG] = &slv_crypto_0_cfg, 1247 [SLV_USB_HS] = &slv_usb_hs, 1248 [SLV_TCU] = &slv_tcu, 1249 [SLV_PCNOC_SNOC] = &slv_pcnoc_snoc, 1250 }; 1251 1252 static const struct regmap_config msm8937_pcnoc_regmap_config = { 1253 .reg_bits = 32, 1254 .reg_stride = 4, 1255 .val_bits = 32, 1256 .max_register = 0x13080, 1257 .fast_io = true, 1258 }; 1259 1260 static const struct qcom_icc_desc msm8937_pcnoc = { 1261 .type = QCOM_ICC_NOC, 1262 .nodes = msm8937_pcnoc_nodes, 1263 .num_nodes = ARRAY_SIZE(msm8937_pcnoc_nodes), 1264 .bus_clk_desc = &bus_0_clk, 1265 .qos_offset = 0x7000, 1266 .keep_alive = true, 1267 .regmap_cfg = &msm8937_pcnoc_regmap_config, 1268 }; 1269 1270 static struct qcom_icc_node * const msm8937_snoc_nodes[] = { 1271 [MAS_QDSS_BAM] = &mas_qdss_bam, 1272 [MAS_BIMC_SNOC] = &mas_bimc_snoc, 1273 [MAS_PCNOC_SNOC] = &mas_pcnoc_snoc, 1274 [MAS_QDSS_ETR] = &mas_qdss_etr, 1275 [QDSS_INT] = &qdss_int, 1276 [SNOC_INT_0] = &snoc_int_0, 1277 [SNOC_INT_1] = &snoc_int_1, 1278 [SNOC_INT_2] = &snoc_int_2, 1279 [SLV_KPSS_AHB] = &slv_kpss_ahb, 1280 [SLV_WCSS] = &slv_wcss, 1281 [SLV_SNOC_BIMC_1] = &slv_snoc_bimc_1, 1282 [SLV_IMEM] = &slv_imem, 1283 [SLV_SNOC_PCNOC] = &slv_snoc_pcnoc, 1284 [SLV_QDSS_STM] = &slv_qdss_stm, 1285 [SLV_CATS_1] = &slv_cats_1, 1286 [SLV_LPASS] = &slv_lpass, 1287 }; 1288 1289 static const struct regmap_config msm8937_snoc_regmap_config = { 1290 .reg_bits = 32, 1291 .reg_stride = 4, 1292 .val_bits = 32, 1293 .max_register = 0x16080, 1294 .fast_io = true, 1295 }; 1296 1297 static const struct qcom_icc_desc msm8937_snoc = { 1298 .type = QCOM_ICC_NOC, 1299 .nodes = msm8937_snoc_nodes, 1300 .num_nodes = ARRAY_SIZE(msm8937_snoc_nodes), 1301 .bus_clk_desc = &bus_1_clk, 1302 .regmap_cfg = &msm8937_snoc_regmap_config, 1303 .qos_offset = 0x7000, 1304 }; 1305 1306 static struct qcom_icc_node * const msm8937_snoc_mm_nodes[] = { 1307 [MAS_JPEG] = &mas_jpeg, 1308 [MAS_MDP] = &mas_mdp, 1309 [MAS_VENUS] = &mas_venus, 1310 [MAS_VFE0] = &mas_vfe0, 1311 [MAS_VFE1] = &mas_vfe1, 1312 [MAS_CPP] = &mas_cpp, 1313 [SLV_SNOC_BIMC_0] = &slv_snoc_bimc_0, 1314 [SLV_SNOC_BIMC_2] = &slv_snoc_bimc_2, 1315 [SLV_CATS_0] = &slv_cats_0, 1316 }; 1317 1318 static const struct qcom_icc_desc msm8937_snoc_mm = { 1319 .type = QCOM_ICC_NOC, 1320 .nodes = msm8937_snoc_mm_nodes, 1321 .num_nodes = ARRAY_SIZE(msm8937_snoc_mm_nodes), 1322 .bus_clk_desc = &bus_2_clk, 1323 .regmap_cfg = &msm8937_snoc_regmap_config, 1324 .qos_offset = 0x7000, 1325 .ab_coeff = 154, 1326 }; 1327 1328 static const struct of_device_id msm8937_noc_of_match[] = { 1329 { .compatible = "qcom,msm8937-bimc", .data = &msm8937_bimc }, 1330 { .compatible = "qcom,msm8937-pcnoc", .data = &msm8937_pcnoc }, 1331 { .compatible = "qcom,msm8937-snoc", .data = &msm8937_snoc }, 1332 { .compatible = "qcom,msm8937-snoc-mm", .data = &msm8937_snoc_mm }, 1333 { } 1334 }; 1335 MODULE_DEVICE_TABLE(of, msm8937_noc_of_match); 1336 1337 static struct platform_driver msm8937_noc_driver = { 1338 .probe = qnoc_probe, 1339 .remove = qnoc_remove, 1340 .driver = { 1341 .name = "qnoc-msm8937", 1342 .of_match_table = msm8937_noc_of_match, 1343 .sync_state = icc_sync_state, 1344 }, 1345 }; 1346 module_platform_driver(msm8937_noc_driver); 1347 1348 MODULE_DESCRIPTION("Qualcomm MSM8937 NoC driver"); 1349 MODULE_LICENSE("GPL"); 1350