1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2018-2020 Linaro Ltd 4 * Author: Georgi Djakov <georgi.djakov@linaro.org> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/device.h> 9 #include <linux/interconnect-provider.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 #include <linux/of_device.h> 15 16 #include <dt-bindings/interconnect/qcom,msm8916.h> 17 18 #include "smd-rpm.h" 19 #include "icc-rpm.h" 20 21 enum { 22 MSM8916_BIMC_SNOC_MAS = 1, 23 MSM8916_BIMC_SNOC_SLV, 24 MSM8916_MASTER_AMPSS_M0, 25 MSM8916_MASTER_LPASS, 26 MSM8916_MASTER_BLSP_1, 27 MSM8916_MASTER_DEHR, 28 MSM8916_MASTER_GRAPHICS_3D, 29 MSM8916_MASTER_JPEG, 30 MSM8916_MASTER_MDP_PORT0, 31 MSM8916_MASTER_CRYPTO_CORE0, 32 MSM8916_MASTER_SDCC_1, 33 MSM8916_MASTER_SDCC_2, 34 MSM8916_MASTER_QDSS_BAM, 35 MSM8916_MASTER_QDSS_ETR, 36 MSM8916_MASTER_SNOC_CFG, 37 MSM8916_MASTER_SPDM, 38 MSM8916_MASTER_TCU0, 39 MSM8916_MASTER_TCU1, 40 MSM8916_MASTER_USB_HS, 41 MSM8916_MASTER_VFE, 42 MSM8916_MASTER_VIDEO_P0, 43 MSM8916_SNOC_MM_INT_0, 44 MSM8916_SNOC_MM_INT_1, 45 MSM8916_SNOC_MM_INT_2, 46 MSM8916_SNOC_MM_INT_BIMC, 47 MSM8916_PNOC_INT_0, 48 MSM8916_PNOC_INT_1, 49 MSM8916_PNOC_MAS_0, 50 MSM8916_PNOC_MAS_1, 51 MSM8916_PNOC_SLV_0, 52 MSM8916_PNOC_SLV_1, 53 MSM8916_PNOC_SLV_2, 54 MSM8916_PNOC_SLV_3, 55 MSM8916_PNOC_SLV_4, 56 MSM8916_PNOC_SLV_8, 57 MSM8916_PNOC_SLV_9, 58 MSM8916_PNOC_SNOC_MAS, 59 MSM8916_PNOC_SNOC_SLV, 60 MSM8916_SNOC_QDSS_INT, 61 MSM8916_SLAVE_AMPSS_L2, 62 MSM8916_SLAVE_APSS, 63 MSM8916_SLAVE_LPASS, 64 MSM8916_SLAVE_BIMC_CFG, 65 MSM8916_SLAVE_BLSP_1, 66 MSM8916_SLAVE_BOOT_ROM, 67 MSM8916_SLAVE_CAMERA_CFG, 68 MSM8916_SLAVE_CATS_128, 69 MSM8916_SLAVE_OCMEM_64, 70 MSM8916_SLAVE_CLK_CTL, 71 MSM8916_SLAVE_CRYPTO_0_CFG, 72 MSM8916_SLAVE_DEHR_CFG, 73 MSM8916_SLAVE_DISPLAY_CFG, 74 MSM8916_SLAVE_EBI_CH0, 75 MSM8916_SLAVE_GRAPHICS_3D_CFG, 76 MSM8916_SLAVE_IMEM_CFG, 77 MSM8916_SLAVE_IMEM, 78 MSM8916_SLAVE_MPM, 79 MSM8916_SLAVE_MSG_RAM, 80 MSM8916_SLAVE_MSS, 81 MSM8916_SLAVE_PDM, 82 MSM8916_SLAVE_PMIC_ARB, 83 MSM8916_SLAVE_PNOC_CFG, 84 MSM8916_SLAVE_PRNG, 85 MSM8916_SLAVE_QDSS_CFG, 86 MSM8916_SLAVE_QDSS_STM, 87 MSM8916_SLAVE_RBCPR_CFG, 88 MSM8916_SLAVE_SDCC_1, 89 MSM8916_SLAVE_SDCC_2, 90 MSM8916_SLAVE_SECURITY, 91 MSM8916_SLAVE_SNOC_CFG, 92 MSM8916_SLAVE_SPDM, 93 MSM8916_SLAVE_SRVC_SNOC, 94 MSM8916_SLAVE_TCSR, 95 MSM8916_SLAVE_TLMM, 96 MSM8916_SLAVE_USB_HS, 97 MSM8916_SLAVE_VENUS_CFG, 98 MSM8916_SNOC_BIMC_0_MAS, 99 MSM8916_SNOC_BIMC_0_SLV, 100 MSM8916_SNOC_BIMC_1_MAS, 101 MSM8916_SNOC_BIMC_1_SLV, 102 MSM8916_SNOC_INT_0, 103 MSM8916_SNOC_INT_1, 104 MSM8916_SNOC_INT_BIMC, 105 MSM8916_SNOC_PNOC_MAS, 106 MSM8916_SNOC_PNOC_SLV, 107 }; 108 109 static const u16 bimc_snoc_mas_links[] = { 110 MSM8916_BIMC_SNOC_SLV 111 }; 112 113 static struct qcom_icc_node bimc_snoc_mas = { 114 .name = "bimc_snoc_mas", 115 .id = MSM8916_BIMC_SNOC_MAS, 116 .buswidth = 8, 117 .mas_rpm_id = -1, 118 .slv_rpm_id = -1, 119 .qos.ap_owned = true, 120 .qos.qos_mode = NOC_QOS_MODE_INVALID, 121 .num_links = ARRAY_SIZE(bimc_snoc_mas_links), 122 .links = bimc_snoc_mas_links, 123 }; 124 125 static const u16 bimc_snoc_slv_links[] = { 126 MSM8916_SNOC_INT_0, 127 MSM8916_SNOC_INT_1 128 }; 129 130 static struct qcom_icc_node bimc_snoc_slv = { 131 .name = "bimc_snoc_slv", 132 .id = MSM8916_BIMC_SNOC_SLV, 133 .buswidth = 8, 134 .mas_rpm_id = -1, 135 .slv_rpm_id = -1, 136 .qos.ap_owned = true, 137 .qos.qos_mode = NOC_QOS_MODE_INVALID, 138 .num_links = ARRAY_SIZE(bimc_snoc_slv_links), 139 .links = bimc_snoc_slv_links, 140 }; 141 142 static const u16 mas_apss_links[] = { 143 MSM8916_SLAVE_EBI_CH0, 144 MSM8916_BIMC_SNOC_MAS, 145 MSM8916_SLAVE_AMPSS_L2 146 }; 147 148 static struct qcom_icc_node mas_apss = { 149 .name = "mas_apss", 150 .id = MSM8916_MASTER_AMPSS_M0, 151 .buswidth = 8, 152 .mas_rpm_id = -1, 153 .slv_rpm_id = -1, 154 .qos.ap_owned = true, 155 .qos.qos_mode = NOC_QOS_MODE_FIXED, 156 .qos.areq_prio = 0, 157 .qos.prio_level = 0, 158 .qos.qos_port = 0, 159 .num_links = ARRAY_SIZE(mas_apss_links), 160 .links = mas_apss_links, 161 }; 162 163 static const u16 mas_audio_links[] = { 164 MSM8916_PNOC_MAS_0 165 }; 166 167 static struct qcom_icc_node mas_audio = { 168 .name = "mas_audio", 169 .id = MSM8916_MASTER_LPASS, 170 .buswidth = 4, 171 .mas_rpm_id = -1, 172 .slv_rpm_id = -1, 173 .num_links = ARRAY_SIZE(mas_audio_links), 174 .links = mas_audio_links, 175 }; 176 177 static const u16 mas_blsp_1_links[] = { 178 MSM8916_PNOC_MAS_1 179 }; 180 181 static struct qcom_icc_node mas_blsp_1 = { 182 .name = "mas_blsp_1", 183 .id = MSM8916_MASTER_BLSP_1, 184 .buswidth = 4, 185 .mas_rpm_id = -1, 186 .slv_rpm_id = -1, 187 .num_links = ARRAY_SIZE(mas_blsp_1_links), 188 .links = mas_blsp_1_links, 189 }; 190 191 static const u16 mas_dehr_links[] = { 192 MSM8916_PNOC_MAS_0 193 }; 194 195 static struct qcom_icc_node mas_dehr = { 196 .name = "mas_dehr", 197 .id = MSM8916_MASTER_DEHR, 198 .buswidth = 4, 199 .mas_rpm_id = -1, 200 .slv_rpm_id = -1, 201 .num_links = ARRAY_SIZE(mas_dehr_links), 202 .links = mas_dehr_links, 203 }; 204 205 static const u16 mas_gfx_links[] = { 206 MSM8916_SLAVE_EBI_CH0, 207 MSM8916_BIMC_SNOC_MAS, 208 MSM8916_SLAVE_AMPSS_L2 209 }; 210 211 static struct qcom_icc_node mas_gfx = { 212 .name = "mas_gfx", 213 .id = MSM8916_MASTER_GRAPHICS_3D, 214 .buswidth = 8, 215 .mas_rpm_id = -1, 216 .slv_rpm_id = -1, 217 .qos.ap_owned = true, 218 .qos.qos_mode = NOC_QOS_MODE_FIXED, 219 .qos.areq_prio = 0, 220 .qos.prio_level = 0, 221 .qos.qos_port = 2, 222 .num_links = ARRAY_SIZE(mas_gfx_links), 223 .links = mas_gfx_links, 224 }; 225 226 static const u16 mas_jpeg_links[] = { 227 MSM8916_SNOC_MM_INT_0, 228 MSM8916_SNOC_MM_INT_2 229 }; 230 231 static struct qcom_icc_node mas_jpeg = { 232 .name = "mas_jpeg", 233 .id = MSM8916_MASTER_JPEG, 234 .buswidth = 16, 235 .mas_rpm_id = -1, 236 .slv_rpm_id = -1, 237 .qos.ap_owned = true, 238 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 239 .qos.areq_prio = 0, 240 .qos.prio_level = 0, 241 .qos.qos_port = 6, 242 .num_links = ARRAY_SIZE(mas_jpeg_links), 243 .links = mas_jpeg_links, 244 }; 245 246 static const u16 mas_mdp_links[] = { 247 MSM8916_SNOC_MM_INT_0, 248 MSM8916_SNOC_MM_INT_2 249 }; 250 251 static struct qcom_icc_node mas_mdp = { 252 .name = "mas_mdp", 253 .id = MSM8916_MASTER_MDP_PORT0, 254 .buswidth = 16, 255 .mas_rpm_id = -1, 256 .slv_rpm_id = -1, 257 .qos.ap_owned = true, 258 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 259 .qos.areq_prio = 0, 260 .qos.prio_level = 0, 261 .qos.qos_port = 7, 262 .num_links = ARRAY_SIZE(mas_mdp_links), 263 .links = mas_mdp_links, 264 }; 265 266 static const u16 mas_pcnoc_crypto_0_links[] = { 267 MSM8916_PNOC_INT_1 268 }; 269 270 static struct qcom_icc_node mas_pcnoc_crypto_0 = { 271 .name = "mas_pcnoc_crypto_0", 272 .id = MSM8916_MASTER_CRYPTO_CORE0, 273 .buswidth = 8, 274 .mas_rpm_id = -1, 275 .slv_rpm_id = -1, 276 .num_links = ARRAY_SIZE(mas_pcnoc_crypto_0_links), 277 .links = mas_pcnoc_crypto_0_links, 278 }; 279 280 static const u16 mas_pcnoc_sdcc_1_links[] = { 281 MSM8916_PNOC_INT_1 282 }; 283 284 static struct qcom_icc_node mas_pcnoc_sdcc_1 = { 285 .name = "mas_pcnoc_sdcc_1", 286 .id = MSM8916_MASTER_SDCC_1, 287 .buswidth = 8, 288 .mas_rpm_id = -1, 289 .slv_rpm_id = -1, 290 .num_links = ARRAY_SIZE(mas_pcnoc_sdcc_1_links), 291 .links = mas_pcnoc_sdcc_1_links, 292 }; 293 294 static const u16 mas_pcnoc_sdcc_2_links[] = { 295 MSM8916_PNOC_INT_1 296 }; 297 298 static struct qcom_icc_node mas_pcnoc_sdcc_2 = { 299 .name = "mas_pcnoc_sdcc_2", 300 .id = MSM8916_MASTER_SDCC_2, 301 .buswidth = 8, 302 .mas_rpm_id = -1, 303 .slv_rpm_id = -1, 304 .num_links = ARRAY_SIZE(mas_pcnoc_sdcc_2_links), 305 .links = mas_pcnoc_sdcc_2_links, 306 }; 307 308 static const u16 mas_qdss_bam_links[] = { 309 MSM8916_SNOC_QDSS_INT 310 }; 311 312 static struct qcom_icc_node mas_qdss_bam = { 313 .name = "mas_qdss_bam", 314 .id = MSM8916_MASTER_QDSS_BAM, 315 .buswidth = 8, 316 .mas_rpm_id = -1, 317 .slv_rpm_id = -1, 318 .qos.ap_owned = true, 319 .qos.qos_mode = NOC_QOS_MODE_FIXED, 320 .qos.areq_prio = 1, 321 .qos.prio_level = 1, 322 .qos.qos_port = 11, 323 .num_links = ARRAY_SIZE(mas_qdss_bam_links), 324 .links = mas_qdss_bam_links, 325 }; 326 327 static const u16 mas_qdss_etr_links[] = { 328 MSM8916_SNOC_QDSS_INT 329 }; 330 331 static struct qcom_icc_node mas_qdss_etr = { 332 .name = "mas_qdss_etr", 333 .id = MSM8916_MASTER_QDSS_ETR, 334 .buswidth = 8, 335 .mas_rpm_id = -1, 336 .slv_rpm_id = -1, 337 .qos.ap_owned = true, 338 .qos.qos_mode = NOC_QOS_MODE_FIXED, 339 .qos.areq_prio = 1, 340 .qos.prio_level = 1, 341 .qos.qos_port = 10, 342 .num_links = ARRAY_SIZE(mas_qdss_etr_links), 343 .links = mas_qdss_etr_links, 344 }; 345 346 static const u16 mas_snoc_cfg_links[] = { 347 MSM8916_SNOC_QDSS_INT 348 }; 349 350 static struct qcom_icc_node mas_snoc_cfg = { 351 .name = "mas_snoc_cfg", 352 .id = MSM8916_MASTER_SNOC_CFG, 353 .buswidth = 4, 354 .mas_rpm_id = -1, 355 .slv_rpm_id = -1, 356 .num_links = ARRAY_SIZE(mas_snoc_cfg_links), 357 .links = mas_snoc_cfg_links, 358 }; 359 360 static const u16 mas_spdm_links[] = { 361 MSM8916_PNOC_MAS_0 362 }; 363 364 static struct qcom_icc_node mas_spdm = { 365 .name = "mas_spdm", 366 .id = MSM8916_MASTER_SPDM, 367 .buswidth = 4, 368 .mas_rpm_id = -1, 369 .slv_rpm_id = -1, 370 .num_links = ARRAY_SIZE(mas_spdm_links), 371 .links = mas_spdm_links, 372 }; 373 374 static const u16 mas_tcu0_links[] = { 375 MSM8916_SLAVE_EBI_CH0, 376 MSM8916_BIMC_SNOC_MAS, 377 MSM8916_SLAVE_AMPSS_L2 378 }; 379 380 static struct qcom_icc_node mas_tcu0 = { 381 .name = "mas_tcu0", 382 .id = MSM8916_MASTER_TCU0, 383 .buswidth = 8, 384 .mas_rpm_id = -1, 385 .slv_rpm_id = -1, 386 .qos.ap_owned = true, 387 .qos.qos_mode = NOC_QOS_MODE_FIXED, 388 .qos.areq_prio = 2, 389 .qos.prio_level = 2, 390 .qos.qos_port = 5, 391 .num_links = ARRAY_SIZE(mas_tcu0_links), 392 .links = mas_tcu0_links, 393 }; 394 395 static const u16 mas_tcu1_links[] = { 396 MSM8916_SLAVE_EBI_CH0, 397 MSM8916_BIMC_SNOC_MAS, 398 MSM8916_SLAVE_AMPSS_L2 399 }; 400 401 static struct qcom_icc_node mas_tcu1 = { 402 .name = "mas_tcu1", 403 .id = MSM8916_MASTER_TCU1, 404 .buswidth = 8, 405 .mas_rpm_id = -1, 406 .slv_rpm_id = -1, 407 .qos.ap_owned = true, 408 .qos.qos_mode = NOC_QOS_MODE_FIXED, 409 .qos.areq_prio = 2, 410 .qos.prio_level = 2, 411 .qos.qos_port = 6, 412 .num_links = ARRAY_SIZE(mas_tcu1_links), 413 .links = mas_tcu1_links, 414 }; 415 416 static const u16 mas_usb_hs_links[] = { 417 MSM8916_PNOC_MAS_1 418 }; 419 420 static struct qcom_icc_node mas_usb_hs = { 421 .name = "mas_usb_hs", 422 .id = MSM8916_MASTER_USB_HS, 423 .buswidth = 4, 424 .mas_rpm_id = -1, 425 .slv_rpm_id = -1, 426 .num_links = ARRAY_SIZE(mas_usb_hs_links), 427 .links = mas_usb_hs_links, 428 }; 429 430 static const u16 mas_vfe_links[] = { 431 MSM8916_SNOC_MM_INT_1, 432 MSM8916_SNOC_MM_INT_2 433 }; 434 435 static struct qcom_icc_node mas_vfe = { 436 .name = "mas_vfe", 437 .id = MSM8916_MASTER_VFE, 438 .buswidth = 16, 439 .mas_rpm_id = -1, 440 .slv_rpm_id = -1, 441 .qos.ap_owned = true, 442 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 443 .qos.areq_prio = 0, 444 .qos.prio_level = 0, 445 .qos.qos_port = 9, 446 .num_links = ARRAY_SIZE(mas_vfe_links), 447 .links = mas_vfe_links, 448 }; 449 450 static const u16 mas_video_links[] = { 451 MSM8916_SNOC_MM_INT_0, 452 MSM8916_SNOC_MM_INT_2 453 }; 454 455 static struct qcom_icc_node mas_video = { 456 .name = "mas_video", 457 .id = MSM8916_MASTER_VIDEO_P0, 458 .buswidth = 16, 459 .mas_rpm_id = -1, 460 .slv_rpm_id = -1, 461 .qos.ap_owned = true, 462 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 463 .qos.areq_prio = 0, 464 .qos.prio_level = 0, 465 .qos.qos_port = 8, 466 .num_links = ARRAY_SIZE(mas_video_links), 467 .links = mas_video_links, 468 }; 469 470 static const u16 mm_int_0_links[] = { 471 MSM8916_SNOC_MM_INT_BIMC 472 }; 473 474 static struct qcom_icc_node mm_int_0 = { 475 .name = "mm_int_0", 476 .id = MSM8916_SNOC_MM_INT_0, 477 .buswidth = 16, 478 .mas_rpm_id = -1, 479 .slv_rpm_id = -1, 480 .qos.ap_owned = true, 481 .qos.qos_mode = NOC_QOS_MODE_INVALID, 482 .num_links = ARRAY_SIZE(mm_int_0_links), 483 .links = mm_int_0_links, 484 }; 485 486 static const u16 mm_int_1_links[] = { 487 MSM8916_SNOC_MM_INT_BIMC 488 }; 489 490 static struct qcom_icc_node mm_int_1 = { 491 .name = "mm_int_1", 492 .id = MSM8916_SNOC_MM_INT_1, 493 .buswidth = 16, 494 .mas_rpm_id = -1, 495 .slv_rpm_id = -1, 496 .qos.ap_owned = true, 497 .qos.qos_mode = NOC_QOS_MODE_INVALID, 498 .num_links = ARRAY_SIZE(mm_int_1_links), 499 .links = mm_int_1_links, 500 }; 501 502 static const u16 mm_int_2_links[] = { 503 MSM8916_SNOC_INT_0 504 }; 505 506 static struct qcom_icc_node mm_int_2 = { 507 .name = "mm_int_2", 508 .id = MSM8916_SNOC_MM_INT_2, 509 .buswidth = 16, 510 .mas_rpm_id = -1, 511 .slv_rpm_id = -1, 512 .qos.ap_owned = true, 513 .qos.qos_mode = NOC_QOS_MODE_INVALID, 514 .num_links = ARRAY_SIZE(mm_int_2_links), 515 .links = mm_int_2_links, 516 }; 517 518 static const u16 mm_int_bimc_links[] = { 519 MSM8916_SNOC_BIMC_1_MAS 520 }; 521 522 static struct qcom_icc_node mm_int_bimc = { 523 .name = "mm_int_bimc", 524 .id = MSM8916_SNOC_MM_INT_BIMC, 525 .buswidth = 16, 526 .mas_rpm_id = -1, 527 .slv_rpm_id = -1, 528 .qos.ap_owned = true, 529 .qos.qos_mode = NOC_QOS_MODE_INVALID, 530 .num_links = ARRAY_SIZE(mm_int_bimc_links), 531 .links = mm_int_bimc_links, 532 }; 533 534 static const u16 pcnoc_int_0_links[] = { 535 MSM8916_PNOC_SNOC_MAS, 536 MSM8916_PNOC_SLV_0, 537 MSM8916_PNOC_SLV_1, 538 MSM8916_PNOC_SLV_2, 539 MSM8916_PNOC_SLV_3, 540 MSM8916_PNOC_SLV_4, 541 MSM8916_PNOC_SLV_8, 542 MSM8916_PNOC_SLV_9 543 }; 544 545 static struct qcom_icc_node pcnoc_int_0 = { 546 .name = "pcnoc_int_0", 547 .id = MSM8916_PNOC_INT_0, 548 .buswidth = 8, 549 .mas_rpm_id = -1, 550 .slv_rpm_id = -1, 551 .num_links = ARRAY_SIZE(pcnoc_int_0_links), 552 .links = pcnoc_int_0_links, 553 }; 554 555 static const u16 pcnoc_int_1_links[] = { 556 MSM8916_PNOC_SNOC_MAS 557 }; 558 559 static struct qcom_icc_node pcnoc_int_1 = { 560 .name = "pcnoc_int_1", 561 .id = MSM8916_PNOC_INT_1, 562 .buswidth = 8, 563 .mas_rpm_id = -1, 564 .slv_rpm_id = -1, 565 .num_links = ARRAY_SIZE(pcnoc_int_1_links), 566 .links = pcnoc_int_1_links, 567 }; 568 569 static const u16 pcnoc_m_0_links[] = { 570 MSM8916_PNOC_INT_0 571 }; 572 573 static struct qcom_icc_node pcnoc_m_0 = { 574 .name = "pcnoc_m_0", 575 .id = MSM8916_PNOC_MAS_0, 576 .buswidth = 8, 577 .mas_rpm_id = -1, 578 .slv_rpm_id = -1, 579 .num_links = ARRAY_SIZE(pcnoc_m_0_links), 580 .links = pcnoc_m_0_links, 581 }; 582 583 static const u16 pcnoc_m_1_links[] = { 584 MSM8916_PNOC_SNOC_MAS 585 }; 586 587 static struct qcom_icc_node pcnoc_m_1 = { 588 .name = "pcnoc_m_1", 589 .id = MSM8916_PNOC_MAS_1, 590 .buswidth = 8, 591 .mas_rpm_id = -1, 592 .slv_rpm_id = -1, 593 .num_links = ARRAY_SIZE(pcnoc_m_1_links), 594 .links = pcnoc_m_1_links, 595 }; 596 597 static const u16 pcnoc_s_0_links[] = { 598 MSM8916_SLAVE_CLK_CTL, 599 MSM8916_SLAVE_TLMM, 600 MSM8916_SLAVE_TCSR, 601 MSM8916_SLAVE_SECURITY, 602 MSM8916_SLAVE_MSS 603 }; 604 605 static struct qcom_icc_node pcnoc_s_0 = { 606 .name = "pcnoc_s_0", 607 .id = MSM8916_PNOC_SLV_0, 608 .buswidth = 4, 609 .mas_rpm_id = -1, 610 .slv_rpm_id = -1, 611 .num_links = ARRAY_SIZE(pcnoc_s_0_links), 612 .links = pcnoc_s_0_links, 613 }; 614 615 static const u16 pcnoc_s_1_links[] = { 616 MSM8916_SLAVE_IMEM_CFG, 617 MSM8916_SLAVE_CRYPTO_0_CFG, 618 MSM8916_SLAVE_MSG_RAM, 619 MSM8916_SLAVE_PDM, 620 MSM8916_SLAVE_PRNG 621 }; 622 623 static struct qcom_icc_node pcnoc_s_1 = { 624 .name = "pcnoc_s_1", 625 .id = MSM8916_PNOC_SLV_1, 626 .buswidth = 4, 627 .mas_rpm_id = -1, 628 .slv_rpm_id = -1, 629 .num_links = ARRAY_SIZE(pcnoc_s_1_links), 630 .links = pcnoc_s_1_links, 631 }; 632 633 static const u16 pcnoc_s_2_links[] = { 634 MSM8916_SLAVE_SPDM, 635 MSM8916_SLAVE_BOOT_ROM, 636 MSM8916_SLAVE_BIMC_CFG, 637 MSM8916_SLAVE_PNOC_CFG, 638 MSM8916_SLAVE_PMIC_ARB 639 }; 640 641 static struct qcom_icc_node pcnoc_s_2 = { 642 .name = "pcnoc_s_2", 643 .id = MSM8916_PNOC_SLV_2, 644 .buswidth = 4, 645 .mas_rpm_id = -1, 646 .slv_rpm_id = -1, 647 .num_links = ARRAY_SIZE(pcnoc_s_2_links), 648 .links = pcnoc_s_2_links, 649 }; 650 651 static const u16 pcnoc_s_3_links[] = { 652 MSM8916_SLAVE_MPM, 653 MSM8916_SLAVE_SNOC_CFG, 654 MSM8916_SLAVE_RBCPR_CFG, 655 MSM8916_SLAVE_QDSS_CFG, 656 MSM8916_SLAVE_DEHR_CFG 657 }; 658 659 static struct qcom_icc_node pcnoc_s_3 = { 660 .name = "pcnoc_s_3", 661 .id = MSM8916_PNOC_SLV_3, 662 .buswidth = 4, 663 .mas_rpm_id = -1, 664 .slv_rpm_id = -1, 665 .num_links = ARRAY_SIZE(pcnoc_s_3_links), 666 .links = pcnoc_s_3_links, 667 }; 668 669 static const u16 pcnoc_s_4_links[] = { 670 MSM8916_SLAVE_VENUS_CFG, 671 MSM8916_SLAVE_CAMERA_CFG, 672 MSM8916_SLAVE_DISPLAY_CFG 673 }; 674 675 static struct qcom_icc_node pcnoc_s_4 = { 676 .name = "pcnoc_s_4", 677 .id = MSM8916_PNOC_SLV_4, 678 .buswidth = 4, 679 .mas_rpm_id = -1, 680 .slv_rpm_id = -1, 681 .num_links = ARRAY_SIZE(pcnoc_s_4_links), 682 .links = pcnoc_s_4_links, 683 }; 684 685 static const u16 pcnoc_s_8_links[] = { 686 MSM8916_SLAVE_USB_HS, 687 MSM8916_SLAVE_SDCC_1, 688 MSM8916_SLAVE_BLSP_1 689 }; 690 691 static struct qcom_icc_node pcnoc_s_8 = { 692 .name = "pcnoc_s_8", 693 .id = MSM8916_PNOC_SLV_8, 694 .buswidth = 4, 695 .mas_rpm_id = -1, 696 .slv_rpm_id = -1, 697 .num_links = ARRAY_SIZE(pcnoc_s_8_links), 698 .links = pcnoc_s_8_links, 699 }; 700 701 static const u16 pcnoc_s_9_links[] = { 702 MSM8916_SLAVE_SDCC_2, 703 MSM8916_SLAVE_LPASS, 704 MSM8916_SLAVE_GRAPHICS_3D_CFG 705 }; 706 707 static struct qcom_icc_node pcnoc_s_9 = { 708 .name = "pcnoc_s_9", 709 .id = MSM8916_PNOC_SLV_9, 710 .buswidth = 4, 711 .mas_rpm_id = -1, 712 .slv_rpm_id = -1, 713 .num_links = ARRAY_SIZE(pcnoc_s_9_links), 714 .links = pcnoc_s_9_links, 715 }; 716 717 static const u16 pcnoc_snoc_mas_links[] = { 718 MSM8916_PNOC_SNOC_SLV 719 }; 720 721 static struct qcom_icc_node pcnoc_snoc_mas = { 722 .name = "pcnoc_snoc_mas", 723 .id = MSM8916_PNOC_SNOC_MAS, 724 .buswidth = 8, 725 .mas_rpm_id = 29, 726 .slv_rpm_id = -1, 727 .num_links = ARRAY_SIZE(pcnoc_snoc_mas_links), 728 .links = pcnoc_snoc_mas_links, 729 }; 730 731 static const u16 pcnoc_snoc_slv_links[] = { 732 MSM8916_SNOC_INT_0, 733 MSM8916_SNOC_INT_BIMC, 734 MSM8916_SNOC_INT_1 735 }; 736 737 static struct qcom_icc_node pcnoc_snoc_slv = { 738 .name = "pcnoc_snoc_slv", 739 .id = MSM8916_PNOC_SNOC_SLV, 740 .buswidth = 8, 741 .mas_rpm_id = -1, 742 .slv_rpm_id = 45, 743 .num_links = ARRAY_SIZE(pcnoc_snoc_slv_links), 744 .links = pcnoc_snoc_slv_links, 745 }; 746 747 static const u16 qdss_int_links[] = { 748 MSM8916_SNOC_INT_0, 749 MSM8916_SNOC_INT_BIMC 750 }; 751 752 static struct qcom_icc_node qdss_int = { 753 .name = "qdss_int", 754 .id = MSM8916_SNOC_QDSS_INT, 755 .buswidth = 8, 756 .mas_rpm_id = -1, 757 .slv_rpm_id = -1, 758 .qos.ap_owned = true, 759 .qos.qos_mode = NOC_QOS_MODE_INVALID, 760 .num_links = ARRAY_SIZE(qdss_int_links), 761 .links = qdss_int_links, 762 }; 763 764 static struct qcom_icc_node slv_apps_l2 = { 765 .name = "slv_apps_l2", 766 .id = MSM8916_SLAVE_AMPSS_L2, 767 .buswidth = 8, 768 .mas_rpm_id = -1, 769 .slv_rpm_id = -1, 770 }; 771 772 static struct qcom_icc_node slv_apss = { 773 .name = "slv_apss", 774 .id = MSM8916_SLAVE_APSS, 775 .buswidth = 4, 776 .mas_rpm_id = -1, 777 .slv_rpm_id = -1, 778 }; 779 780 static struct qcom_icc_node slv_audio = { 781 .name = "slv_audio", 782 .id = MSM8916_SLAVE_LPASS, 783 .buswidth = 4, 784 .mas_rpm_id = -1, 785 .slv_rpm_id = -1, 786 }; 787 788 static struct qcom_icc_node slv_bimc_cfg = { 789 .name = "slv_bimc_cfg", 790 .id = MSM8916_SLAVE_BIMC_CFG, 791 .buswidth = 4, 792 .mas_rpm_id = -1, 793 .slv_rpm_id = -1, 794 }; 795 796 static struct qcom_icc_node slv_blsp_1 = { 797 .name = "slv_blsp_1", 798 .id = MSM8916_SLAVE_BLSP_1, 799 .buswidth = 4, 800 .mas_rpm_id = -1, 801 .slv_rpm_id = -1, 802 }; 803 804 static struct qcom_icc_node slv_boot_rom = { 805 .name = "slv_boot_rom", 806 .id = MSM8916_SLAVE_BOOT_ROM, 807 .buswidth = 4, 808 .mas_rpm_id = -1, 809 .slv_rpm_id = -1, 810 }; 811 812 static struct qcom_icc_node slv_camera_cfg = { 813 .name = "slv_camera_cfg", 814 .id = MSM8916_SLAVE_CAMERA_CFG, 815 .buswidth = 4, 816 .mas_rpm_id = -1, 817 .slv_rpm_id = -1, 818 }; 819 820 static struct qcom_icc_node slv_cats_0 = { 821 .name = "slv_cats_0", 822 .id = MSM8916_SLAVE_CATS_128, 823 .buswidth = 16, 824 .mas_rpm_id = -1, 825 .slv_rpm_id = -1, 826 }; 827 828 static struct qcom_icc_node slv_cats_1 = { 829 .name = "slv_cats_1", 830 .id = MSM8916_SLAVE_OCMEM_64, 831 .buswidth = 8, 832 .mas_rpm_id = -1, 833 .slv_rpm_id = -1, 834 }; 835 836 static struct qcom_icc_node slv_clk_ctl = { 837 .name = "slv_clk_ctl", 838 .id = MSM8916_SLAVE_CLK_CTL, 839 .buswidth = 4, 840 .mas_rpm_id = -1, 841 .slv_rpm_id = -1, 842 }; 843 844 static struct qcom_icc_node slv_crypto_0_cfg = { 845 .name = "slv_crypto_0_cfg", 846 .id = MSM8916_SLAVE_CRYPTO_0_CFG, 847 .buswidth = 4, 848 .mas_rpm_id = -1, 849 .slv_rpm_id = -1, 850 }; 851 852 static struct qcom_icc_node slv_dehr_cfg = { 853 .name = "slv_dehr_cfg", 854 .id = MSM8916_SLAVE_DEHR_CFG, 855 .buswidth = 4, 856 .mas_rpm_id = -1, 857 .slv_rpm_id = -1, 858 }; 859 860 static struct qcom_icc_node slv_display_cfg = { 861 .name = "slv_display_cfg", 862 .id = MSM8916_SLAVE_DISPLAY_CFG, 863 .buswidth = 4, 864 .mas_rpm_id = -1, 865 .slv_rpm_id = -1, 866 }; 867 868 static struct qcom_icc_node slv_ebi_ch0 = { 869 .name = "slv_ebi_ch0", 870 .id = MSM8916_SLAVE_EBI_CH0, 871 .buswidth = 8, 872 .mas_rpm_id = -1, 873 .slv_rpm_id = 0, 874 }; 875 876 static struct qcom_icc_node slv_gfx_cfg = { 877 .name = "slv_gfx_cfg", 878 .id = MSM8916_SLAVE_GRAPHICS_3D_CFG, 879 .buswidth = 4, 880 .mas_rpm_id = -1, 881 .slv_rpm_id = -1, 882 }; 883 884 static struct qcom_icc_node slv_imem_cfg = { 885 .name = "slv_imem_cfg", 886 .id = MSM8916_SLAVE_IMEM_CFG, 887 .buswidth = 4, 888 .mas_rpm_id = -1, 889 .slv_rpm_id = -1, 890 }; 891 892 static struct qcom_icc_node slv_imem = { 893 .name = "slv_imem", 894 .id = MSM8916_SLAVE_IMEM, 895 .buswidth = 8, 896 .mas_rpm_id = -1, 897 .slv_rpm_id = 26, 898 }; 899 900 static struct qcom_icc_node slv_mpm = { 901 .name = "slv_mpm", 902 .id = MSM8916_SLAVE_MPM, 903 .buswidth = 4, 904 .mas_rpm_id = -1, 905 .slv_rpm_id = -1, 906 }; 907 908 static struct qcom_icc_node slv_msg_ram = { 909 .name = "slv_msg_ram", 910 .id = MSM8916_SLAVE_MSG_RAM, 911 .buswidth = 4, 912 .mas_rpm_id = -1, 913 .slv_rpm_id = -1, 914 }; 915 916 static struct qcom_icc_node slv_mss = { 917 .name = "slv_mss", 918 .id = MSM8916_SLAVE_MSS, 919 .buswidth = 4, 920 .mas_rpm_id = -1, 921 .slv_rpm_id = -1, 922 }; 923 924 static struct qcom_icc_node slv_pdm = { 925 .name = "slv_pdm", 926 .id = MSM8916_SLAVE_PDM, 927 .buswidth = 4, 928 .mas_rpm_id = -1, 929 .slv_rpm_id = -1, 930 }; 931 932 static struct qcom_icc_node slv_pmic_arb = { 933 .name = "slv_pmic_arb", 934 .id = MSM8916_SLAVE_PMIC_ARB, 935 .buswidth = 4, 936 .mas_rpm_id = -1, 937 .slv_rpm_id = -1, 938 }; 939 940 static struct qcom_icc_node slv_pcnoc_cfg = { 941 .name = "slv_pcnoc_cfg", 942 .id = MSM8916_SLAVE_PNOC_CFG, 943 .buswidth = 4, 944 .mas_rpm_id = -1, 945 .slv_rpm_id = -1, 946 }; 947 948 static struct qcom_icc_node slv_prng = { 949 .name = "slv_prng", 950 .id = MSM8916_SLAVE_PRNG, 951 .buswidth = 4, 952 .mas_rpm_id = -1, 953 .slv_rpm_id = -1, 954 }; 955 956 static struct qcom_icc_node slv_qdss_cfg = { 957 .name = "slv_qdss_cfg", 958 .id = MSM8916_SLAVE_QDSS_CFG, 959 .buswidth = 4, 960 .mas_rpm_id = -1, 961 .slv_rpm_id = -1, 962 }; 963 964 static struct qcom_icc_node slv_qdss_stm = { 965 .name = "slv_qdss_stm", 966 .id = MSM8916_SLAVE_QDSS_STM, 967 .buswidth = 4, 968 .mas_rpm_id = -1, 969 .slv_rpm_id = 30, 970 }; 971 972 static struct qcom_icc_node slv_rbcpr_cfg = { 973 .name = "slv_rbcpr_cfg", 974 .id = MSM8916_SLAVE_RBCPR_CFG, 975 .buswidth = 4, 976 .mas_rpm_id = -1, 977 .slv_rpm_id = -1, 978 }; 979 980 static struct qcom_icc_node slv_sdcc_1 = { 981 .name = "slv_sdcc_1", 982 .id = MSM8916_SLAVE_SDCC_1, 983 .buswidth = 4, 984 .mas_rpm_id = -1, 985 .slv_rpm_id = -1, 986 }; 987 988 static struct qcom_icc_node slv_sdcc_2 = { 989 .name = "slv_sdcc_2", 990 .id = MSM8916_SLAVE_SDCC_2, 991 .buswidth = 4, 992 .mas_rpm_id = -1, 993 .slv_rpm_id = -1, 994 }; 995 996 static struct qcom_icc_node slv_security = { 997 .name = "slv_security", 998 .id = MSM8916_SLAVE_SECURITY, 999 .buswidth = 4, 1000 .mas_rpm_id = -1, 1001 .slv_rpm_id = -1, 1002 }; 1003 1004 static struct qcom_icc_node slv_snoc_cfg = { 1005 .name = "slv_snoc_cfg", 1006 .id = MSM8916_SLAVE_SNOC_CFG, 1007 .buswidth = 4, 1008 .mas_rpm_id = -1, 1009 .slv_rpm_id = -1, 1010 }; 1011 1012 static struct qcom_icc_node slv_spdm = { 1013 .name = "slv_spdm", 1014 .id = MSM8916_SLAVE_SPDM, 1015 .buswidth = 4, 1016 .mas_rpm_id = -1, 1017 .slv_rpm_id = -1, 1018 }; 1019 1020 static struct qcom_icc_node slv_srvc_snoc = { 1021 .name = "slv_srvc_snoc", 1022 .id = MSM8916_SLAVE_SRVC_SNOC, 1023 .buswidth = 8, 1024 .mas_rpm_id = -1, 1025 .slv_rpm_id = -1, 1026 }; 1027 1028 static struct qcom_icc_node slv_tcsr = { 1029 .name = "slv_tcsr", 1030 .id = MSM8916_SLAVE_TCSR, 1031 .buswidth = 4, 1032 .mas_rpm_id = -1, 1033 .slv_rpm_id = -1, 1034 }; 1035 1036 static struct qcom_icc_node slv_tlmm = { 1037 .name = "slv_tlmm", 1038 .id = MSM8916_SLAVE_TLMM, 1039 .buswidth = 4, 1040 .mas_rpm_id = -1, 1041 .slv_rpm_id = -1, 1042 }; 1043 1044 static struct qcom_icc_node slv_usb_hs = { 1045 .name = "slv_usb_hs", 1046 .id = MSM8916_SLAVE_USB_HS, 1047 .buswidth = 4, 1048 .mas_rpm_id = -1, 1049 .slv_rpm_id = -1, 1050 }; 1051 1052 static struct qcom_icc_node slv_venus_cfg = { 1053 .name = "slv_venus_cfg", 1054 .id = MSM8916_SLAVE_VENUS_CFG, 1055 .buswidth = 4, 1056 .mas_rpm_id = -1, 1057 .slv_rpm_id = -1, 1058 }; 1059 1060 static const u16 snoc_bimc_0_mas_links[] = { 1061 MSM8916_SNOC_BIMC_0_SLV 1062 }; 1063 1064 static struct qcom_icc_node snoc_bimc_0_mas = { 1065 .name = "snoc_bimc_0_mas", 1066 .id = MSM8916_SNOC_BIMC_0_MAS, 1067 .buswidth = 8, 1068 .mas_rpm_id = 3, 1069 .slv_rpm_id = -1, 1070 .num_links = ARRAY_SIZE(snoc_bimc_0_mas_links), 1071 .links = snoc_bimc_0_mas_links, 1072 }; 1073 1074 static const u16 snoc_bimc_0_slv_links[] = { 1075 MSM8916_SLAVE_EBI_CH0 1076 }; 1077 1078 static struct qcom_icc_node snoc_bimc_0_slv = { 1079 .name = "snoc_bimc_0_slv", 1080 .id = MSM8916_SNOC_BIMC_0_SLV, 1081 .buswidth = 8, 1082 .mas_rpm_id = -1, 1083 .slv_rpm_id = 24, 1084 .num_links = ARRAY_SIZE(snoc_bimc_0_slv_links), 1085 .links = snoc_bimc_0_slv_links, 1086 }; 1087 1088 static const u16 snoc_bimc_1_mas_links[] = { 1089 MSM8916_SNOC_BIMC_1_SLV 1090 }; 1091 1092 static struct qcom_icc_node snoc_bimc_1_mas = { 1093 .name = "snoc_bimc_1_mas", 1094 .id = MSM8916_SNOC_BIMC_1_MAS, 1095 .buswidth = 16, 1096 .mas_rpm_id = -1, 1097 .slv_rpm_id = -1, 1098 .qos.ap_owned = true, 1099 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1100 .num_links = ARRAY_SIZE(snoc_bimc_1_mas_links), 1101 .links = snoc_bimc_1_mas_links, 1102 }; 1103 1104 static const u16 snoc_bimc_1_slv_links[] = { 1105 MSM8916_SLAVE_EBI_CH0 1106 }; 1107 1108 static struct qcom_icc_node snoc_bimc_1_slv = { 1109 .name = "snoc_bimc_1_slv", 1110 .id = MSM8916_SNOC_BIMC_1_SLV, 1111 .buswidth = 8, 1112 .mas_rpm_id = -1, 1113 .slv_rpm_id = -1, 1114 .qos.ap_owned = true, 1115 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1116 .num_links = ARRAY_SIZE(snoc_bimc_1_slv_links), 1117 .links = snoc_bimc_1_slv_links, 1118 }; 1119 1120 static const u16 snoc_int_0_links[] = { 1121 MSM8916_SLAVE_QDSS_STM, 1122 MSM8916_SLAVE_IMEM, 1123 MSM8916_SNOC_PNOC_MAS 1124 }; 1125 1126 static struct qcom_icc_node snoc_int_0 = { 1127 .name = "snoc_int_0", 1128 .id = MSM8916_SNOC_INT_0, 1129 .buswidth = 8, 1130 .mas_rpm_id = 99, 1131 .slv_rpm_id = 130, 1132 .num_links = ARRAY_SIZE(snoc_int_0_links), 1133 .links = snoc_int_0_links, 1134 }; 1135 1136 static const u16 snoc_int_1_links[] = { 1137 MSM8916_SLAVE_APSS, 1138 MSM8916_SLAVE_CATS_128, 1139 MSM8916_SLAVE_OCMEM_64 1140 }; 1141 1142 static struct qcom_icc_node snoc_int_1 = { 1143 .name = "snoc_int_1", 1144 .id = MSM8916_SNOC_INT_1, 1145 .buswidth = 8, 1146 .mas_rpm_id = -1, 1147 .slv_rpm_id = -1, 1148 .num_links = ARRAY_SIZE(snoc_int_1_links), 1149 .links = snoc_int_1_links, 1150 }; 1151 1152 static const u16 snoc_int_bimc_links[] = { 1153 MSM8916_SNOC_BIMC_0_MAS 1154 }; 1155 1156 static struct qcom_icc_node snoc_int_bimc = { 1157 .name = "snoc_int_bimc", 1158 .id = MSM8916_SNOC_INT_BIMC, 1159 .buswidth = 8, 1160 .mas_rpm_id = 101, 1161 .slv_rpm_id = 132, 1162 .num_links = ARRAY_SIZE(snoc_int_bimc_links), 1163 .links = snoc_int_bimc_links, 1164 }; 1165 1166 static const u16 snoc_pcnoc_mas_links[] = { 1167 MSM8916_SNOC_PNOC_SLV 1168 }; 1169 1170 static struct qcom_icc_node snoc_pcnoc_mas = { 1171 .name = "snoc_pcnoc_mas", 1172 .id = MSM8916_SNOC_PNOC_MAS, 1173 .buswidth = 8, 1174 .mas_rpm_id = -1, 1175 .slv_rpm_id = -1, 1176 .num_links = ARRAY_SIZE(snoc_pcnoc_mas_links), 1177 .links = snoc_pcnoc_mas_links, 1178 }; 1179 1180 static const u16 snoc_pcnoc_slv_links[] = { 1181 MSM8916_PNOC_INT_0 1182 }; 1183 1184 static struct qcom_icc_node snoc_pcnoc_slv = { 1185 .name = "snoc_pcnoc_slv", 1186 .id = MSM8916_SNOC_PNOC_SLV, 1187 .buswidth = 8, 1188 .mas_rpm_id = -1, 1189 .slv_rpm_id = -1, 1190 .num_links = ARRAY_SIZE(snoc_pcnoc_slv_links), 1191 .links = snoc_pcnoc_slv_links, 1192 }; 1193 1194 static struct qcom_icc_node *msm8916_snoc_nodes[] = { 1195 [BIMC_SNOC_SLV] = &bimc_snoc_slv, 1196 [MASTER_JPEG] = &mas_jpeg, 1197 [MASTER_MDP_PORT0] = &mas_mdp, 1198 [MASTER_QDSS_BAM] = &mas_qdss_bam, 1199 [MASTER_QDSS_ETR] = &mas_qdss_etr, 1200 [MASTER_SNOC_CFG] = &mas_snoc_cfg, 1201 [MASTER_VFE] = &mas_vfe, 1202 [MASTER_VIDEO_P0] = &mas_video, 1203 [SNOC_MM_INT_0] = &mm_int_0, 1204 [SNOC_MM_INT_1] = &mm_int_1, 1205 [SNOC_MM_INT_2] = &mm_int_2, 1206 [SNOC_MM_INT_BIMC] = &mm_int_bimc, 1207 [PCNOC_SNOC_SLV] = &pcnoc_snoc_slv, 1208 [SLAVE_APSS] = &slv_apss, 1209 [SLAVE_CATS_128] = &slv_cats_0, 1210 [SLAVE_OCMEM_64] = &slv_cats_1, 1211 [SLAVE_IMEM] = &slv_imem, 1212 [SLAVE_QDSS_STM] = &slv_qdss_stm, 1213 [SLAVE_SRVC_SNOC] = &slv_srvc_snoc, 1214 [SNOC_BIMC_0_MAS] = &snoc_bimc_0_mas, 1215 [SNOC_BIMC_1_MAS] = &snoc_bimc_1_mas, 1216 [SNOC_INT_0] = &snoc_int_0, 1217 [SNOC_INT_1] = &snoc_int_1, 1218 [SNOC_INT_BIMC] = &snoc_int_bimc, 1219 [SNOC_PCNOC_MAS] = &snoc_pcnoc_mas, 1220 [SNOC_QDSS_INT] = &qdss_int, 1221 }; 1222 1223 static const struct regmap_config msm8916_snoc_regmap_config = { 1224 .reg_bits = 32, 1225 .reg_stride = 4, 1226 .val_bits = 32, 1227 .max_register = 0x14000, 1228 .fast_io = true, 1229 }; 1230 1231 static struct qcom_icc_desc msm8916_snoc = { 1232 .type = QCOM_ICC_NOC, 1233 .nodes = msm8916_snoc_nodes, 1234 .num_nodes = ARRAY_SIZE(msm8916_snoc_nodes), 1235 .regmap_cfg = &msm8916_snoc_regmap_config, 1236 .qos_offset = 0x7000, 1237 }; 1238 1239 static struct qcom_icc_node *msm8916_bimc_nodes[] = { 1240 [BIMC_SNOC_MAS] = &bimc_snoc_mas, 1241 [MASTER_AMPSS_M0] = &mas_apss, 1242 [MASTER_GRAPHICS_3D] = &mas_gfx, 1243 [MASTER_TCU0] = &mas_tcu0, 1244 [MASTER_TCU1] = &mas_tcu1, 1245 [SLAVE_AMPSS_L2] = &slv_apps_l2, 1246 [SLAVE_EBI_CH0] = &slv_ebi_ch0, 1247 [SNOC_BIMC_0_SLV] = &snoc_bimc_0_slv, 1248 [SNOC_BIMC_1_SLV] = &snoc_bimc_1_slv, 1249 }; 1250 1251 static const struct regmap_config msm8916_bimc_regmap_config = { 1252 .reg_bits = 32, 1253 .reg_stride = 4, 1254 .val_bits = 32, 1255 .max_register = 0x62000, 1256 .fast_io = true, 1257 }; 1258 1259 static struct qcom_icc_desc msm8916_bimc = { 1260 .type = QCOM_ICC_BIMC, 1261 .nodes = msm8916_bimc_nodes, 1262 .num_nodes = ARRAY_SIZE(msm8916_bimc_nodes), 1263 .regmap_cfg = &msm8916_bimc_regmap_config, 1264 .qos_offset = 0x8000, 1265 }; 1266 1267 static struct qcom_icc_node *msm8916_pcnoc_nodes[] = { 1268 [MASTER_BLSP_1] = &mas_blsp_1, 1269 [MASTER_DEHR] = &mas_dehr, 1270 [MASTER_LPASS] = &mas_audio, 1271 [MASTER_CRYPTO_CORE0] = &mas_pcnoc_crypto_0, 1272 [MASTER_SDCC_1] = &mas_pcnoc_sdcc_1, 1273 [MASTER_SDCC_2] = &mas_pcnoc_sdcc_2, 1274 [MASTER_SPDM] = &mas_spdm, 1275 [MASTER_USB_HS] = &mas_usb_hs, 1276 [PCNOC_INT_0] = &pcnoc_int_0, 1277 [PCNOC_INT_1] = &pcnoc_int_1, 1278 [PCNOC_MAS_0] = &pcnoc_m_0, 1279 [PCNOC_MAS_1] = &pcnoc_m_1, 1280 [PCNOC_SLV_0] = &pcnoc_s_0, 1281 [PCNOC_SLV_1] = &pcnoc_s_1, 1282 [PCNOC_SLV_2] = &pcnoc_s_2, 1283 [PCNOC_SLV_3] = &pcnoc_s_3, 1284 [PCNOC_SLV_4] = &pcnoc_s_4, 1285 [PCNOC_SLV_8] = &pcnoc_s_8, 1286 [PCNOC_SLV_9] = &pcnoc_s_9, 1287 [PCNOC_SNOC_MAS] = &pcnoc_snoc_mas, 1288 [SLAVE_BIMC_CFG] = &slv_bimc_cfg, 1289 [SLAVE_BLSP_1] = &slv_blsp_1, 1290 [SLAVE_BOOT_ROM] = &slv_boot_rom, 1291 [SLAVE_CAMERA_CFG] = &slv_camera_cfg, 1292 [SLAVE_CLK_CTL] = &slv_clk_ctl, 1293 [SLAVE_CRYPTO_0_CFG] = &slv_crypto_0_cfg, 1294 [SLAVE_DEHR_CFG] = &slv_dehr_cfg, 1295 [SLAVE_DISPLAY_CFG] = &slv_display_cfg, 1296 [SLAVE_GRAPHICS_3D_CFG] = &slv_gfx_cfg, 1297 [SLAVE_IMEM_CFG] = &slv_imem_cfg, 1298 [SLAVE_LPASS] = &slv_audio, 1299 [SLAVE_MPM] = &slv_mpm, 1300 [SLAVE_MSG_RAM] = &slv_msg_ram, 1301 [SLAVE_MSS] = &slv_mss, 1302 [SLAVE_PDM] = &slv_pdm, 1303 [SLAVE_PMIC_ARB] = &slv_pmic_arb, 1304 [SLAVE_PCNOC_CFG] = &slv_pcnoc_cfg, 1305 [SLAVE_PRNG] = &slv_prng, 1306 [SLAVE_QDSS_CFG] = &slv_qdss_cfg, 1307 [SLAVE_RBCPR_CFG] = &slv_rbcpr_cfg, 1308 [SLAVE_SDCC_1] = &slv_sdcc_1, 1309 [SLAVE_SDCC_2] = &slv_sdcc_2, 1310 [SLAVE_SECURITY] = &slv_security, 1311 [SLAVE_SNOC_CFG] = &slv_snoc_cfg, 1312 [SLAVE_SPDM] = &slv_spdm, 1313 [SLAVE_TCSR] = &slv_tcsr, 1314 [SLAVE_TLMM] = &slv_tlmm, 1315 [SLAVE_USB_HS] = &slv_usb_hs, 1316 [SLAVE_VENUS_CFG] = &slv_venus_cfg, 1317 [SNOC_PCNOC_SLV] = &snoc_pcnoc_slv, 1318 }; 1319 1320 static const struct regmap_config msm8916_pcnoc_regmap_config = { 1321 .reg_bits = 32, 1322 .reg_stride = 4, 1323 .val_bits = 32, 1324 .max_register = 0x11000, 1325 .fast_io = true, 1326 }; 1327 1328 static struct qcom_icc_desc msm8916_pcnoc = { 1329 .type = QCOM_ICC_NOC, 1330 .nodes = msm8916_pcnoc_nodes, 1331 .num_nodes = ARRAY_SIZE(msm8916_pcnoc_nodes), 1332 .regmap_cfg = &msm8916_pcnoc_regmap_config, 1333 .qos_offset = 0x7000, 1334 }; 1335 1336 static const struct of_device_id msm8916_noc_of_match[] = { 1337 { .compatible = "qcom,msm8916-bimc", .data = &msm8916_bimc }, 1338 { .compatible = "qcom,msm8916-pcnoc", .data = &msm8916_pcnoc }, 1339 { .compatible = "qcom,msm8916-snoc", .data = &msm8916_snoc }, 1340 { } 1341 }; 1342 MODULE_DEVICE_TABLE(of, msm8916_noc_of_match); 1343 1344 static struct platform_driver msm8916_noc_driver = { 1345 .probe = qnoc_probe, 1346 .remove = qnoc_remove, 1347 .driver = { 1348 .name = "qnoc-msm8916", 1349 .of_match_table = msm8916_noc_of_match, 1350 }, 1351 }; 1352 module_platform_driver(msm8916_noc_driver); 1353 MODULE_AUTHOR("Georgi Djakov <georgi.djakov@linaro.org>"); 1354 MODULE_DESCRIPTION("Qualcomm MSM8916 NoC driver"); 1355 MODULE_LICENSE("GPL v2"); 1356