1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Based on data from msm8909-bus.dtsi in Qualcomm's msm-3.18 release: 4 * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. 5 */ 6 7 #include <linux/device.h> 8 #include <linux/interconnect-provider.h> 9 #include <linux/module.h> 10 #include <linux/platform_device.h> 11 #include <linux/regmap.h> 12 13 #include <dt-bindings/interconnect/qcom,msm8909.h> 14 15 #include "icc-rpm.h" 16 17 enum { 18 QNOC_MASTER_AMPSS_M0 = 1, 19 QNOC_MASTER_GRAPHICS_3D, 20 QNOC_SNOC_BIMC_0_MAS, 21 QNOC_SNOC_BIMC_1_MAS, 22 QNOC_MASTER_TCU_0, 23 QNOC_MASTER_TCU_1, 24 QNOC_MASTER_AUDIO, 25 QNOC_MASTER_SPDM, 26 QNOC_MASTER_DEHR, 27 QNOC_MASTER_QPIC, 28 QNOC_MASTER_BLSP_1, 29 QNOC_MASTER_USB_HS, 30 QNOC_MASTER_CRYPTO_CORE0, 31 QNOC_MASTER_SDCC_1, 32 QNOC_MASTER_SDCC_2, 33 QNOC_SNOC_PNOC_MAS, 34 QNOC_MASTER_QDSS_BAM, 35 QNOC_BIMC_SNOC_MAS, 36 QNOC_MASTER_MDP_PORT0, 37 QNOC_PNOC_SNOC_MAS, 38 QNOC_MASTER_VIDEO_P0, 39 QNOC_MASTER_VFE, 40 QNOC_MASTER_QDSS_ETR, 41 QNOC_PNOC_M_0, 42 QNOC_PNOC_M_1, 43 QNOC_PNOC_INT_0, 44 QNOC_PNOC_INT_1, 45 QNOC_PNOC_SLV_0, 46 QNOC_PNOC_SLV_1, 47 QNOC_PNOC_SLV_2, 48 QNOC_PNOC_SLV_3, 49 QNOC_PNOC_SLV_4, 50 QNOC_PNOC_SLV_5, 51 QNOC_PNOC_SLV_7, 52 QNOC_SNOC_MM_INT_0, 53 QNOC_SNOC_MM_INT_1, 54 QNOC_SNOC_MM_INT_2, 55 QNOC_SNOC_MM_INT_BIMC, 56 QNOC_SNOC_QDSS_INT, 57 QNOC_SNOC_INT_0, 58 QNOC_SNOC_INT_1, 59 QNOC_SNOC_INT_BIMC, 60 QNOC_SLAVE_EBI_CH0, 61 QNOC_BIMC_SNOC_SLV, 62 QNOC_SLAVE_TCSR, 63 QNOC_SLAVE_SDCC_1, 64 QNOC_SLAVE_BLSP_1, 65 QNOC_SLAVE_CRYPTO_0_CFG, 66 QNOC_SLAVE_MESSAGE_RAM, 67 QNOC_SLAVE_PDM, 68 QNOC_SLAVE_PRNG, 69 QNOC_SLAVE_USB_HS, 70 QNOC_SLAVE_QPIC, 71 QNOC_SLAVE_SPDM, 72 QNOC_SLAVE_SDCC_2, 73 QNOC_SLAVE_AUDIO, 74 QNOC_SLAVE_DEHR_CFG, 75 QNOC_SLAVE_SNOC_CFG, 76 QNOC_SLAVE_QDSS_CFG, 77 QNOC_SLAVE_USB_PHYS_CFG, 78 QNOC_SLAVE_CAMERA_CFG, 79 QNOC_SLAVE_DISPLAY_CFG, 80 QNOC_SLAVE_VENUS_CFG, 81 QNOC_SLAVE_TLMM, 82 QNOC_SLAVE_GRAPHICS_3D_CFG, 83 QNOC_SLAVE_IMEM_CFG, 84 QNOC_SLAVE_BIMC_CFG, 85 QNOC_SLAVE_PMIC_ARB, 86 QNOC_SLAVE_TCU, 87 QNOC_PNOC_SNOC_SLV, 88 QNOC_SLAVE_APPSS, 89 QNOC_SNOC_BIMC_0_SLV, 90 QNOC_SNOC_BIMC_1_SLV, 91 QNOC_SLAVE_SYSTEM_IMEM, 92 QNOC_SNOC_PNOC_SLV, 93 QNOC_SLAVE_QDSS_STM, 94 QNOC_SLAVE_CATS_128, 95 QNOC_SLAVE_OCMEM_64, 96 }; 97 98 static const u16 mas_apps_proc_links[] = { 99 QNOC_BIMC_SNOC_SLV, 100 QNOC_SLAVE_EBI_CH0 101 }; 102 103 static struct qcom_icc_node mas_apps_proc = { 104 .name = "mas_apps_proc", 105 .id = QNOC_MASTER_AMPSS_M0, 106 .buswidth = 8, 107 .mas_rpm_id = 0, 108 .slv_rpm_id = -1, 109 .qos.ap_owned = true, 110 .qos.qos_mode = NOC_QOS_MODE_FIXED, 111 .qos.areq_prio = 0, 112 .qos.prio_level = 0, 113 .qos.qos_port = 0, 114 .num_links = ARRAY_SIZE(mas_apps_proc_links), 115 .links = mas_apps_proc_links, 116 }; 117 118 static const u16 mas_oxili_links[] = { 119 QNOC_BIMC_SNOC_SLV, 120 QNOC_SLAVE_EBI_CH0 121 }; 122 123 static struct qcom_icc_node mas_oxili = { 124 .name = "mas_oxili", 125 .id = QNOC_MASTER_GRAPHICS_3D, 126 .buswidth = 8, 127 .mas_rpm_id = 6, 128 .slv_rpm_id = -1, 129 .qos.ap_owned = true, 130 .qos.qos_mode = NOC_QOS_MODE_FIXED, 131 .qos.areq_prio = 0, 132 .qos.prio_level = 0, 133 .qos.qos_port = 2, 134 .num_links = ARRAY_SIZE(mas_oxili_links), 135 .links = mas_oxili_links, 136 }; 137 138 static const u16 mas_snoc_bimc_0_links[] = { 139 QNOC_SLAVE_EBI_CH0 140 }; 141 142 static struct qcom_icc_node mas_snoc_bimc_0 = { 143 .name = "mas_snoc_bimc_0", 144 .id = QNOC_SNOC_BIMC_0_MAS, 145 .buswidth = 8, 146 .mas_rpm_id = 3, 147 .slv_rpm_id = -1, 148 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 149 .qos.areq_prio = 0, 150 .qos.prio_level = 0, 151 .qos.qos_port = 3, 152 .num_links = ARRAY_SIZE(mas_snoc_bimc_0_links), 153 .links = mas_snoc_bimc_0_links, 154 }; 155 156 static const u16 mas_snoc_bimc_1_links[] = { 157 QNOC_SLAVE_EBI_CH0 158 }; 159 160 static struct qcom_icc_node mas_snoc_bimc_1 = { 161 .name = "mas_snoc_bimc_1", 162 .id = QNOC_SNOC_BIMC_1_MAS, 163 .buswidth = 8, 164 .mas_rpm_id = 76, 165 .slv_rpm_id = -1, 166 .qos.ap_owned = true, 167 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 168 .qos.areq_prio = 0, 169 .qos.prio_level = 0, 170 .qos.qos_port = 4, 171 .num_links = ARRAY_SIZE(mas_snoc_bimc_1_links), 172 .links = mas_snoc_bimc_1_links, 173 }; 174 175 static const u16 mas_tcu_0_links[] = { 176 QNOC_BIMC_SNOC_SLV, 177 QNOC_SLAVE_EBI_CH0 178 }; 179 180 static struct qcom_icc_node mas_tcu_0 = { 181 .name = "mas_tcu_0", 182 .id = QNOC_MASTER_TCU_0, 183 .buswidth = 8, 184 .mas_rpm_id = 102, 185 .slv_rpm_id = -1, 186 .qos.ap_owned = true, 187 .qos.qos_mode = NOC_QOS_MODE_FIXED, 188 .qos.areq_prio = 0, 189 .qos.prio_level = 2, 190 .qos.qos_port = 5, 191 .num_links = ARRAY_SIZE(mas_tcu_0_links), 192 .links = mas_tcu_0_links, 193 }; 194 195 static const u16 mas_tcu_1_links[] = { 196 QNOC_BIMC_SNOC_SLV, 197 QNOC_SLAVE_EBI_CH0 198 }; 199 200 static struct qcom_icc_node mas_tcu_1 = { 201 .name = "mas_tcu_1", 202 .id = QNOC_MASTER_TCU_1, 203 .buswidth = 8, 204 .mas_rpm_id = 103, 205 .slv_rpm_id = -1, 206 .qos.ap_owned = true, 207 .qos.qos_mode = NOC_QOS_MODE_FIXED, 208 .qos.areq_prio = 0, 209 .qos.prio_level = 2, 210 .qos.qos_port = 6, 211 .num_links = ARRAY_SIZE(mas_tcu_1_links), 212 .links = mas_tcu_1_links, 213 }; 214 215 static const u16 mas_audio_links[] = { 216 QNOC_PNOC_M_0 217 }; 218 219 static struct qcom_icc_node mas_audio = { 220 .name = "mas_audio", 221 .id = QNOC_MASTER_AUDIO, 222 .buswidth = 4, 223 .mas_rpm_id = 78, 224 .slv_rpm_id = -1, 225 .num_links = ARRAY_SIZE(mas_audio_links), 226 .links = mas_audio_links, 227 }; 228 229 static const u16 mas_spdm_links[] = { 230 QNOC_PNOC_M_0 231 }; 232 233 static struct qcom_icc_node mas_spdm = { 234 .name = "mas_spdm", 235 .id = QNOC_MASTER_SPDM, 236 .buswidth = 4, 237 .mas_rpm_id = 50, 238 .slv_rpm_id = -1, 239 .num_links = ARRAY_SIZE(mas_spdm_links), 240 .links = mas_spdm_links, 241 }; 242 243 static const u16 mas_dehr_links[] = { 244 QNOC_PNOC_M_0 245 }; 246 247 static struct qcom_icc_node mas_dehr = { 248 .name = "mas_dehr", 249 .id = QNOC_MASTER_DEHR, 250 .buswidth = 4, 251 .mas_rpm_id = 48, 252 .slv_rpm_id = -1, 253 .num_links = ARRAY_SIZE(mas_dehr_links), 254 .links = mas_dehr_links, 255 }; 256 257 static const u16 mas_qpic_links[] = { 258 QNOC_PNOC_M_0 259 }; 260 261 static struct qcom_icc_node mas_qpic = { 262 .name = "mas_qpic", 263 .id = QNOC_MASTER_QPIC, 264 .buswidth = 4, 265 .mas_rpm_id = 58, 266 .slv_rpm_id = -1, 267 .num_links = ARRAY_SIZE(mas_qpic_links), 268 .links = mas_qpic_links, 269 }; 270 271 static const u16 mas_blsp_1_links[] = { 272 QNOC_PNOC_M_1 273 }; 274 275 static struct qcom_icc_node mas_blsp_1 = { 276 .name = "mas_blsp_1", 277 .id = QNOC_MASTER_BLSP_1, 278 .buswidth = 4, 279 .mas_rpm_id = 41, 280 .slv_rpm_id = -1, 281 .num_links = ARRAY_SIZE(mas_blsp_1_links), 282 .links = mas_blsp_1_links, 283 }; 284 285 static const u16 mas_usb_hs_links[] = { 286 QNOC_PNOC_M_1 287 }; 288 289 static struct qcom_icc_node mas_usb_hs = { 290 .name = "mas_usb_hs", 291 .id = QNOC_MASTER_USB_HS, 292 .buswidth = 4, 293 .mas_rpm_id = 42, 294 .slv_rpm_id = -1, 295 .num_links = ARRAY_SIZE(mas_usb_hs_links), 296 .links = mas_usb_hs_links, 297 }; 298 299 static const u16 mas_crypto_links[] = { 300 QNOC_PNOC_INT_1 301 }; 302 303 static struct qcom_icc_node mas_crypto = { 304 .name = "mas_crypto", 305 .id = QNOC_MASTER_CRYPTO_CORE0, 306 .buswidth = 8, 307 .mas_rpm_id = 23, 308 .slv_rpm_id = -1, 309 .qos.ap_owned = true, 310 .qos.qos_mode = NOC_QOS_MODE_FIXED, 311 .qos.areq_prio = 0, 312 .qos.prio_level = 0, 313 .qos.qos_port = 0, 314 .num_links = ARRAY_SIZE(mas_crypto_links), 315 .links = mas_crypto_links, 316 }; 317 318 static const u16 mas_sdcc_1_links[] = { 319 QNOC_PNOC_INT_1 320 }; 321 322 static struct qcom_icc_node mas_sdcc_1 = { 323 .name = "mas_sdcc_1", 324 .id = QNOC_MASTER_SDCC_1, 325 .buswidth = 8, 326 .mas_rpm_id = 33, 327 .slv_rpm_id = -1, 328 .qos.qos_mode = NOC_QOS_MODE_FIXED, 329 .qos.areq_prio = 0, 330 .qos.prio_level = 0, 331 .qos.qos_port = 7, 332 .num_links = ARRAY_SIZE(mas_sdcc_1_links), 333 .links = mas_sdcc_1_links, 334 }; 335 336 static const u16 mas_sdcc_2_links[] = { 337 QNOC_PNOC_INT_1 338 }; 339 340 static struct qcom_icc_node mas_sdcc_2 = { 341 .name = "mas_sdcc_2", 342 .id = QNOC_MASTER_SDCC_2, 343 .buswidth = 8, 344 .mas_rpm_id = 35, 345 .slv_rpm_id = -1, 346 .qos.qos_mode = NOC_QOS_MODE_FIXED, 347 .qos.areq_prio = 0, 348 .qos.prio_level = 0, 349 .qos.qos_port = 8, 350 .num_links = ARRAY_SIZE(mas_sdcc_2_links), 351 .links = mas_sdcc_2_links, 352 }; 353 354 static const u16 mas_snoc_pcnoc_links[] = { 355 QNOC_PNOC_INT_0 356 }; 357 358 static struct qcom_icc_node mas_snoc_pcnoc = { 359 .name = "mas_snoc_pcnoc", 360 .id = QNOC_SNOC_PNOC_MAS, 361 .buswidth = 8, 362 .mas_rpm_id = 77, 363 .slv_rpm_id = -1, 364 .qos.qos_mode = NOC_QOS_MODE_FIXED, 365 .qos.areq_prio = 0, 366 .qos.prio_level = 0, 367 .qos.qos_port = 9, 368 .num_links = ARRAY_SIZE(mas_snoc_pcnoc_links), 369 .links = mas_snoc_pcnoc_links, 370 }; 371 372 static const u16 mas_qdss_bam_links[] = { 373 QNOC_SNOC_QDSS_INT 374 }; 375 376 static struct qcom_icc_node mas_qdss_bam = { 377 .name = "mas_qdss_bam", 378 .id = QNOC_MASTER_QDSS_BAM, 379 .buswidth = 4, 380 .mas_rpm_id = 19, 381 .slv_rpm_id = -1, 382 .qos.ap_owned = true, 383 .qos.qos_mode = NOC_QOS_MODE_FIXED, 384 .qos.areq_prio = 1, 385 .qos.prio_level = 1, 386 .qos.qos_port = 11, 387 .num_links = ARRAY_SIZE(mas_qdss_bam_links), 388 .links = mas_qdss_bam_links, 389 }; 390 391 static const u16 mas_bimc_snoc_links[] = { 392 QNOC_SNOC_INT_0, 393 QNOC_SNOC_INT_1 394 }; 395 396 static struct qcom_icc_node mas_bimc_snoc = { 397 .name = "mas_bimc_snoc", 398 .id = QNOC_BIMC_SNOC_MAS, 399 .buswidth = 8, 400 .mas_rpm_id = 21, 401 .slv_rpm_id = -1, 402 .num_links = ARRAY_SIZE(mas_bimc_snoc_links), 403 .links = mas_bimc_snoc_links, 404 }; 405 406 static const u16 mas_mdp_links[] = { 407 QNOC_SNOC_MM_INT_1, 408 QNOC_SNOC_MM_INT_2 409 }; 410 411 static struct qcom_icc_node mas_mdp = { 412 .name = "mas_mdp", 413 .id = QNOC_MASTER_MDP_PORT0, 414 .buswidth = 16, 415 .mas_rpm_id = 8, 416 .slv_rpm_id = -1, 417 .qos.ap_owned = true, 418 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 419 .qos.areq_prio = 0, 420 .qos.prio_level = 0, 421 .qos.qos_port = 7, 422 .num_links = ARRAY_SIZE(mas_mdp_links), 423 .links = mas_mdp_links, 424 .ab_coeff = 167, 425 }; 426 427 static const u16 mas_pcnoc_snoc_links[] = { 428 QNOC_SNOC_INT_0, 429 QNOC_SNOC_INT_1, 430 QNOC_SNOC_INT_BIMC 431 }; 432 433 static struct qcom_icc_node mas_pcnoc_snoc = { 434 .name = "mas_pcnoc_snoc", 435 .id = QNOC_PNOC_SNOC_MAS, 436 .buswidth = 8, 437 .mas_rpm_id = 29, 438 .slv_rpm_id = -1, 439 .qos.qos_mode = NOC_QOS_MODE_FIXED, 440 .qos.areq_prio = 0, 441 .qos.prio_level = 0, 442 .qos.qos_port = 5, 443 .num_links = ARRAY_SIZE(mas_pcnoc_snoc_links), 444 .links = mas_pcnoc_snoc_links, 445 }; 446 447 static const u16 mas_venus_links[] = { 448 QNOC_SNOC_MM_INT_0, 449 QNOC_SNOC_MM_INT_2 450 }; 451 452 static struct qcom_icc_node mas_venus = { 453 .name = "mas_venus", 454 .id = QNOC_MASTER_VIDEO_P0, 455 .buswidth = 16, 456 .mas_rpm_id = 9, 457 .slv_rpm_id = -1, 458 .qos.ap_owned = true, 459 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 460 .qos.areq_prio = 0, 461 .qos.prio_level = 0, 462 .qos.qos_port = 8, 463 .num_links = ARRAY_SIZE(mas_venus_links), 464 .links = mas_venus_links, 465 .ab_coeff = 167, 466 }; 467 468 static const u16 mas_vfe_links[] = { 469 QNOC_SNOC_MM_INT_1, 470 QNOC_SNOC_MM_INT_2 471 }; 472 473 static struct qcom_icc_node mas_vfe = { 474 .name = "mas_vfe", 475 .id = QNOC_MASTER_VFE, 476 .buswidth = 16, 477 .mas_rpm_id = 11, 478 .slv_rpm_id = -1, 479 .qos.ap_owned = true, 480 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 481 .qos.areq_prio = 0, 482 .qos.prio_level = 0, 483 .qos.qos_port = 9, 484 .num_links = ARRAY_SIZE(mas_vfe_links), 485 .links = mas_vfe_links, 486 .ab_coeff = 167, 487 }; 488 489 static const u16 mas_qdss_etr_links[] = { 490 QNOC_SNOC_QDSS_INT 491 }; 492 493 static struct qcom_icc_node mas_qdss_etr = { 494 .name = "mas_qdss_etr", 495 .id = QNOC_MASTER_QDSS_ETR, 496 .buswidth = 8, 497 .mas_rpm_id = 31, 498 .slv_rpm_id = -1, 499 .qos.ap_owned = true, 500 .qos.qos_mode = NOC_QOS_MODE_FIXED, 501 .qos.areq_prio = 1, 502 .qos.prio_level = 1, 503 .qos.qos_port = 10, 504 .num_links = ARRAY_SIZE(mas_qdss_etr_links), 505 .links = mas_qdss_etr_links, 506 }; 507 508 static const u16 pcnoc_m_0_links[] = { 509 QNOC_PNOC_SNOC_SLV 510 }; 511 512 static struct qcom_icc_node pcnoc_m_0 = { 513 .name = "pcnoc_m_0", 514 .id = QNOC_PNOC_M_0, 515 .buswidth = 8, 516 .mas_rpm_id = 87, 517 .slv_rpm_id = 116, 518 .qos.qos_mode = NOC_QOS_MODE_BYPASS, 519 .qos.areq_prio = 0, 520 .qos.prio_level = 0, 521 .qos.qos_port = 5, 522 .num_links = ARRAY_SIZE(pcnoc_m_0_links), 523 .links = pcnoc_m_0_links, 524 }; 525 526 static const u16 pcnoc_m_1_links[] = { 527 QNOC_PNOC_SNOC_SLV 528 }; 529 530 static struct qcom_icc_node pcnoc_m_1 = { 531 .name = "pcnoc_m_1", 532 .id = QNOC_PNOC_M_1, 533 .buswidth = 8, 534 .mas_rpm_id = 88, 535 .slv_rpm_id = 117, 536 .qos.qos_mode = NOC_QOS_MODE_FIXED, 537 .qos.areq_prio = 0, 538 .qos.prio_level = 0, 539 .qos.qos_port = 6, 540 .num_links = ARRAY_SIZE(pcnoc_m_1_links), 541 .links = pcnoc_m_1_links, 542 }; 543 544 static const u16 pcnoc_int_0_links[] = { 545 QNOC_PNOC_SLV_3, 546 QNOC_PNOC_SLV_2, 547 QNOC_PNOC_SLV_1, 548 QNOC_PNOC_SLV_0, 549 QNOC_PNOC_SLV_7, 550 QNOC_PNOC_SLV_5, 551 QNOC_PNOC_SLV_4, 552 QNOC_SLAVE_TCU 553 }; 554 555 static struct qcom_icc_node pcnoc_int_0 = { 556 .name = "pcnoc_int_0", 557 .id = QNOC_PNOC_INT_0, 558 .buswidth = 8, 559 .mas_rpm_id = 85, 560 .slv_rpm_id = 114, 561 .num_links = ARRAY_SIZE(pcnoc_int_0_links), 562 .links = pcnoc_int_0_links, 563 }; 564 565 static const u16 pcnoc_int_1_links[] = { 566 QNOC_PNOC_SNOC_SLV 567 }; 568 569 static struct qcom_icc_node pcnoc_int_1 = { 570 .name = "pcnoc_int_1", 571 .id = QNOC_PNOC_INT_1, 572 .buswidth = 8, 573 .mas_rpm_id = 86, 574 .slv_rpm_id = 115, 575 .num_links = ARRAY_SIZE(pcnoc_int_1_links), 576 .links = pcnoc_int_1_links, 577 }; 578 579 static const u16 pcnoc_s_0_links[] = { 580 QNOC_SLAVE_SDCC_1, 581 QNOC_SLAVE_TCSR, 582 QNOC_SLAVE_BLSP_1 583 }; 584 585 static struct qcom_icc_node pcnoc_s_0 = { 586 .name = "pcnoc_s_0", 587 .id = QNOC_PNOC_SLV_0, 588 .buswidth = 4, 589 .mas_rpm_id = 89, 590 .slv_rpm_id = 118, 591 .num_links = ARRAY_SIZE(pcnoc_s_0_links), 592 .links = pcnoc_s_0_links, 593 }; 594 595 static const u16 pcnoc_s_1_links[] = { 596 QNOC_SLAVE_MESSAGE_RAM, 597 QNOC_SLAVE_CRYPTO_0_CFG, 598 QNOC_SLAVE_USB_HS, 599 QNOC_SLAVE_PDM, 600 QNOC_SLAVE_PRNG, 601 QNOC_SLAVE_QPIC 602 }; 603 604 static struct qcom_icc_node pcnoc_s_1 = { 605 .name = "pcnoc_s_1", 606 .id = QNOC_PNOC_SLV_1, 607 .buswidth = 4, 608 .mas_rpm_id = 90, 609 .slv_rpm_id = 119, 610 .num_links = ARRAY_SIZE(pcnoc_s_1_links), 611 .links = pcnoc_s_1_links, 612 }; 613 614 static const u16 pcnoc_s_2_links[] = { 615 QNOC_SLAVE_SPDM, 616 QNOC_SLAVE_SDCC_2, 617 QNOC_SLAVE_AUDIO, 618 QNOC_SLAVE_DEHR_CFG 619 }; 620 621 static struct qcom_icc_node pcnoc_s_2 = { 622 .name = "pcnoc_s_2", 623 .id = QNOC_PNOC_SLV_2, 624 .buswidth = 4, 625 .mas_rpm_id = 91, 626 .slv_rpm_id = 120, 627 .num_links = ARRAY_SIZE(pcnoc_s_2_links), 628 .links = pcnoc_s_2_links, 629 }; 630 631 static const u16 pcnoc_s_3_links[] = { 632 QNOC_SLAVE_QDSS_CFG, 633 QNOC_SLAVE_USB_PHYS_CFG, 634 QNOC_SLAVE_SNOC_CFG 635 }; 636 637 static struct qcom_icc_node pcnoc_s_3 = { 638 .name = "pcnoc_s_3", 639 .id = QNOC_PNOC_SLV_3, 640 .buswidth = 4, 641 .mas_rpm_id = 92, 642 .slv_rpm_id = 121, 643 .num_links = ARRAY_SIZE(pcnoc_s_3_links), 644 .links = pcnoc_s_3_links, 645 }; 646 647 static const u16 pcnoc_s_4_links[] = { 648 QNOC_SLAVE_CAMERA_CFG, 649 QNOC_SLAVE_DISPLAY_CFG, 650 QNOC_SLAVE_VENUS_CFG 651 }; 652 653 static struct qcom_icc_node pcnoc_s_4 = { 654 .name = "pcnoc_s_4", 655 .id = QNOC_PNOC_SLV_4, 656 .buswidth = 4, 657 .mas_rpm_id = 93, 658 .slv_rpm_id = 122, 659 .qos.ap_owned = true, 660 .qos.qos_mode = NOC_QOS_MODE_INVALID, 661 .num_links = ARRAY_SIZE(pcnoc_s_4_links), 662 .links = pcnoc_s_4_links, 663 }; 664 665 static const u16 pcnoc_s_5_links[] = { 666 QNOC_SLAVE_TLMM 667 }; 668 669 static struct qcom_icc_node pcnoc_s_5 = { 670 .name = "pcnoc_s_5", 671 .id = QNOC_PNOC_SLV_5, 672 .buswidth = 4, 673 .mas_rpm_id = 129, 674 .slv_rpm_id = 189, 675 .num_links = ARRAY_SIZE(pcnoc_s_5_links), 676 .links = pcnoc_s_5_links, 677 }; 678 679 static const u16 pcnoc_s_7_links[] = { 680 QNOC_SLAVE_GRAPHICS_3D_CFG, 681 QNOC_SLAVE_IMEM_CFG, 682 QNOC_SLAVE_BIMC_CFG, 683 QNOC_SLAVE_PMIC_ARB 684 }; 685 686 static struct qcom_icc_node pcnoc_s_7 = { 687 .name = "pcnoc_s_7", 688 .id = QNOC_PNOC_SLV_7, 689 .buswidth = 4, 690 .mas_rpm_id = 95, 691 .slv_rpm_id = 124, 692 .num_links = ARRAY_SIZE(pcnoc_s_7_links), 693 .links = pcnoc_s_7_links, 694 }; 695 696 static const u16 mm_int_0_links[] = { 697 QNOC_SNOC_MM_INT_BIMC 698 }; 699 700 static struct qcom_icc_node mm_int_0 = { 701 .name = "mm_int_0", 702 .id = QNOC_SNOC_MM_INT_0, 703 .buswidth = 16, 704 .mas_rpm_id = 79, 705 .slv_rpm_id = 108, 706 .qos.ap_owned = true, 707 .qos.qos_mode = NOC_QOS_MODE_INVALID, 708 .num_links = ARRAY_SIZE(mm_int_0_links), 709 .links = mm_int_0_links, 710 .ab_coeff = 167, 711 }; 712 713 static const u16 mm_int_1_links[] = { 714 QNOC_SNOC_MM_INT_BIMC 715 }; 716 717 static struct qcom_icc_node mm_int_1 = { 718 .name = "mm_int_1", 719 .id = QNOC_SNOC_MM_INT_1, 720 .buswidth = 16, 721 .mas_rpm_id = 80, 722 .slv_rpm_id = 109, 723 .qos.ap_owned = true, 724 .qos.qos_mode = NOC_QOS_MODE_INVALID, 725 .num_links = ARRAY_SIZE(mm_int_1_links), 726 .links = mm_int_1_links, 727 .ab_coeff = 167, 728 }; 729 730 static const u16 mm_int_2_links[] = { 731 QNOC_SNOC_INT_0 732 }; 733 734 static struct qcom_icc_node mm_int_2 = { 735 .name = "mm_int_2", 736 .id = QNOC_SNOC_MM_INT_2, 737 .buswidth = 16, 738 .mas_rpm_id = 81, 739 .slv_rpm_id = 110, 740 .qos.ap_owned = true, 741 .qos.qos_mode = NOC_QOS_MODE_INVALID, 742 .num_links = ARRAY_SIZE(mm_int_2_links), 743 .links = mm_int_2_links, 744 .ab_coeff = 167, 745 }; 746 747 static const u16 mm_int_bimc_links[] = { 748 QNOC_SNOC_BIMC_1_SLV 749 }; 750 751 static struct qcom_icc_node mm_int_bimc = { 752 .name = "mm_int_bimc", 753 .id = QNOC_SNOC_MM_INT_BIMC, 754 .buswidth = 16, 755 .mas_rpm_id = 82, 756 .slv_rpm_id = 111, 757 .qos.ap_owned = true, 758 .qos.qos_mode = NOC_QOS_MODE_INVALID, 759 .num_links = ARRAY_SIZE(mm_int_bimc_links), 760 .links = mm_int_bimc_links, 761 .ab_coeff = 167, 762 }; 763 764 static const u16 qdss_int_links[] = { 765 QNOC_SNOC_INT_0, 766 QNOC_SNOC_INT_BIMC 767 }; 768 769 static struct qcom_icc_node qdss_int = { 770 .name = "qdss_int", 771 .id = QNOC_SNOC_QDSS_INT, 772 .buswidth = 8, 773 .mas_rpm_id = 98, 774 .slv_rpm_id = 128, 775 .qos.ap_owned = true, 776 .qos.qos_mode = NOC_QOS_MODE_INVALID, 777 .num_links = ARRAY_SIZE(qdss_int_links), 778 .links = qdss_int_links, 779 }; 780 781 static const u16 snoc_int_0_links[] = { 782 QNOC_SLAVE_SYSTEM_IMEM, 783 QNOC_SLAVE_QDSS_STM, 784 QNOC_SNOC_PNOC_SLV 785 }; 786 787 static struct qcom_icc_node snoc_int_0 = { 788 .name = "snoc_int_0", 789 .id = QNOC_SNOC_INT_0, 790 .buswidth = 8, 791 .mas_rpm_id = 99, 792 .slv_rpm_id = 130, 793 .num_links = ARRAY_SIZE(snoc_int_0_links), 794 .links = snoc_int_0_links, 795 }; 796 797 static const u16 snoc_int_1_links[] = { 798 QNOC_SLAVE_CATS_128, 799 QNOC_SLAVE_APPSS, 800 QNOC_SLAVE_OCMEM_64 801 }; 802 803 static struct qcom_icc_node snoc_int_1 = { 804 .name = "snoc_int_1", 805 .id = QNOC_SNOC_INT_1, 806 .buswidth = 8, 807 .mas_rpm_id = 100, 808 .slv_rpm_id = 131, 809 .qos.ap_owned = true, 810 .qos.qos_mode = NOC_QOS_MODE_INVALID, 811 .num_links = ARRAY_SIZE(snoc_int_1_links), 812 .links = snoc_int_1_links, 813 }; 814 815 static const u16 snoc_int_bimc_links[] = { 816 QNOC_SNOC_BIMC_0_SLV 817 }; 818 819 static struct qcom_icc_node snoc_int_bimc = { 820 .name = "snoc_int_bimc", 821 .id = QNOC_SNOC_INT_BIMC, 822 .buswidth = 8, 823 .mas_rpm_id = 101, 824 .slv_rpm_id = 132, 825 .num_links = ARRAY_SIZE(snoc_int_bimc_links), 826 .links = snoc_int_bimc_links, 827 }; 828 829 static struct qcom_icc_node slv_ebi = { 830 .name = "slv_ebi", 831 .id = QNOC_SLAVE_EBI_CH0, 832 .buswidth = 8, 833 .mas_rpm_id = -1, 834 .slv_rpm_id = 0, 835 }; 836 837 static const u16 slv_bimc_snoc_links[] = { 838 QNOC_BIMC_SNOC_MAS 839 }; 840 841 static struct qcom_icc_node slv_bimc_snoc = { 842 .name = "slv_bimc_snoc", 843 .id = QNOC_BIMC_SNOC_SLV, 844 .buswidth = 8, 845 .mas_rpm_id = -1, 846 .slv_rpm_id = 2, 847 .num_links = ARRAY_SIZE(slv_bimc_snoc_links), 848 .links = slv_bimc_snoc_links, 849 }; 850 851 static struct qcom_icc_node slv_tcsr = { 852 .name = "slv_tcsr", 853 .id = QNOC_SLAVE_TCSR, 854 .buswidth = 4, 855 .mas_rpm_id = -1, 856 .slv_rpm_id = 50, 857 }; 858 859 static struct qcom_icc_node slv_sdcc_1 = { 860 .name = "slv_sdcc_1", 861 .id = QNOC_SLAVE_SDCC_1, 862 .buswidth = 4, 863 .mas_rpm_id = -1, 864 .slv_rpm_id = 31, 865 }; 866 867 static struct qcom_icc_node slv_blsp_1 = { 868 .name = "slv_blsp_1", 869 .id = QNOC_SLAVE_BLSP_1, 870 .buswidth = 4, 871 .mas_rpm_id = -1, 872 .slv_rpm_id = 39, 873 }; 874 875 static struct qcom_icc_node slv_crypto_0_cfg = { 876 .name = "slv_crypto_0_cfg", 877 .id = QNOC_SLAVE_CRYPTO_0_CFG, 878 .buswidth = 4, 879 .mas_rpm_id = -1, 880 .slv_rpm_id = 52, 881 .qos.ap_owned = true, 882 .qos.qos_mode = NOC_QOS_MODE_INVALID, 883 }; 884 885 static struct qcom_icc_node slv_message_ram = { 886 .name = "slv_message_ram", 887 .id = QNOC_SLAVE_MESSAGE_RAM, 888 .buswidth = 4, 889 .mas_rpm_id = -1, 890 .slv_rpm_id = 55, 891 }; 892 893 static struct qcom_icc_node slv_pdm = { 894 .name = "slv_pdm", 895 .id = QNOC_SLAVE_PDM, 896 .buswidth = 4, 897 .mas_rpm_id = -1, 898 .slv_rpm_id = 41, 899 }; 900 901 static struct qcom_icc_node slv_prng = { 902 .name = "slv_prng", 903 .id = QNOC_SLAVE_PRNG, 904 .buswidth = 4, 905 .mas_rpm_id = -1, 906 .slv_rpm_id = 44, 907 .qos.ap_owned = true, 908 .qos.qos_mode = NOC_QOS_MODE_INVALID, 909 }; 910 911 static struct qcom_icc_node slv_usb_hs = { 912 .name = "slv_usb_hs", 913 .id = QNOC_SLAVE_USB_HS, 914 .buswidth = 4, 915 .mas_rpm_id = -1, 916 .slv_rpm_id = 40, 917 }; 918 919 static struct qcom_icc_node slv_qpic = { 920 .name = "slv_qpic", 921 .id = QNOC_SLAVE_QPIC, 922 .buswidth = 4, 923 .mas_rpm_id = -1, 924 .slv_rpm_id = 80, 925 }; 926 927 static struct qcom_icc_node slv_spdm = { 928 .name = "slv_spdm", 929 .id = QNOC_SLAVE_SPDM, 930 .buswidth = 4, 931 .mas_rpm_id = -1, 932 .slv_rpm_id = 60, 933 }; 934 935 static struct qcom_icc_node slv_sdcc_2 = { 936 .name = "slv_sdcc_2", 937 .id = QNOC_SLAVE_SDCC_2, 938 .buswidth = 4, 939 .mas_rpm_id = -1, 940 .slv_rpm_id = 33, 941 }; 942 943 static struct qcom_icc_node slv_audio = { 944 .name = "slv_audio", 945 .id = QNOC_SLAVE_AUDIO, 946 .buswidth = 4, 947 .mas_rpm_id = -1, 948 .slv_rpm_id = 105, 949 }; 950 951 static struct qcom_icc_node slv_dehr_cfg = { 952 .name = "slv_dehr_cfg", 953 .id = QNOC_SLAVE_DEHR_CFG, 954 .buswidth = 4, 955 .mas_rpm_id = -1, 956 .slv_rpm_id = 61, 957 }; 958 959 static struct qcom_icc_node slv_snoc_cfg = { 960 .name = "slv_snoc_cfg", 961 .id = QNOC_SLAVE_SNOC_CFG, 962 .buswidth = 4, 963 .mas_rpm_id = -1, 964 .slv_rpm_id = 70, 965 }; 966 967 static struct qcom_icc_node slv_qdss_cfg = { 968 .name = "slv_qdss_cfg", 969 .id = QNOC_SLAVE_QDSS_CFG, 970 .buswidth = 4, 971 .mas_rpm_id = -1, 972 .slv_rpm_id = 63, 973 }; 974 975 static struct qcom_icc_node slv_usb_phy = { 976 .name = "slv_usb_phy", 977 .id = QNOC_SLAVE_USB_PHYS_CFG, 978 .buswidth = 4, 979 .mas_rpm_id = -1, 980 .slv_rpm_id = 95, 981 }; 982 983 static struct qcom_icc_node slv_camera_ss_cfg = { 984 .name = "slv_camera_ss_cfg", 985 .id = QNOC_SLAVE_CAMERA_CFG, 986 .buswidth = 4, 987 .mas_rpm_id = -1, 988 .slv_rpm_id = 3, 989 .qos.ap_owned = true, 990 .qos.qos_mode = NOC_QOS_MODE_INVALID, 991 }; 992 993 static struct qcom_icc_node slv_disp_ss_cfg = { 994 .name = "slv_disp_ss_cfg", 995 .id = QNOC_SLAVE_DISPLAY_CFG, 996 .buswidth = 4, 997 .mas_rpm_id = -1, 998 .slv_rpm_id = 4, 999 .qos.ap_owned = true, 1000 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1001 }; 1002 1003 static struct qcom_icc_node slv_venus_cfg = { 1004 .name = "slv_venus_cfg", 1005 .id = QNOC_SLAVE_VENUS_CFG, 1006 .buswidth = 4, 1007 .mas_rpm_id = -1, 1008 .slv_rpm_id = 10, 1009 .qos.ap_owned = true, 1010 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1011 }; 1012 1013 static struct qcom_icc_node slv_tlmm = { 1014 .name = "slv_tlmm", 1015 .id = QNOC_SLAVE_TLMM, 1016 .buswidth = 4, 1017 .mas_rpm_id = -1, 1018 .slv_rpm_id = 51, 1019 }; 1020 1021 static struct qcom_icc_node slv_gpu_cfg = { 1022 .name = "slv_gpu_cfg", 1023 .id = QNOC_SLAVE_GRAPHICS_3D_CFG, 1024 .buswidth = 4, 1025 .mas_rpm_id = -1, 1026 .slv_rpm_id = 11, 1027 .qos.ap_owned = true, 1028 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1029 }; 1030 1031 static struct qcom_icc_node slv_imem_cfg = { 1032 .name = "slv_imem_cfg", 1033 .id = QNOC_SLAVE_IMEM_CFG, 1034 .buswidth = 4, 1035 .mas_rpm_id = -1, 1036 .slv_rpm_id = 54, 1037 }; 1038 1039 static struct qcom_icc_node slv_bimc_cfg = { 1040 .name = "slv_bimc_cfg", 1041 .id = QNOC_SLAVE_BIMC_CFG, 1042 .buswidth = 4, 1043 .mas_rpm_id = -1, 1044 .slv_rpm_id = 56, 1045 }; 1046 1047 static struct qcom_icc_node slv_pmic_arb = { 1048 .name = "slv_pmic_arb", 1049 .id = QNOC_SLAVE_PMIC_ARB, 1050 .buswidth = 4, 1051 .mas_rpm_id = -1, 1052 .slv_rpm_id = 59, 1053 }; 1054 1055 static struct qcom_icc_node slv_tcu = { 1056 .name = "slv_tcu", 1057 .id = QNOC_SLAVE_TCU, 1058 .buswidth = 8, 1059 .mas_rpm_id = -1, 1060 .slv_rpm_id = 133, 1061 .qos.ap_owned = true, 1062 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1063 }; 1064 1065 static const u16 slv_pcnoc_snoc_links[] = { 1066 QNOC_PNOC_SNOC_MAS 1067 }; 1068 1069 static struct qcom_icc_node slv_pcnoc_snoc = { 1070 .name = "slv_pcnoc_snoc", 1071 .id = QNOC_PNOC_SNOC_SLV, 1072 .buswidth = 8, 1073 .mas_rpm_id = -1, 1074 .slv_rpm_id = 45, 1075 .num_links = ARRAY_SIZE(slv_pcnoc_snoc_links), 1076 .links = slv_pcnoc_snoc_links, 1077 }; 1078 1079 static struct qcom_icc_node slv_kpss_ahb = { 1080 .name = "slv_kpss_ahb", 1081 .id = QNOC_SLAVE_APPSS, 1082 .buswidth = 4, 1083 .mas_rpm_id = -1, 1084 .slv_rpm_id = 20, 1085 .qos.ap_owned = true, 1086 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1087 }; 1088 1089 static const u16 slv_snoc_bimc_0_links[] = { 1090 QNOC_SNOC_BIMC_0_MAS 1091 }; 1092 1093 static struct qcom_icc_node slv_snoc_bimc_0 = { 1094 .name = "slv_snoc_bimc_0", 1095 .id = QNOC_SNOC_BIMC_0_SLV, 1096 .buswidth = 8, 1097 .mas_rpm_id = -1, 1098 .slv_rpm_id = 24, 1099 .num_links = ARRAY_SIZE(slv_snoc_bimc_0_links), 1100 .links = slv_snoc_bimc_0_links, 1101 }; 1102 1103 static const u16 slv_snoc_bimc_1_links[] = { 1104 QNOC_SNOC_BIMC_1_MAS 1105 }; 1106 1107 static struct qcom_icc_node slv_snoc_bimc_1 = { 1108 .name = "slv_snoc_bimc_1", 1109 .id = QNOC_SNOC_BIMC_1_SLV, 1110 .buswidth = 16, 1111 .mas_rpm_id = -1, 1112 .slv_rpm_id = 104, 1113 .qos.ap_owned = true, 1114 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1115 .num_links = ARRAY_SIZE(slv_snoc_bimc_1_links), 1116 .links = slv_snoc_bimc_1_links, 1117 }; 1118 1119 static struct qcom_icc_node slv_imem = { 1120 .name = "slv_imem", 1121 .id = QNOC_SLAVE_SYSTEM_IMEM, 1122 .buswidth = 8, 1123 .mas_rpm_id = -1, 1124 .slv_rpm_id = 26, 1125 }; 1126 1127 static const u16 slv_snoc_pcnoc_links[] = { 1128 QNOC_SNOC_PNOC_MAS 1129 }; 1130 1131 static struct qcom_icc_node slv_snoc_pcnoc = { 1132 .name = "slv_snoc_pcnoc", 1133 .id = QNOC_SNOC_PNOC_SLV, 1134 .buswidth = 8, 1135 .mas_rpm_id = -1, 1136 .slv_rpm_id = 28, 1137 .num_links = ARRAY_SIZE(slv_snoc_pcnoc_links), 1138 .links = slv_snoc_pcnoc_links, 1139 }; 1140 1141 static struct qcom_icc_node slv_qdss_stm = { 1142 .name = "slv_qdss_stm", 1143 .id = QNOC_SLAVE_QDSS_STM, 1144 .buswidth = 4, 1145 .mas_rpm_id = -1, 1146 .slv_rpm_id = 30, 1147 }; 1148 1149 static struct qcom_icc_node slv_cats_0 = { 1150 .name = "slv_cats_0", 1151 .id = QNOC_SLAVE_CATS_128, 1152 .buswidth = 16, 1153 .mas_rpm_id = -1, 1154 .slv_rpm_id = 106, 1155 .qos.ap_owned = true, 1156 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1157 }; 1158 1159 static struct qcom_icc_node slv_cats_1 = { 1160 .name = "slv_cats_1", 1161 .id = QNOC_SLAVE_OCMEM_64, 1162 .buswidth = 8, 1163 .mas_rpm_id = -1, 1164 .slv_rpm_id = 107, 1165 .qos.ap_owned = true, 1166 .qos.qos_mode = NOC_QOS_MODE_INVALID, 1167 }; 1168 1169 static struct qcom_icc_node * const msm8909_bimc_nodes[] = { 1170 [MAS_APPS_PROC] = &mas_apps_proc, 1171 [MAS_OXILI] = &mas_oxili, 1172 [MAS_SNOC_BIMC_0] = &mas_snoc_bimc_0, 1173 [MAS_SNOC_BIMC_1] = &mas_snoc_bimc_1, 1174 [MAS_TCU_0] = &mas_tcu_0, 1175 [MAS_TCU_1] = &mas_tcu_1, 1176 [SLV_EBI] = &slv_ebi, 1177 [SLV_BIMC_SNOC] = &slv_bimc_snoc, 1178 }; 1179 1180 static const struct regmap_config msm8909_bimc_regmap_config = { 1181 .reg_bits = 32, 1182 .reg_stride = 4, 1183 .val_bits = 32, 1184 .max_register = 0x62000, 1185 .fast_io = true, 1186 }; 1187 1188 static const struct qcom_icc_desc msm8909_bimc = { 1189 .type = QCOM_ICC_BIMC, 1190 .nodes = msm8909_bimc_nodes, 1191 .num_nodes = ARRAY_SIZE(msm8909_bimc_nodes), 1192 .bus_clk_desc = &bimc_clk, 1193 .regmap_cfg = &msm8909_bimc_regmap_config, 1194 .qos_offset = 0x8000, 1195 .ab_coeff = 154, 1196 }; 1197 1198 static struct qcom_icc_node * const msm8909_pcnoc_nodes[] = { 1199 [MAS_AUDIO] = &mas_audio, 1200 [MAS_SPDM] = &mas_spdm, 1201 [MAS_DEHR] = &mas_dehr, 1202 [MAS_QPIC] = &mas_qpic, 1203 [MAS_BLSP_1] = &mas_blsp_1, 1204 [MAS_USB_HS] = &mas_usb_hs, 1205 [MAS_CRYPTO] = &mas_crypto, 1206 [MAS_SDCC_1] = &mas_sdcc_1, 1207 [MAS_SDCC_2] = &mas_sdcc_2, 1208 [MAS_SNOC_PCNOC] = &mas_snoc_pcnoc, 1209 [PCNOC_M_0] = &pcnoc_m_0, 1210 [PCNOC_M_1] = &pcnoc_m_1, 1211 [PCNOC_INT_0] = &pcnoc_int_0, 1212 [PCNOC_INT_1] = &pcnoc_int_1, 1213 [PCNOC_S_0] = &pcnoc_s_0, 1214 [PCNOC_S_1] = &pcnoc_s_1, 1215 [PCNOC_S_2] = &pcnoc_s_2, 1216 [PCNOC_S_3] = &pcnoc_s_3, 1217 [PCNOC_S_4] = &pcnoc_s_4, 1218 [PCNOC_S_5] = &pcnoc_s_5, 1219 [PCNOC_S_7] = &pcnoc_s_7, 1220 [SLV_TCSR] = &slv_tcsr, 1221 [SLV_SDCC_1] = &slv_sdcc_1, 1222 [SLV_BLSP_1] = &slv_blsp_1, 1223 [SLV_CRYPTO_0_CFG] = &slv_crypto_0_cfg, 1224 [SLV_MESSAGE_RAM] = &slv_message_ram, 1225 [SLV_PDM] = &slv_pdm, 1226 [SLV_PRNG] = &slv_prng, 1227 [SLV_USB_HS] = &slv_usb_hs, 1228 [SLV_QPIC] = &slv_qpic, 1229 [SLV_SPDM] = &slv_spdm, 1230 [SLV_SDCC_2] = &slv_sdcc_2, 1231 [SLV_AUDIO] = &slv_audio, 1232 [SLV_DEHR_CFG] = &slv_dehr_cfg, 1233 [SLV_SNOC_CFG] = &slv_snoc_cfg, 1234 [SLV_QDSS_CFG] = &slv_qdss_cfg, 1235 [SLV_USB_PHY] = &slv_usb_phy, 1236 [SLV_CAMERA_SS_CFG] = &slv_camera_ss_cfg, 1237 [SLV_DISP_SS_CFG] = &slv_disp_ss_cfg, 1238 [SLV_VENUS_CFG] = &slv_venus_cfg, 1239 [SLV_TLMM] = &slv_tlmm, 1240 [SLV_GPU_CFG] = &slv_gpu_cfg, 1241 [SLV_IMEM_CFG] = &slv_imem_cfg, 1242 [SLV_BIMC_CFG] = &slv_bimc_cfg, 1243 [SLV_PMIC_ARB] = &slv_pmic_arb, 1244 [SLV_TCU] = &slv_tcu, 1245 [SLV_PCNOC_SNOC] = &slv_pcnoc_snoc, 1246 }; 1247 1248 static const struct regmap_config msm8909_pcnoc_regmap_config = { 1249 .reg_bits = 32, 1250 .reg_stride = 4, 1251 .val_bits = 32, 1252 .max_register = 0x11000, 1253 .fast_io = true, 1254 }; 1255 1256 static const struct qcom_icc_desc msm8909_pcnoc = { 1257 .type = QCOM_ICC_NOC, 1258 .nodes = msm8909_pcnoc_nodes, 1259 .num_nodes = ARRAY_SIZE(msm8909_pcnoc_nodes), 1260 .bus_clk_desc = &bus_0_clk, 1261 .regmap_cfg = &msm8909_pcnoc_regmap_config, 1262 .qos_offset = 0x7000, 1263 }; 1264 1265 static struct qcom_icc_node * const msm8909_snoc_nodes[] = { 1266 [MAS_QDSS_BAM] = &mas_qdss_bam, 1267 [MAS_BIMC_SNOC] = &mas_bimc_snoc, 1268 [MAS_MDP] = &mas_mdp, 1269 [MAS_PCNOC_SNOC] = &mas_pcnoc_snoc, 1270 [MAS_VENUS] = &mas_venus, 1271 [MAS_VFE] = &mas_vfe, 1272 [MAS_QDSS_ETR] = &mas_qdss_etr, 1273 [MM_INT_0] = &mm_int_0, 1274 [MM_INT_1] = &mm_int_1, 1275 [MM_INT_2] = &mm_int_2, 1276 [MM_INT_BIMC] = &mm_int_bimc, 1277 [QDSS_INT] = &qdss_int, 1278 [SNOC_INT_0] = &snoc_int_0, 1279 [SNOC_INT_1] = &snoc_int_1, 1280 [SNOC_INT_BIMC] = &snoc_int_bimc, 1281 [SLV_KPSS_AHB] = &slv_kpss_ahb, 1282 [SLV_SNOC_BIMC_0] = &slv_snoc_bimc_0, 1283 [SLV_SNOC_BIMC_1] = &slv_snoc_bimc_1, 1284 [SLV_IMEM] = &slv_imem, 1285 [SLV_SNOC_PCNOC] = &slv_snoc_pcnoc, 1286 [SLV_QDSS_STM] = &slv_qdss_stm, 1287 [SLV_CATS_0] = &slv_cats_0, 1288 [SLV_CATS_1] = &slv_cats_1, 1289 }; 1290 1291 static const struct regmap_config msm8909_snoc_regmap_config = { 1292 .reg_bits = 32, 1293 .reg_stride = 4, 1294 .val_bits = 32, 1295 .max_register = 0x13000, 1296 .fast_io = true, 1297 }; 1298 1299 static const struct qcom_icc_desc msm8909_snoc = { 1300 .type = QCOM_ICC_NOC, 1301 .nodes = msm8909_snoc_nodes, 1302 .num_nodes = ARRAY_SIZE(msm8909_snoc_nodes), 1303 .bus_clk_desc = &bus_1_clk, 1304 .regmap_cfg = &msm8909_snoc_regmap_config, 1305 .qos_offset = 0x7000, 1306 }; 1307 1308 static const struct of_device_id msm8909_noc_of_match[] = { 1309 { .compatible = "qcom,msm8909-bimc", .data = &msm8909_bimc }, 1310 { .compatible = "qcom,msm8909-pcnoc", .data = &msm8909_pcnoc }, 1311 { .compatible = "qcom,msm8909-snoc", .data = &msm8909_snoc }, 1312 { } 1313 }; 1314 MODULE_DEVICE_TABLE(of, msm8909_noc_of_match); 1315 1316 static struct platform_driver msm8909_noc_driver = { 1317 .probe = qnoc_probe, 1318 .remove = qnoc_remove, 1319 .driver = { 1320 .name = "qnoc-msm8909", 1321 .of_match_table = msm8909_noc_of_match, 1322 .sync_state = icc_sync_state, 1323 }, 1324 }; 1325 module_platform_driver(msm8909_noc_driver); 1326 1327 MODULE_DESCRIPTION("Qualcomm MSM8909 NoC driver"); 1328 MODULE_LICENSE("GPL"); 1329