1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 * 5 */ 6 7 #include <linux/device.h> 8 #include <linux/interconnect.h> 9 #include <linux/interconnect-provider.h> 10 #include <linux/module.h> 11 #include <linux/of_platform.h> 12 #include <dt-bindings/interconnect/qcom,kaanapali-rpmh.h> 13 14 #include "bcm-voter.h" 15 #include "icc-rpmh.h" 16 17 static struct qcom_icc_node qup0_core_slave = { 18 .name = "qup0_core_slave", 19 .channels = 1, 20 .buswidth = 4, 21 }; 22 23 static struct qcom_icc_node qup1_core_slave = { 24 .name = "qup1_core_slave", 25 .channels = 1, 26 .buswidth = 4, 27 }; 28 29 static struct qcom_icc_node qup2_core_slave = { 30 .name = "qup2_core_slave", 31 .channels = 1, 32 .buswidth = 4, 33 }; 34 35 static struct qcom_icc_node qup3_core_slave = { 36 .name = "qup3_core_slave", 37 .channels = 1, 38 .buswidth = 4, 39 }; 40 41 static struct qcom_icc_node qup4_core_slave = { 42 .name = "qup4_core_slave", 43 .channels = 1, 44 .buswidth = 4, 45 }; 46 47 static struct qcom_icc_node qhs_ahb2phy0 = { 48 .name = "qhs_ahb2phy0", 49 .channels = 1, 50 .buswidth = 4, 51 }; 52 53 static struct qcom_icc_node qhs_ahb2phy1 = { 54 .name = "qhs_ahb2phy1", 55 .channels = 1, 56 .buswidth = 4, 57 }; 58 59 static struct qcom_icc_node qhs_camera_cfg = { 60 .name = "qhs_camera_cfg", 61 .channels = 1, 62 .buswidth = 4, 63 }; 64 65 static struct qcom_icc_node qhs_clk_ctl = { 66 .name = "qhs_clk_ctl", 67 .channels = 1, 68 .buswidth = 4, 69 }; 70 71 static struct qcom_icc_node qhs_crypto0_cfg = { 72 .name = "qhs_crypto0_cfg", 73 .channels = 1, 74 .buswidth = 4, 75 }; 76 77 static struct qcom_icc_node qhs_display_cfg = { 78 .name = "qhs_display_cfg", 79 .channels = 1, 80 .buswidth = 4, 81 }; 82 83 static struct qcom_icc_node qhs_eva_cfg = { 84 .name = "qhs_eva_cfg", 85 .channels = 1, 86 .buswidth = 4, 87 }; 88 89 static struct qcom_icc_node qhs_gpuss_cfg = { 90 .name = "qhs_gpuss_cfg", 91 .channels = 1, 92 .buswidth = 8, 93 }; 94 95 static struct qcom_icc_node qhs_i2c = { 96 .name = "qhs_i2c", 97 .channels = 1, 98 .buswidth = 4, 99 }; 100 101 static struct qcom_icc_node qhs_i3c_ibi0_cfg = { 102 .name = "qhs_i3c_ibi0_cfg", 103 .channels = 1, 104 .buswidth = 4, 105 }; 106 107 static struct qcom_icc_node qhs_i3c_ibi1_cfg = { 108 .name = "qhs_i3c_ibi1_cfg", 109 .channels = 1, 110 .buswidth = 4, 111 }; 112 113 static struct qcom_icc_node qhs_imem_cfg = { 114 .name = "qhs_imem_cfg", 115 .channels = 1, 116 .buswidth = 4, 117 }; 118 119 static struct qcom_icc_node qhs_ipc_router = { 120 .name = "qhs_ipc_router", 121 .channels = 4, 122 .buswidth = 4, 123 }; 124 125 static struct qcom_icc_node qhs_mss_cfg = { 126 .name = "qhs_mss_cfg", 127 .channels = 1, 128 .buswidth = 4, 129 }; 130 131 static struct qcom_icc_node qhs_pcie_cfg = { 132 .name = "qhs_pcie_cfg", 133 .channels = 1, 134 .buswidth = 4, 135 }; 136 137 static struct qcom_icc_node qhs_prng = { 138 .name = "qhs_prng", 139 .channels = 1, 140 .buswidth = 4, 141 }; 142 143 static struct qcom_icc_node qhs_qdss_cfg = { 144 .name = "qhs_qdss_cfg", 145 .channels = 1, 146 .buswidth = 4, 147 }; 148 149 static struct qcom_icc_node qhs_qspi = { 150 .name = "qhs_qspi", 151 .channels = 1, 152 .buswidth = 4, 153 }; 154 155 static struct qcom_icc_node qhs_qup1 = { 156 .name = "qhs_qup1", 157 .channels = 1, 158 .buswidth = 4, 159 }; 160 161 static struct qcom_icc_node qhs_qup2 = { 162 .name = "qhs_qup2", 163 .channels = 1, 164 .buswidth = 4, 165 }; 166 167 static struct qcom_icc_node qhs_qup3 = { 168 .name = "qhs_qup3", 169 .channels = 1, 170 .buswidth = 4, 171 }; 172 173 static struct qcom_icc_node qhs_qup4 = { 174 .name = "qhs_qup4", 175 .channels = 1, 176 .buswidth = 4, 177 }; 178 179 static struct qcom_icc_node qhs_sdc2 = { 180 .name = "qhs_sdc2", 181 .channels = 1, 182 .buswidth = 4, 183 }; 184 185 static struct qcom_icc_node qhs_sdc4 = { 186 .name = "qhs_sdc4", 187 .channels = 1, 188 .buswidth = 4, 189 }; 190 191 static struct qcom_icc_node qhs_spss_cfg = { 192 .name = "qhs_spss_cfg", 193 .channels = 1, 194 .buswidth = 4, 195 }; 196 197 static struct qcom_icc_node qhs_tcsr = { 198 .name = "qhs_tcsr", 199 .channels = 1, 200 .buswidth = 4, 201 }; 202 203 static struct qcom_icc_node qhs_tlmm = { 204 .name = "qhs_tlmm", 205 .channels = 1, 206 .buswidth = 4, 207 }; 208 209 static struct qcom_icc_node qhs_ufs_mem_cfg = { 210 .name = "qhs_ufs_mem_cfg", 211 .channels = 1, 212 .buswidth = 4, 213 }; 214 215 static struct qcom_icc_node qhs_usb3 = { 216 .name = "qhs_usb3", 217 .channels = 1, 218 .buswidth = 4, 219 }; 220 221 static struct qcom_icc_node qhs_venus_cfg = { 222 .name = "qhs_venus_cfg", 223 .channels = 1, 224 .buswidth = 4, 225 }; 226 227 static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 228 .name = "qhs_vsense_ctrl_cfg", 229 .channels = 1, 230 .buswidth = 4, 231 }; 232 233 static struct qcom_icc_node xs_qdss_stm = { 234 .name = "xs_qdss_stm", 235 .channels = 1, 236 .buswidth = 4, 237 }; 238 239 static struct qcom_icc_node xs_sys_tcu_cfg = { 240 .name = "xs_sys_tcu_cfg", 241 .channels = 1, 242 .buswidth = 8, 243 }; 244 245 static struct qcom_icc_node qhs_aoss = { 246 .name = "qhs_aoss", 247 .channels = 1, 248 .buswidth = 4, 249 }; 250 251 static struct qcom_icc_node qhs_ipa = { 252 .name = "qhs_ipa", 253 .channels = 1, 254 .buswidth = 4, 255 }; 256 257 static struct qcom_icc_node qhs_ipc_router_fence = { 258 .name = "qhs_ipc_router_fence", 259 .channels = 1, 260 .buswidth = 4, 261 }; 262 263 static struct qcom_icc_node qhs_soccp = { 264 .name = "qhs_soccp", 265 .channels = 1, 266 .buswidth = 4, 267 }; 268 269 static struct qcom_icc_node qhs_tme_cfg = { 270 .name = "qhs_tme_cfg", 271 .channels = 1, 272 .buswidth = 4, 273 }; 274 275 static struct qcom_icc_node qns_apss = { 276 .name = "qns_apss", 277 .channels = 1, 278 .buswidth = 8, 279 }; 280 281 static struct qcom_icc_node qss_ddrss_cfg = { 282 .name = "qss_ddrss_cfg", 283 .channels = 1, 284 .buswidth = 4, 285 }; 286 287 static struct qcom_icc_node qxs_boot_imem = { 288 .name = "qxs_boot_imem", 289 .channels = 1, 290 .buswidth = 16, 291 }; 292 293 static struct qcom_icc_node qxs_imem = { 294 .name = "qxs_imem", 295 .channels = 1, 296 .buswidth = 8, 297 }; 298 299 static struct qcom_icc_node xs_pcie = { 300 .name = "xs_pcie", 301 .channels = 1, 302 .buswidth = 16, 303 }; 304 305 static struct qcom_icc_node ebi = { 306 .name = "ebi", 307 .channels = 4, 308 .buswidth = 4, 309 }; 310 311 static struct qcom_icc_node srvc_mnoc = { 312 .name = "srvc_mnoc", 313 .channels = 1, 314 .buswidth = 4, 315 }; 316 317 static struct qcom_icc_node srvc_pcie_aggre_noc = { 318 .name = "srvc_pcie_aggre_noc", 319 .channels = 1, 320 .buswidth = 4, 321 }; 322 323 static struct qcom_icc_node qup0_core_master = { 324 .name = "qup0_core_master", 325 .channels = 1, 326 .buswidth = 4, 327 .num_links = 1, 328 .link_nodes = { &qup0_core_slave }, 329 }; 330 331 static struct qcom_icc_node qup1_core_master = { 332 .name = "qup1_core_master", 333 .channels = 1, 334 .buswidth = 4, 335 .num_links = 1, 336 .link_nodes = { &qup1_core_slave }, 337 }; 338 339 static struct qcom_icc_node qup2_core_master = { 340 .name = "qup2_core_master", 341 .channels = 1, 342 .buswidth = 4, 343 .num_links = 1, 344 .link_nodes = { &qup2_core_slave }, 345 }; 346 347 static struct qcom_icc_node qup3_core_master = { 348 .name = "qup3_core_master", 349 .channels = 1, 350 .buswidth = 4, 351 .num_links = 1, 352 .link_nodes = { &qup3_core_slave }, 353 }; 354 355 static struct qcom_icc_node qup4_core_master = { 356 .name = "qup4_core_master", 357 .channels = 1, 358 .buswidth = 4, 359 .num_links = 1, 360 .link_nodes = { &qup4_core_slave }, 361 }; 362 363 static struct qcom_icc_node qnm_gemnoc_pcie = { 364 .name = "qnm_gemnoc_pcie", 365 .channels = 1, 366 .buswidth = 8, 367 .num_links = 1, 368 .link_nodes = { &xs_pcie }, 369 }; 370 371 static struct qcom_icc_node llcc_mc = { 372 .name = "llcc_mc", 373 .channels = 4, 374 .buswidth = 4, 375 .num_links = 1, 376 .link_nodes = { &ebi }, 377 }; 378 379 static struct qcom_icc_node qsm_mnoc_cfg = { 380 .name = "qsm_mnoc_cfg", 381 .channels = 1, 382 .buswidth = 4, 383 .num_links = 1, 384 .link_nodes = { &srvc_mnoc }, 385 }; 386 387 static struct qcom_icc_node qsm_pcie_anoc_cfg = { 388 .name = "qsm_pcie_anoc_cfg", 389 .channels = 1, 390 .buswidth = 4, 391 .num_links = 1, 392 .link_nodes = { &srvc_pcie_aggre_noc }, 393 }; 394 395 static struct qcom_icc_node qss_mnoc_cfg = { 396 .name = "qss_mnoc_cfg", 397 .channels = 1, 398 .buswidth = 4, 399 .num_links = 1, 400 .link_nodes = { &qsm_mnoc_cfg }, 401 }; 402 403 static struct qcom_icc_node qss_pcie_anoc_cfg = { 404 .name = "qss_pcie_anoc_cfg", 405 .channels = 1, 406 .buswidth = 4, 407 .num_links = 1, 408 .link_nodes = { &qsm_pcie_anoc_cfg }, 409 }; 410 411 static struct qcom_icc_node qns_llcc = { 412 .name = "qns_llcc", 413 .channels = 4, 414 .buswidth = 16, 415 .num_links = 1, 416 .link_nodes = { &llcc_mc }, 417 }; 418 419 static struct qcom_icc_node qns_pcie = { 420 .name = "qns_pcie", 421 .channels = 1, 422 .buswidth = 8, 423 .num_links = 1, 424 .link_nodes = { &qnm_gemnoc_pcie }, 425 }; 426 427 static struct qcom_icc_node qsm_cfg = { 428 .name = "qsm_cfg", 429 .channels = 1, 430 .buswidth = 4, 431 .num_links = 35, 432 .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, 433 &qhs_camera_cfg, &qhs_clk_ctl, 434 &qhs_crypto0_cfg, &qhs_display_cfg, 435 &qhs_eva_cfg, &qhs_gpuss_cfg, 436 &qhs_i2c, &qhs_i3c_ibi0_cfg, 437 &qhs_i3c_ibi1_cfg, &qhs_imem_cfg, 438 &qhs_ipc_router, &qhs_mss_cfg, 439 &qhs_pcie_cfg, &qhs_prng, 440 &qhs_qdss_cfg, &qhs_qspi, 441 &qhs_qup1, &qhs_qup2, 442 &qhs_qup3, &qhs_qup4, 443 &qhs_sdc2, &qhs_sdc4, 444 &qhs_spss_cfg, &qhs_tcsr, 445 &qhs_tlmm, &qhs_ufs_mem_cfg, 446 &qhs_usb3, &qhs_venus_cfg, 447 &qhs_vsense_ctrl_cfg, &qss_mnoc_cfg, 448 &qss_pcie_anoc_cfg, &xs_qdss_stm, 449 &xs_sys_tcu_cfg }, 450 }; 451 452 static struct qcom_icc_node qnm_qpace = { 453 .name = "qnm_qpace", 454 .channels = 1, 455 .buswidth = 32, 456 .qosbox = &(const struct qcom_icc_qosbox) { 457 .num_ports = 1, 458 .port_offsets = { 0x14e000 }, 459 .prio = 0, 460 .urg_fwd = 1, 461 .prio_fwd_disable = 0, 462 }, 463 .num_links = 1, 464 .link_nodes = { &qns_llcc }, 465 }; 466 467 static struct qcom_icc_node xm_gic = { 468 .name = "xm_gic", 469 .channels = 1, 470 .buswidth = 8, 471 .qosbox = &(const struct qcom_icc_qosbox) { 472 .num_ports = 1, 473 .port_offsets = { 0x145000 }, 474 .prio = 4, 475 .urg_fwd = 0, 476 .prio_fwd_disable = 1, 477 }, 478 .num_links = 1, 479 .link_nodes = { &qns_llcc }, 480 }; 481 482 static struct qcom_icc_node qss_cfg = { 483 .name = "qss_cfg", 484 .channels = 1, 485 .buswidth = 4, 486 .num_links = 1, 487 .link_nodes = { &qsm_cfg }, 488 }; 489 490 static struct qcom_icc_node qnm_gemnoc_cnoc = { 491 .name = "qnm_gemnoc_cnoc", 492 .channels = 1, 493 .buswidth = 16, 494 .num_links = 10, 495 .link_nodes = { &qhs_aoss, &qhs_ipa, 496 &qhs_ipc_router_fence, &qhs_soccp, 497 &qhs_tme_cfg, &qns_apss, 498 &qss_cfg, &qss_ddrss_cfg, 499 &qxs_boot_imem, &qxs_imem }, 500 }; 501 502 static struct qcom_icc_node qns_gem_noc_cnoc = { 503 .name = "qns_gem_noc_cnoc", 504 .channels = 1, 505 .buswidth = 16, 506 .num_links = 1, 507 .link_nodes = { &qnm_gemnoc_cnoc }, 508 }; 509 510 static struct qcom_icc_node alm_gpu_tcu = { 511 .name = "alm_gpu_tcu", 512 .channels = 1, 513 .buswidth = 8, 514 .qosbox = &(const struct qcom_icc_qosbox) { 515 .num_ports = 1, 516 .port_offsets = { 0x13d000 }, 517 .prio = 1, 518 .urg_fwd = 0, 519 .prio_fwd_disable = 1, 520 }, 521 .num_links = 2, 522 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 523 }; 524 525 static struct qcom_icc_node alm_sys_tcu = { 526 .name = "alm_sys_tcu", 527 .channels = 1, 528 .buswidth = 8, 529 .qosbox = &(const struct qcom_icc_qosbox) { 530 .num_ports = 1, 531 .port_offsets = { 0x13f000 }, 532 .prio = 6, 533 .urg_fwd = 0, 534 .prio_fwd_disable = 1, 535 }, 536 .num_links = 2, 537 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 538 }; 539 540 static struct qcom_icc_node chm_apps = { 541 .name = "chm_apps", 542 .channels = 4, 543 .buswidth = 32, 544 .num_links = 3, 545 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 546 &qns_pcie }, 547 }; 548 549 static struct qcom_icc_node qnm_gpu = { 550 .name = "qnm_gpu", 551 .channels = 2, 552 .buswidth = 32, 553 .qosbox = &(const struct qcom_icc_qosbox) { 554 .num_ports = 2, 555 .port_offsets = { 0x31000, 0xb1000 }, 556 .prio = 0, 557 .urg_fwd = 1, 558 .prio_fwd_disable = 1, 559 }, 560 .num_links = 3, 561 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 562 &qns_pcie }, 563 }; 564 565 static struct qcom_icc_node qnm_lpass_gemnoc = { 566 .name = "qnm_lpass_gemnoc", 567 .channels = 1, 568 .buswidth = 16, 569 .qosbox = &(const struct qcom_icc_qosbox) { 570 .num_ports = 1, 571 .port_offsets = { 0x141000 }, 572 .prio = 0, 573 .urg_fwd = 1, 574 .prio_fwd_disable = 0, 575 }, 576 .num_links = 3, 577 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 578 &qns_pcie }, 579 }; 580 581 static struct qcom_icc_node qnm_mdsp = { 582 .name = "qnm_mdsp", 583 .channels = 1, 584 .buswidth = 16, 585 .num_links = 3, 586 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 587 &qns_pcie }, 588 }; 589 590 static struct qcom_icc_node qnm_mnoc_hf = { 591 .name = "qnm_mnoc_hf", 592 .channels = 2, 593 .buswidth = 32, 594 .qosbox = &(const struct qcom_icc_qosbox) { 595 .num_ports = 2, 596 .port_offsets = { 0x33000, 0xb3000 }, 597 .prio = 0, 598 .urg_fwd = 1, 599 .prio_fwd_disable = 0, 600 }, 601 .num_links = 3, 602 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 603 &qns_pcie }, 604 }; 605 606 static struct qcom_icc_node qnm_mnoc_sf = { 607 .name = "qnm_mnoc_sf", 608 .channels = 2, 609 .buswidth = 32, 610 .qosbox = &(const struct qcom_icc_qosbox) { 611 .num_ports = 2, 612 .port_offsets = { 0x35000, 0xb5000 }, 613 .prio = 0, 614 .urg_fwd = 1, 615 .prio_fwd_disable = 0, 616 }, 617 .num_links = 3, 618 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 619 &qns_pcie }, 620 }; 621 622 static struct qcom_icc_node qnm_nsp_gemnoc = { 623 .name = "qnm_nsp_gemnoc", 624 .channels = 2, 625 .buswidth = 32, 626 .qosbox = &(const struct qcom_icc_qosbox) { 627 .num_ports = 2, 628 .port_offsets = { 0x37000, 0xb7000 }, 629 .prio = 0, 630 .urg_fwd = 1, 631 .prio_fwd_disable = 1, 632 }, 633 .num_links = 3, 634 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 635 &qns_pcie }, 636 }; 637 638 static struct qcom_icc_node qnm_pcie = { 639 .name = "qnm_pcie", 640 .channels = 1, 641 .buswidth = 16, 642 .qosbox = &(const struct qcom_icc_qosbox) { 643 .num_ports = 1, 644 .port_offsets = { 0x143000 }, 645 .prio = 2, 646 .urg_fwd = 1, 647 .prio_fwd_disable = 0, 648 }, 649 .num_links = 2, 650 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 651 }; 652 653 static struct qcom_icc_node qnm_snoc_sf = { 654 .name = "qnm_snoc_sf", 655 .channels = 1, 656 .buswidth = 16, 657 .qosbox = &(const struct qcom_icc_qosbox) { 658 .num_ports = 1, 659 .port_offsets = { 0x147000 }, 660 .prio = 0, 661 .urg_fwd = 1, 662 .prio_fwd_disable = 0, 663 }, 664 .num_links = 3, 665 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 666 &qns_pcie }, 667 }; 668 669 static struct qcom_icc_node qnm_wlan_q6 = { 670 .name = "qnm_wlan_q6", 671 .channels = 1, 672 .buswidth = 8, 673 .num_links = 3, 674 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 675 &qns_pcie }, 676 }; 677 678 static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = { 679 .name = "qns_lpass_ag_noc_gemnoc", 680 .channels = 1, 681 .buswidth = 16, 682 .num_links = 1, 683 .link_nodes = { &qnm_lpass_gemnoc }, 684 }; 685 686 static struct qcom_icc_node qns_mem_noc_hf = { 687 .name = "qns_mem_noc_hf", 688 .channels = 2, 689 .buswidth = 32, 690 .num_links = 1, 691 .link_nodes = { &qnm_mnoc_hf }, 692 }; 693 694 static struct qcom_icc_node qns_mem_noc_sf = { 695 .name = "qns_mem_noc_sf", 696 .channels = 2, 697 .buswidth = 32, 698 .num_links = 1, 699 .link_nodes = { &qnm_mnoc_sf }, 700 }; 701 702 static struct qcom_icc_node qns_nsp_gemnoc = { 703 .name = "qns_nsp_gemnoc", 704 .channels = 2, 705 .buswidth = 32, 706 .num_links = 1, 707 .link_nodes = { &qnm_nsp_gemnoc }, 708 }; 709 710 static struct qcom_icc_node qns_pcie_gemnoc = { 711 .name = "qns_pcie_gemnoc", 712 .channels = 1, 713 .buswidth = 16, 714 .num_links = 1, 715 .link_nodes = { &qnm_pcie }, 716 }; 717 718 static struct qcom_icc_node qns_gemnoc_sf = { 719 .name = "qns_gemnoc_sf", 720 .channels = 1, 721 .buswidth = 16, 722 .num_links = 1, 723 .link_nodes = { &qnm_snoc_sf }, 724 }; 725 726 static struct qcom_icc_node qnm_lpiaon_noc = { 727 .name = "qnm_lpiaon_noc", 728 .channels = 1, 729 .buswidth = 16, 730 .num_links = 1, 731 .link_nodes = { &qns_lpass_ag_noc_gemnoc }, 732 }; 733 734 static struct qcom_icc_node qnm_camnoc_hf = { 735 .name = "qnm_camnoc_hf", 736 .channels = 2, 737 .buswidth = 32, 738 .qosbox = &(const struct qcom_icc_qosbox) { 739 .num_ports = 2, 740 .port_offsets = { 0x2a000, 0x2b000 }, 741 .prio = 0, 742 .urg_fwd = 1, 743 .prio_fwd_disable = 0, 744 }, 745 .num_links = 1, 746 .link_nodes = { &qns_mem_noc_hf }, 747 }; 748 749 static struct qcom_icc_node qnm_camnoc_nrt_icp_sf = { 750 .name = "qnm_camnoc_nrt_icp_sf", 751 .channels = 1, 752 .buswidth = 8, 753 .qosbox = &(const struct qcom_icc_qosbox) { 754 .num_ports = 1, 755 .port_offsets = { 0x2c000 }, 756 .prio = 4, 757 .urg_fwd = 1, 758 .prio_fwd_disable = 1, 759 }, 760 .num_links = 1, 761 .link_nodes = { &qns_mem_noc_sf }, 762 }; 763 764 static struct qcom_icc_node qnm_camnoc_rt_cdm_sf = { 765 .name = "qnm_camnoc_rt_cdm_sf", 766 .channels = 1, 767 .buswidth = 8, 768 .qosbox = &(const struct qcom_icc_qosbox) { 769 .num_ports = 1, 770 .port_offsets = { 0x38000 }, 771 .prio = 2, 772 .urg_fwd = 1, 773 .prio_fwd_disable = 1, 774 }, 775 .num_links = 1, 776 .link_nodes = { &qns_mem_noc_sf }, 777 }; 778 779 static struct qcom_icc_node qnm_camnoc_sf = { 780 .name = "qnm_camnoc_sf", 781 .channels = 2, 782 .buswidth = 32, 783 .qosbox = &(const struct qcom_icc_qosbox) { 784 .num_ports = 2, 785 .port_offsets = { 0x2d000, 0x2e000 }, 786 .prio = 0, 787 .urg_fwd = 1, 788 .prio_fwd_disable = 0, 789 }, 790 .num_links = 1, 791 .link_nodes = { &qns_mem_noc_sf }, 792 }; 793 794 static struct qcom_icc_node qnm_mdp = { 795 .name = "qnm_mdp", 796 .channels = 2, 797 .buswidth = 32, 798 .qosbox = &(const struct qcom_icc_qosbox) { 799 .num_ports = 2, 800 .port_offsets = { 0x2f000, 0x30000 }, 801 .prio = 0, 802 .urg_fwd = 1, 803 .prio_fwd_disable = 0, 804 }, 805 .num_links = 1, 806 .link_nodes = { &qns_mem_noc_hf }, 807 }; 808 809 static struct qcom_icc_node qnm_mdss_dcp = { 810 .name = "qnm_mdss_dcp", 811 .channels = 1, 812 .buswidth = 8, 813 .qosbox = &(const struct qcom_icc_qosbox) { 814 .num_ports = 1, 815 .port_offsets = { 0x39000 }, 816 .prio = 0, 817 .urg_fwd = 1, 818 .prio_fwd_disable = 0, 819 }, 820 .num_links = 1, 821 .link_nodes = { &qns_mem_noc_sf }, 822 }; 823 824 static struct qcom_icc_node qnm_vapss_hcp = { 825 .name = "qnm_vapss_hcp", 826 .channels = 1, 827 .buswidth = 32, 828 .num_links = 1, 829 .link_nodes = { &qns_mem_noc_sf }, 830 }; 831 832 static struct qcom_icc_node qnm_video_cv_cpu = { 833 .name = "qnm_video_cv_cpu", 834 .channels = 1, 835 .buswidth = 8, 836 .qosbox = &(const struct qcom_icc_qosbox) { 837 .num_ports = 1, 838 .port_offsets = { 0x34000 }, 839 .prio = 4, 840 .urg_fwd = 1, 841 .prio_fwd_disable = 1, 842 }, 843 .num_links = 1, 844 .link_nodes = { &qns_mem_noc_sf }, 845 }; 846 847 static struct qcom_icc_node qnm_video_eva = { 848 .name = "qnm_video_eva", 849 .channels = 2, 850 .buswidth = 32, 851 .qosbox = &(const struct qcom_icc_qosbox) { 852 .num_ports = 2, 853 .port_offsets = { 0x35000, 0x36000 }, 854 .prio = 0, 855 .urg_fwd = 1, 856 .prio_fwd_disable = 0, 857 }, 858 .num_links = 1, 859 .link_nodes = { &qns_mem_noc_sf }, 860 }; 861 862 static struct qcom_icc_node qnm_video_mvp = { 863 .name = "qnm_video_mvp", 864 .channels = 2, 865 .buswidth = 32, 866 .qosbox = &(const struct qcom_icc_qosbox) { 867 .num_ports = 2, 868 .port_offsets = { 0x32000, 0x33000 }, 869 .prio = 0, 870 .urg_fwd = 1, 871 .prio_fwd_disable = 0, 872 }, 873 .num_links = 1, 874 .link_nodes = { &qns_mem_noc_sf }, 875 }; 876 877 static struct qcom_icc_node qnm_video_v_cpu = { 878 .name = "qnm_video_v_cpu", 879 .channels = 1, 880 .buswidth = 8, 881 .qosbox = &(const struct qcom_icc_qosbox) { 882 .num_ports = 1, 883 .port_offsets = { 0x37000 }, 884 .prio = 4, 885 .urg_fwd = 1, 886 .prio_fwd_disable = 1, 887 }, 888 .num_links = 1, 889 .link_nodes = { &qns_mem_noc_sf }, 890 }; 891 892 static struct qcom_icc_node qnm_nsp = { 893 .name = "qnm_nsp", 894 .channels = 2, 895 .buswidth = 32, 896 .num_links = 1, 897 .link_nodes = { &qns_nsp_gemnoc }, 898 }; 899 900 static struct qcom_icc_node xm_pcie = { 901 .name = "xm_pcie", 902 .channels = 1, 903 .buswidth = 16, 904 .qosbox = &(const struct qcom_icc_qosbox) { 905 .num_ports = 1, 906 .port_offsets = { 0xb000 }, 907 .prio = 3, 908 .urg_fwd = 0, 909 .prio_fwd_disable = 1, 910 }, 911 .num_links = 1, 912 .link_nodes = { &qns_pcie_gemnoc }, 913 }; 914 915 static struct qcom_icc_node qnm_aggre1_noc = { 916 .name = "qnm_aggre1_noc", 917 .channels = 1, 918 .buswidth = 16, 919 .num_links = 1, 920 .link_nodes = { &qns_gemnoc_sf }, 921 }; 922 923 static struct qcom_icc_node qnm_aggre2_noc = { 924 .name = "qnm_aggre2_noc", 925 .channels = 1, 926 .buswidth = 16, 927 .num_links = 1, 928 .link_nodes = { &qns_gemnoc_sf }, 929 }; 930 931 static struct qcom_icc_node qnm_apss_noc = { 932 .name = "qnm_apss_noc", 933 .channels = 1, 934 .buswidth = 8, 935 .qosbox = &(const struct qcom_icc_qosbox) { 936 .num_ports = 1, 937 .port_offsets = { 0x1e000 }, 938 .prio = 2, 939 .urg_fwd = 1, 940 .prio_fwd_disable = 1, 941 }, 942 .num_links = 1, 943 .link_nodes = { &qns_gemnoc_sf }, 944 }; 945 946 static struct qcom_icc_node qnm_cnoc_data = { 947 .name = "qnm_cnoc_data", 948 .channels = 1, 949 .buswidth = 8, 950 .qosbox = &(const struct qcom_icc_qosbox) { 951 .num_ports = 1, 952 .port_offsets = { 0x1f000 }, 953 .prio = 2, 954 .urg_fwd = 0, 955 .prio_fwd_disable = 1, 956 }, 957 .num_links = 1, 958 .link_nodes = { &qns_gemnoc_sf }, 959 }; 960 961 static struct qcom_icc_node qns_a1noc_snoc = { 962 .name = "qns_a1noc_snoc", 963 .channels = 1, 964 .buswidth = 16, 965 .num_links = 1, 966 .link_nodes = { &qnm_aggre1_noc }, 967 }; 968 969 static struct qcom_icc_node qns_a2noc_snoc = { 970 .name = "qns_a2noc_snoc", 971 .channels = 1, 972 .buswidth = 16, 973 .num_links = 1, 974 .link_nodes = { &qnm_aggre2_noc }, 975 }; 976 977 static struct qcom_icc_node qns_lpass_aggnoc = { 978 .name = "qns_lpass_aggnoc", 979 .channels = 1, 980 .buswidth = 16, 981 .num_links = 1, 982 .link_nodes = { &qnm_lpiaon_noc }, 983 }; 984 985 static struct qcom_icc_node qhm_qspi = { 986 .name = "qhm_qspi", 987 .channels = 1, 988 .buswidth = 4, 989 .qosbox = &(const struct qcom_icc_qosbox) { 990 .num_ports = 1, 991 .port_offsets = { 0xc000 }, 992 .prio = 2, 993 .urg_fwd = 0, 994 .prio_fwd_disable = 1, 995 }, 996 .num_links = 1, 997 .link_nodes = { &qns_a1noc_snoc }, 998 }; 999 1000 static struct qcom_icc_node qxm_crypto = { 1001 .name = "qxm_crypto", 1002 .channels = 1, 1003 .buswidth = 16, 1004 .qosbox = &(const struct qcom_icc_qosbox) { 1005 .num_ports = 1, 1006 .port_offsets = { 0x36000 }, 1007 .prio = 2, 1008 .urg_fwd = 1, 1009 .prio_fwd_disable = 1, 1010 }, 1011 .num_links = 1, 1012 .link_nodes = { &qns_a1noc_snoc }, 1013 }; 1014 1015 static struct qcom_icc_node qxm_qup1 = { 1016 .name = "qxm_qup1", 1017 .channels = 1, 1018 .buswidth = 8, 1019 .qosbox = &(const struct qcom_icc_qosbox) { 1020 .num_ports = 1, 1021 .port_offsets = { 0x11000 }, 1022 .prio = 2, 1023 .urg_fwd = 1, 1024 .prio_fwd_disable = 1, 1025 }, 1026 .num_links = 1, 1027 .link_nodes = { &qns_a1noc_snoc }, 1028 }; 1029 1030 static struct qcom_icc_node xm_sdc4 = { 1031 .name = "xm_sdc4", 1032 .channels = 1, 1033 .buswidth = 8, 1034 .qosbox = &(const struct qcom_icc_qosbox) { 1035 .num_ports = 1, 1036 .port_offsets = { 0xe000 }, 1037 .prio = 2, 1038 .urg_fwd = 0, 1039 .prio_fwd_disable = 1, 1040 }, 1041 .num_links = 1, 1042 .link_nodes = { &qns_a1noc_snoc }, 1043 }; 1044 1045 static struct qcom_icc_node xm_ufs_mem = { 1046 .name = "xm_ufs_mem", 1047 .channels = 1, 1048 .buswidth = 16, 1049 .qosbox = &(const struct qcom_icc_qosbox) { 1050 .num_ports = 1, 1051 .port_offsets = { 0xf000 }, 1052 .prio = 2, 1053 .urg_fwd = 0, 1054 .prio_fwd_disable = 1, 1055 }, 1056 .num_links = 1, 1057 .link_nodes = { &qns_a1noc_snoc }, 1058 }; 1059 1060 static struct qcom_icc_node xm_usb3 = { 1061 .name = "xm_usb3", 1062 .channels = 1, 1063 .buswidth = 8, 1064 .qosbox = &(const struct qcom_icc_qosbox) { 1065 .num_ports = 1, 1066 .port_offsets = { 0x10000 }, 1067 .prio = 2, 1068 .urg_fwd = 0, 1069 .prio_fwd_disable = 1, 1070 }, 1071 .num_links = 1, 1072 .link_nodes = { &qns_a1noc_snoc }, 1073 }; 1074 1075 static struct qcom_icc_node qhm_qup2 = { 1076 .name = "qhm_qup2", 1077 .channels = 1, 1078 .buswidth = 4, 1079 .qosbox = &(const struct qcom_icc_qosbox) { 1080 .num_ports = 1, 1081 .port_offsets = { 0x35000 }, 1082 .prio = 2, 1083 .urg_fwd = 0, 1084 .prio_fwd_disable = 1, 1085 }, 1086 .num_links = 1, 1087 .link_nodes = { &qns_a2noc_snoc }, 1088 }; 1089 1090 static struct qcom_icc_node qhm_qup3 = { 1091 .name = "qhm_qup3", 1092 .channels = 1, 1093 .buswidth = 4, 1094 .qosbox = &(const struct qcom_icc_qosbox) { 1095 .num_ports = 1, 1096 .port_offsets = { 0x3c000 }, 1097 .prio = 2, 1098 .urg_fwd = 0, 1099 .prio_fwd_disable = 1, 1100 }, 1101 .num_links = 1, 1102 .link_nodes = { &qns_a2noc_snoc }, 1103 }; 1104 1105 static struct qcom_icc_node qhm_qup4 = { 1106 .name = "qhm_qup4", 1107 .channels = 1, 1108 .buswidth = 4, 1109 .qosbox = &(const struct qcom_icc_qosbox) { 1110 .num_ports = 1, 1111 .port_offsets = { 0x3d000 }, 1112 .prio = 2, 1113 .urg_fwd = 0, 1114 .prio_fwd_disable = 1, 1115 }, 1116 .num_links = 1, 1117 .link_nodes = { &qns_a2noc_snoc }, 1118 }; 1119 1120 static struct qcom_icc_node qxm_ipa = { 1121 .name = "qxm_ipa", 1122 .channels = 1, 1123 .buswidth = 8, 1124 .qosbox = &(const struct qcom_icc_qosbox) { 1125 .num_ports = 1, 1126 .port_offsets = { 0x37000 }, 1127 .prio = 2, 1128 .urg_fwd = 1, 1129 .prio_fwd_disable = 1, 1130 }, 1131 .num_links = 1, 1132 .link_nodes = { &qns_a2noc_snoc }, 1133 }; 1134 1135 static struct qcom_icc_node qxm_soccp = { 1136 .name = "qxm_soccp", 1137 .channels = 1, 1138 .buswidth = 8, 1139 .qosbox = &(const struct qcom_icc_qosbox) { 1140 .num_ports = 1, 1141 .port_offsets = { 0x3b000 }, 1142 .prio = 2, 1143 .urg_fwd = 1, 1144 .prio_fwd_disable = 1, 1145 }, 1146 .num_links = 1, 1147 .link_nodes = { &qns_a2noc_snoc }, 1148 }; 1149 1150 static struct qcom_icc_node qxm_sp = { 1151 .name = "qxm_sp", 1152 .channels = 1, 1153 .buswidth = 8, 1154 .num_links = 1, 1155 .link_nodes = { &qns_a2noc_snoc }, 1156 }; 1157 1158 static struct qcom_icc_node xm_qdss_etr_0 = { 1159 .name = "xm_qdss_etr_0", 1160 .channels = 1, 1161 .buswidth = 8, 1162 .qosbox = &(const struct qcom_icc_qosbox) { 1163 .num_ports = 1, 1164 .port_offsets = { 0x38000 }, 1165 .prio = 2, 1166 .urg_fwd = 0, 1167 .prio_fwd_disable = 1, 1168 }, 1169 .num_links = 1, 1170 .link_nodes = { &qns_a2noc_snoc }, 1171 }; 1172 1173 static struct qcom_icc_node xm_qdss_etr_1 = { 1174 .name = "xm_qdss_etr_1", 1175 .channels = 1, 1176 .buswidth = 8, 1177 .qosbox = &(const struct qcom_icc_qosbox) { 1178 .num_ports = 1, 1179 .port_offsets = { 0x39000 }, 1180 .prio = 2, 1181 .urg_fwd = 0, 1182 .prio_fwd_disable = 1, 1183 }, 1184 .num_links = 1, 1185 .link_nodes = { &qns_a2noc_snoc }, 1186 }; 1187 1188 static struct qcom_icc_node xm_sdc2 = { 1189 .name = "xm_sdc2", 1190 .channels = 1, 1191 .buswidth = 8, 1192 .qosbox = &(const struct qcom_icc_qosbox) { 1193 .num_ports = 1, 1194 .port_offsets = { 0x3a000 }, 1195 .prio = 2, 1196 .urg_fwd = 0, 1197 .prio_fwd_disable = 1, 1198 }, 1199 .num_links = 1, 1200 .link_nodes = { &qns_a2noc_snoc }, 1201 }; 1202 1203 static struct qcom_icc_node qnm_lpass_lpinoc = { 1204 .name = "qnm_lpass_lpinoc", 1205 .channels = 1, 1206 .buswidth = 16, 1207 .num_links = 1, 1208 .link_nodes = { &qns_lpass_aggnoc }, 1209 }; 1210 1211 static struct qcom_icc_node qns_lpi_aon_noc = { 1212 .name = "qns_lpi_aon_noc", 1213 .channels = 1, 1214 .buswidth = 16, 1215 .num_links = 1, 1216 .link_nodes = { &qnm_lpass_lpinoc }, 1217 }; 1218 1219 static struct qcom_icc_node qnm_lpinoc_dsp_qns4m = { 1220 .name = "qnm_lpinoc_dsp_qns4m", 1221 .channels = 1, 1222 .buswidth = 16, 1223 .num_links = 1, 1224 .link_nodes = { &qns_lpi_aon_noc }, 1225 }; 1226 1227 static struct qcom_icc_bcm bcm_acv = { 1228 .name = "ACV", 1229 .enable_mask = BIT(3), 1230 .num_nodes = 1, 1231 .nodes = { &ebi }, 1232 }; 1233 1234 static struct qcom_icc_bcm bcm_ce0 = { 1235 .name = "CE0", 1236 .num_nodes = 1, 1237 .nodes = { &qxm_crypto }, 1238 }; 1239 1240 static struct qcom_icc_bcm bcm_cn0 = { 1241 .name = "CN0", 1242 .enable_mask = BIT(0), 1243 .keepalive = true, 1244 .num_nodes = 43, 1245 .nodes = { &qsm_cfg, &qhs_ahb2phy0, 1246 &qhs_ahb2phy1, &qhs_camera_cfg, 1247 &qhs_clk_ctl, &qhs_crypto0_cfg, 1248 &qhs_eva_cfg, &qhs_gpuss_cfg, 1249 &qhs_i3c_ibi0_cfg, &qhs_i3c_ibi1_cfg, 1250 &qhs_imem_cfg, &qhs_ipc_router, 1251 &qhs_mss_cfg, &qhs_pcie_cfg, 1252 &qhs_prng, &qhs_qdss_cfg, 1253 &qhs_qspi, &qhs_sdc2, 1254 &qhs_sdc4, &qhs_spss_cfg, 1255 &qhs_tcsr, &qhs_tlmm, 1256 &qhs_ufs_mem_cfg, &qhs_usb3, 1257 &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, 1258 &qss_mnoc_cfg, &qss_pcie_anoc_cfg, 1259 &xs_qdss_stm, &xs_sys_tcu_cfg, 1260 &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie, 1261 &qhs_aoss, &qhs_ipa, 1262 &qhs_ipc_router_fence, &qhs_soccp, 1263 &qhs_tme_cfg, &qns_apss, 1264 &qss_cfg, &qss_ddrss_cfg, 1265 &qxs_boot_imem, &qxs_imem, 1266 &xs_pcie }, 1267 }; 1268 1269 static struct qcom_icc_bcm bcm_cn1 = { 1270 .name = "CN1", 1271 .num_nodes = 6, 1272 .nodes = { &qhs_display_cfg, &qhs_i2c, 1273 &qhs_qup1, &qhs_qup2, 1274 &qhs_qup3, &qhs_qup4 }, 1275 }; 1276 1277 static struct qcom_icc_bcm bcm_co0 = { 1278 .name = "CO0", 1279 .enable_mask = BIT(0), 1280 .num_nodes = 2, 1281 .nodes = { &qnm_nsp, &qns_nsp_gemnoc }, 1282 }; 1283 1284 static struct qcom_icc_bcm bcm_lp0 = { 1285 .name = "LP0", 1286 .num_nodes = 2, 1287 .nodes = { &qnm_lpass_lpinoc, &qns_lpass_aggnoc }, 1288 }; 1289 1290 static struct qcom_icc_bcm bcm_mc0 = { 1291 .name = "MC0", 1292 .keepalive = true, 1293 .num_nodes = 1, 1294 .nodes = { &ebi }, 1295 }; 1296 1297 static struct qcom_icc_bcm bcm_mm0 = { 1298 .name = "MM0", 1299 .num_nodes = 1, 1300 .nodes = { &qns_mem_noc_hf }, 1301 }; 1302 1303 static struct qcom_icc_bcm bcm_mm1 = { 1304 .name = "MM1", 1305 .enable_mask = BIT(0), 1306 .num_nodes = 9, 1307 .nodes = { &qnm_camnoc_hf, &qnm_camnoc_nrt_icp_sf, 1308 &qnm_camnoc_rt_cdm_sf, &qnm_camnoc_sf, 1309 &qnm_vapss_hcp, &qnm_video_cv_cpu, 1310 &qnm_video_mvp, &qnm_video_v_cpu, 1311 &qns_mem_noc_sf }, 1312 }; 1313 1314 static struct qcom_icc_bcm bcm_qpc0 = { 1315 .name = "QPC0", 1316 .num_nodes = 1, 1317 .nodes = { &qnm_qpace }, 1318 }; 1319 1320 static struct qcom_icc_bcm bcm_qup0 = { 1321 .name = "QUP0", 1322 .keepalive = true, 1323 .vote_scale = 1, 1324 .num_nodes = 1, 1325 .nodes = { &qup0_core_slave }, 1326 }; 1327 1328 static struct qcom_icc_bcm bcm_qup1 = { 1329 .name = "QUP1", 1330 .keepalive = true, 1331 .vote_scale = 1, 1332 .num_nodes = 1, 1333 .nodes = { &qup1_core_slave }, 1334 }; 1335 1336 static struct qcom_icc_bcm bcm_qup2 = { 1337 .name = "QUP2", 1338 .keepalive = true, 1339 .vote_scale = 1, 1340 .num_nodes = 1, 1341 .nodes = { &qup2_core_slave }, 1342 }; 1343 1344 static struct qcom_icc_bcm bcm_qup3 = { 1345 .name = "QUP3", 1346 .keepalive = true, 1347 .vote_scale = 1, 1348 .num_nodes = 1, 1349 .nodes = { &qup3_core_slave }, 1350 }; 1351 1352 static struct qcom_icc_bcm bcm_qup4 = { 1353 .name = "QUP4", 1354 .keepalive = true, 1355 .vote_scale = 1, 1356 .num_nodes = 1, 1357 .nodes = { &qup4_core_slave }, 1358 }; 1359 1360 static struct qcom_icc_bcm bcm_sh0 = { 1361 .name = "SH0", 1362 .keepalive = true, 1363 .num_nodes = 1, 1364 .nodes = { &qns_llcc }, 1365 }; 1366 1367 static struct qcom_icc_bcm bcm_sh1 = { 1368 .name = "SH1", 1369 .enable_mask = BIT(0), 1370 .num_nodes = 14, 1371 .nodes = { &alm_gpu_tcu, &alm_sys_tcu, 1372 &chm_apps, &qnm_gpu, 1373 &qnm_mdsp, &qnm_mnoc_hf, 1374 &qnm_mnoc_sf, &qnm_nsp_gemnoc, 1375 &qnm_pcie, &qnm_snoc_sf, 1376 &qnm_wlan_q6, &xm_gic, 1377 &qns_gem_noc_cnoc, &qns_pcie }, 1378 }; 1379 1380 static struct qcom_icc_bcm bcm_sn0 = { 1381 .name = "SN0", 1382 .keepalive = true, 1383 .num_nodes = 1, 1384 .nodes = { &qns_gemnoc_sf }, 1385 }; 1386 1387 static struct qcom_icc_bcm bcm_sn2 = { 1388 .name = "SN2", 1389 .num_nodes = 1, 1390 .nodes = { &qnm_aggre1_noc }, 1391 }; 1392 1393 static struct qcom_icc_bcm bcm_sn3 = { 1394 .name = "SN3", 1395 .num_nodes = 1, 1396 .nodes = { &qnm_aggre2_noc }, 1397 }; 1398 1399 static struct qcom_icc_bcm bcm_sn4 = { 1400 .name = "SN4", 1401 .num_nodes = 1, 1402 .nodes = { &qns_pcie_gemnoc }, 1403 }; 1404 1405 static struct qcom_icc_bcm * const aggre_noc_bcms[] = { 1406 &bcm_ce0, 1407 }; 1408 1409 static struct qcom_icc_node * const aggre_noc_nodes[] = { 1410 [MASTER_QSPI_0] = &qhm_qspi, 1411 [MASTER_CRYPTO] = &qxm_crypto, 1412 [MASTER_QUP_1] = &qxm_qup1, 1413 [MASTER_SDCC_4] = &xm_sdc4, 1414 [MASTER_UFS_MEM] = &xm_ufs_mem, 1415 [MASTER_USB3] = &xm_usb3, 1416 [MASTER_QUP_2] = &qhm_qup2, 1417 [MASTER_QUP_3] = &qhm_qup3, 1418 [MASTER_QUP_4] = &qhm_qup4, 1419 [MASTER_IPA] = &qxm_ipa, 1420 [MASTER_SOCCP_PROC] = &qxm_soccp, 1421 [MASTER_SP] = &qxm_sp, 1422 [MASTER_QDSS_ETR] = &xm_qdss_etr_0, 1423 [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1, 1424 [MASTER_SDCC_2] = &xm_sdc2, 1425 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, 1426 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, 1427 }; 1428 1429 static const struct regmap_config kaanapali_aggre_noc_regmap_config = { 1430 .reg_bits = 32, 1431 .reg_stride = 4, 1432 .val_bits = 32, 1433 .max_register = 0x42400, 1434 .fast_io = true, 1435 }; 1436 1437 static const struct qcom_icc_desc kaanapali_aggre_noc = { 1438 .config = &kaanapali_aggre_noc_regmap_config, 1439 .nodes = aggre_noc_nodes, 1440 .num_nodes = ARRAY_SIZE(aggre_noc_nodes), 1441 .bcms = aggre_noc_bcms, 1442 .num_bcms = ARRAY_SIZE(aggre_noc_bcms), 1443 .qos_requires_clocks = true, 1444 }; 1445 1446 static struct qcom_icc_bcm * const clk_virt_bcms[] = { 1447 &bcm_qup0, 1448 &bcm_qup1, 1449 &bcm_qup2, 1450 &bcm_qup3, 1451 &bcm_qup4, 1452 }; 1453 1454 static struct qcom_icc_node * const clk_virt_nodes[] = { 1455 [MASTER_QUP_CORE_0] = &qup0_core_master, 1456 [MASTER_QUP_CORE_1] = &qup1_core_master, 1457 [MASTER_QUP_CORE_2] = &qup2_core_master, 1458 [MASTER_QUP_CORE_3] = &qup3_core_master, 1459 [MASTER_QUP_CORE_4] = &qup4_core_master, 1460 [SLAVE_QUP_CORE_0] = &qup0_core_slave, 1461 [SLAVE_QUP_CORE_1] = &qup1_core_slave, 1462 [SLAVE_QUP_CORE_2] = &qup2_core_slave, 1463 [SLAVE_QUP_CORE_3] = &qup3_core_slave, 1464 [SLAVE_QUP_CORE_4] = &qup4_core_slave, 1465 }; 1466 1467 static const struct qcom_icc_desc kaanapali_clk_virt = { 1468 .nodes = clk_virt_nodes, 1469 .num_nodes = ARRAY_SIZE(clk_virt_nodes), 1470 .bcms = clk_virt_bcms, 1471 .num_bcms = ARRAY_SIZE(clk_virt_bcms), 1472 }; 1473 1474 static struct qcom_icc_bcm * const cnoc_cfg_bcms[] = { 1475 &bcm_cn0, 1476 &bcm_cn1, 1477 }; 1478 1479 static struct qcom_icc_node * const cnoc_cfg_nodes[] = { 1480 [MASTER_CNOC_CFG] = &qsm_cfg, 1481 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, 1482 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1, 1483 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 1484 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1485 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1486 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 1487 [SLAVE_EVA_CFG] = &qhs_eva_cfg, 1488 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, 1489 [SLAVE_I2C] = &qhs_i2c, 1490 [SLAVE_I3C_IBI0_CFG] = &qhs_i3c_ibi0_cfg, 1491 [SLAVE_I3C_IBI1_CFG] = &qhs_i3c_ibi1_cfg, 1492 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1493 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, 1494 [SLAVE_CNOC_MSS] = &qhs_mss_cfg, 1495 [SLAVE_PCIE_CFG] = &qhs_pcie_cfg, 1496 [SLAVE_PRNG] = &qhs_prng, 1497 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1498 [SLAVE_QSPI_0] = &qhs_qspi, 1499 [SLAVE_QUP_1] = &qhs_qup1, 1500 [SLAVE_QUP_2] = &qhs_qup2, 1501 [SLAVE_QUP_3] = &qhs_qup3, 1502 [SLAVE_QUP_4] = &qhs_qup4, 1503 [SLAVE_SDCC_2] = &qhs_sdc2, 1504 [SLAVE_SDCC_4] = &qhs_sdc4, 1505 [SLAVE_SPSS_CFG] = &qhs_spss_cfg, 1506 [SLAVE_TCSR] = &qhs_tcsr, 1507 [SLAVE_TLMM] = &qhs_tlmm, 1508 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 1509 [SLAVE_USB3] = &qhs_usb3, 1510 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1511 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 1512 [SLAVE_CNOC_MNOC_CFG] = &qss_mnoc_cfg, 1513 [SLAVE_PCIE_ANOC_CFG] = &qss_pcie_anoc_cfg, 1514 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1515 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1516 }; 1517 1518 static const struct regmap_config kaanapali_cnoc_cfg_regmap_config = { 1519 .reg_bits = 32, 1520 .reg_stride = 4, 1521 .val_bits = 32, 1522 .max_register = 0x6200, 1523 .fast_io = true, 1524 }; 1525 1526 static const struct qcom_icc_desc kaanapali_cnoc_cfg = { 1527 .config = &kaanapali_cnoc_cfg_regmap_config, 1528 .nodes = cnoc_cfg_nodes, 1529 .num_nodes = ARRAY_SIZE(cnoc_cfg_nodes), 1530 .bcms = cnoc_cfg_bcms, 1531 .num_bcms = ARRAY_SIZE(cnoc_cfg_bcms), 1532 }; 1533 1534 static struct qcom_icc_bcm * const cnoc_main_bcms[] = { 1535 &bcm_cn0, 1536 }; 1537 1538 static struct qcom_icc_node * const cnoc_main_nodes[] = { 1539 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, 1540 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, 1541 [SLAVE_AOSS] = &qhs_aoss, 1542 [SLAVE_IPA_CFG] = &qhs_ipa, 1543 [SLAVE_IPC_ROUTER_FENCE] = &qhs_ipc_router_fence, 1544 [SLAVE_SOCCP] = &qhs_soccp, 1545 [SLAVE_TME_CFG] = &qhs_tme_cfg, 1546 [SLAVE_APPSS] = &qns_apss, 1547 [SLAVE_CNOC_CFG] = &qss_cfg, 1548 [SLAVE_DDRSS_CFG] = &qss_ddrss_cfg, 1549 [SLAVE_BOOT_IMEM] = &qxs_boot_imem, 1550 [SLAVE_IMEM] = &qxs_imem, 1551 [SLAVE_PCIE_0] = &xs_pcie, 1552 }; 1553 1554 static const struct regmap_config kaanapali_cnoc_main_regmap_config = { 1555 .reg_bits = 32, 1556 .reg_stride = 4, 1557 .val_bits = 32, 1558 .max_register = 0x1a080, 1559 .fast_io = true, 1560 }; 1561 1562 static const struct qcom_icc_desc kaanapali_cnoc_main = { 1563 .config = &kaanapali_cnoc_main_regmap_config, 1564 .nodes = cnoc_main_nodes, 1565 .num_nodes = ARRAY_SIZE(cnoc_main_nodes), 1566 .bcms = cnoc_main_bcms, 1567 .num_bcms = ARRAY_SIZE(cnoc_main_bcms), 1568 }; 1569 1570 static struct qcom_icc_bcm * const gem_noc_bcms[] = { 1571 &bcm_qpc0, 1572 &bcm_sh0, 1573 &bcm_sh1, 1574 }; 1575 1576 static struct qcom_icc_node * const gem_noc_nodes[] = { 1577 [MASTER_GPU_TCU] = &alm_gpu_tcu, 1578 [MASTER_SYS_TCU] = &alm_sys_tcu, 1579 [MASTER_APPSS_PROC] = &chm_apps, 1580 [MASTER_GFX3D] = &qnm_gpu, 1581 [MASTER_LPASS_GEM_NOC] = &qnm_lpass_gemnoc, 1582 [MASTER_MSS_PROC] = &qnm_mdsp, 1583 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 1584 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 1585 [MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc, 1586 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, 1587 [MASTER_QPACE] = &qnm_qpace, 1588 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 1589 [MASTER_WLAN_Q6] = &qnm_wlan_q6, 1590 [MASTER_GIC] = &xm_gic, 1591 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, 1592 [SLAVE_LLCC] = &qns_llcc, 1593 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, 1594 }; 1595 1596 static const struct regmap_config kaanapali_gem_noc_regmap_config = { 1597 .reg_bits = 32, 1598 .reg_stride = 4, 1599 .val_bits = 32, 1600 .max_register = 0x153080, 1601 .fast_io = true, 1602 }; 1603 1604 static const struct qcom_icc_desc kaanapali_gem_noc = { 1605 .config = &kaanapali_gem_noc_regmap_config, 1606 .nodes = gem_noc_nodes, 1607 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 1608 .bcms = gem_noc_bcms, 1609 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 1610 }; 1611 1612 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { 1613 [MASTER_LPIAON_NOC] = &qnm_lpiaon_noc, 1614 [SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc, 1615 }; 1616 1617 static const struct regmap_config kaanapali_lpass_ag_noc_regmap_config = { 1618 .reg_bits = 32, 1619 .reg_stride = 4, 1620 .val_bits = 32, 1621 .max_register = 0xe080, 1622 .fast_io = true, 1623 }; 1624 1625 static const struct qcom_icc_desc kaanapali_lpass_ag_noc = { 1626 .config = &kaanapali_lpass_ag_noc_regmap_config, 1627 .nodes = lpass_ag_noc_nodes, 1628 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), 1629 }; 1630 1631 static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = { 1632 &bcm_lp0, 1633 }; 1634 1635 static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = { 1636 [MASTER_LPASS_LPINOC] = &qnm_lpass_lpinoc, 1637 [SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &qns_lpass_aggnoc, 1638 }; 1639 1640 static const struct regmap_config kaanapali_lpass_lpiaon_noc_regmap_config = { 1641 .reg_bits = 32, 1642 .reg_stride = 4, 1643 .val_bits = 32, 1644 .max_register = 0x19080, 1645 .fast_io = true, 1646 }; 1647 1648 static const struct qcom_icc_desc kaanapali_lpass_lpiaon_noc = { 1649 .config = &kaanapali_lpass_lpiaon_noc_regmap_config, 1650 .nodes = lpass_lpiaon_noc_nodes, 1651 .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes), 1652 .bcms = lpass_lpiaon_noc_bcms, 1653 .num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms), 1654 }; 1655 1656 static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = { 1657 [MASTER_LPASS_PROC] = &qnm_lpinoc_dsp_qns4m, 1658 [SLAVE_LPICX_NOC_LPIAON_NOC] = &qns_lpi_aon_noc, 1659 }; 1660 1661 static const struct regmap_config kaanapali_lpass_lpicx_noc_regmap_config = { 1662 .reg_bits = 32, 1663 .reg_stride = 4, 1664 .val_bits = 32, 1665 .max_register = 0x44080, 1666 .fast_io = true, 1667 }; 1668 1669 static const struct qcom_icc_desc kaanapali_lpass_lpicx_noc = { 1670 .config = &kaanapali_lpass_lpicx_noc_regmap_config, 1671 .nodes = lpass_lpicx_noc_nodes, 1672 .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes), 1673 }; 1674 1675 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 1676 &bcm_acv, 1677 &bcm_mc0, 1678 }; 1679 1680 static struct qcom_icc_node * const mc_virt_nodes[] = { 1681 [MASTER_LLCC] = &llcc_mc, 1682 [SLAVE_EBI1] = &ebi, 1683 }; 1684 1685 static const struct qcom_icc_desc kaanapali_mc_virt = { 1686 .nodes = mc_virt_nodes, 1687 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 1688 .bcms = mc_virt_bcms, 1689 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 1690 }; 1691 1692 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 1693 &bcm_mm0, 1694 &bcm_mm1, 1695 }; 1696 1697 static struct qcom_icc_node * const mmss_noc_nodes[] = { 1698 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, 1699 [MASTER_CAMNOC_NRT_ICP_SF] = &qnm_camnoc_nrt_icp_sf, 1700 [MASTER_CAMNOC_RT_CDM_SF] = &qnm_camnoc_rt_cdm_sf, 1701 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, 1702 [MASTER_MDP] = &qnm_mdp, 1703 [MASTER_MDSS_DCP] = &qnm_mdss_dcp, 1704 [MASTER_CDSP_HCP] = &qnm_vapss_hcp, 1705 [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu, 1706 [MASTER_VIDEO_EVA] = &qnm_video_eva, 1707 [MASTER_VIDEO_MVP] = &qnm_video_mvp, 1708 [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu, 1709 [MASTER_CNOC_MNOC_CFG] = &qsm_mnoc_cfg, 1710 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 1711 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, 1712 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 1713 }; 1714 1715 static const struct regmap_config kaanapali_mmss_noc_regmap_config = { 1716 .reg_bits = 32, 1717 .reg_stride = 4, 1718 .val_bits = 32, 1719 .max_register = 0x5b800, 1720 .fast_io = true, 1721 }; 1722 1723 static const struct qcom_icc_desc kaanapali_mmss_noc = { 1724 .config = &kaanapali_mmss_noc_regmap_config, 1725 .nodes = mmss_noc_nodes, 1726 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 1727 .bcms = mmss_noc_bcms, 1728 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 1729 }; 1730 1731 static struct qcom_icc_bcm * const nsp_noc_bcms[] = { 1732 &bcm_co0, 1733 }; 1734 1735 static struct qcom_icc_node * const nsp_noc_nodes[] = { 1736 [MASTER_CDSP_PROC] = &qnm_nsp, 1737 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, 1738 }; 1739 1740 static const struct regmap_config kaanapali_nsp_noc_regmap_config = { 1741 .reg_bits = 32, 1742 .reg_stride = 4, 1743 .val_bits = 32, 1744 .max_register = 0x21280, 1745 .fast_io = true, 1746 }; 1747 1748 static const struct qcom_icc_desc kaanapali_nsp_noc = { 1749 .config = &kaanapali_nsp_noc_regmap_config, 1750 .nodes = nsp_noc_nodes, 1751 .num_nodes = ARRAY_SIZE(nsp_noc_nodes), 1752 .bcms = nsp_noc_bcms, 1753 .num_bcms = ARRAY_SIZE(nsp_noc_bcms), 1754 }; 1755 1756 static struct qcom_icc_bcm * const pcie_anoc_bcms[] = { 1757 &bcm_sn4, 1758 }; 1759 1760 static struct qcom_icc_node * const pcie_anoc_nodes[] = { 1761 [MASTER_PCIE_ANOC_CFG] = &qsm_pcie_anoc_cfg, 1762 [MASTER_PCIE_0] = &xm_pcie, 1763 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_gemnoc, 1764 [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc, 1765 }; 1766 1767 static const struct regmap_config kaanapali_pcie_anoc_regmap_config = { 1768 .reg_bits = 32, 1769 .reg_stride = 4, 1770 .val_bits = 32, 1771 .max_register = 0x11400, 1772 .fast_io = true, 1773 }; 1774 1775 static const struct qcom_icc_desc kaanapali_pcie_anoc = { 1776 .config = &kaanapali_pcie_anoc_regmap_config, 1777 .nodes = pcie_anoc_nodes, 1778 .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), 1779 .bcms = pcie_anoc_bcms, 1780 .num_bcms = ARRAY_SIZE(pcie_anoc_bcms), 1781 .qos_requires_clocks = true, 1782 }; 1783 1784 static struct qcom_icc_bcm * const system_noc_bcms[] = { 1785 &bcm_sn0, 1786 &bcm_sn2, 1787 &bcm_sn3, 1788 }; 1789 1790 static struct qcom_icc_node * const system_noc_nodes[] = { 1791 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, 1792 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, 1793 [MASTER_APSS_NOC] = &qnm_apss_noc, 1794 [MASTER_CNOC_SNOC] = &qnm_cnoc_data, 1795 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 1796 }; 1797 1798 static const struct regmap_config kaanapali_system_noc_regmap_config = { 1799 .reg_bits = 32, 1800 .reg_stride = 4, 1801 .val_bits = 32, 1802 .max_register = 0x1f080, 1803 .fast_io = true, 1804 }; 1805 1806 static const struct qcom_icc_desc kaanapali_system_noc = { 1807 .config = &kaanapali_system_noc_regmap_config, 1808 .nodes = system_noc_nodes, 1809 .num_nodes = ARRAY_SIZE(system_noc_nodes), 1810 .bcms = system_noc_bcms, 1811 .num_bcms = ARRAY_SIZE(system_noc_bcms), 1812 }; 1813 1814 static const struct of_device_id qnoc_of_match[] = { 1815 { .compatible = "qcom,kaanapali-aggre-noc", .data = &kaanapali_aggre_noc }, 1816 { .compatible = "qcom,kaanapali-clk-virt", .data = &kaanapali_clk_virt }, 1817 { .compatible = "qcom,kaanapali-cnoc-cfg", .data = &kaanapali_cnoc_cfg }, 1818 { .compatible = "qcom,kaanapali-cnoc-main", .data = &kaanapali_cnoc_main }, 1819 { .compatible = "qcom,kaanapali-gem-noc", .data = &kaanapali_gem_noc }, 1820 { .compatible = "qcom,kaanapali-lpass-ag-noc", .data = &kaanapali_lpass_ag_noc }, 1821 { .compatible = "qcom,kaanapali-lpass-lpiaon-noc", .data = &kaanapali_lpass_lpiaon_noc }, 1822 { .compatible = "qcom,kaanapali-lpass-lpicx-noc", .data = &kaanapali_lpass_lpicx_noc }, 1823 { .compatible = "qcom,kaanapali-mc-virt", .data = &kaanapali_mc_virt }, 1824 { .compatible = "qcom,kaanapali-mmss-noc", .data = &kaanapali_mmss_noc }, 1825 { .compatible = "qcom,kaanapali-nsp-noc", .data = &kaanapali_nsp_noc }, 1826 { .compatible = "qcom,kaanapali-pcie-anoc", .data = &kaanapali_pcie_anoc }, 1827 { .compatible = "qcom,kaanapali-system-noc", .data = &kaanapali_system_noc }, 1828 { } 1829 }; 1830 MODULE_DEVICE_TABLE(of, qnoc_of_match); 1831 1832 static struct platform_driver qnoc_driver = { 1833 .probe = qcom_icc_rpmh_probe, 1834 .remove = qcom_icc_rpmh_remove, 1835 .driver = { 1836 .name = "qnoc-kaanapali", 1837 .of_match_table = qnoc_of_match, 1838 .sync_state = icc_sync_state, 1839 }, 1840 }; 1841 1842 static int __init qnoc_driver_init(void) 1843 { 1844 return platform_driver_register(&qnoc_driver); 1845 } 1846 core_initcall(qnoc_driver_init); 1847 1848 static void __exit qnoc_driver_exit(void) 1849 { 1850 platform_driver_unregister(&qnoc_driver); 1851 } 1852 module_exit(qnoc_driver_exit); 1853 1854 MODULE_DESCRIPTION("Qualcomm Kaanapali NoC driver"); 1855 MODULE_LICENSE("GPL"); 1856