1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 */ 6 7 #include <linux/device.h> 8 #include <linux/interconnect.h> 9 #include <linux/interconnect-provider.h> 10 #include <linux/module.h> 11 #include <linux/of_platform.h> 12 #include <dt-bindings/interconnect/qcom,glymur-rpmh.h> 13 14 #include "bcm-voter.h" 15 #include "icc-rpmh.h" 16 17 static struct qcom_icc_node qup0_core_slave = { 18 .name = "qup0_core_slave", 19 .channels = 1, 20 .buswidth = 4, 21 }; 22 23 static struct qcom_icc_node qup1_core_slave = { 24 .name = "qup1_core_slave", 25 .channels = 1, 26 .buswidth = 4, 27 }; 28 29 static struct qcom_icc_node qup2_core_slave = { 30 .name = "qup2_core_slave", 31 .channels = 1, 32 .buswidth = 4, 33 }; 34 35 static struct qcom_icc_node qhs_ahb2phy0 = { 36 .name = "qhs_ahb2phy0", 37 .channels = 1, 38 .buswidth = 4, 39 }; 40 41 static struct qcom_icc_node qhs_ahb2phy1 = { 42 .name = "qhs_ahb2phy1", 43 .channels = 1, 44 .buswidth = 4, 45 }; 46 47 static struct qcom_icc_node qhs_ahb2phy2 = { 48 .name = "qhs_ahb2phy2", 49 .channels = 1, 50 .buswidth = 4, 51 }; 52 53 static struct qcom_icc_node qhs_ahb2phy3 = { 54 .name = "qhs_ahb2phy3", 55 .channels = 1, 56 .buswidth = 4, 57 }; 58 59 static struct qcom_icc_node qhs_av1_enc_cfg = { 60 .name = "qhs_av1_enc_cfg", 61 .channels = 1, 62 .buswidth = 4, 63 }; 64 65 static struct qcom_icc_node qhs_camera_cfg = { 66 .name = "qhs_camera_cfg", 67 .channels = 1, 68 .buswidth = 4, 69 }; 70 71 static struct qcom_icc_node qhs_clk_ctl = { 72 .name = "qhs_clk_ctl", 73 .channels = 1, 74 .buswidth = 4, 75 }; 76 77 static struct qcom_icc_node qhs_crypto0_cfg = { 78 .name = "qhs_crypto0_cfg", 79 .channels = 1, 80 .buswidth = 4, 81 }; 82 83 static struct qcom_icc_node qhs_display_cfg = { 84 .name = "qhs_display_cfg", 85 .channels = 1, 86 .buswidth = 4, 87 }; 88 89 static struct qcom_icc_node qhs_gpuss_cfg = { 90 .name = "qhs_gpuss_cfg", 91 .channels = 1, 92 .buswidth = 8, 93 }; 94 95 static struct qcom_icc_node qhs_imem_cfg = { 96 .name = "qhs_imem_cfg", 97 .channels = 1, 98 .buswidth = 4, 99 }; 100 101 static struct qcom_icc_node qhs_pcie0_cfg = { 102 .name = "qhs_pcie0_cfg", 103 .channels = 1, 104 .buswidth = 4, 105 }; 106 107 static struct qcom_icc_node qhs_pcie1_cfg = { 108 .name = "qhs_pcie1_cfg", 109 .channels = 1, 110 .buswidth = 4, 111 }; 112 113 static struct qcom_icc_node qhs_pcie2_cfg = { 114 .name = "qhs_pcie2_cfg", 115 .channels = 1, 116 .buswidth = 4, 117 }; 118 119 static struct qcom_icc_node qhs_pcie3a_cfg = { 120 .name = "qhs_pcie3a_cfg", 121 .channels = 1, 122 .buswidth = 4, 123 }; 124 125 static struct qcom_icc_node qhs_pcie3b_cfg = { 126 .name = "qhs_pcie3b_cfg", 127 .channels = 1, 128 .buswidth = 4, 129 }; 130 131 static struct qcom_icc_node qhs_pcie4_cfg = { 132 .name = "qhs_pcie4_cfg", 133 .channels = 1, 134 .buswidth = 4, 135 }; 136 137 static struct qcom_icc_node qhs_pcie5_cfg = { 138 .name = "qhs_pcie5_cfg", 139 .channels = 1, 140 .buswidth = 4, 141 }; 142 143 static struct qcom_icc_node qhs_pcie6_cfg = { 144 .name = "qhs_pcie6_cfg", 145 .channels = 1, 146 .buswidth = 4, 147 }; 148 149 static struct qcom_icc_node qhs_pcie_rscc = { 150 .name = "qhs_pcie_rscc", 151 .channels = 1, 152 .buswidth = 4, 153 }; 154 155 static struct qcom_icc_node qhs_pdm = { 156 .name = "qhs_pdm", 157 .channels = 1, 158 .buswidth = 4, 159 }; 160 161 static struct qcom_icc_node qhs_prng = { 162 .name = "qhs_prng", 163 .channels = 1, 164 .buswidth = 4, 165 }; 166 167 static struct qcom_icc_node qhs_qdss_cfg = { 168 .name = "qhs_qdss_cfg", 169 .channels = 1, 170 .buswidth = 4, 171 }; 172 173 static struct qcom_icc_node qhs_qspi = { 174 .name = "qhs_qspi", 175 .channels = 1, 176 .buswidth = 4, 177 }; 178 179 static struct qcom_icc_node qhs_qup0 = { 180 .name = "qhs_qup0", 181 .channels = 1, 182 .buswidth = 4, 183 }; 184 185 static struct qcom_icc_node qhs_qup1 = { 186 .name = "qhs_qup1", 187 .channels = 1, 188 .buswidth = 4, 189 }; 190 191 static struct qcom_icc_node qhs_qup2 = { 192 .name = "qhs_qup2", 193 .channels = 1, 194 .buswidth = 4, 195 }; 196 197 static struct qcom_icc_node qhs_sdc2 = { 198 .name = "qhs_sdc2", 199 .channels = 1, 200 .buswidth = 4, 201 }; 202 203 static struct qcom_icc_node qhs_sdc4 = { 204 .name = "qhs_sdc4", 205 .channels = 1, 206 .buswidth = 4, 207 }; 208 209 static struct qcom_icc_node qhs_smmuv3_cfg = { 210 .name = "qhs_smmuv3_cfg", 211 .channels = 1, 212 .buswidth = 8, 213 }; 214 215 static struct qcom_icc_node qhs_tcsr = { 216 .name = "qhs_tcsr", 217 .channels = 1, 218 .buswidth = 4, 219 }; 220 221 static struct qcom_icc_node qhs_tlmm = { 222 .name = "qhs_tlmm", 223 .channels = 1, 224 .buswidth = 4, 225 }; 226 227 static struct qcom_icc_node qhs_ufs_mem_cfg = { 228 .name = "qhs_ufs_mem_cfg", 229 .channels = 1, 230 .buswidth = 4, 231 }; 232 233 static struct qcom_icc_node qhs_usb2_0_cfg = { 234 .name = "qhs_usb2_0_cfg", 235 .channels = 1, 236 .buswidth = 4, 237 }; 238 239 static struct qcom_icc_node qhs_usb3_0_cfg = { 240 .name = "qhs_usb3_0_cfg", 241 .channels = 1, 242 .buswidth = 4, 243 }; 244 245 static struct qcom_icc_node qhs_usb3_1_cfg = { 246 .name = "qhs_usb3_1_cfg", 247 .channels = 1, 248 .buswidth = 4, 249 }; 250 251 static struct qcom_icc_node qhs_usb3_2_cfg = { 252 .name = "qhs_usb3_2_cfg", 253 .channels = 1, 254 .buswidth = 4, 255 }; 256 257 static struct qcom_icc_node qhs_usb3_mp_cfg = { 258 .name = "qhs_usb3_mp_cfg", 259 .channels = 1, 260 .buswidth = 4, 261 }; 262 263 static struct qcom_icc_node qhs_usb4_0_cfg = { 264 .name = "qhs_usb4_0_cfg", 265 .channels = 1, 266 .buswidth = 4, 267 }; 268 269 static struct qcom_icc_node qhs_usb4_1_cfg = { 270 .name = "qhs_usb4_1_cfg", 271 .channels = 1, 272 .buswidth = 4, 273 }; 274 275 static struct qcom_icc_node qhs_usb4_2_cfg = { 276 .name = "qhs_usb4_2_cfg", 277 .channels = 1, 278 .buswidth = 4, 279 }; 280 281 static struct qcom_icc_node qhs_venus_cfg = { 282 .name = "qhs_venus_cfg", 283 .channels = 1, 284 .buswidth = 4, 285 }; 286 287 static struct qcom_icc_node qss_lpass_qtb_cfg = { 288 .name = "qss_lpass_qtb_cfg", 289 .channels = 1, 290 .buswidth = 4, 291 }; 292 293 static struct qcom_icc_node qss_nsp_qtb_cfg = { 294 .name = "qss_nsp_qtb_cfg", 295 .channels = 1, 296 .buswidth = 4, 297 }; 298 299 static struct qcom_icc_node xs_qdss_stm = { 300 .name = "xs_qdss_stm", 301 .channels = 1, 302 .buswidth = 4, 303 }; 304 305 static struct qcom_icc_node xs_sys_tcu_cfg = { 306 .name = "xs_sys_tcu_cfg", 307 .channels = 1, 308 .buswidth = 8, 309 }; 310 311 static struct qcom_icc_node qhs_aoss = { 312 .name = "qhs_aoss", 313 .channels = 1, 314 .buswidth = 4, 315 }; 316 317 static struct qcom_icc_node qhs_ipc_router = { 318 .name = "qhs_ipc_router", 319 .channels = 1, 320 .buswidth = 4, 321 }; 322 323 static struct qcom_icc_node qhs_soccp = { 324 .name = "qhs_soccp", 325 .channels = 1, 326 .buswidth = 4, 327 }; 328 329 static struct qcom_icc_node qhs_tme_cfg = { 330 .name = "qhs_tme_cfg", 331 .channels = 1, 332 .buswidth = 4, 333 }; 334 335 static struct qcom_icc_node qns_apss = { 336 .name = "qns_apss", 337 .channels = 1, 338 .buswidth = 8, 339 }; 340 341 static struct qcom_icc_node qxs_boot_imem = { 342 .name = "qxs_boot_imem", 343 .channels = 1, 344 .buswidth = 16, 345 }; 346 347 static struct qcom_icc_node qxs_imem = { 348 .name = "qxs_imem", 349 .channels = 1, 350 .buswidth = 8, 351 }; 352 353 static struct qcom_icc_node ebi = { 354 .name = "ebi", 355 .channels = 12, 356 .buswidth = 4, 357 }; 358 359 static struct qcom_icc_node srvc_mnoc = { 360 .name = "srvc_mnoc", 361 .channels = 1, 362 .buswidth = 4, 363 }; 364 365 static struct qcom_icc_node srvc_nsinoc = { 366 .name = "srvc_nsinoc", 367 .channels = 1, 368 .buswidth = 4, 369 }; 370 371 static struct qcom_icc_node srvc_pcie_east_aggre_noc = { 372 .name = "srvc_pcie_east_aggre_noc", 373 .channels = 1, 374 .buswidth = 4, 375 }; 376 377 static struct qcom_icc_node qhs_hscnoc_pcie_east_ms_mpu_cfg = { 378 .name = "qhs_hscnoc_pcie_east_ms_mpu_cfg", 379 .channels = 1, 380 .buswidth = 4, 381 }; 382 383 static struct qcom_icc_node srvc_pcie_east = { 384 .name = "srvc_pcie_east", 385 .channels = 1, 386 .buswidth = 4, 387 }; 388 389 static struct qcom_icc_node xs_pcie_0 = { 390 .name = "xs_pcie_0", 391 .channels = 1, 392 .buswidth = 16, 393 }; 394 395 static struct qcom_icc_node xs_pcie_1 = { 396 .name = "xs_pcie_1", 397 .channels = 1, 398 .buswidth = 32, 399 }; 400 401 static struct qcom_icc_node xs_pcie_5 = { 402 .name = "xs_pcie_5", 403 .channels = 1, 404 .buswidth = 32, 405 }; 406 407 static struct qcom_icc_node srvc_pcie_west_aggre_noc = { 408 .name = "srvc_pcie_west_aggre_noc", 409 .channels = 1, 410 .buswidth = 4, 411 }; 412 413 static struct qcom_icc_node qhs_hscnoc_pcie_west_ms_mpu_cfg = { 414 .name = "qhs_hscnoc_pcie_west_ms_mpu_cfg", 415 .channels = 1, 416 .buswidth = 4, 417 }; 418 419 static struct qcom_icc_node srvc_pcie_west = { 420 .name = "srvc_pcie_west", 421 .channels = 1, 422 .buswidth = 4, 423 }; 424 425 static struct qcom_icc_node xs_pcie_2 = { 426 .name = "xs_pcie_2", 427 .channels = 1, 428 .buswidth = 16, 429 }; 430 431 static struct qcom_icc_node xs_pcie_3a = { 432 .name = "xs_pcie_3a", 433 .channels = 1, 434 .buswidth = 64, 435 }; 436 437 static struct qcom_icc_node xs_pcie_3b = { 438 .name = "xs_pcie_3b", 439 .channels = 1, 440 .buswidth = 32, 441 }; 442 443 static struct qcom_icc_node xs_pcie_4 = { 444 .name = "xs_pcie_4", 445 .channels = 1, 446 .buswidth = 16, 447 }; 448 449 static struct qcom_icc_node xs_pcie_6 = { 450 .name = "xs_pcie_6", 451 .channels = 1, 452 .buswidth = 16, 453 }; 454 455 static struct qcom_icc_node qup0_core_master = { 456 .name = "qup0_core_master", 457 .channels = 1, 458 .buswidth = 4, 459 .num_links = 1, 460 .link_nodes = (struct qcom_icc_node *[]) { &qup0_core_slave }, 461 }; 462 463 static struct qcom_icc_node qup1_core_master = { 464 .name = "qup1_core_master", 465 .channels = 1, 466 .buswidth = 4, 467 .num_links = 1, 468 .link_nodes = (struct qcom_icc_node *[]) { &qup1_core_slave }, 469 }; 470 471 static struct qcom_icc_node qup2_core_master = { 472 .name = "qup2_core_master", 473 .channels = 1, 474 .buswidth = 4, 475 .num_links = 1, 476 .link_nodes = (struct qcom_icc_node *[]) { &qup2_core_slave }, 477 }; 478 479 static struct qcom_icc_node llcc_mc = { 480 .name = "llcc_mc", 481 .channels = 12, 482 .buswidth = 4, 483 .num_links = 1, 484 .link_nodes = (struct qcom_icc_node *[]) { &ebi }, 485 }; 486 487 static struct qcom_icc_node qsm_mnoc_cfg = { 488 .name = "qsm_mnoc_cfg", 489 .channels = 1, 490 .buswidth = 4, 491 .num_links = 1, 492 .link_nodes = (struct qcom_icc_node *[]) { &srvc_mnoc }, 493 }; 494 495 static struct qcom_icc_node qsm_pcie_east_anoc_cfg = { 496 .name = "qsm_pcie_east_anoc_cfg", 497 .channels = 1, 498 .buswidth = 4, 499 .num_links = 1, 500 .link_nodes = (struct qcom_icc_node *[]) { &srvc_pcie_east_aggre_noc }, 501 }; 502 503 static struct qcom_icc_node qnm_hscnoc_pcie_east = { 504 .name = "qnm_hscnoc_pcie_east", 505 .channels = 1, 506 .buswidth = 32, 507 .num_links = 3, 508 .link_nodes = (struct qcom_icc_node *[]) { &xs_pcie_0, &xs_pcie_1, 509 &xs_pcie_5 }, 510 }; 511 512 static struct qcom_icc_node qsm_cnoc_pcie_east_slave_cfg = { 513 .name = "qsm_cnoc_pcie_east_slave_cfg", 514 .channels = 1, 515 .buswidth = 4, 516 .num_links = 2, 517 .link_nodes = (struct qcom_icc_node *[]) { &qhs_hscnoc_pcie_east_ms_mpu_cfg, 518 &srvc_pcie_east }, 519 }; 520 521 static struct qcom_icc_node qsm_pcie_west_anoc_cfg = { 522 .name = "qsm_pcie_west_anoc_cfg", 523 .channels = 1, 524 .buswidth = 4, 525 .num_links = 1, 526 .link_nodes = (struct qcom_icc_node *[]) { &srvc_pcie_west_aggre_noc }, 527 }; 528 529 static struct qcom_icc_node qnm_hscnoc_pcie_west = { 530 .name = "qnm_hscnoc_pcie_west", 531 .channels = 1, 532 .buswidth = 32, 533 .num_links = 5, 534 .link_nodes = (struct qcom_icc_node *[]) { &xs_pcie_2, &xs_pcie_3a, 535 &xs_pcie_3b, &xs_pcie_4, 536 &xs_pcie_6 }, 537 }; 538 539 static struct qcom_icc_node qsm_cnoc_pcie_west_slave_cfg = { 540 .name = "qsm_cnoc_pcie_west_slave_cfg", 541 .channels = 1, 542 .buswidth = 4, 543 .num_links = 2, 544 .link_nodes = (struct qcom_icc_node *[]) { &qhs_hscnoc_pcie_west_ms_mpu_cfg, 545 &srvc_pcie_west }, 546 }; 547 548 static struct qcom_icc_node qss_cnoc_pcie_slave_east_cfg = { 549 .name = "qss_cnoc_pcie_slave_east_cfg", 550 .channels = 1, 551 .buswidth = 4, 552 .num_links = 1, 553 .link_nodes = (struct qcom_icc_node *[]) { &qsm_cnoc_pcie_east_slave_cfg }, 554 }; 555 556 static struct qcom_icc_node qss_cnoc_pcie_slave_west_cfg = { 557 .name = "qss_cnoc_pcie_slave_west_cfg", 558 .channels = 1, 559 .buswidth = 4, 560 .num_links = 1, 561 .link_nodes = (struct qcom_icc_node *[]) { &qsm_cnoc_pcie_west_slave_cfg }, 562 }; 563 564 static struct qcom_icc_node qss_mnoc_cfg = { 565 .name = "qss_mnoc_cfg", 566 .channels = 1, 567 .buswidth = 4, 568 .num_links = 1, 569 .link_nodes = (struct qcom_icc_node *[]) { &qsm_mnoc_cfg }, 570 }; 571 572 static struct qcom_icc_node qss_pcie_east_anoc_cfg = { 573 .name = "qss_pcie_east_anoc_cfg", 574 .channels = 1, 575 .buswidth = 4, 576 .num_links = 1, 577 .link_nodes = (struct qcom_icc_node *[]) { &qsm_pcie_east_anoc_cfg }, 578 }; 579 580 static struct qcom_icc_node qss_pcie_west_anoc_cfg = { 581 .name = "qss_pcie_west_anoc_cfg", 582 .channels = 1, 583 .buswidth = 4, 584 .num_links = 1, 585 .link_nodes = (struct qcom_icc_node *[]) { &qsm_pcie_west_anoc_cfg }, 586 }; 587 588 static struct qcom_icc_node qns_llcc = { 589 .name = "qns_llcc", 590 .channels = 12, 591 .buswidth = 16, 592 .num_links = 1, 593 .link_nodes = (struct qcom_icc_node *[]) { &llcc_mc }, 594 }; 595 596 static struct qcom_icc_node qns_pcie_east = { 597 .name = "qns_pcie_east", 598 .channels = 1, 599 .buswidth = 32, 600 .num_links = 1, 601 .link_nodes = (struct qcom_icc_node *[]) { &qnm_hscnoc_pcie_east }, 602 }; 603 604 static struct qcom_icc_node qns_pcie_west = { 605 .name = "qns_pcie_west", 606 .channels = 1, 607 .buswidth = 32, 608 .num_links = 1, 609 .link_nodes = (struct qcom_icc_node *[]) { &qnm_hscnoc_pcie_west }, 610 }; 611 612 static struct qcom_icc_node qsm_cfg = { 613 .name = "qsm_cfg", 614 .channels = 1, 615 .buswidth = 4, 616 .num_links = 51, 617 .link_nodes = (struct qcom_icc_node *[]) { &qhs_ahb2phy0, &qhs_ahb2phy1, 618 &qhs_ahb2phy2, &qhs_ahb2phy3, 619 &qhs_av1_enc_cfg, &qhs_camera_cfg, 620 &qhs_clk_ctl, &qhs_crypto0_cfg, 621 &qhs_display_cfg, &qhs_gpuss_cfg, 622 &qhs_imem_cfg, &qhs_pcie0_cfg, 623 &qhs_pcie1_cfg, &qhs_pcie2_cfg, 624 &qhs_pcie3a_cfg, &qhs_pcie3b_cfg, 625 &qhs_pcie4_cfg, &qhs_pcie5_cfg, 626 &qhs_pcie6_cfg, &qhs_pcie_rscc, 627 &qhs_pdm, &qhs_prng, 628 &qhs_qdss_cfg, &qhs_qspi, 629 &qhs_qup0, &qhs_qup1, 630 &qhs_qup2, &qhs_sdc2, 631 &qhs_sdc4, &qhs_smmuv3_cfg, 632 &qhs_tcsr, &qhs_tlmm, 633 &qhs_ufs_mem_cfg, &qhs_usb2_0_cfg, 634 &qhs_usb3_0_cfg, &qhs_usb3_1_cfg, 635 &qhs_usb3_2_cfg, &qhs_usb3_mp_cfg, 636 &qhs_usb4_0_cfg, &qhs_usb4_1_cfg, 637 &qhs_usb4_2_cfg, &qhs_venus_cfg, 638 &qss_cnoc_pcie_slave_east_cfg, &qss_cnoc_pcie_slave_west_cfg, 639 &qss_lpass_qtb_cfg, &qss_mnoc_cfg, 640 &qss_nsp_qtb_cfg, &qss_pcie_east_anoc_cfg, 641 &qss_pcie_west_anoc_cfg, &xs_qdss_stm, 642 &xs_sys_tcu_cfg }, 643 }; 644 645 static struct qcom_icc_node xm_gic = { 646 .name = "xm_gic", 647 .channels = 1, 648 .buswidth = 8, 649 .qosbox = &(const struct qcom_icc_qosbox) { 650 .num_ports = 1, 651 .port_offsets = { 0x33000 }, 652 .prio = 0, 653 .urg_fwd = 1, 654 .prio_fwd_disable = 0, 655 }, 656 .num_links = 1, 657 .link_nodes = (struct qcom_icc_node *[]) { &qns_llcc }, 658 }; 659 660 static struct qcom_icc_node qss_cfg = { 661 .name = "qss_cfg", 662 .channels = 1, 663 .buswidth = 4, 664 .num_links = 1, 665 .link_nodes = (struct qcom_icc_node *[]) { &qsm_cfg }, 666 }; 667 668 static struct qcom_icc_node qnm_hscnoc_cnoc = { 669 .name = "qnm_hscnoc_cnoc", 670 .channels = 1, 671 .buswidth = 16, 672 .num_links = 8, 673 .link_nodes = (struct qcom_icc_node *[]) { &qhs_aoss, &qhs_ipc_router, 674 &qhs_soccp, &qhs_tme_cfg, 675 &qns_apss, &qss_cfg, 676 &qxs_boot_imem, &qxs_imem }, 677 }; 678 679 static struct qcom_icc_node qns_hscnoc_cnoc = { 680 .name = "qns_hscnoc_cnoc", 681 .channels = 1, 682 .buswidth = 16, 683 .num_links = 1, 684 .link_nodes = (struct qcom_icc_node *[]) { &qnm_hscnoc_cnoc }, 685 }; 686 687 static struct qcom_icc_node alm_gpu_tcu = { 688 .name = "alm_gpu_tcu", 689 .channels = 1, 690 .buswidth = 8, 691 .qosbox = &(const struct qcom_icc_qosbox) { 692 .num_ports = 1, 693 .port_offsets = { 0x933000 }, 694 .prio = 1, 695 .urg_fwd = 0, 696 .prio_fwd_disable = 1, 697 }, 698 .num_links = 2, 699 .link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc }, 700 }; 701 702 static struct qcom_icc_node alm_pcie_qtc = { 703 .name = "alm_pcie_qtc", 704 .channels = 1, 705 .buswidth = 8, 706 .qosbox = &(const struct qcom_icc_qosbox) { 707 .num_ports = 1, 708 .port_offsets = { 0x51f000 }, 709 .prio = 3, 710 .urg_fwd = 0, 711 .prio_fwd_disable = 1, 712 }, 713 .num_links = 2, 714 .link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc }, 715 }; 716 717 static struct qcom_icc_node alm_sys_tcu = { 718 .name = "alm_sys_tcu", 719 .channels = 1, 720 .buswidth = 8, 721 .qosbox = &(const struct qcom_icc_qosbox) { 722 .num_ports = 1, 723 .port_offsets = { 0x51f080 }, 724 .prio = 6, 725 .urg_fwd = 0, 726 .prio_fwd_disable = 1, 727 }, 728 .num_links = 2, 729 .link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc }, 730 }; 731 732 static struct qcom_icc_node chm_apps = { 733 .name = "chm_apps", 734 .channels = 6, 735 .buswidth = 32, 736 .num_links = 4, 737 .link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, 738 &qns_pcie_east, &qns_pcie_west }, 739 }; 740 741 static struct qcom_icc_node qnm_aggre_noc_east = { 742 .name = "qnm_aggre_noc_east", 743 .channels = 1, 744 .buswidth = 32, 745 .qosbox = &(const struct qcom_icc_qosbox) { 746 .num_ports = 1, 747 .port_offsets = { 0x934000 }, 748 .prio = 2, 749 .urg_fwd = 1, 750 .prio_fwd_disable = 1, 751 }, 752 .num_links = 4, 753 .link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, 754 &qns_pcie_east, &qns_pcie_west }, 755 }; 756 757 static struct qcom_icc_node qnm_gpu = { 758 .name = "qnm_gpu", 759 .channels = 4, 760 .buswidth = 32, 761 .qosbox = &(const struct qcom_icc_qosbox) { 762 .num_ports = 4, 763 .port_offsets = { 0x935000, 0x936000, 0x937000, 0x938000 }, 764 .prio = 0, 765 .urg_fwd = 1, 766 .prio_fwd_disable = 1, 767 }, 768 .num_links = 4, 769 .link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, 770 &qns_pcie_east, &qns_pcie_west }, 771 }; 772 773 static struct qcom_icc_node qnm_lpass = { 774 .name = "qnm_lpass", 775 .channels = 1, 776 .buswidth = 16, 777 .qosbox = &(const struct qcom_icc_qosbox) { 778 .num_ports = 1, 779 .port_offsets = { 0x939000 }, 780 .prio = 0, 781 .urg_fwd = 1, 782 .prio_fwd_disable = 0, 783 }, 784 .num_links = 4, 785 .link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, 786 &qns_pcie_east, &qns_pcie_west }, 787 }; 788 789 static struct qcom_icc_node qnm_mnoc_hf = { 790 .name = "qnm_mnoc_hf", 791 .channels = 2, 792 .buswidth = 32, 793 .qosbox = &(const struct qcom_icc_qosbox) { 794 .num_ports = 2, 795 .port_offsets = { 0x721000, 0x721080 }, 796 .prio = 0, 797 .urg_fwd = 1, 798 .prio_fwd_disable = 0, 799 }, 800 .num_links = 4, 801 .link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, 802 &qns_pcie_east, &qns_pcie_west }, 803 }; 804 805 static struct qcom_icc_node qnm_mnoc_sf = { 806 .name = "qnm_mnoc_sf", 807 .channels = 2, 808 .buswidth = 32, 809 .qosbox = &(const struct qcom_icc_qosbox) { 810 .num_ports = 2, 811 .port_offsets = { 0x721100, 0x721180 }, 812 .prio = 0, 813 .urg_fwd = 1, 814 .prio_fwd_disable = 0, 815 }, 816 .num_links = 4, 817 .link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, 818 &qns_pcie_east, &qns_pcie_west }, 819 }; 820 821 static struct qcom_icc_node qnm_nsp_noc = { 822 .name = "qnm_nsp_noc", 823 .channels = 4, 824 .buswidth = 32, 825 .qosbox = &(const struct qcom_icc_qosbox) { 826 .num_ports = 4, 827 .port_offsets = { 0x816000, 0x816080, 0x816100, 0x816180 }, 828 .prio = 0, 829 .urg_fwd = 1, 830 .prio_fwd_disable = 1, 831 }, 832 .num_links = 4, 833 .link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, 834 &qns_pcie_east, &qns_pcie_west }, 835 }; 836 837 static struct qcom_icc_node qnm_pcie_east = { 838 .name = "qnm_pcie_east", 839 .channels = 1, 840 .buswidth = 32, 841 .qosbox = &(const struct qcom_icc_qosbox) { 842 .num_ports = 1, 843 .port_offsets = { 0x93a000 }, 844 .prio = 2, 845 .urg_fwd = 1, 846 .prio_fwd_disable = 1, 847 }, 848 .num_links = 2, 849 .link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc }, 850 }; 851 852 static struct qcom_icc_node qnm_pcie_west = { 853 .name = "qnm_pcie_west", 854 .channels = 1, 855 .buswidth = 64, 856 .qosbox = &(const struct qcom_icc_qosbox) { 857 .num_ports = 1, 858 .port_offsets = { 0x721200 }, 859 .prio = 2, 860 .urg_fwd = 1, 861 .prio_fwd_disable = 1, 862 }, 863 .num_links = 2, 864 .link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc }, 865 }; 866 867 static struct qcom_icc_node qnm_snoc_sf = { 868 .name = "qnm_snoc_sf", 869 .channels = 1, 870 .buswidth = 64, 871 .qosbox = &(const struct qcom_icc_qosbox) { 872 .num_ports = 1, 873 .port_offsets = { 0x51f100 }, 874 .prio = 2, 875 .urg_fwd = 1, 876 .prio_fwd_disable = 1, 877 }, 878 .num_links = 4, 879 .link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, 880 &qns_pcie_east, &qns_pcie_west }, 881 }; 882 883 static struct qcom_icc_node qxm_wlan_q6 = { 884 .name = "qxm_wlan_q6", 885 .channels = 1, 886 .buswidth = 8, 887 .num_links = 4, 888 .link_nodes = (struct qcom_icc_node *[]) { &qns_hscnoc_cnoc, &qns_llcc, 889 &qns_pcie_east, &qns_pcie_west }, 890 }; 891 892 static struct qcom_icc_node qns_a4noc_hscnoc = { 893 .name = "qns_a4noc_hscnoc", 894 .channels = 1, 895 .buswidth = 32, 896 .num_links = 1, 897 .link_nodes = (struct qcom_icc_node *[]) { &qnm_aggre_noc_east }, 898 }; 899 900 static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = { 901 .name = "qns_lpass_ag_noc_gemnoc", 902 .channels = 1, 903 .buswidth = 16, 904 .num_links = 1, 905 .link_nodes = (struct qcom_icc_node *[]) { &qnm_lpass }, 906 }; 907 908 static struct qcom_icc_node qns_mem_noc_hf = { 909 .name = "qns_mem_noc_hf", 910 .channels = 2, 911 .buswidth = 32, 912 .num_links = 1, 913 .link_nodes = (struct qcom_icc_node *[]) { &qnm_mnoc_hf }, 914 }; 915 916 static struct qcom_icc_node qns_mem_noc_sf = { 917 .name = "qns_mem_noc_sf", 918 .channels = 2, 919 .buswidth = 32, 920 .num_links = 1, 921 .link_nodes = (struct qcom_icc_node *[]) { &qnm_mnoc_sf }, 922 }; 923 924 static struct qcom_icc_node qns_nsp_hscnoc = { 925 .name = "qns_nsp_hscnoc", 926 .channels = 4, 927 .buswidth = 32, 928 .num_links = 1, 929 .link_nodes = (struct qcom_icc_node *[]) { &qnm_nsp_noc }, 930 }; 931 932 static struct qcom_icc_node qns_pcie_east_mem_noc = { 933 .name = "qns_pcie_east_mem_noc", 934 .channels = 1, 935 .buswidth = 32, 936 .num_links = 1, 937 .link_nodes = (struct qcom_icc_node *[]) { &qnm_pcie_east }, 938 }; 939 940 static struct qcom_icc_node qns_pcie_west_mem_noc = { 941 .name = "qns_pcie_west_mem_noc", 942 .channels = 1, 943 .buswidth = 64, 944 .num_links = 1, 945 .link_nodes = (struct qcom_icc_node *[]) { &qnm_pcie_west }, 946 }; 947 948 static struct qcom_icc_node qns_gemnoc_sf = { 949 .name = "qns_gemnoc_sf", 950 .channels = 1, 951 .buswidth = 64, 952 .num_links = 1, 953 .link_nodes = (struct qcom_icc_node *[]) { &qnm_snoc_sf }, 954 }; 955 956 static struct qcom_icc_node xm_usb3_0 = { 957 .name = "xm_usb3_0", 958 .channels = 1, 959 .buswidth = 8, 960 .qosbox = &(const struct qcom_icc_qosbox) { 961 .num_ports = 1, 962 .port_offsets = { 0xa000 }, 963 .prio = 0, 964 .urg_fwd = 0, 965 .prio_fwd_disable = 1, 966 }, 967 .num_links = 1, 968 .link_nodes = (struct qcom_icc_node *[]) { &qns_a4noc_hscnoc }, 969 }; 970 971 static struct qcom_icc_node xm_usb3_1 = { 972 .name = "xm_usb3_1", 973 .channels = 1, 974 .buswidth = 8, 975 .qosbox = &(const struct qcom_icc_qosbox) { 976 .num_ports = 1, 977 .port_offsets = { 0xb000 }, 978 .prio = 0, 979 .urg_fwd = 0, 980 .prio_fwd_disable = 1, 981 }, 982 .num_links = 1, 983 .link_nodes = (struct qcom_icc_node *[]) { &qns_a4noc_hscnoc }, 984 }; 985 986 static struct qcom_icc_node xm_usb4_0 = { 987 .name = "xm_usb4_0", 988 .channels = 1, 989 .buswidth = 16, 990 .qosbox = &(const struct qcom_icc_qosbox) { 991 .num_ports = 1, 992 .port_offsets = { 0xc000 }, 993 .prio = 0, 994 .urg_fwd = 0, 995 .prio_fwd_disable = 1, 996 }, 997 .num_links = 1, 998 .link_nodes = (struct qcom_icc_node *[]) { &qns_a4noc_hscnoc }, 999 }; 1000 1001 static struct qcom_icc_node xm_usb4_1 = { 1002 .name = "xm_usb4_1", 1003 .channels = 1, 1004 .buswidth = 32, 1005 .qosbox = &(const struct qcom_icc_qosbox) { 1006 .num_ports = 1, 1007 .port_offsets = { 0xd000 }, 1008 .prio = 0, 1009 .urg_fwd = 0, 1010 .prio_fwd_disable = 1, 1011 }, 1012 .num_links = 1, 1013 .link_nodes = (struct qcom_icc_node *[]) { &qns_a4noc_hscnoc }, 1014 }; 1015 1016 static struct qcom_icc_node qnm_lpiaon_noc = { 1017 .name = "qnm_lpiaon_noc", 1018 .channels = 1, 1019 .buswidth = 16, 1020 .num_links = 1, 1021 .link_nodes = (struct qcom_icc_node *[]) { &qns_lpass_ag_noc_gemnoc }, 1022 }; 1023 1024 static struct qcom_icc_node qnm_av1_enc = { 1025 .name = "qnm_av1_enc", 1026 .channels = 1, 1027 .buswidth = 32, 1028 .qosbox = &(const struct qcom_icc_qosbox) { 1029 .num_ports = 1, 1030 .port_offsets = { 0x30000 }, 1031 .prio = 4, 1032 .urg_fwd = 1, 1033 .prio_fwd_disable = 1, 1034 }, 1035 .num_links = 1, 1036 .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, 1037 }; 1038 1039 static struct qcom_icc_node qnm_camnoc_hf = { 1040 .name = "qnm_camnoc_hf", 1041 .channels = 2, 1042 .buswidth = 32, 1043 .qosbox = &(const struct qcom_icc_qosbox) { 1044 .num_ports = 2, 1045 .port_offsets = { 0x29000, 0x2a000 }, 1046 .prio = 0, 1047 .urg_fwd = 1, 1048 .prio_fwd_disable = 0, 1049 }, 1050 .num_links = 1, 1051 .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, 1052 }; 1053 1054 static struct qcom_icc_node qnm_camnoc_icp = { 1055 .name = "qnm_camnoc_icp", 1056 .channels = 1, 1057 .buswidth = 8, 1058 .qosbox = &(const struct qcom_icc_qosbox) { 1059 .num_ports = 1, 1060 .port_offsets = { 0x2b000 }, 1061 .prio = 4, 1062 .urg_fwd = 1, 1063 .prio_fwd_disable = 1, 1064 }, 1065 .num_links = 1, 1066 .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, 1067 }; 1068 1069 static struct qcom_icc_node qnm_camnoc_sf = { 1070 .name = "qnm_camnoc_sf", 1071 .channels = 2, 1072 .buswidth = 32, 1073 .qosbox = &(const struct qcom_icc_qosbox) { 1074 .num_ports = 2, 1075 .port_offsets = { 0x2c000, 0x2d000 }, 1076 .prio = 0, 1077 .urg_fwd = 1, 1078 .prio_fwd_disable = 0, 1079 }, 1080 .num_links = 1, 1081 .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, 1082 }; 1083 1084 static struct qcom_icc_node qnm_eva = { 1085 .name = "qnm_eva", 1086 .channels = 1, 1087 .buswidth = 32, 1088 .qosbox = &(const struct qcom_icc_qosbox) { 1089 .num_ports = 1, 1090 .port_offsets = { 0x34000 }, 1091 .prio = 0, 1092 .urg_fwd = 1, 1093 .prio_fwd_disable = 0, 1094 }, 1095 .num_links = 1, 1096 .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, 1097 }; 1098 1099 static struct qcom_icc_node qnm_mdp = { 1100 .name = "qnm_mdp", 1101 .channels = 2, 1102 .buswidth = 32, 1103 .qosbox = &(const struct qcom_icc_qosbox) { 1104 .num_ports = 2, 1105 .port_offsets = { 0x2e000, 0x2f000 }, 1106 .prio = 0, 1107 .urg_fwd = 1, 1108 .prio_fwd_disable = 0, 1109 }, 1110 .num_links = 1, 1111 .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_hf }, 1112 }; 1113 1114 static struct qcom_icc_node qnm_vapss_hcp = { 1115 .name = "qnm_vapss_hcp", 1116 .channels = 1, 1117 .buswidth = 32, 1118 .num_links = 1, 1119 .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, 1120 }; 1121 1122 static struct qcom_icc_node qnm_video = { 1123 .name = "qnm_video", 1124 .channels = 4, 1125 .buswidth = 32, 1126 .qosbox = &(const struct qcom_icc_qosbox) { 1127 .num_ports = 4, 1128 .port_offsets = { 0x31000, 0x32000, 0x37000, 0x38000 }, 1129 .prio = 0, 1130 .urg_fwd = 1, 1131 .prio_fwd_disable = 0, 1132 }, 1133 .num_links = 1, 1134 .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, 1135 }; 1136 1137 static struct qcom_icc_node qnm_video_cv_cpu = { 1138 .name = "qnm_video_cv_cpu", 1139 .channels = 1, 1140 .buswidth = 8, 1141 .qosbox = &(const struct qcom_icc_qosbox) { 1142 .num_ports = 1, 1143 .port_offsets = { 0x33000 }, 1144 .prio = 4, 1145 .urg_fwd = 1, 1146 .prio_fwd_disable = 1, 1147 }, 1148 .num_links = 1, 1149 .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, 1150 }; 1151 1152 static struct qcom_icc_node qnm_video_v_cpu = { 1153 .name = "qnm_video_v_cpu", 1154 .channels = 1, 1155 .buswidth = 8, 1156 .qosbox = &(const struct qcom_icc_qosbox) { 1157 .num_ports = 1, 1158 .port_offsets = { 0x35000 }, 1159 .prio = 4, 1160 .urg_fwd = 1, 1161 .prio_fwd_disable = 1, 1162 }, 1163 .num_links = 1, 1164 .link_nodes = (struct qcom_icc_node *[]) { &qns_mem_noc_sf }, 1165 }; 1166 1167 static struct qcom_icc_node qnm_nsp = { 1168 .name = "qnm_nsp", 1169 .channels = 4, 1170 .buswidth = 32, 1171 .num_links = 1, 1172 .link_nodes = (struct qcom_icc_node *[]) { &qns_nsp_hscnoc }, 1173 }; 1174 1175 static struct qcom_icc_node xm_pcie_0 = { 1176 .name = "xm_pcie_0", 1177 .channels = 1, 1178 .buswidth = 16, 1179 .qosbox = &(const struct qcom_icc_qosbox) { 1180 .num_ports = 1, 1181 .port_offsets = { 0xb000 }, 1182 .prio = 2, 1183 .urg_fwd = 0, 1184 .prio_fwd_disable = 0, 1185 }, 1186 .num_links = 1, 1187 .link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_east_mem_noc }, 1188 }; 1189 1190 static struct qcom_icc_node xm_pcie_1 = { 1191 .name = "xm_pcie_1", 1192 .channels = 1, 1193 .buswidth = 32, 1194 .qosbox = &(const struct qcom_icc_qosbox) { 1195 .num_ports = 1, 1196 .port_offsets = { 0xc000 }, 1197 .prio = 2, 1198 .urg_fwd = 0, 1199 .prio_fwd_disable = 0, 1200 }, 1201 .num_links = 1, 1202 .link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_east_mem_noc }, 1203 }; 1204 1205 static struct qcom_icc_node xm_pcie_5 = { 1206 .name = "xm_pcie_5", 1207 .channels = 1, 1208 .buswidth = 32, 1209 .qosbox = &(const struct qcom_icc_qosbox) { 1210 .num_ports = 1, 1211 .port_offsets = { 0xd000 }, 1212 .prio = 2, 1213 .urg_fwd = 0, 1214 .prio_fwd_disable = 0, 1215 }, 1216 .num_links = 1, 1217 .link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_east_mem_noc }, 1218 }; 1219 1220 static struct qcom_icc_node xm_pcie_2 = { 1221 .name = "xm_pcie_2", 1222 .channels = 1, 1223 .buswidth = 16, 1224 .qosbox = &(const struct qcom_icc_qosbox) { 1225 .num_ports = 1, 1226 .port_offsets = { 0xd000 }, 1227 .prio = 2, 1228 .urg_fwd = 0, 1229 .prio_fwd_disable = 0, 1230 }, 1231 .num_links = 1, 1232 .link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_west_mem_noc }, 1233 }; 1234 1235 static struct qcom_icc_node xm_pcie_3a = { 1236 .name = "xm_pcie_3a", 1237 .channels = 1, 1238 .buswidth = 64, 1239 .qosbox = &(const struct qcom_icc_qosbox) { 1240 .num_ports = 1, 1241 .port_offsets = { 0xd200 }, 1242 .prio = 2, 1243 .urg_fwd = 0, 1244 .prio_fwd_disable = 0, 1245 }, 1246 .num_links = 1, 1247 .link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_west_mem_noc }, 1248 }; 1249 1250 static struct qcom_icc_node xm_pcie_3b = { 1251 .name = "xm_pcie_3b", 1252 .channels = 1, 1253 .buswidth = 32, 1254 .qosbox = &(const struct qcom_icc_qosbox) { 1255 .num_ports = 1, 1256 .port_offsets = { 0xd400 }, 1257 .prio = 2, 1258 .urg_fwd = 0, 1259 .prio_fwd_disable = 0, 1260 }, 1261 .num_links = 1, 1262 .link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_west_mem_noc }, 1263 }; 1264 1265 static struct qcom_icc_node xm_pcie_4 = { 1266 .name = "xm_pcie_4", 1267 .channels = 1, 1268 .buswidth = 16, 1269 .qosbox = &(const struct qcom_icc_qosbox) { 1270 .num_ports = 1, 1271 .port_offsets = { 0xd600 }, 1272 .prio = 2, 1273 .urg_fwd = 0, 1274 .prio_fwd_disable = 0, 1275 }, 1276 .num_links = 1, 1277 .link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_west_mem_noc }, 1278 }; 1279 1280 static struct qcom_icc_node xm_pcie_6 = { 1281 .name = "xm_pcie_6", 1282 .channels = 1, 1283 .buswidth = 16, 1284 .qosbox = &(const struct qcom_icc_qosbox) { 1285 .num_ports = 1, 1286 .port_offsets = { 0xd800 }, 1287 .prio = 2, 1288 .urg_fwd = 0, 1289 .prio_fwd_disable = 0, 1290 }, 1291 .num_links = 1, 1292 .link_nodes = (struct qcom_icc_node *[]) { &qns_pcie_west_mem_noc }, 1293 }; 1294 1295 static struct qcom_icc_node qnm_aggre1_noc = { 1296 .name = "qnm_aggre1_noc", 1297 .channels = 1, 1298 .buswidth = 16, 1299 .num_links = 1, 1300 .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, 1301 }; 1302 1303 static struct qcom_icc_node qnm_aggre2_noc = { 1304 .name = "qnm_aggre2_noc", 1305 .channels = 1, 1306 .buswidth = 16, 1307 .num_links = 1, 1308 .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, 1309 }; 1310 1311 static struct qcom_icc_node qnm_aggre3_noc = { 1312 .name = "qnm_aggre3_noc", 1313 .channels = 1, 1314 .buswidth = 32, 1315 .num_links = 1, 1316 .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, 1317 }; 1318 1319 static struct qcom_icc_node qnm_nsi_noc = { 1320 .name = "qnm_nsi_noc", 1321 .channels = 1, 1322 .buswidth = 8, 1323 .qosbox = &(const struct qcom_icc_qosbox) { 1324 .num_ports = 1, 1325 .port_offsets = { 0x1c000 }, 1326 .prio = 0, 1327 .urg_fwd = 0, 1328 .prio_fwd_disable = 1, 1329 }, 1330 .num_links = 1, 1331 .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, 1332 }; 1333 1334 static struct qcom_icc_node qnm_oobmss = { 1335 .name = "qnm_oobmss", 1336 .channels = 1, 1337 .buswidth = 16, 1338 .qosbox = &(const struct qcom_icc_qosbox) { 1339 .num_ports = 1, 1340 .port_offsets = { 0x1b000 }, 1341 .prio = 0, 1342 .urg_fwd = 0, 1343 .prio_fwd_disable = 1, 1344 }, 1345 .num_links = 1, 1346 .link_nodes = (struct qcom_icc_node *[]) { &qns_gemnoc_sf }, 1347 }; 1348 1349 static struct qcom_icc_node qns_a1noc_snoc = { 1350 .name = "qns_a1noc_snoc", 1351 .channels = 1, 1352 .buswidth = 16, 1353 .num_links = 1, 1354 .link_nodes = (struct qcom_icc_node *[]) { &qnm_aggre1_noc }, 1355 }; 1356 1357 static struct qcom_icc_node qns_a2noc_snoc = { 1358 .name = "qns_a2noc_snoc", 1359 .channels = 1, 1360 .buswidth = 16, 1361 .num_links = 1, 1362 .link_nodes = (struct qcom_icc_node *[]) { &qnm_aggre2_noc }, 1363 }; 1364 1365 static struct qcom_icc_node qns_a3noc_snoc = { 1366 .name = "qns_a3noc_snoc", 1367 .channels = 1, 1368 .buswidth = 32, 1369 .num_links = 1, 1370 .link_nodes = (struct qcom_icc_node *[]) { &qnm_aggre3_noc }, 1371 }; 1372 1373 static struct qcom_icc_node qns_lpass_aggnoc = { 1374 .name = "qns_lpass_aggnoc", 1375 .channels = 1, 1376 .buswidth = 16, 1377 .num_links = 1, 1378 .link_nodes = (struct qcom_icc_node *[]) { &qnm_lpiaon_noc }, 1379 }; 1380 1381 static struct qcom_icc_node qns_system_noc = { 1382 .name = "qns_system_noc", 1383 .channels = 1, 1384 .buswidth = 8, 1385 .num_links = 1, 1386 .link_nodes = (struct qcom_icc_node *[]) { &qnm_nsi_noc }, 1387 }; 1388 1389 static struct qcom_icc_node qns_oobmss_snoc = { 1390 .name = "qns_oobmss_snoc", 1391 .channels = 1, 1392 .buswidth = 16, 1393 .num_links = 1, 1394 .link_nodes = (struct qcom_icc_node *[]) { &qnm_oobmss }, 1395 }; 1396 1397 static struct qcom_icc_node qxm_crypto = { 1398 .name = "qxm_crypto", 1399 .channels = 1, 1400 .buswidth = 8, 1401 .qosbox = &(const struct qcom_icc_qosbox) { 1402 .num_ports = 1, 1403 .port_offsets = { 0xb000 }, 1404 .prio = 0, 1405 .urg_fwd = 1, 1406 .prio_fwd_disable = 1, 1407 }, 1408 .num_links = 1, 1409 .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, 1410 }; 1411 1412 static struct qcom_icc_node qxm_soccp = { 1413 .name = "qxm_soccp", 1414 .channels = 1, 1415 .buswidth = 8, 1416 .qosbox = &(const struct qcom_icc_qosbox) { 1417 .num_ports = 1, 1418 .port_offsets = { 0xe000 }, 1419 .prio = 0, 1420 .urg_fwd = 1, 1421 .prio_fwd_disable = 1, 1422 }, 1423 .num_links = 1, 1424 .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, 1425 }; 1426 1427 static struct qcom_icc_node xm_qdss_etr_0 = { 1428 .name = "xm_qdss_etr_0", 1429 .channels = 1, 1430 .buswidth = 8, 1431 .qosbox = &(const struct qcom_icc_qosbox) { 1432 .num_ports = 1, 1433 .port_offsets = { 0xc000 }, 1434 .prio = 0, 1435 .urg_fwd = 0, 1436 .prio_fwd_disable = 1, 1437 }, 1438 .num_links = 1, 1439 .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, 1440 }; 1441 1442 static struct qcom_icc_node xm_qdss_etr_1 = { 1443 .name = "xm_qdss_etr_1", 1444 .channels = 1, 1445 .buswidth = 8, 1446 .qosbox = &(const struct qcom_icc_qosbox) { 1447 .num_ports = 1, 1448 .port_offsets = { 0xd000 }, 1449 .prio = 0, 1450 .urg_fwd = 0, 1451 .prio_fwd_disable = 1, 1452 }, 1453 .num_links = 1, 1454 .link_nodes = (struct qcom_icc_node *[]) { &qns_a1noc_snoc }, 1455 }; 1456 1457 static struct qcom_icc_node xm_ufs_mem = { 1458 .name = "xm_ufs_mem", 1459 .channels = 1, 1460 .buswidth = 16, 1461 .qosbox = &(const struct qcom_icc_qosbox) { 1462 .num_ports = 1, 1463 .port_offsets = { 0xa000 }, 1464 .prio = 0, 1465 .urg_fwd = 0, 1466 .prio_fwd_disable = 1, 1467 }, 1468 .num_links = 1, 1469 .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, 1470 }; 1471 1472 static struct qcom_icc_node xm_usb3_2 = { 1473 .name = "xm_usb3_2", 1474 .channels = 1, 1475 .buswidth = 8, 1476 .qosbox = &(const struct qcom_icc_qosbox) { 1477 .num_ports = 1, 1478 .port_offsets = { 0x8000 }, 1479 .prio = 0, 1480 .urg_fwd = 0, 1481 .prio_fwd_disable = 1, 1482 }, 1483 .num_links = 1, 1484 .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, 1485 }; 1486 1487 static struct qcom_icc_node xm_usb4_2 = { 1488 .name = "xm_usb4_2", 1489 .channels = 1, 1490 .buswidth = 16, 1491 .qosbox = &(const struct qcom_icc_qosbox) { 1492 .num_ports = 1, 1493 .port_offsets = { 0x9000 }, 1494 .prio = 0, 1495 .urg_fwd = 0, 1496 .prio_fwd_disable = 1, 1497 }, 1498 .num_links = 1, 1499 .link_nodes = (struct qcom_icc_node *[]) { &qns_a2noc_snoc }, 1500 }; 1501 1502 static struct qcom_icc_node qhm_qspi = { 1503 .name = "qhm_qspi", 1504 .channels = 1, 1505 .buswidth = 4, 1506 .qosbox = &(const struct qcom_icc_qosbox) { 1507 .num_ports = 1, 1508 .port_offsets = { 0x10000 }, 1509 .prio = 0, 1510 .urg_fwd = 0, 1511 .prio_fwd_disable = 1, 1512 }, 1513 .num_links = 1, 1514 .link_nodes = (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, 1515 }; 1516 1517 static struct qcom_icc_node qhm_qup0 = { 1518 .name = "qhm_qup0", 1519 .channels = 1, 1520 .buswidth = 4, 1521 .qosbox = &(const struct qcom_icc_qosbox) { 1522 .num_ports = 1, 1523 .port_offsets = { 0x11000 }, 1524 .prio = 0, 1525 .urg_fwd = 0, 1526 .prio_fwd_disable = 1, 1527 }, 1528 .num_links = 1, 1529 .link_nodes = (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, 1530 }; 1531 1532 static struct qcom_icc_node qhm_qup1 = { 1533 .name = "qhm_qup1", 1534 .channels = 1, 1535 .buswidth = 4, 1536 .qosbox = &(const struct qcom_icc_qosbox) { 1537 .num_ports = 1, 1538 .port_offsets = { 0x12000 }, 1539 .prio = 0, 1540 .urg_fwd = 0, 1541 .prio_fwd_disable = 1, 1542 }, 1543 .num_links = 1, 1544 .link_nodes = (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, 1545 }; 1546 1547 static struct qcom_icc_node qhm_qup2 = { 1548 .name = "qhm_qup2", 1549 .channels = 1, 1550 .buswidth = 4, 1551 .qosbox = &(const struct qcom_icc_qosbox) { 1552 .num_ports = 1, 1553 .port_offsets = { 0x13000 }, 1554 .prio = 0, 1555 .urg_fwd = 0, 1556 .prio_fwd_disable = 1, 1557 }, 1558 .num_links = 1, 1559 .link_nodes = (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, 1560 }; 1561 1562 static struct qcom_icc_node qxm_sp = { 1563 .name = "qxm_sp", 1564 .channels = 1, 1565 .buswidth = 8, 1566 .num_links = 1, 1567 .link_nodes = (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, 1568 }; 1569 1570 static struct qcom_icc_node xm_sdc2 = { 1571 .name = "xm_sdc2", 1572 .channels = 1, 1573 .buswidth = 8, 1574 .qosbox = &(const struct qcom_icc_qosbox) { 1575 .num_ports = 1, 1576 .port_offsets = { 0x18000 }, 1577 .prio = 0, 1578 .urg_fwd = 0, 1579 .prio_fwd_disable = 1, 1580 }, 1581 .num_links = 1, 1582 .link_nodes = (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, 1583 }; 1584 1585 static struct qcom_icc_node xm_sdc4 = { 1586 .name = "xm_sdc4", 1587 .channels = 1, 1588 .buswidth = 8, 1589 .qosbox = &(const struct qcom_icc_qosbox) { 1590 .num_ports = 1, 1591 .port_offsets = { 0x14000 }, 1592 .prio = 0, 1593 .urg_fwd = 0, 1594 .prio_fwd_disable = 1, 1595 }, 1596 .num_links = 1, 1597 .link_nodes = (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, 1598 }; 1599 1600 static struct qcom_icc_node xm_usb2_0 = { 1601 .name = "xm_usb2_0", 1602 .channels = 1, 1603 .buswidth = 8, 1604 .qosbox = &(const struct qcom_icc_qosbox) { 1605 .num_ports = 1, 1606 .port_offsets = { 0x15000 }, 1607 .prio = 0, 1608 .urg_fwd = 0, 1609 .prio_fwd_disable = 1, 1610 }, 1611 .num_links = 1, 1612 .link_nodes = (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, 1613 }; 1614 1615 static struct qcom_icc_node xm_usb3_mp = { 1616 .name = "xm_usb3_mp", 1617 .channels = 1, 1618 .buswidth = 16, 1619 .qosbox = &(const struct qcom_icc_qosbox) { 1620 .num_ports = 1, 1621 .port_offsets = { 0x16000 }, 1622 .prio = 0, 1623 .urg_fwd = 0, 1624 .prio_fwd_disable = 1, 1625 }, 1626 .num_links = 1, 1627 .link_nodes = (struct qcom_icc_node *[]) { &qns_a3noc_snoc }, 1628 }; 1629 1630 static struct qcom_icc_node qnm_lpass_lpinoc = { 1631 .name = "qnm_lpass_lpinoc", 1632 .channels = 1, 1633 .buswidth = 16, 1634 .num_links = 1, 1635 .link_nodes = (struct qcom_icc_node *[]) { &qns_lpass_aggnoc }, 1636 }; 1637 1638 static struct qcom_icc_node xm_cpucp = { 1639 .name = "xm_cpucp", 1640 .channels = 1, 1641 .buswidth = 8, 1642 .num_links = 2, 1643 .link_nodes = (struct qcom_icc_node *[]) { &qns_system_noc, &srvc_nsinoc }, 1644 }; 1645 1646 static struct qcom_icc_node xm_mem_sp = { 1647 .name = "xm_mem_sp", 1648 .channels = 1, 1649 .buswidth = 8, 1650 .num_links = 1, 1651 .link_nodes = (struct qcom_icc_node *[]) { &qns_oobmss_snoc }, 1652 }; 1653 1654 static struct qcom_icc_node qns_lpi_aon_noc = { 1655 .name = "qns_lpi_aon_noc", 1656 .channels = 1, 1657 .buswidth = 16, 1658 .num_links = 1, 1659 .link_nodes = (struct qcom_icc_node *[]) { &qnm_lpass_lpinoc }, 1660 }; 1661 1662 static struct qcom_icc_node qnm_lpinoc_dsp_qns4m = { 1663 .name = "qnm_lpinoc_dsp_qns4m", 1664 .channels = 1, 1665 .buswidth = 16, 1666 .num_links = 1, 1667 .link_nodes = (struct qcom_icc_node *[]) { &qns_lpi_aon_noc }, 1668 }; 1669 1670 static struct qcom_icc_bcm bcm_acv = { 1671 .name = "ACV", 1672 .enable_mask = BIT(3), 1673 .num_nodes = 1, 1674 .nodes = { &ebi }, 1675 }; 1676 1677 static struct qcom_icc_bcm bcm_ce0 = { 1678 .name = "CE0", 1679 .num_nodes = 1, 1680 .nodes = { &qxm_crypto }, 1681 }; 1682 1683 static struct qcom_icc_bcm bcm_cn0 = { 1684 .name = "CN0", 1685 .keepalive = true, 1686 .enable_mask = BIT(0), 1687 .num_nodes = 60, 1688 .nodes = { &qsm_cfg, &qhs_ahb2phy0, 1689 &qhs_ahb2phy1, &qhs_ahb2phy2, 1690 &qhs_ahb2phy3, &qhs_av1_enc_cfg, 1691 &qhs_camera_cfg, &qhs_clk_ctl, 1692 &qhs_crypto0_cfg, &qhs_gpuss_cfg, 1693 &qhs_imem_cfg, &qhs_pcie0_cfg, 1694 &qhs_pcie1_cfg, &qhs_pcie2_cfg, 1695 &qhs_pcie3a_cfg, &qhs_pcie3b_cfg, 1696 &qhs_pcie4_cfg, &qhs_pcie5_cfg, 1697 &qhs_pcie6_cfg, &qhs_pcie_rscc, 1698 &qhs_pdm, &qhs_prng, 1699 &qhs_qdss_cfg, &qhs_qspi, 1700 &qhs_qup0, &qhs_qup1, 1701 &qhs_qup2, &qhs_sdc2, 1702 &qhs_sdc4, &qhs_smmuv3_cfg, 1703 &qhs_tcsr, &qhs_tlmm, 1704 &qhs_ufs_mem_cfg, &qhs_usb2_0_cfg, 1705 &qhs_usb3_0_cfg, &qhs_usb3_1_cfg, 1706 &qhs_usb3_2_cfg, &qhs_usb3_mp_cfg, 1707 &qhs_usb4_0_cfg, &qhs_usb4_1_cfg, 1708 &qhs_usb4_2_cfg, &qhs_venus_cfg, 1709 &qss_cnoc_pcie_slave_east_cfg, &qss_cnoc_pcie_slave_west_cfg, 1710 &qss_lpass_qtb_cfg, &qss_mnoc_cfg, 1711 &qss_nsp_qtb_cfg, &qss_pcie_east_anoc_cfg, 1712 &qss_pcie_west_anoc_cfg, &xs_qdss_stm, 1713 &xs_sys_tcu_cfg, &qnm_hscnoc_cnoc, 1714 &qhs_aoss, &qhs_ipc_router, 1715 &qhs_soccp, &qhs_tme_cfg, 1716 &qns_apss, &qss_cfg, 1717 &qxs_boot_imem, &qxs_imem }, 1718 }; 1719 1720 static struct qcom_icc_bcm bcm_cn1 = { 1721 .name = "CN1", 1722 .num_nodes = 1, 1723 .nodes = { &qhs_display_cfg }, 1724 }; 1725 1726 static struct qcom_icc_bcm bcm_co0 = { 1727 .name = "CO0", 1728 .enable_mask = BIT(0), 1729 .num_nodes = 2, 1730 .nodes = { &qnm_nsp, &qns_nsp_hscnoc }, 1731 }; 1732 1733 static struct qcom_icc_bcm bcm_lp0 = { 1734 .name = "LP0", 1735 .num_nodes = 2, 1736 .nodes = { &qnm_lpass_lpinoc, &qns_lpass_aggnoc }, 1737 }; 1738 1739 static struct qcom_icc_bcm bcm_mc0 = { 1740 .name = "MC0", 1741 .keepalive = true, 1742 .num_nodes = 1, 1743 .nodes = { &ebi }, 1744 }; 1745 1746 static struct qcom_icc_bcm bcm_mm0 = { 1747 .name = "MM0", 1748 .num_nodes = 1, 1749 .nodes = { &qns_mem_noc_hf }, 1750 }; 1751 1752 static struct qcom_icc_bcm bcm_mm1 = { 1753 .name = "MM1", 1754 .enable_mask = BIT(0), 1755 .num_nodes = 11, 1756 .nodes = { &qnm_av1_enc, &qnm_camnoc_hf, 1757 &qnm_camnoc_icp, &qnm_camnoc_sf, 1758 &qnm_eva, &qnm_mdp, 1759 &qnm_vapss_hcp, &qnm_video, 1760 &qnm_video_cv_cpu, &qnm_video_v_cpu, 1761 &qns_mem_noc_sf }, 1762 }; 1763 1764 static struct qcom_icc_bcm bcm_qup0 = { 1765 .name = "QUP0", 1766 .vote_scale = 1, 1767 .keepalive = true, 1768 .num_nodes = 1, 1769 .nodes = { &qup0_core_slave }, 1770 }; 1771 1772 static struct qcom_icc_bcm bcm_qup1 = { 1773 .name = "QUP1", 1774 .vote_scale = 1, 1775 .keepalive = true, 1776 .num_nodes = 1, 1777 .nodes = { &qup1_core_slave }, 1778 }; 1779 1780 static struct qcom_icc_bcm bcm_qup2 = { 1781 .name = "QUP2", 1782 .vote_scale = 1, 1783 .keepalive = true, 1784 .num_nodes = 1, 1785 .nodes = { &qup2_core_slave }, 1786 }; 1787 1788 static struct qcom_icc_bcm bcm_sh0 = { 1789 .name = "SH0", 1790 .keepalive = true, 1791 .num_nodes = 1, 1792 .nodes = { &qns_llcc }, 1793 }; 1794 1795 static struct qcom_icc_bcm bcm_sh1 = { 1796 .name = "SH1", 1797 .enable_mask = BIT(0), 1798 .num_nodes = 18, 1799 .nodes = { &alm_gpu_tcu, &alm_pcie_qtc, 1800 &alm_sys_tcu, &chm_apps, 1801 &qnm_aggre_noc_east, &qnm_gpu, 1802 &qnm_lpass, &qnm_mnoc_hf, 1803 &qnm_mnoc_sf, &qnm_nsp_noc, 1804 &qnm_pcie_east, &qnm_pcie_west, 1805 &qnm_snoc_sf, &qxm_wlan_q6, 1806 &xm_gic, &qns_hscnoc_cnoc, 1807 &qns_pcie_east, &qns_pcie_west }, 1808 }; 1809 1810 static struct qcom_icc_bcm bcm_sn0 = { 1811 .name = "SN0", 1812 .keepalive = true, 1813 .num_nodes = 1, 1814 .nodes = { &qns_gemnoc_sf }, 1815 }; 1816 1817 static struct qcom_icc_bcm bcm_sn1 = { 1818 .name = "SN1", 1819 .enable_mask = BIT(0), 1820 .num_nodes = 1, 1821 .nodes = { &qnm_oobmss }, 1822 }; 1823 1824 static struct qcom_icc_bcm bcm_sn2 = { 1825 .name = "SN2", 1826 .num_nodes = 1, 1827 .nodes = { &qnm_aggre1_noc }, 1828 }; 1829 1830 static struct qcom_icc_bcm bcm_sn3 = { 1831 .name = "SN3", 1832 .num_nodes = 1, 1833 .nodes = { &qnm_aggre2_noc }, 1834 }; 1835 1836 static struct qcom_icc_bcm bcm_sn4 = { 1837 .name = "SN4", 1838 .num_nodes = 1, 1839 .nodes = { &qnm_aggre3_noc }, 1840 }; 1841 1842 static struct qcom_icc_bcm bcm_sn5 = { 1843 .name = "SN5", 1844 .num_nodes = 1, 1845 .nodes = { &qns_a4noc_hscnoc }, 1846 }; 1847 1848 static struct qcom_icc_bcm bcm_sn6 = { 1849 .name = "SN6", 1850 .num_nodes = 4, 1851 .nodes = { &qns_pcie_east_mem_noc, &qnm_hscnoc_pcie_east, 1852 &qns_pcie_west_mem_noc, &qnm_hscnoc_pcie_west }, 1853 }; 1854 1855 static struct qcom_icc_bcm * const aggre1_noc_bcms[] = { 1856 &bcm_ce0, 1857 }; 1858 1859 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1860 [MASTER_CRYPTO] = &qxm_crypto, 1861 [MASTER_SOCCP_PROC] = &qxm_soccp, 1862 [MASTER_QDSS_ETR] = &xm_qdss_etr_0, 1863 [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1, 1864 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, 1865 }; 1866 1867 static const struct regmap_config glymur_aggre1_noc_regmap_config = { 1868 .reg_bits = 32, 1869 .reg_stride = 4, 1870 .val_bits = 32, 1871 .max_register = 0x14400, 1872 .fast_io = true, 1873 }; 1874 1875 static const struct qcom_icc_desc glymur_aggre1_noc = { 1876 .config = &glymur_aggre1_noc_regmap_config, 1877 .nodes = aggre1_noc_nodes, 1878 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 1879 .bcms = aggre1_noc_bcms, 1880 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms), 1881 .alloc_dyn_id = true, 1882 }; 1883 1884 static struct qcom_icc_node * const aggre2_noc_nodes[] = { 1885 [MASTER_UFS_MEM] = &xm_ufs_mem, 1886 [MASTER_USB3_2] = &xm_usb3_2, 1887 [MASTER_USB4_2] = &xm_usb4_2, 1888 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, 1889 }; 1890 1891 static const struct regmap_config glymur_aggre2_noc_regmap_config = { 1892 .reg_bits = 32, 1893 .reg_stride = 4, 1894 .val_bits = 32, 1895 .max_register = 0x14400, 1896 .fast_io = true, 1897 }; 1898 1899 static const struct qcom_icc_desc glymur_aggre2_noc = { 1900 .config = &glymur_aggre2_noc_regmap_config, 1901 .nodes = aggre2_noc_nodes, 1902 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 1903 .alloc_dyn_id = true, 1904 .qos_requires_clocks = true, 1905 }; 1906 1907 static struct qcom_icc_node * const aggre3_noc_nodes[] = { 1908 [MASTER_QSPI_0] = &qhm_qspi, 1909 [MASTER_QUP_0] = &qhm_qup0, 1910 [MASTER_QUP_1] = &qhm_qup1, 1911 [MASTER_QUP_2] = &qhm_qup2, 1912 [MASTER_SP] = &qxm_sp, 1913 [MASTER_SDCC_2] = &xm_sdc2, 1914 [MASTER_SDCC_4] = &xm_sdc4, 1915 [MASTER_USB2] = &xm_usb2_0, 1916 [MASTER_USB3_MP] = &xm_usb3_mp, 1917 [SLAVE_A3NOC_SNOC] = &qns_a3noc_snoc, 1918 }; 1919 1920 static const struct regmap_config glymur_aggre3_noc_regmap_config = { 1921 .reg_bits = 32, 1922 .reg_stride = 4, 1923 .val_bits = 32, 1924 .max_register = 0x1d400, 1925 .fast_io = true, 1926 }; 1927 1928 static const struct qcom_icc_desc glymur_aggre3_noc = { 1929 .config = &glymur_aggre3_noc_regmap_config, 1930 .nodes = aggre3_noc_nodes, 1931 .num_nodes = ARRAY_SIZE(aggre3_noc_nodes), 1932 .alloc_dyn_id = true, 1933 }; 1934 1935 static struct qcom_icc_bcm * const aggre4_noc_bcms[] = { 1936 &bcm_sn5, 1937 }; 1938 1939 static struct qcom_icc_node * const aggre4_noc_nodes[] = { 1940 [MASTER_USB3_0] = &xm_usb3_0, 1941 [MASTER_USB3_1] = &xm_usb3_1, 1942 [MASTER_USB4_0] = &xm_usb4_0, 1943 [MASTER_USB4_1] = &xm_usb4_1, 1944 [SLAVE_A4NOC_HSCNOC] = &qns_a4noc_hscnoc, 1945 }; 1946 1947 static const struct regmap_config glymur_aggre4_noc_regmap_config = { 1948 .reg_bits = 32, 1949 .reg_stride = 4, 1950 .val_bits = 32, 1951 .max_register = 0x14400, 1952 .fast_io = true, 1953 }; 1954 1955 static const struct qcom_icc_desc glymur_aggre4_noc = { 1956 .config = &glymur_aggre4_noc_regmap_config, 1957 .nodes = aggre4_noc_nodes, 1958 .num_nodes = ARRAY_SIZE(aggre4_noc_nodes), 1959 .bcms = aggre4_noc_bcms, 1960 .num_bcms = ARRAY_SIZE(aggre4_noc_bcms), 1961 .alloc_dyn_id = true, 1962 .qos_requires_clocks = true, 1963 }; 1964 1965 static struct qcom_icc_bcm * const clk_virt_bcms[] = { 1966 &bcm_qup0, 1967 &bcm_qup1, 1968 &bcm_qup2, 1969 }; 1970 1971 static struct qcom_icc_node * const clk_virt_nodes[] = { 1972 [MASTER_QUP_CORE_0] = &qup0_core_master, 1973 [MASTER_QUP_CORE_1] = &qup1_core_master, 1974 [MASTER_QUP_CORE_2] = &qup2_core_master, 1975 [SLAVE_QUP_CORE_0] = &qup0_core_slave, 1976 [SLAVE_QUP_CORE_1] = &qup1_core_slave, 1977 [SLAVE_QUP_CORE_2] = &qup2_core_slave, 1978 }; 1979 1980 static const struct qcom_icc_desc glymur_clk_virt = { 1981 .nodes = clk_virt_nodes, 1982 .num_nodes = ARRAY_SIZE(clk_virt_nodes), 1983 .bcms = clk_virt_bcms, 1984 .num_bcms = ARRAY_SIZE(clk_virt_bcms), 1985 .alloc_dyn_id = true, 1986 }; 1987 1988 static struct qcom_icc_bcm * const cnoc_cfg_bcms[] = { 1989 &bcm_cn0, 1990 &bcm_cn1, 1991 }; 1992 1993 static struct qcom_icc_node * const cnoc_cfg_nodes[] = { 1994 [MASTER_CNOC_CFG] = &qsm_cfg, 1995 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, 1996 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1, 1997 [SLAVE_AHB2PHY_2] = &qhs_ahb2phy2, 1998 [SLAVE_AHB2PHY_3] = &qhs_ahb2phy3, 1999 [SLAVE_AV1_ENC_CFG] = &qhs_av1_enc_cfg, 2000 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 2001 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 2002 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 2003 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 2004 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, 2005 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 2006 [SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg, 2007 [SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg, 2008 [SLAVE_PCIE_2_CFG] = &qhs_pcie2_cfg, 2009 [SLAVE_PCIE_3A_CFG] = &qhs_pcie3a_cfg, 2010 [SLAVE_PCIE_3B_CFG] = &qhs_pcie3b_cfg, 2011 [SLAVE_PCIE_4_CFG] = &qhs_pcie4_cfg, 2012 [SLAVE_PCIE_5_CFG] = &qhs_pcie5_cfg, 2013 [SLAVE_PCIE_6_CFG] = &qhs_pcie6_cfg, 2014 [SLAVE_PCIE_RSCC] = &qhs_pcie_rscc, 2015 [SLAVE_PDM] = &qhs_pdm, 2016 [SLAVE_PRNG] = &qhs_prng, 2017 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 2018 [SLAVE_QSPI_0] = &qhs_qspi, 2019 [SLAVE_QUP_0] = &qhs_qup0, 2020 [SLAVE_QUP_1] = &qhs_qup1, 2021 [SLAVE_QUP_2] = &qhs_qup2, 2022 [SLAVE_SDCC_2] = &qhs_sdc2, 2023 [SLAVE_SDCC_4] = &qhs_sdc4, 2024 [SLAVE_SMMUV3_CFG] = &qhs_smmuv3_cfg, 2025 [SLAVE_TCSR] = &qhs_tcsr, 2026 [SLAVE_TLMM] = &qhs_tlmm, 2027 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 2028 [SLAVE_USB2] = &qhs_usb2_0_cfg, 2029 [SLAVE_USB3_0] = &qhs_usb3_0_cfg, 2030 [SLAVE_USB3_1] = &qhs_usb3_1_cfg, 2031 [SLAVE_USB3_2] = &qhs_usb3_2_cfg, 2032 [SLAVE_USB3_MP] = &qhs_usb3_mp_cfg, 2033 [SLAVE_USB4_0] = &qhs_usb4_0_cfg, 2034 [SLAVE_USB4_1] = &qhs_usb4_1_cfg, 2035 [SLAVE_USB4_2] = &qhs_usb4_2_cfg, 2036 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 2037 [SLAVE_CNOC_PCIE_SLAVE_EAST_CFG] = &qss_cnoc_pcie_slave_east_cfg, 2038 [SLAVE_CNOC_PCIE_SLAVE_WEST_CFG] = &qss_cnoc_pcie_slave_west_cfg, 2039 [SLAVE_LPASS_QTB_CFG] = &qss_lpass_qtb_cfg, 2040 [SLAVE_CNOC_MNOC_CFG] = &qss_mnoc_cfg, 2041 [SLAVE_NSP_QTB_CFG] = &qss_nsp_qtb_cfg, 2042 [SLAVE_PCIE_EAST_ANOC_CFG] = &qss_pcie_east_anoc_cfg, 2043 [SLAVE_PCIE_WEST_ANOC_CFG] = &qss_pcie_west_anoc_cfg, 2044 [SLAVE_QDSS_STM] = &xs_qdss_stm, 2045 [SLAVE_TCU] = &xs_sys_tcu_cfg, 2046 }; 2047 2048 static const struct regmap_config glymur_cnoc_cfg_regmap_config = { 2049 .reg_bits = 32, 2050 .reg_stride = 4, 2051 .val_bits = 32, 2052 .max_register = 0x6600, 2053 .fast_io = true, 2054 }; 2055 2056 static const struct qcom_icc_desc glymur_cnoc_cfg = { 2057 .config = &glymur_cnoc_cfg_regmap_config, 2058 .nodes = cnoc_cfg_nodes, 2059 .num_nodes = ARRAY_SIZE(cnoc_cfg_nodes), 2060 .bcms = cnoc_cfg_bcms, 2061 .num_bcms = ARRAY_SIZE(cnoc_cfg_bcms), 2062 .alloc_dyn_id = true, 2063 }; 2064 2065 static struct qcom_icc_bcm * const cnoc_main_bcms[] = { 2066 &bcm_cn0, 2067 }; 2068 2069 static struct qcom_icc_node * const cnoc_main_nodes[] = { 2070 [MASTER_HSCNOC_CNOC] = &qnm_hscnoc_cnoc, 2071 [SLAVE_AOSS] = &qhs_aoss, 2072 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, 2073 [SLAVE_SOCCP] = &qhs_soccp, 2074 [SLAVE_TME_CFG] = &qhs_tme_cfg, 2075 [SLAVE_APPSS] = &qns_apss, 2076 [SLAVE_CNOC_CFG] = &qss_cfg, 2077 [SLAVE_BOOT_IMEM] = &qxs_boot_imem, 2078 [SLAVE_IMEM] = &qxs_imem, 2079 }; 2080 2081 static const struct regmap_config glymur_cnoc_main_regmap_config = { 2082 .reg_bits = 32, 2083 .reg_stride = 4, 2084 .val_bits = 32, 2085 .max_register = 0x17080, 2086 .fast_io = true, 2087 }; 2088 2089 static const struct qcom_icc_desc glymur_cnoc_main = { 2090 .config = &glymur_cnoc_main_regmap_config, 2091 .nodes = cnoc_main_nodes, 2092 .num_nodes = ARRAY_SIZE(cnoc_main_nodes), 2093 .bcms = cnoc_main_bcms, 2094 .num_bcms = ARRAY_SIZE(cnoc_main_bcms), 2095 .alloc_dyn_id = true, 2096 }; 2097 2098 static struct qcom_icc_bcm * const hscnoc_bcms[] = { 2099 &bcm_sh0, 2100 &bcm_sh1, 2101 }; 2102 2103 static struct qcom_icc_node * const hscnoc_nodes[] = { 2104 [MASTER_GPU_TCU] = &alm_gpu_tcu, 2105 [MASTER_PCIE_TCU] = &alm_pcie_qtc, 2106 [MASTER_SYS_TCU] = &alm_sys_tcu, 2107 [MASTER_APPSS_PROC] = &chm_apps, 2108 [MASTER_AGGRE_NOC_EAST] = &qnm_aggre_noc_east, 2109 [MASTER_GFX3D] = &qnm_gpu, 2110 [MASTER_LPASS_GEM_NOC] = &qnm_lpass, 2111 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 2112 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 2113 [MASTER_COMPUTE_NOC] = &qnm_nsp_noc, 2114 [MASTER_PCIE_EAST] = &qnm_pcie_east, 2115 [MASTER_PCIE_WEST] = &qnm_pcie_west, 2116 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 2117 [MASTER_WLAN_Q6] = &qxm_wlan_q6, 2118 [MASTER_GIC] = &xm_gic, 2119 [SLAVE_HSCNOC_CNOC] = &qns_hscnoc_cnoc, 2120 [SLAVE_LLCC] = &qns_llcc, 2121 [SLAVE_PCIE_EAST] = &qns_pcie_east, 2122 [SLAVE_PCIE_WEST] = &qns_pcie_west, 2123 }; 2124 2125 static const struct regmap_config glymur_hscnoc_regmap_config = { 2126 .reg_bits = 32, 2127 .reg_stride = 4, 2128 .val_bits = 32, 2129 .max_register = 0x93a080, 2130 .fast_io = true, 2131 }; 2132 2133 static const struct qcom_icc_desc glymur_hscnoc = { 2134 .config = &glymur_hscnoc_regmap_config, 2135 .nodes = hscnoc_nodes, 2136 .num_nodes = ARRAY_SIZE(hscnoc_nodes), 2137 .bcms = hscnoc_bcms, 2138 .num_bcms = ARRAY_SIZE(hscnoc_bcms), 2139 .alloc_dyn_id = true, 2140 }; 2141 2142 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { 2143 [MASTER_LPIAON_NOC] = &qnm_lpiaon_noc, 2144 [SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc, 2145 }; 2146 2147 static const struct regmap_config glymur_lpass_ag_noc_regmap_config = { 2148 .reg_bits = 32, 2149 .reg_stride = 4, 2150 .val_bits = 32, 2151 .max_register = 0xe080, 2152 .fast_io = true, 2153 }; 2154 2155 static const struct qcom_icc_desc glymur_lpass_ag_noc = { 2156 .config = &glymur_lpass_ag_noc_regmap_config, 2157 .nodes = lpass_ag_noc_nodes, 2158 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), 2159 .alloc_dyn_id = true, 2160 }; 2161 2162 static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = { 2163 &bcm_lp0, 2164 }; 2165 2166 static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = { 2167 [MASTER_LPASS_LPINOC] = &qnm_lpass_lpinoc, 2168 [SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &qns_lpass_aggnoc, 2169 }; 2170 2171 static const struct regmap_config glymur_lpass_lpiaon_noc_regmap_config = { 2172 .reg_bits = 32, 2173 .reg_stride = 4, 2174 .val_bits = 32, 2175 .max_register = 0x19080, 2176 .fast_io = true, 2177 }; 2178 2179 static const struct qcom_icc_desc glymur_lpass_lpiaon_noc = { 2180 .config = &glymur_lpass_lpiaon_noc_regmap_config, 2181 .nodes = lpass_lpiaon_noc_nodes, 2182 .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes), 2183 .bcms = lpass_lpiaon_noc_bcms, 2184 .num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms), 2185 .alloc_dyn_id = true, 2186 }; 2187 2188 static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = { 2189 [MASTER_LPASS_PROC] = &qnm_lpinoc_dsp_qns4m, 2190 [SLAVE_LPICX_NOC_LPIAON_NOC] = &qns_lpi_aon_noc, 2191 }; 2192 2193 static const struct regmap_config glymur_lpass_lpicx_noc_regmap_config = { 2194 .reg_bits = 32, 2195 .reg_stride = 4, 2196 .val_bits = 32, 2197 .max_register = 0x44080, 2198 .fast_io = true, 2199 }; 2200 2201 static const struct qcom_icc_desc glymur_lpass_lpicx_noc = { 2202 .config = &glymur_lpass_lpicx_noc_regmap_config, 2203 .nodes = lpass_lpicx_noc_nodes, 2204 .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes), 2205 .alloc_dyn_id = true, 2206 }; 2207 2208 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 2209 &bcm_acv, 2210 &bcm_mc0, 2211 }; 2212 2213 static struct qcom_icc_node * const mc_virt_nodes[] = { 2214 [MASTER_LLCC] = &llcc_mc, 2215 [SLAVE_EBI1] = &ebi, 2216 }; 2217 2218 static const struct qcom_icc_desc glymur_mc_virt = { 2219 .nodes = mc_virt_nodes, 2220 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 2221 .bcms = mc_virt_bcms, 2222 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 2223 .alloc_dyn_id = true, 2224 }; 2225 2226 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 2227 &bcm_mm0, 2228 &bcm_mm1, 2229 }; 2230 2231 static struct qcom_icc_node * const mmss_noc_nodes[] = { 2232 [MASTER_AV1_ENC] = &qnm_av1_enc, 2233 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, 2234 [MASTER_CAMNOC_ICP] = &qnm_camnoc_icp, 2235 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, 2236 [MASTER_EVA] = &qnm_eva, 2237 [MASTER_MDP] = &qnm_mdp, 2238 [MASTER_CDSP_HCP] = &qnm_vapss_hcp, 2239 [MASTER_VIDEO] = &qnm_video, 2240 [MASTER_VIDEO_CV_PROC] = &qnm_video_cv_cpu, 2241 [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu, 2242 [MASTER_CNOC_MNOC_CFG] = &qsm_mnoc_cfg, 2243 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 2244 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, 2245 [SLAVE_SERVICE_MNOC] = &srvc_mnoc, 2246 }; 2247 2248 static const struct regmap_config glymur_mmss_noc_regmap_config = { 2249 .reg_bits = 32, 2250 .reg_stride = 4, 2251 .val_bits = 32, 2252 .max_register = 0x5b800, 2253 .fast_io = true, 2254 }; 2255 2256 static const struct qcom_icc_desc glymur_mmss_noc = { 2257 .config = &glymur_mmss_noc_regmap_config, 2258 .nodes = mmss_noc_nodes, 2259 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 2260 .bcms = mmss_noc_bcms, 2261 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 2262 .alloc_dyn_id = true, 2263 }; 2264 2265 static struct qcom_icc_node * const nsinoc_nodes[] = { 2266 [MASTER_CPUCP] = &xm_cpucp, 2267 [SLAVE_NSINOC_SYSTEM_NOC] = &qns_system_noc, 2268 [SLAVE_SERVICE_NSINOC] = &srvc_nsinoc, 2269 }; 2270 2271 static const struct regmap_config glymur_nsinoc_regmap_config = { 2272 .reg_bits = 32, 2273 .reg_stride = 4, 2274 .val_bits = 32, 2275 .max_register = 0x14080, 2276 .fast_io = true, 2277 }; 2278 2279 static const struct qcom_icc_desc glymur_nsinoc = { 2280 .config = &glymur_nsinoc_regmap_config, 2281 .nodes = nsinoc_nodes, 2282 .num_nodes = ARRAY_SIZE(nsinoc_nodes), 2283 .alloc_dyn_id = true, 2284 }; 2285 2286 static struct qcom_icc_bcm * const nsp_noc_bcms[] = { 2287 &bcm_co0, 2288 }; 2289 2290 static struct qcom_icc_node * const nsp_noc_nodes[] = { 2291 [MASTER_CDSP_PROC] = &qnm_nsp, 2292 [SLAVE_NSP0_HSC_NOC] = &qns_nsp_hscnoc, 2293 }; 2294 2295 static const struct regmap_config glymur_nsp_noc_regmap_config = { 2296 .reg_bits = 32, 2297 .reg_stride = 4, 2298 .val_bits = 32, 2299 .max_register = 0x21280, 2300 .fast_io = true, 2301 }; 2302 2303 static const struct qcom_icc_desc glymur_nsp_noc = { 2304 .config = &glymur_nsp_noc_regmap_config, 2305 .nodes = nsp_noc_nodes, 2306 .num_nodes = ARRAY_SIZE(nsp_noc_nodes), 2307 .bcms = nsp_noc_bcms, 2308 .num_bcms = ARRAY_SIZE(nsp_noc_bcms), 2309 .alloc_dyn_id = true, 2310 }; 2311 2312 static struct qcom_icc_node * const oobm_ss_noc_nodes[] = { 2313 [MASTER_OOBMSS_SP_PROC] = &xm_mem_sp, 2314 [SLAVE_OOBMSS_SNOC] = &qns_oobmss_snoc, 2315 }; 2316 2317 static const struct regmap_config glymur_oobm_ss_noc_regmap_config = { 2318 .reg_bits = 32, 2319 .reg_stride = 4, 2320 .val_bits = 32, 2321 .max_register = 0x1e080, 2322 .fast_io = true, 2323 }; 2324 2325 static const struct qcom_icc_desc glymur_oobm_ss_noc = { 2326 .config = &glymur_oobm_ss_noc_regmap_config, 2327 .nodes = oobm_ss_noc_nodes, 2328 .num_nodes = ARRAY_SIZE(oobm_ss_noc_nodes), 2329 .alloc_dyn_id = true, 2330 }; 2331 2332 static struct qcom_icc_bcm * const pcie_east_anoc_bcms[] = { 2333 &bcm_sn6, 2334 }; 2335 2336 static struct qcom_icc_node * const pcie_east_anoc_nodes[] = { 2337 [MASTER_PCIE_EAST_ANOC_CFG] = &qsm_pcie_east_anoc_cfg, 2338 [MASTER_PCIE_0] = &xm_pcie_0, 2339 [MASTER_PCIE_1] = &xm_pcie_1, 2340 [MASTER_PCIE_5] = &xm_pcie_5, 2341 [SLAVE_PCIE_EAST_MEM_NOC] = &qns_pcie_east_mem_noc, 2342 [SLAVE_SERVICE_PCIE_EAST_AGGRE_NOC] = &srvc_pcie_east_aggre_noc, 2343 }; 2344 2345 static const struct regmap_config glymur_pcie_east_anoc_regmap_config = { 2346 .reg_bits = 32, 2347 .reg_stride = 4, 2348 .val_bits = 32, 2349 .max_register = 0xf300, 2350 .fast_io = true, 2351 }; 2352 2353 static const struct qcom_icc_desc glymur_pcie_east_anoc = { 2354 .config = &glymur_pcie_east_anoc_regmap_config, 2355 .nodes = pcie_east_anoc_nodes, 2356 .num_nodes = ARRAY_SIZE(pcie_east_anoc_nodes), 2357 .bcms = pcie_east_anoc_bcms, 2358 .num_bcms = ARRAY_SIZE(pcie_east_anoc_bcms), 2359 .alloc_dyn_id = true, 2360 .qos_requires_clocks = true, 2361 }; 2362 2363 static struct qcom_icc_bcm * const pcie_east_slv_noc_bcms[] = { 2364 &bcm_sn6, 2365 }; 2366 2367 static struct qcom_icc_node * const pcie_east_slv_noc_nodes[] = { 2368 [MASTER_HSCNOC_PCIE_EAST] = &qnm_hscnoc_pcie_east, 2369 [MASTER_CNOC_PCIE_EAST_SLAVE_CFG] = &qsm_cnoc_pcie_east_slave_cfg, 2370 [SLAVE_HSCNOC_PCIE_EAST_MS_MPU_CFG] = &qhs_hscnoc_pcie_east_ms_mpu_cfg, 2371 [SLAVE_SERVICE_PCIE_EAST] = &srvc_pcie_east, 2372 [SLAVE_PCIE_0] = &xs_pcie_0, 2373 [SLAVE_PCIE_1] = &xs_pcie_1, 2374 [SLAVE_PCIE_5] = &xs_pcie_5, 2375 }; 2376 2377 static const struct regmap_config glymur_pcie_east_slv_noc_regmap_config = { 2378 .reg_bits = 32, 2379 .reg_stride = 4, 2380 .val_bits = 32, 2381 .max_register = 0xe080, 2382 .fast_io = true, 2383 }; 2384 2385 static const struct qcom_icc_desc glymur_pcie_east_slv_noc = { 2386 .config = &glymur_pcie_east_slv_noc_regmap_config, 2387 .nodes = pcie_east_slv_noc_nodes, 2388 .num_nodes = ARRAY_SIZE(pcie_east_slv_noc_nodes), 2389 .bcms = pcie_east_slv_noc_bcms, 2390 .num_bcms = ARRAY_SIZE(pcie_east_slv_noc_bcms), 2391 .alloc_dyn_id = true, 2392 }; 2393 2394 static struct qcom_icc_bcm * const pcie_west_anoc_bcms[] = { 2395 &bcm_sn6, 2396 }; 2397 2398 static struct qcom_icc_node * const pcie_west_anoc_nodes[] = { 2399 [MASTER_PCIE_WEST_ANOC_CFG] = &qsm_pcie_west_anoc_cfg, 2400 [MASTER_PCIE_2] = &xm_pcie_2, 2401 [MASTER_PCIE_3A] = &xm_pcie_3a, 2402 [MASTER_PCIE_3B] = &xm_pcie_3b, 2403 [MASTER_PCIE_4] = &xm_pcie_4, 2404 [MASTER_PCIE_6] = &xm_pcie_6, 2405 [SLAVE_PCIE_WEST_MEM_NOC] = &qns_pcie_west_mem_noc, 2406 [SLAVE_SERVICE_PCIE_WEST_AGGRE_NOC] = &srvc_pcie_west_aggre_noc, 2407 }; 2408 2409 static const struct regmap_config glymur_pcie_west_anoc_regmap_config = { 2410 .reg_bits = 32, 2411 .reg_stride = 4, 2412 .val_bits = 32, 2413 .max_register = 0xf580, 2414 .fast_io = true, 2415 }; 2416 2417 static const struct qcom_icc_desc glymur_pcie_west_anoc = { 2418 .config = &glymur_pcie_west_anoc_regmap_config, 2419 .nodes = pcie_west_anoc_nodes, 2420 .num_nodes = ARRAY_SIZE(pcie_west_anoc_nodes), 2421 .bcms = pcie_west_anoc_bcms, 2422 .num_bcms = ARRAY_SIZE(pcie_west_anoc_bcms), 2423 .alloc_dyn_id = true, 2424 .qos_requires_clocks = true, 2425 }; 2426 2427 static struct qcom_icc_bcm * const pcie_west_slv_noc_bcms[] = { 2428 &bcm_sn6, 2429 }; 2430 2431 static struct qcom_icc_node * const pcie_west_slv_noc_nodes[] = { 2432 [MASTER_HSCNOC_PCIE_WEST] = &qnm_hscnoc_pcie_west, 2433 [MASTER_CNOC_PCIE_WEST_SLAVE_CFG] = &qsm_cnoc_pcie_west_slave_cfg, 2434 [SLAVE_HSCNOC_PCIE_WEST_MS_MPU_CFG] = &qhs_hscnoc_pcie_west_ms_mpu_cfg, 2435 [SLAVE_SERVICE_PCIE_WEST] = &srvc_pcie_west, 2436 [SLAVE_PCIE_2] = &xs_pcie_2, 2437 [SLAVE_PCIE_3A] = &xs_pcie_3a, 2438 [SLAVE_PCIE_3B] = &xs_pcie_3b, 2439 [SLAVE_PCIE_4] = &xs_pcie_4, 2440 [SLAVE_PCIE_6] = &xs_pcie_6, 2441 }; 2442 2443 static const struct regmap_config glymur_pcie_west_slv_noc_regmap_config = { 2444 .reg_bits = 32, 2445 .reg_stride = 4, 2446 .val_bits = 32, 2447 .max_register = 0xf180, 2448 .fast_io = true, 2449 }; 2450 2451 static const struct qcom_icc_desc glymur_pcie_west_slv_noc = { 2452 .config = &glymur_pcie_west_slv_noc_regmap_config, 2453 .nodes = pcie_west_slv_noc_nodes, 2454 .num_nodes = ARRAY_SIZE(pcie_west_slv_noc_nodes), 2455 .bcms = pcie_west_slv_noc_bcms, 2456 .num_bcms = ARRAY_SIZE(pcie_west_slv_noc_bcms), 2457 .alloc_dyn_id = true, 2458 }; 2459 2460 static struct qcom_icc_bcm * const system_noc_bcms[] = { 2461 &bcm_sn0, 2462 &bcm_sn1, 2463 &bcm_sn2, 2464 &bcm_sn3, 2465 &bcm_sn4, 2466 }; 2467 2468 static struct qcom_icc_node * const system_noc_nodes[] = { 2469 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, 2470 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, 2471 [MASTER_A3NOC_SNOC] = &qnm_aggre3_noc, 2472 [MASTER_NSINOC_SNOC] = &qnm_nsi_noc, 2473 [MASTER_OOBMSS] = &qnm_oobmss, 2474 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 2475 }; 2476 2477 static const struct regmap_config glymur_system_noc_regmap_config = { 2478 .reg_bits = 32, 2479 .reg_stride = 4, 2480 .val_bits = 32, 2481 .max_register = 0x1c080, 2482 .fast_io = true, 2483 }; 2484 2485 static const struct qcom_icc_desc glymur_system_noc = { 2486 .config = &glymur_system_noc_regmap_config, 2487 .nodes = system_noc_nodes, 2488 .num_nodes = ARRAY_SIZE(system_noc_nodes), 2489 .bcms = system_noc_bcms, 2490 .num_bcms = ARRAY_SIZE(system_noc_bcms), 2491 .alloc_dyn_id = true, 2492 }; 2493 2494 static const struct of_device_id qnoc_of_match[] = { 2495 { .compatible = "qcom,glymur-aggre1-noc", .data = &glymur_aggre1_noc}, 2496 { .compatible = "qcom,glymur-aggre2-noc", .data = &glymur_aggre2_noc}, 2497 { .compatible = "qcom,glymur-aggre3-noc", .data = &glymur_aggre3_noc}, 2498 { .compatible = "qcom,glymur-aggre4-noc", .data = &glymur_aggre4_noc}, 2499 { .compatible = "qcom,glymur-clk-virt", .data = &glymur_clk_virt}, 2500 { .compatible = "qcom,glymur-cnoc-cfg", .data = &glymur_cnoc_cfg}, 2501 { .compatible = "qcom,glymur-cnoc-main", .data = &glymur_cnoc_main}, 2502 { .compatible = "qcom,glymur-hscnoc", .data = &glymur_hscnoc}, 2503 { .compatible = "qcom,glymur-lpass-ag-noc", .data = &glymur_lpass_ag_noc}, 2504 { .compatible = "qcom,glymur-lpass-lpiaon-noc", .data = &glymur_lpass_lpiaon_noc}, 2505 { .compatible = "qcom,glymur-lpass-lpicx-noc", .data = &glymur_lpass_lpicx_noc}, 2506 { .compatible = "qcom,glymur-mc-virt", .data = &glymur_mc_virt}, 2507 { .compatible = "qcom,glymur-mmss-noc", .data = &glymur_mmss_noc}, 2508 { .compatible = "qcom,glymur-nsinoc", .data = &glymur_nsinoc}, 2509 { .compatible = "qcom,glymur-nsp-noc", .data = &glymur_nsp_noc}, 2510 { .compatible = "qcom,glymur-oobm-ss-noc", .data = &glymur_oobm_ss_noc}, 2511 { .compatible = "qcom,glymur-pcie-east-anoc", .data = &glymur_pcie_east_anoc}, 2512 { .compatible = "qcom,glymur-pcie-east-slv-noc", .data = &glymur_pcie_east_slv_noc}, 2513 { .compatible = "qcom,glymur-pcie-west-anoc", .data = &glymur_pcie_west_anoc}, 2514 { .compatible = "qcom,glymur-pcie-west-slv-noc", .data = &glymur_pcie_west_slv_noc}, 2515 { .compatible = "qcom,glymur-system-noc", .data = &glymur_system_noc}, 2516 { } 2517 }; 2518 MODULE_DEVICE_TABLE(of, qnoc_of_match); 2519 2520 static struct platform_driver qnoc_driver = { 2521 .probe = qcom_icc_rpmh_probe, 2522 .remove = qcom_icc_rpmh_remove, 2523 .driver = { 2524 .name = "qnoc-glymur", 2525 .of_match_table = qnoc_of_match, 2526 .sync_state = icc_sync_state, 2527 }, 2528 }; 2529 2530 static int __init qnoc_driver_init(void) 2531 { 2532 return platform_driver_register(&qnoc_driver); 2533 } 2534 core_initcall(qnoc_driver_init); 2535 2536 static void __exit qnoc_driver_exit(void) 2537 { 2538 platform_driver_unregister(&qnoc_driver); 2539 } 2540 module_exit(qnoc_driver_exit); 2541 2542 MODULE_DESCRIPTION("GLYMUR NoC driver"); 2543 MODULE_LICENSE("GPL"); 2544