1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include <linux/device.h> 7 #include <linux/interconnect.h> 8 #include <linux/interconnect-provider.h> 9 #include <linux/module.h> 10 #include <linux/of_platform.h> 11 #include <dt-bindings/interconnect/qcom,eliza-rpmh.h> 12 13 #include "bcm-voter.h" 14 #include "icc-rpmh.h" 15 16 static struct qcom_icc_node qup1_core_slave = { 17 .name = "qup1_core_slave", 18 .channels = 1, 19 .buswidth = 4, 20 }; 21 22 static struct qcom_icc_node qup2_core_slave = { 23 .name = "qup2_core_slave", 24 .channels = 1, 25 .buswidth = 4, 26 }; 27 28 static struct qcom_icc_node qhs_ahb2phy0 = { 29 .name = "qhs_ahb2phy0", 30 .channels = 1, 31 .buswidth = 4, 32 }; 33 34 static struct qcom_icc_node qhs_ahb2phy1 = { 35 .name = "qhs_ahb2phy1", 36 .channels = 1, 37 .buswidth = 4, 38 }; 39 40 static struct qcom_icc_node qhs_camera_cfg = { 41 .name = "qhs_camera_cfg", 42 .channels = 1, 43 .buswidth = 4, 44 }; 45 46 static struct qcom_icc_node qhs_clk_ctl = { 47 .name = "qhs_clk_ctl", 48 .channels = 1, 49 .buswidth = 4, 50 }; 51 52 static struct qcom_icc_node qhs_crypto0_cfg = { 53 .name = "qhs_crypto0_cfg", 54 .channels = 1, 55 .buswidth = 4, 56 }; 57 58 static struct qcom_icc_node qhs_display_cfg = { 59 .name = "qhs_display_cfg", 60 .channels = 1, 61 .buswidth = 4, 62 }; 63 64 static struct qcom_icc_node qhs_gpuss_cfg = { 65 .name = "qhs_gpuss_cfg", 66 .channels = 1, 67 .buswidth = 8, 68 }; 69 70 static struct qcom_icc_node qhs_i3c_ibi0_cfg = { 71 .name = "qhs_i3c_ibi0_cfg", 72 .channels = 1, 73 .buswidth = 4, 74 }; 75 76 static struct qcom_icc_node qhs_i3c_ibi1_cfg = { 77 .name = "qhs_i3c_ibi1_cfg", 78 .channels = 1, 79 .buswidth = 4, 80 }; 81 82 static struct qcom_icc_node qhs_imem_cfg = { 83 .name = "qhs_imem_cfg", 84 .channels = 1, 85 .buswidth = 4, 86 }; 87 88 static struct qcom_icc_node qhs_mss_cfg = { 89 .name = "qhs_mss_cfg", 90 .channels = 1, 91 .buswidth = 4, 92 }; 93 94 static struct qcom_icc_node qhs_pcie_0_cfg = { 95 .name = "qhs_pcie_0_cfg", 96 .channels = 1, 97 .buswidth = 4, 98 }; 99 100 static struct qcom_icc_node qhs_prng = { 101 .name = "qhs_prng", 102 .channels = 1, 103 .buswidth = 4, 104 }; 105 106 static struct qcom_icc_node qhs_qdss_cfg = { 107 .name = "qhs_qdss_cfg", 108 .channels = 1, 109 .buswidth = 4, 110 }; 111 112 static struct qcom_icc_node qhs_qspi = { 113 .name = "qhs_qspi", 114 .channels = 1, 115 .buswidth = 4, 116 }; 117 118 static struct qcom_icc_node qhs_qup1 = { 119 .name = "qhs_qup1", 120 .channels = 1, 121 .buswidth = 4, 122 }; 123 124 static struct qcom_icc_node qhs_qup2 = { 125 .name = "qhs_qup2", 126 .channels = 1, 127 .buswidth = 4, 128 }; 129 130 static struct qcom_icc_node qhs_sdc1 = { 131 .name = "qhs_sdc1", 132 .channels = 1, 133 .buswidth = 4, 134 }; 135 136 static struct qcom_icc_node qhs_sdc2 = { 137 .name = "qhs_sdc2", 138 .channels = 1, 139 .buswidth = 4, 140 }; 141 142 static struct qcom_icc_node qhs_tcsr = { 143 .name = "qhs_tcsr", 144 .channels = 1, 145 .buswidth = 4, 146 }; 147 148 static struct qcom_icc_node qhs_tlmm = { 149 .name = "qhs_tlmm", 150 .channels = 1, 151 .buswidth = 4, 152 }; 153 154 static struct qcom_icc_node qhs_ufs_mem_cfg = { 155 .name = "qhs_ufs_mem_cfg", 156 .channels = 1, 157 .buswidth = 4, 158 }; 159 160 static struct qcom_icc_node qhs_usb3_0 = { 161 .name = "qhs_usb3_0", 162 .channels = 1, 163 .buswidth = 4, 164 }; 165 166 static struct qcom_icc_node qhs_venus_cfg = { 167 .name = "qhs_venus_cfg", 168 .channels = 1, 169 .buswidth = 4, 170 }; 171 172 static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 173 .name = "qhs_vsense_ctrl_cfg", 174 .channels = 1, 175 .buswidth = 4, 176 }; 177 178 static struct qcom_icc_node xs_qdss_stm = { 179 .name = "xs_qdss_stm", 180 .channels = 1, 181 .buswidth = 4, 182 }; 183 184 static struct qcom_icc_node xs_sys_tcu_cfg = { 185 .name = "xs_sys_tcu_cfg", 186 .channels = 1, 187 .buswidth = 8, 188 }; 189 190 static struct qcom_icc_node qhs_aoss = { 191 .name = "qhs_aoss", 192 .channels = 1, 193 .buswidth = 4, 194 }; 195 196 static struct qcom_icc_node qhs_ipa = { 197 .name = "qhs_ipa", 198 .channels = 1, 199 .buswidth = 4, 200 }; 201 202 static struct qcom_icc_node qhs_ipc_router = { 203 .name = "qhs_ipc_router", 204 .channels = 1, 205 .buswidth = 4, 206 }; 207 208 static struct qcom_icc_node qhs_soccp = { 209 .name = "qhs_soccp", 210 .channels = 1, 211 .buswidth = 4, 212 }; 213 214 static struct qcom_icc_node qhs_tme_cfg = { 215 .name = "qhs_tme_cfg", 216 .channels = 1, 217 .buswidth = 4, 218 }; 219 220 static struct qcom_icc_node qss_apss = { 221 .name = "qss_apss", 222 .channels = 1, 223 .buswidth = 4, 224 }; 225 226 static struct qcom_icc_node qss_ddrss_cfg = { 227 .name = "qss_ddrss_cfg", 228 .channels = 1, 229 .buswidth = 4, 230 }; 231 232 static struct qcom_icc_node qxs_boot_imem = { 233 .name = "qxs_boot_imem", 234 .channels = 1, 235 .buswidth = 16, 236 }; 237 238 static struct qcom_icc_node qxs_imem = { 239 .name = "qxs_imem", 240 .channels = 1, 241 .buswidth = 8, 242 }; 243 244 static struct qcom_icc_node qxs_modem_boot_imem = { 245 .name = "qxs_modem_boot_imem", 246 .channels = 1, 247 .buswidth = 8, 248 }; 249 250 static struct qcom_icc_node srvc_cnoc_main = { 251 .name = "srvc_cnoc_main", 252 .channels = 1, 253 .buswidth = 4, 254 }; 255 256 static struct qcom_icc_node xs_pcie_0 = { 257 .name = "xs_pcie_0", 258 .channels = 1, 259 .buswidth = 8, 260 }; 261 262 static struct qcom_icc_node xs_pcie_1 = { 263 .name = "xs_pcie_1", 264 .channels = 1, 265 .buswidth = 8, 266 }; 267 268 static struct qcom_icc_node ebi = { 269 .name = "ebi", 270 .channels = 4, 271 .buswidth = 4, 272 }; 273 274 static struct qcom_icc_node srvc_mnoc_sf = { 275 .name = "srvc_mnoc_sf", 276 .channels = 1, 277 .buswidth = 4, 278 }; 279 280 static struct qcom_icc_node srvc_mnoc_hf = { 281 .name = "srvc_mnoc_hf", 282 .channels = 1, 283 .buswidth = 4, 284 }; 285 286 static struct qcom_icc_node srvc_pcie_aggre_noc = { 287 .name = "srvc_pcie_aggre_noc", 288 .channels = 1, 289 .buswidth = 4, 290 }; 291 292 static struct qcom_icc_node qup1_core_master = { 293 .name = "qup1_core_master", 294 .channels = 1, 295 .buswidth = 4, 296 .num_links = 1, 297 .link_nodes = { &qup1_core_slave }, 298 }; 299 300 static struct qcom_icc_node qup2_core_master = { 301 .name = "qup2_core_master", 302 .channels = 1, 303 .buswidth = 4, 304 .num_links = 1, 305 .link_nodes = { &qup2_core_slave }, 306 }; 307 308 static struct qcom_icc_node qnm_gemnoc_pcie = { 309 .name = "qnm_gemnoc_pcie", 310 .channels = 1, 311 .buswidth = 16, 312 .num_links = 2, 313 .link_nodes = { &xs_pcie_0, &xs_pcie_1 }, 314 }; 315 316 static struct qcom_icc_node llcc_mc = { 317 .name = "llcc_mc", 318 .channels = 4, 319 .buswidth = 4, 320 .num_links = 1, 321 .link_nodes = { &ebi }, 322 }; 323 324 static struct qcom_icc_node qsm_sf_mnoc_cfg = { 325 .name = "qsm_sf_mnoc_cfg", 326 .channels = 1, 327 .buswidth = 4, 328 .num_links = 1, 329 .link_nodes = { &srvc_mnoc_sf }, 330 }; 331 332 static struct qcom_icc_node qsm_hf_mnoc_cfg = { 333 .name = "qsm_hf_mnoc_cfg", 334 .channels = 1, 335 .buswidth = 4, 336 .num_links = 1, 337 .link_nodes = { &srvc_mnoc_hf }, 338 }; 339 340 static struct qcom_icc_node qsm_pcie_anoc_cfg = { 341 .name = "qsm_pcie_anoc_cfg", 342 .channels = 1, 343 .buswidth = 4, 344 .num_links = 1, 345 .link_nodes = { &srvc_pcie_aggre_noc }, 346 }; 347 348 static struct qcom_icc_node qss_mnoc_hf_cfg = { 349 .name = "qss_mnoc_hf_cfg", 350 .channels = 1, 351 .buswidth = 4, 352 .num_links = 1, 353 .link_nodes = { &qsm_hf_mnoc_cfg }, 354 }; 355 356 static struct qcom_icc_node qss_mnoc_sf_cfg = { 357 .name = "qss_mnoc_sf_cfg", 358 .channels = 1, 359 .buswidth = 4, 360 .num_links = 1, 361 .link_nodes = { &qsm_sf_mnoc_cfg }, 362 }; 363 364 static struct qcom_icc_node qss_pcie_anoc_cfg = { 365 .name = "qss_pcie_anoc_cfg", 366 .channels = 1, 367 .buswidth = 4, 368 .num_links = 1, 369 .link_nodes = { &qsm_pcie_anoc_cfg }, 370 }; 371 372 static struct qcom_icc_node qns_llcc = { 373 .name = "qns_llcc", 374 .channels = 2, 375 .buswidth = 16, 376 .num_links = 1, 377 .link_nodes = { &llcc_mc }, 378 }; 379 380 static struct qcom_icc_node qns_pcie = { 381 .name = "qns_pcie", 382 .channels = 1, 383 .buswidth = 16, 384 .num_links = 1, 385 .link_nodes = { &qnm_gemnoc_pcie }, 386 }; 387 388 static struct qcom_icc_node qsm_cfg = { 389 .name = "qsm_cfg", 390 .channels = 1, 391 .buswidth = 4, 392 .num_links = 30, 393 .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, 394 &qhs_camera_cfg, &qhs_clk_ctl, 395 &qhs_crypto0_cfg, &qhs_display_cfg, 396 &qhs_gpuss_cfg, &qhs_i3c_ibi0_cfg, 397 &qhs_i3c_ibi1_cfg, &qhs_imem_cfg, 398 &qhs_mss_cfg, &qhs_pcie_0_cfg, 399 &qhs_prng, &qhs_qdss_cfg, 400 &qhs_qspi, &qhs_qup1, 401 &qhs_qup2, &qhs_sdc1, &qhs_sdc2, 402 &qhs_tcsr, &qhs_tlmm, 403 &qhs_ufs_mem_cfg, &qhs_usb3_0, 404 &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, 405 &qss_mnoc_hf_cfg, &qss_mnoc_sf_cfg, 406 &qss_pcie_anoc_cfg, &xs_qdss_stm, 407 &xs_sys_tcu_cfg }, 408 }; 409 410 static struct qcom_icc_node xm_gic = { 411 .name = "xm_gic", 412 .channels = 1, 413 .buswidth = 8, 414 .qosbox = &(const struct qcom_icc_qosbox) { 415 .num_ports = 1, 416 .port_offsets = { 0x15d000 }, 417 .prio = 4, 418 .urg_fwd = 0, 419 .prio_fwd_disable = 1, 420 }, 421 .num_links = 1, 422 .link_nodes = { &qns_llcc }, 423 }; 424 425 static struct qcom_icc_node qss_cfg = { 426 .name = "qss_cfg", 427 .channels = 1, 428 .buswidth = 4, 429 .num_links = 1, 430 .link_nodes = { &qsm_cfg }, 431 }; 432 433 static struct qcom_icc_node qnm_gemnoc_cnoc = { 434 .name = "qnm_gemnoc_cnoc", 435 .channels = 1, 436 .buswidth = 16, 437 .num_links = 12, 438 .link_nodes = { &qhs_aoss, &qhs_ipa, 439 &qhs_ipc_router, &qhs_soccp, 440 &qhs_tme_cfg, &qss_apss, 441 &qss_cfg, &qss_ddrss_cfg, 442 &qxs_boot_imem, &qxs_imem, 443 &qxs_modem_boot_imem, &srvc_cnoc_main }, 444 }; 445 446 static struct qcom_icc_node qns_gem_noc_cnoc = { 447 .name = "qns_gem_noc_cnoc", 448 .channels = 1, 449 .buswidth = 16, 450 .num_links = 1, 451 .link_nodes = { &qnm_gemnoc_cnoc }, 452 }; 453 454 static struct qcom_icc_qosbox alm_gpu_tcu_qos = { 455 .num_ports = 1, 456 .port_offsets = { 0x155000 }, 457 .prio = 1, 458 .urg_fwd = 0, 459 .prio_fwd_disable = 1, 460 }; 461 462 static struct qcom_icc_node alm_gpu_tcu = { 463 .name = "alm_gpu_tcu", 464 .channels = 1, 465 .buswidth = 8, 466 .qosbox = &alm_gpu_tcu_qos, 467 .num_links = 2, 468 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 469 }; 470 471 static struct qcom_icc_qosbox alm_sys_tcu_qos = { 472 .num_ports = 1, 473 .port_offsets = { 0x157000 }, 474 .prio = 6, 475 .urg_fwd = 0, 476 .prio_fwd_disable = 1, 477 }; 478 479 static struct qcom_icc_node alm_sys_tcu = { 480 .name = "alm_sys_tcu", 481 .channels = 1, 482 .buswidth = 8, 483 .qosbox = &alm_sys_tcu_qos, 484 .num_links = 2, 485 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 486 }; 487 488 static struct qcom_icc_node chm_apps = { 489 .name = "chm_apps", 490 .channels = 3, 491 .buswidth = 32, 492 .num_links = 3, 493 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 494 &qns_pcie }, 495 }; 496 497 static struct qcom_icc_qosbox qnm_gpu_qos = { 498 .num_ports = 2, 499 .port_offsets = { 0x31000, 0xb1000 }, 500 .prio = 0, 501 .urg_fwd = 1, 502 .prio_fwd_disable = 1, 503 }; 504 505 static struct qcom_icc_node qnm_gpu = { 506 .name = "qnm_gpu", 507 .channels = 2, 508 .buswidth = 32, 509 .qosbox = &qnm_gpu_qos, 510 .num_links = 2, 511 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 512 }; 513 514 static struct qcom_icc_qosbox qnm_lpass_gemnoc_qos = { 515 .num_ports = 1, 516 .port_offsets = { 0x159000 }, 517 .prio = 0, 518 .urg_fwd = 1, 519 .prio_fwd_disable = 0, 520 }; 521 522 static struct qcom_icc_node qnm_lpass_gemnoc = { 523 .name = "qnm_lpass_gemnoc", 524 .channels = 1, 525 .buswidth = 16, 526 .qosbox = &qnm_lpass_gemnoc_qos, 527 .num_links = 3, 528 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 529 &qns_pcie }, 530 }; 531 532 static struct qcom_icc_node qnm_mdsp = { 533 .name = "qnm_mdsp", 534 .channels = 1, 535 .buswidth = 16, 536 .num_links = 3, 537 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 538 &qns_pcie }, 539 }; 540 541 static struct qcom_icc_qosbox qnm_mnoc_hf_qos = { 542 .num_ports = 2, 543 .port_offsets = { 0x33000, 0xb3000 }, 544 .prio = 0, 545 .urg_fwd = 1, 546 .prio_fwd_disable = 0, 547 }; 548 549 static struct qcom_icc_node qnm_mnoc_hf = { 550 .name = "qnm_mnoc_hf", 551 .channels = 2, 552 .buswidth = 32, 553 .qosbox = &qnm_mnoc_hf_qos, 554 .num_links = 2, 555 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 556 }; 557 558 static struct qcom_icc_qosbox qnm_mnoc_sf_qos = { 559 .num_ports = 2, 560 .port_offsets = { 0x35000, 0xb5000 }, 561 .prio = 0, 562 .urg_fwd = 0, 563 .prio_fwd_disable = 0, 564 }; 565 566 static struct qcom_icc_node qnm_mnoc_sf = { 567 .name = "qnm_mnoc_sf", 568 .channels = 2, 569 .buswidth = 32, 570 .qosbox = &qnm_mnoc_sf_qos, 571 .num_links = 2, 572 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 573 }; 574 575 static struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = { 576 .num_ports = 2, 577 .port_offsets = { 0x37000, 0xb7000 }, 578 .prio = 0, 579 .urg_fwd = 1, 580 .prio_fwd_disable = 1, 581 }; 582 583 static struct qcom_icc_node qnm_nsp_gemnoc = { 584 .name = "qnm_nsp_gemnoc", 585 .channels = 2, 586 .buswidth = 32, 587 .qosbox = &qnm_nsp_gemnoc_qos, 588 .num_links = 3, 589 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 590 &qns_pcie }, 591 }; 592 593 static struct qcom_icc_qosbox qnm_pcie_qos = { 594 .num_ports = 1, 595 .port_offsets = { 0x15b000 }, 596 .prio = 2, 597 .urg_fwd = 1, 598 .prio_fwd_disable = 0, 599 }; 600 601 static struct qcom_icc_node qnm_pcie = { 602 .name = "qnm_pcie", 603 .channels = 1, 604 .buswidth = 16, 605 .qosbox = &qnm_pcie_qos, 606 .num_links = 2, 607 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 608 }; 609 610 static struct qcom_icc_node qnm_snoc_sf = { 611 .name = "qnm_snoc_sf", 612 .channels = 1, 613 .buswidth = 16, 614 .qosbox = &(const struct qcom_icc_qosbox) { 615 .num_ports = 1, 616 .port_offsets = { 0x15f000 }, 617 .prio = 0, 618 .urg_fwd = 1, 619 .prio_fwd_disable = 0, 620 }, 621 .num_links = 3, 622 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 623 &qns_pcie }, 624 }; 625 626 static struct qcom_icc_node qxm_wlan_q6 = { 627 .name = "qxm_wlan_q6", 628 .channels = 1, 629 .buswidth = 8, 630 .num_links = 3, 631 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 632 &qns_pcie }, 633 }; 634 635 static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = { 636 .name = "qns_lpass_ag_noc_gemnoc", 637 .channels = 1, 638 .buswidth = 16, 639 .num_links = 1, 640 .link_nodes = { &qnm_lpass_gemnoc }, 641 }; 642 643 static struct qcom_icc_node qns_mem_noc_sf = { 644 .name = "qns_mem_noc_sf", 645 .channels = 2, 646 .buswidth = 32, 647 .num_links = 1, 648 .link_nodes = { &qnm_mnoc_sf }, 649 }; 650 651 static struct qcom_icc_node qns_mem_noc_hf = { 652 .name = "qns_mem_noc_hf", 653 .channels = 2, 654 .buswidth = 32, 655 .num_links = 1, 656 .link_nodes = { &qnm_mnoc_hf }, 657 }; 658 659 static struct qcom_icc_node qns_nsp_gemnoc = { 660 .name = "qns_nsp_gemnoc", 661 .channels = 2, 662 .buswidth = 32, 663 .num_links = 1, 664 .link_nodes = { &qnm_nsp_gemnoc }, 665 }; 666 667 static struct qcom_icc_node qns_pcie_mem_noc = { 668 .name = "qns_pcie_mem_noc", 669 .channels = 1, 670 .buswidth = 16, 671 .num_links = 1, 672 .link_nodes = { &qnm_pcie }, 673 }; 674 675 static struct qcom_icc_node qns_gemnoc_sf = { 676 .name = "qns_gemnoc_sf", 677 .channels = 1, 678 .buswidth = 16, 679 .num_links = 1, 680 .link_nodes = { &qnm_snoc_sf }, 681 }; 682 683 static struct qcom_icc_node qnm_lpiaon_noc = { 684 .name = "qnm_lpiaon_noc", 685 .channels = 1, 686 .buswidth = 16, 687 .num_links = 1, 688 .link_nodes = { &qns_lpass_ag_noc_gemnoc }, 689 }; 690 691 static struct qcom_icc_qosbox qnm_camnoc_nrt_icp_sf_qos = { 692 .num_ports = 1, 693 .port_offsets = { 0x25000 }, 694 .prio = 4, 695 .urg_fwd = 0, 696 .prio_fwd_disable = 1, 697 }; 698 699 static struct qcom_icc_node qnm_camnoc_nrt_icp_sf = { 700 .name = "qnm_camnoc_nrt_icp_sf", 701 .channels = 1, 702 .buswidth = 8, 703 .qosbox = &qnm_camnoc_nrt_icp_sf_qos, 704 .num_links = 1, 705 .link_nodes = { &qns_mem_noc_sf }, 706 }; 707 708 static struct qcom_icc_node qnm_camnoc_rt_cdm_sf = { 709 .name = "qnm_camnoc_rt_cdm_sf", 710 .channels = 1, 711 .buswidth = 8, 712 .qosbox = &(const struct qcom_icc_qosbox) { 713 .num_ports = 1, 714 .port_offsets = { 0x2c000 }, 715 .prio = 2, 716 .urg_fwd = 0, 717 .prio_fwd_disable = 1, 718 }, 719 .num_links = 1, 720 .link_nodes = { &qns_mem_noc_sf }, 721 }; 722 723 static struct qcom_icc_node qnm_camnoc_sf = { 724 .name = "qnm_camnoc_sf", 725 .channels = 2, 726 .buswidth = 32, 727 .qosbox = &(const struct qcom_icc_qosbox) { 728 .num_ports = 2, 729 .port_offsets = { 0x26000, 0x27000 }, 730 .prio = 0, 731 .urg_fwd = 1, 732 .prio_fwd_disable = 0, 733 }, 734 .num_links = 1, 735 .link_nodes = { &qns_mem_noc_sf }, 736 }; 737 738 static struct qcom_icc_node qnm_video_mvp = { 739 .name = "qnm_video_mvp", 740 .channels = 1, 741 .buswidth = 32, 742 .qosbox = &(const struct qcom_icc_qosbox) { 743 .num_ports = 1, 744 .port_offsets = { 0x28000 }, 745 .prio = 0, 746 .urg_fwd = 1, 747 .prio_fwd_disable = 0, 748 }, 749 .num_links = 1, 750 .link_nodes = { &qns_mem_noc_sf }, 751 }; 752 753 static struct qcom_icc_node qnm_video_v_cpu = { 754 .name = "qnm_video_v_cpu", 755 .channels = 1, 756 .buswidth = 8, 757 .qosbox = &(const struct qcom_icc_qosbox) { 758 .num_ports = 1, 759 .port_offsets = { 0x2b000 }, 760 .prio = 4, 761 .urg_fwd = 0, 762 .prio_fwd_disable = 1, 763 }, 764 .num_links = 1, 765 .link_nodes = { &qns_mem_noc_sf }, 766 }; 767 768 static struct qcom_icc_node qnm_camnoc_hf = { 769 .name = "qnm_camnoc_hf", 770 .channels = 2, 771 .buswidth = 32, 772 .qosbox = &(const struct qcom_icc_qosbox) { 773 .num_ports = 2, 774 .port_offsets = { 0x64000, 0x65000 }, 775 .prio = 0, 776 .urg_fwd = 1, 777 .prio_fwd_disable = 0, 778 }, 779 .num_links = 1, 780 .link_nodes = { &qns_mem_noc_hf }, 781 }; 782 783 static struct qcom_icc_node qnm_mdp = { 784 .name = "qnm_mdp", 785 .channels = 2, 786 .buswidth = 32, 787 .qosbox = &(const struct qcom_icc_qosbox) { 788 .num_ports = 2, 789 .port_offsets = { 0x66000, 0x67000 }, 790 .prio = 0, 791 .urg_fwd = 1, 792 .prio_fwd_disable = 0, 793 }, 794 .num_links = 1, 795 .link_nodes = { &qns_mem_noc_hf }, 796 }; 797 798 static struct qcom_icc_node qxm_nsp = { 799 .name = "qxm_nsp", 800 .channels = 2, 801 .buswidth = 32, 802 .num_links = 1, 803 .link_nodes = { &qns_nsp_gemnoc }, 804 }; 805 806 static struct qcom_icc_node xm_pcie3_0 = { 807 .name = "xm_pcie3_0", 808 .channels = 1, 809 .buswidth = 8, 810 .qosbox = &(const struct qcom_icc_qosbox) { 811 .num_ports = 1, 812 .port_offsets = { 0xb000 }, 813 .prio = 3, 814 .urg_fwd = 0, 815 .prio_fwd_disable = 1, 816 }, 817 .num_links = 1, 818 .link_nodes = { &qns_pcie_mem_noc }, 819 }; 820 821 static struct qcom_icc_node xm_pcie3_1 = { 822 .name = "xm_pcie3_1", 823 .channels = 1, 824 .buswidth = 8, 825 .qosbox = &(const struct qcom_icc_qosbox) { 826 .num_ports = 1, 827 .port_offsets = { 0xc000 }, 828 .prio = 3, 829 .urg_fwd = 0, 830 .prio_fwd_disable = 1, 831 }, 832 .num_links = 1, 833 .link_nodes = { &qns_pcie_mem_noc }, 834 }; 835 836 static struct qcom_icc_node qnm_aggre1_noc = { 837 .name = "qnm_aggre1_noc", 838 .channels = 1, 839 .buswidth = 16, 840 .num_links = 1, 841 .link_nodes = { &qns_gemnoc_sf }, 842 }; 843 844 static struct qcom_icc_node qnm_aggre2_noc = { 845 .name = "qnm_aggre2_noc", 846 .channels = 1, 847 .buswidth = 16, 848 .num_links = 1, 849 .link_nodes = { &qns_gemnoc_sf }, 850 }; 851 852 static struct qcom_icc_node qnm_cnoc_data = { 853 .name = "qnm_cnoc_data", 854 .channels = 1, 855 .buswidth = 8, 856 .qosbox = &(const struct qcom_icc_qosbox) { 857 .num_ports = 1, 858 .port_offsets = { 0x1d000 }, 859 .prio = 2, 860 .urg_fwd = 0, 861 .prio_fwd_disable = 1, 862 }, 863 .num_links = 1, 864 .link_nodes = { &qns_gemnoc_sf }, 865 }; 866 867 static struct qcom_icc_node qnm_nsinoc_snoc = { 868 .name = "qnm_nsinoc_snoc", 869 .channels = 1, 870 .buswidth = 8, 871 .qosbox = &(const struct qcom_icc_qosbox) { 872 .num_ports = 1, 873 .port_offsets = { 0x1c000 }, 874 .prio = 2, 875 .urg_fwd = 0, 876 .prio_fwd_disable = 1, 877 }, 878 .num_links = 1, 879 .link_nodes = { &qns_gemnoc_sf }, 880 }; 881 882 static struct qcom_icc_node qns_a1noc_snoc = { 883 .name = "qns_a1noc_snoc", 884 .channels = 1, 885 .buswidth = 16, 886 .num_links = 1, 887 .link_nodes = { &qnm_aggre1_noc }, 888 }; 889 890 static struct qcom_icc_node qns_a2noc_snoc = { 891 .name = "qns_a2noc_snoc", 892 .channels = 1, 893 .buswidth = 16, 894 .num_links = 1, 895 .link_nodes = { &qnm_aggre2_noc }, 896 }; 897 898 static struct qcom_icc_node qns_lpass_aggnoc = { 899 .name = "qns_lpass_aggnoc", 900 .channels = 1, 901 .buswidth = 16, 902 .num_links = 1, 903 .link_nodes = { &qnm_lpiaon_noc }, 904 }; 905 906 static struct qcom_icc_node qhm_qspi = { 907 .name = "qhm_qspi", 908 .channels = 1, 909 .buswidth = 4, 910 .qosbox = &(const struct qcom_icc_qosbox) { 911 .num_ports = 1, 912 .port_offsets = { 0xc000 }, 913 .prio = 2, 914 .urg_fwd = 0, 915 .prio_fwd_disable = 1, 916 }, 917 .num_links = 1, 918 .link_nodes = { &qns_a1noc_snoc }, 919 }; 920 921 static struct qcom_icc_node qhm_qup1 = { 922 .name = "qhm_qup1", 923 .channels = 1, 924 .buswidth = 4, 925 .qosbox = &(const struct qcom_icc_qosbox) { 926 .num_ports = 1, 927 .port_offsets = { 0xd000 }, 928 .prio = 2, 929 .urg_fwd = 0, 930 .prio_fwd_disable = 1, 931 }, 932 .num_links = 1, 933 .link_nodes = { &qns_a1noc_snoc }, 934 }; 935 936 static struct qcom_icc_node xm_ufs_mem = { 937 .name = "xm_ufs_mem", 938 .channels = 1, 939 .buswidth = 16, 940 .qosbox = &(const struct qcom_icc_qosbox) { 941 .num_ports = 1, 942 .port_offsets = { 0xf000 }, 943 .prio = 2, 944 .urg_fwd = 0, 945 .prio_fwd_disable = 1, 946 }, 947 .num_links = 1, 948 .link_nodes = { &qns_a1noc_snoc }, 949 }; 950 951 static struct qcom_icc_node xm_usb3_0 = { 952 .name = "xm_usb3_0", 953 .channels = 1, 954 .buswidth = 8, 955 .qosbox = &(const struct qcom_icc_qosbox) { 956 .num_ports = 1, 957 .port_offsets = { 0x10000 }, 958 .prio = 2, 959 .urg_fwd = 0, 960 .prio_fwd_disable = 1, 961 }, 962 .num_links = 1, 963 .link_nodes = { &qns_a1noc_snoc }, 964 }; 965 966 static struct qcom_icc_node qhm_qup2 = { 967 .name = "qhm_qup2", 968 .channels = 1, 969 .buswidth = 4, 970 .qosbox = &(const struct qcom_icc_qosbox) { 971 .num_ports = 1, 972 .port_offsets = { 0x14000 }, 973 .prio = 2, 974 .urg_fwd = 0, 975 .prio_fwd_disable = 1, 976 }, 977 .num_links = 1, 978 .link_nodes = { &qns_a2noc_snoc }, 979 }; 980 981 static struct qcom_icc_node qxm_crypto = { 982 .name = "qxm_crypto", 983 .channels = 1, 984 .buswidth = 8, 985 .qosbox = &(const struct qcom_icc_qosbox) { 986 .num_ports = 1, 987 .port_offsets = { 0x15000 }, 988 .prio = 2, 989 .urg_fwd = 0, 990 .prio_fwd_disable = 1, 991 }, 992 .num_links = 1, 993 .link_nodes = { &qns_a2noc_snoc }, 994 }; 995 996 static struct qcom_icc_node qxm_ipa = { 997 .name = "qxm_ipa", 998 .channels = 1, 999 .buswidth = 8, 1000 .qosbox = &(const struct qcom_icc_qosbox) { 1001 .num_ports = 1, 1002 .port_offsets = { 0x16000 }, 1003 .prio = 2, 1004 .urg_fwd = 0, 1005 .prio_fwd_disable = 1, 1006 }, 1007 .num_links = 1, 1008 .link_nodes = { &qns_a2noc_snoc }, 1009 }; 1010 1011 static struct qcom_icc_node qxm_soccp = { 1012 .name = "qxm_soccp", 1013 .channels = 1, 1014 .buswidth = 8, 1015 .qosbox = &(const struct qcom_icc_qosbox) { 1016 .num_ports = 1, 1017 .port_offsets = { 0x1a000 }, 1018 .prio = 2, 1019 .urg_fwd = 0, 1020 .prio_fwd_disable = 1, 1021 }, 1022 .num_links = 1, 1023 .link_nodes = { &qns_a2noc_snoc }, 1024 }; 1025 1026 static struct qcom_icc_node xm_qdss_etr_0 = { 1027 .name = "xm_qdss_etr_0", 1028 .channels = 1, 1029 .buswidth = 8, 1030 .qosbox = &(const struct qcom_icc_qosbox) { 1031 .num_ports = 1, 1032 .port_offsets = { 0x17000 }, 1033 .prio = 2, 1034 .urg_fwd = 0, 1035 .prio_fwd_disable = 1, 1036 }, 1037 .num_links = 1, 1038 .link_nodes = { &qns_a2noc_snoc }, 1039 }; 1040 1041 static struct qcom_icc_node xm_qdss_etr_1 = { 1042 .name = "xm_qdss_etr_1", 1043 .channels = 1, 1044 .buswidth = 8, 1045 .qosbox = &(const struct qcom_icc_qosbox) { 1046 .num_ports = 1, 1047 .port_offsets = { 0x18000 }, 1048 .prio = 2, 1049 .urg_fwd = 0, 1050 .prio_fwd_disable = 1, 1051 }, 1052 .num_links = 1, 1053 .link_nodes = { &qns_a2noc_snoc }, 1054 }; 1055 1056 static struct qcom_icc_node xm_sdc1 = { 1057 .name = "xm_sdc1", 1058 .channels = 1, 1059 .buswidth = 8, 1060 .qosbox = &(const struct qcom_icc_qosbox) { 1061 .num_ports = 1, 1062 .port_offsets = { 0x13000 }, 1063 .prio = 2, 1064 .urg_fwd = 0, 1065 .prio_fwd_disable = 1, 1066 }, 1067 .num_links = 1, 1068 .link_nodes = { &qns_a2noc_snoc }, 1069 }; 1070 1071 static struct qcom_icc_node xm_sdc2 = { 1072 .name = "xm_sdc2", 1073 .channels = 1, 1074 .buswidth = 8, 1075 .qosbox = &(const struct qcom_icc_qosbox) { 1076 .num_ports = 1, 1077 .port_offsets = { 0x19000 }, 1078 .prio = 2, 1079 .urg_fwd = 0, 1080 .prio_fwd_disable = 1, 1081 }, 1082 .num_links = 1, 1083 .link_nodes = { &qns_a2noc_snoc }, 1084 }; 1085 1086 static struct qcom_icc_node qnm_lpass_lpinoc = { 1087 .name = "qnm_lpass_lpinoc", 1088 .channels = 1, 1089 .buswidth = 16, 1090 .num_links = 1, 1091 .link_nodes = { &qns_lpass_aggnoc }, 1092 }; 1093 1094 static struct qcom_icc_node qns_lpi_aon_noc = { 1095 .name = "qns_lpi_aon_noc", 1096 .channels = 1, 1097 .buswidth = 16, 1098 .num_links = 1, 1099 .link_nodes = { &qnm_lpass_lpinoc }, 1100 }; 1101 1102 static struct qcom_icc_node qxm_lpinoc_dsp_axim = { 1103 .name = "qxm_lpinoc_dsp_axim", 1104 .channels = 1, 1105 .buswidth = 16, 1106 .num_links = 1, 1107 .link_nodes = { &qns_lpi_aon_noc }, 1108 }; 1109 1110 static struct qcom_icc_bcm bcm_ce0 = { 1111 .name = "CE0", 1112 .num_nodes = 1, 1113 .nodes = { &qxm_crypto }, 1114 }; 1115 1116 static struct qcom_icc_bcm bcm_cn0 = { 1117 .name = "CN0", 1118 .enable_mask = BIT(0), 1119 .keepalive = true, 1120 .num_nodes = 44, 1121 .nodes = { &qsm_cfg, &qhs_ahb2phy0, 1122 &qhs_ahb2phy1, &qhs_camera_cfg, 1123 &qhs_clk_ctl, &qhs_crypto0_cfg, 1124 &qhs_gpuss_cfg, &qhs_i3c_ibi0_cfg, 1125 &qhs_i3c_ibi1_cfg, &qhs_imem_cfg, 1126 &qhs_mss_cfg, &qhs_pcie_0_cfg, 1127 &qhs_prng, &qhs_qdss_cfg, 1128 &qhs_qspi, &qhs_sdc1, &qhs_sdc2, 1129 &qhs_tcsr, &qhs_tlmm, 1130 &qhs_ufs_mem_cfg, &qhs_usb3_0, 1131 &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, 1132 &qss_mnoc_hf_cfg, &qss_mnoc_sf_cfg, 1133 &qss_pcie_anoc_cfg, &xs_qdss_stm, 1134 &xs_sys_tcu_cfg, &qnm_gemnoc_cnoc, 1135 &qnm_gemnoc_pcie, &qhs_aoss, 1136 &qhs_ipa, &qhs_ipc_router, 1137 &qhs_soccp, &qhs_tme_cfg, 1138 &qss_apss, &qss_cfg, 1139 &qss_ddrss_cfg, &qxs_boot_imem, 1140 &qxs_imem, &qxs_modem_boot_imem, 1141 &srvc_cnoc_main, &xs_pcie_0, 1142 &xs_pcie_1 }, 1143 }; 1144 1145 static struct qcom_icc_bcm bcm_cn1 = { 1146 .name = "CN1", 1147 .num_nodes = 3, 1148 .nodes = { &qhs_display_cfg, &qhs_qup1, 1149 &qhs_qup2 }, 1150 }; 1151 1152 static struct qcom_icc_bcm bcm_co0 = { 1153 .name = "CO0", 1154 .enable_mask = BIT(0), 1155 .num_nodes = 2, 1156 .nodes = { &qxm_nsp, &qns_nsp_gemnoc }, 1157 }; 1158 1159 static struct qcom_icc_bcm bcm_lp0 = { 1160 .name = "LP0", 1161 .num_nodes = 2, 1162 .nodes = { &qnm_lpass_lpinoc, &qns_lpass_aggnoc }, 1163 }; 1164 1165 static struct qcom_icc_bcm bcm_mc0 = { 1166 .name = "MC0", 1167 .keepalive = true, 1168 .num_nodes = 1, 1169 .nodes = { &ebi }, 1170 }; 1171 1172 static struct qcom_icc_bcm bcm_mm0 = { 1173 .name = "MM0", 1174 .num_nodes = 1, 1175 .nodes = { &qns_mem_noc_hf }, 1176 }; 1177 1178 static struct qcom_icc_bcm bcm_mm1 = { 1179 .name = "MM1", 1180 .enable_mask = BIT(0), 1181 .num_nodes = 7, 1182 .nodes = { &qnm_camnoc_nrt_icp_sf, &qnm_camnoc_rt_cdm_sf, 1183 &qnm_camnoc_sf, &qnm_video_mvp, 1184 &qnm_video_v_cpu, &qnm_camnoc_hf, 1185 &qns_mem_noc_sf }, 1186 }; 1187 1188 static struct qcom_icc_bcm bcm_qup1 = { 1189 .name = "QUP1", 1190 .vote_scale = 1, 1191 .keepalive = true, 1192 .num_nodes = 1, 1193 .nodes = { &qup1_core_slave }, 1194 }; 1195 1196 static struct qcom_icc_bcm bcm_qup2 = { 1197 .name = "QUP2", 1198 .vote_scale = 1, 1199 .keepalive = true, 1200 .num_nodes = 1, 1201 .nodes = { &qup2_core_slave }, 1202 }; 1203 1204 static struct qcom_icc_bcm bcm_sh0 = { 1205 .name = "SH0", 1206 .keepalive = true, 1207 .num_nodes = 1, 1208 .nodes = { &qns_llcc }, 1209 }; 1210 1211 static struct qcom_icc_bcm bcm_sh1 = { 1212 .name = "SH1", 1213 .enable_mask = BIT(0), 1214 .num_nodes = 14, 1215 .nodes = { &alm_gpu_tcu, &alm_sys_tcu, 1216 &chm_apps, &qnm_gpu, 1217 &qnm_mdsp, &qnm_mnoc_hf, 1218 &qnm_mnoc_sf, &qnm_nsp_gemnoc, 1219 &qnm_pcie, &qnm_snoc_sf, 1220 &qxm_wlan_q6, &xm_gic, 1221 &qns_gem_noc_cnoc, &qns_pcie }, 1222 }; 1223 1224 static struct qcom_icc_bcm bcm_sn0 = { 1225 .name = "SN0", 1226 .keepalive = true, 1227 .num_nodes = 1, 1228 .nodes = { &qns_gemnoc_sf }, 1229 }; 1230 1231 static struct qcom_icc_bcm bcm_sn2 = { 1232 .name = "SN2", 1233 .num_nodes = 1, 1234 .nodes = { &qnm_aggre1_noc }, 1235 }; 1236 1237 static struct qcom_icc_bcm bcm_sn3 = { 1238 .name = "SN3", 1239 .num_nodes = 1, 1240 .nodes = { &qnm_aggre2_noc }, 1241 }; 1242 1243 static struct qcom_icc_bcm bcm_sn4 = { 1244 .name = "SN4", 1245 .num_nodes = 1, 1246 .nodes = { &qns_pcie_mem_noc }, 1247 }; 1248 1249 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1250 [MASTER_QSPI_0] = &qhm_qspi, 1251 [MASTER_QUP_1] = &qhm_qup1, 1252 [MASTER_UFS_MEM] = &xm_ufs_mem, 1253 [MASTER_USB3_0] = &xm_usb3_0, 1254 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, 1255 }; 1256 1257 static const struct qcom_icc_desc eliza_aggre1_noc = { 1258 .nodes = aggre1_noc_nodes, 1259 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 1260 .qos_requires_clocks = true, 1261 }; 1262 1263 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 1264 &bcm_ce0, 1265 }; 1266 1267 static struct qcom_icc_node * const aggre2_noc_nodes[] = { 1268 [MASTER_QUP_2] = &qhm_qup2, 1269 [MASTER_CRYPTO] = &qxm_crypto, 1270 [MASTER_IPA] = &qxm_ipa, 1271 [MASTER_SOCCP_AGGR_NOC] = &qxm_soccp, 1272 [MASTER_QDSS_ETR] = &xm_qdss_etr_0, 1273 [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1, 1274 [MASTER_SDCC_1] = &xm_sdc1, 1275 [MASTER_SDCC_2] = &xm_sdc2, 1276 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, 1277 }; 1278 1279 static const struct qcom_icc_desc eliza_aggre2_noc = { 1280 .nodes = aggre2_noc_nodes, 1281 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 1282 .bcms = aggre2_noc_bcms, 1283 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 1284 .qos_requires_clocks = true, 1285 }; 1286 1287 static struct qcom_icc_bcm * const clk_virt_bcms[] = { 1288 &bcm_qup1, 1289 &bcm_qup2, 1290 }; 1291 1292 static struct qcom_icc_node * const clk_virt_nodes[] = { 1293 [MASTER_QUP_CORE_1] = &qup1_core_master, 1294 [MASTER_QUP_CORE_2] = &qup2_core_master, 1295 [SLAVE_QUP_CORE_1] = &qup1_core_slave, 1296 [SLAVE_QUP_CORE_2] = &qup2_core_slave, 1297 }; 1298 1299 static const struct qcom_icc_desc eliza_clk_virt = { 1300 .nodes = clk_virt_nodes, 1301 .num_nodes = ARRAY_SIZE(clk_virt_nodes), 1302 .bcms = clk_virt_bcms, 1303 .num_bcms = ARRAY_SIZE(clk_virt_bcms), 1304 }; 1305 1306 static struct qcom_icc_bcm * const cnoc_cfg_bcms[] = { 1307 &bcm_cn0, 1308 &bcm_cn1, 1309 }; 1310 1311 static struct qcom_icc_node * const cnoc_cfg_nodes[] = { 1312 [MASTER_CNOC_CFG] = &qsm_cfg, 1313 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, 1314 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1, 1315 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 1316 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1317 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1318 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 1319 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, 1320 [SLAVE_I3C_IBI0_CFG] = &qhs_i3c_ibi0_cfg, 1321 [SLAVE_I3C_IBI1_CFG] = &qhs_i3c_ibi1_cfg, 1322 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1323 [SLAVE_CNOC_MSS] = &qhs_mss_cfg, 1324 [SLAVE_PCIE_0_CFG] = &qhs_pcie_0_cfg, 1325 [SLAVE_PRNG] = &qhs_prng, 1326 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1327 [SLAVE_QSPI_0] = &qhs_qspi, 1328 [SLAVE_QUP_1] = &qhs_qup1, 1329 [SLAVE_QUP_2] = &qhs_qup2, 1330 [SLAVE_SDCC_1] = &qhs_sdc1, 1331 [SLAVE_SDCC_2] = &qhs_sdc2, 1332 [SLAVE_TCSR] = &qhs_tcsr, 1333 [SLAVE_TLMM] = &qhs_tlmm, 1334 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 1335 [SLAVE_USB3_0] = &qhs_usb3_0, 1336 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1337 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 1338 [SLAVE_CNOC_MNOC_HF_CFG] = &qss_mnoc_hf_cfg, 1339 [SLAVE_CNOC_MNOC_SF_CFG] = &qss_mnoc_sf_cfg, 1340 [SLAVE_PCIE_ANOC_CFG] = &qss_pcie_anoc_cfg, 1341 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1342 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1343 }; 1344 1345 static const struct qcom_icc_desc eliza_cnoc_cfg = { 1346 .nodes = cnoc_cfg_nodes, 1347 .num_nodes = ARRAY_SIZE(cnoc_cfg_nodes), 1348 .bcms = cnoc_cfg_bcms, 1349 .num_bcms = ARRAY_SIZE(cnoc_cfg_bcms), 1350 }; 1351 1352 static struct qcom_icc_bcm * const cnoc_main_bcms[] = { 1353 &bcm_cn0, 1354 }; 1355 1356 static struct qcom_icc_node * const cnoc_main_nodes[] = { 1357 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, 1358 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, 1359 [SLAVE_AOSS] = &qhs_aoss, 1360 [SLAVE_IPA_CFG] = &qhs_ipa, 1361 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, 1362 [SLAVE_SOCCP] = &qhs_soccp, 1363 [SLAVE_TME_CFG] = &qhs_tme_cfg, 1364 [SLAVE_APPSS] = &qss_apss, 1365 [SLAVE_CNOC_CFG] = &qss_cfg, 1366 [SLAVE_DDRSS_CFG] = &qss_ddrss_cfg, 1367 [SLAVE_BOOT_IMEM] = &qxs_boot_imem, 1368 [SLAVE_IMEM] = &qxs_imem, 1369 [SLAVE_BOOT_IMEM_2] = &qxs_modem_boot_imem, 1370 [SLAVE_SERVICE_CNOC] = &srvc_cnoc_main, 1371 [SLAVE_PCIE_0] = &xs_pcie_0, 1372 [SLAVE_PCIE_1] = &xs_pcie_1, 1373 }; 1374 1375 static const struct qcom_icc_desc eliza_cnoc_main = { 1376 .nodes = cnoc_main_nodes, 1377 .num_nodes = ARRAY_SIZE(cnoc_main_nodes), 1378 .bcms = cnoc_main_bcms, 1379 .num_bcms = ARRAY_SIZE(cnoc_main_bcms), 1380 }; 1381 1382 static struct qcom_icc_bcm * const gem_noc_bcms[] = { 1383 &bcm_sh0, 1384 &bcm_sh1, 1385 }; 1386 1387 static struct qcom_icc_node * const gem_noc_nodes[] = { 1388 [MASTER_GPU_TCU] = &alm_gpu_tcu, 1389 [MASTER_SYS_TCU] = &alm_sys_tcu, 1390 [MASTER_APPSS_PROC] = &chm_apps, 1391 [MASTER_GFX3D] = &qnm_gpu, 1392 [MASTER_LPASS_GEM_NOC] = &qnm_lpass_gemnoc, 1393 [MASTER_MSS_PROC] = &qnm_mdsp, 1394 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 1395 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 1396 [MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc, 1397 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, 1398 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 1399 [MASTER_WLAN_Q6] = &qxm_wlan_q6, 1400 [MASTER_GIC] = &xm_gic, 1401 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, 1402 [SLAVE_LLCC] = &qns_llcc, 1403 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, 1404 }; 1405 1406 static const struct qcom_icc_desc eliza_gem_noc = { 1407 .nodes = gem_noc_nodes, 1408 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 1409 .bcms = gem_noc_bcms, 1410 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 1411 }; 1412 1413 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { 1414 [MASTER_LPIAON_NOC] = &qnm_lpiaon_noc, 1415 [SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc, 1416 }; 1417 1418 static const struct qcom_icc_desc eliza_lpass_ag_noc = { 1419 .nodes = lpass_ag_noc_nodes, 1420 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), 1421 }; 1422 1423 static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = { 1424 &bcm_lp0, 1425 }; 1426 1427 static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = { 1428 [MASTER_LPASS_LPINOC] = &qnm_lpass_lpinoc, 1429 [SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &qns_lpass_aggnoc, 1430 }; 1431 1432 static const struct qcom_icc_desc eliza_lpass_lpiaon_noc = { 1433 .nodes = lpass_lpiaon_noc_nodes, 1434 .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes), 1435 .bcms = lpass_lpiaon_noc_bcms, 1436 .num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms), 1437 }; 1438 1439 static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = { 1440 [MASTER_LPASS_PROC] = &qxm_lpinoc_dsp_axim, 1441 [SLAVE_LPICX_NOC_LPIAON_NOC] = &qns_lpi_aon_noc, 1442 }; 1443 1444 static const struct qcom_icc_desc eliza_lpass_lpicx_noc = { 1445 .nodes = lpass_lpicx_noc_nodes, 1446 .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes), 1447 }; 1448 1449 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 1450 &bcm_mc0, 1451 }; 1452 1453 static struct qcom_icc_node * const mc_virt_nodes[] = { 1454 [MASTER_LLCC] = &llcc_mc, 1455 [SLAVE_EBI1] = &ebi, 1456 }; 1457 1458 static const struct qcom_icc_desc eliza_mc_virt = { 1459 .nodes = mc_virt_nodes, 1460 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 1461 .bcms = mc_virt_bcms, 1462 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 1463 }; 1464 1465 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 1466 &bcm_mm0, 1467 &bcm_mm1, 1468 }; 1469 1470 static struct qcom_icc_node * const mmss_noc_nodes[] = { 1471 [MASTER_CAMNOC_NRT_ICP_SF] = &qnm_camnoc_nrt_icp_sf, 1472 [MASTER_CAMNOC_RT_CDM_SF] = &qnm_camnoc_rt_cdm_sf, 1473 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, 1474 [MASTER_VIDEO_MVP] = &qnm_video_mvp, 1475 [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu, 1476 [MASTER_CNOC_MNOC_SF_CFG] = &qsm_sf_mnoc_cfg, 1477 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, 1478 [MASTER_MDP] = &qnm_mdp, 1479 [MASTER_CNOC_MNOC_HF_CFG] = &qsm_hf_mnoc_cfg, 1480 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, 1481 [SLAVE_SERVICE_MNOC_SF] = &srvc_mnoc_sf, 1482 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 1483 [SLAVE_SERVICE_MNOC_HF] = &srvc_mnoc_hf, 1484 }; 1485 1486 static const struct qcom_icc_desc eliza_mmss_noc = { 1487 .nodes = mmss_noc_nodes, 1488 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 1489 .bcms = mmss_noc_bcms, 1490 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 1491 }; 1492 1493 static struct qcom_icc_bcm * const nsp_noc_bcms[] = { 1494 &bcm_co0, 1495 }; 1496 1497 static struct qcom_icc_node * const nsp_noc_nodes[] = { 1498 [MASTER_CDSP_PROC] = &qxm_nsp, 1499 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, 1500 }; 1501 1502 static const struct qcom_icc_desc eliza_nsp_noc = { 1503 .nodes = nsp_noc_nodes, 1504 .num_nodes = ARRAY_SIZE(nsp_noc_nodes), 1505 .bcms = nsp_noc_bcms, 1506 .num_bcms = ARRAY_SIZE(nsp_noc_bcms), 1507 }; 1508 1509 static struct qcom_icc_bcm * const pcie_anoc_bcms[] = { 1510 &bcm_sn4, 1511 }; 1512 1513 static struct qcom_icc_node * const pcie_anoc_nodes[] = { 1514 [MASTER_PCIE_ANOC_CFG] = &qsm_pcie_anoc_cfg, 1515 [MASTER_PCIE_0] = &xm_pcie3_0, 1516 [MASTER_PCIE_1] = &xm_pcie3_1, 1517 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, 1518 [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc, 1519 }; 1520 1521 static const struct qcom_icc_desc eliza_pcie_anoc = { 1522 .nodes = pcie_anoc_nodes, 1523 .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), 1524 .bcms = pcie_anoc_bcms, 1525 .num_bcms = ARRAY_SIZE(pcie_anoc_bcms), 1526 .qos_requires_clocks = true, 1527 }; 1528 1529 static struct qcom_icc_bcm * const system_noc_bcms[] = { 1530 &bcm_sn0, 1531 &bcm_sn2, 1532 &bcm_sn3, 1533 }; 1534 1535 static struct qcom_icc_node * const system_noc_nodes[] = { 1536 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, 1537 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, 1538 [MASTER_CNOC_SNOC] = &qnm_cnoc_data, 1539 [MASTER_NSINOC_SNOC] = &qnm_nsinoc_snoc, 1540 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 1541 }; 1542 1543 static const struct qcom_icc_desc eliza_system_noc = { 1544 .nodes = system_noc_nodes, 1545 .num_nodes = ARRAY_SIZE(system_noc_nodes), 1546 .bcms = system_noc_bcms, 1547 .num_bcms = ARRAY_SIZE(system_noc_bcms), 1548 }; 1549 1550 static const struct of_device_id qnoc_of_match[] = { 1551 { .compatible = "qcom,eliza-aggre1-noc", .data = &eliza_aggre1_noc }, 1552 { .compatible = "qcom,eliza-aggre2-noc", .data = &eliza_aggre2_noc }, 1553 { .compatible = "qcom,eliza-clk-virt", .data = &eliza_clk_virt }, 1554 { .compatible = "qcom,eliza-cnoc-cfg", .data = &eliza_cnoc_cfg }, 1555 { .compatible = "qcom,eliza-cnoc-main", .data = &eliza_cnoc_main }, 1556 { .compatible = "qcom,eliza-gem-noc", .data = &eliza_gem_noc }, 1557 { .compatible = "qcom,eliza-lpass-ag-noc", .data = &eliza_lpass_ag_noc }, 1558 { .compatible = "qcom,eliza-lpass-lpiaon-noc", .data = &eliza_lpass_lpiaon_noc }, 1559 { .compatible = "qcom,eliza-lpass-lpicx-noc", .data = &eliza_lpass_lpicx_noc }, 1560 { .compatible = "qcom,eliza-mc-virt", .data = &eliza_mc_virt }, 1561 { .compatible = "qcom,eliza-mmss-noc", .data = &eliza_mmss_noc }, 1562 { .compatible = "qcom,eliza-nsp-noc", .data = &eliza_nsp_noc }, 1563 { .compatible = "qcom,eliza-pcie-anoc", .data = &eliza_pcie_anoc }, 1564 { .compatible = "qcom,eliza-system-noc", .data = &eliza_system_noc }, 1565 { } 1566 }; 1567 MODULE_DEVICE_TABLE(of, qnoc_of_match); 1568 1569 static struct platform_driver qnoc_driver = { 1570 .probe = qcom_icc_rpmh_probe, 1571 .remove = qcom_icc_rpmh_remove, 1572 .driver = { 1573 .name = "qnoc-eliza", 1574 .of_match_table = qnoc_of_match, 1575 .sync_state = icc_sync_state, 1576 }, 1577 }; 1578 1579 static int __init qnoc_driver_init(void) 1580 { 1581 return platform_driver_register(&qnoc_driver); 1582 } 1583 core_initcall(qnoc_driver_init); 1584 1585 static void __exit qnoc_driver_exit(void) 1586 { 1587 platform_driver_unregister(&qnoc_driver); 1588 } 1589 module_exit(qnoc_driver_exit); 1590 1591 MODULE_DESCRIPTION(" Qualcomm Eliza NoC driver"); 1592 MODULE_LICENSE("GPL"); 1593