1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6 #include <linux/device.h> 7 #include <linux/interconnect.h> 8 #include <linux/interconnect-provider.h> 9 #include <linux/module.h> 10 #include <linux/of_platform.h> 11 #include <dt-bindings/interconnect/qcom,eliza-rpmh.h> 12 13 #include "bcm-voter.h" 14 #include "icc-rpmh.h" 15 16 static struct qcom_icc_node qup1_core_slave = { 17 .name = "qup1_core_slave", 18 .channels = 1, 19 .buswidth = 4, 20 }; 21 22 static struct qcom_icc_node qup2_core_slave = { 23 .name = "qup2_core_slave", 24 .channels = 1, 25 .buswidth = 4, 26 }; 27 28 static struct qcom_icc_node qhs_ahb2phy0 = { 29 .name = "qhs_ahb2phy0", 30 .channels = 1, 31 .buswidth = 4, 32 }; 33 34 static struct qcom_icc_node qhs_ahb2phy1 = { 35 .name = "qhs_ahb2phy1", 36 .channels = 1, 37 .buswidth = 4, 38 }; 39 40 static struct qcom_icc_node qhs_camera_cfg = { 41 .name = "qhs_camera_cfg", 42 .channels = 1, 43 .buswidth = 4, 44 }; 45 46 static struct qcom_icc_node qhs_clk_ctl = { 47 .name = "qhs_clk_ctl", 48 .channels = 1, 49 .buswidth = 4, 50 }; 51 52 static struct qcom_icc_node qhs_crypto0_cfg = { 53 .name = "qhs_crypto0_cfg", 54 .channels = 1, 55 .buswidth = 4, 56 }; 57 58 static struct qcom_icc_node qhs_display_cfg = { 59 .name = "qhs_display_cfg", 60 .channels = 1, 61 .buswidth = 4, 62 }; 63 64 static struct qcom_icc_node qhs_gpuss_cfg = { 65 .name = "qhs_gpuss_cfg", 66 .channels = 1, 67 .buswidth = 8, 68 }; 69 70 static struct qcom_icc_node qhs_i3c_ibi0_cfg = { 71 .name = "qhs_i3c_ibi0_cfg", 72 .channels = 1, 73 .buswidth = 4, 74 }; 75 76 static struct qcom_icc_node qhs_i3c_ibi1_cfg = { 77 .name = "qhs_i3c_ibi1_cfg", 78 .channels = 1, 79 .buswidth = 4, 80 }; 81 82 static struct qcom_icc_node qhs_imem_cfg = { 83 .name = "qhs_imem_cfg", 84 .channels = 1, 85 .buswidth = 4, 86 }; 87 88 static struct qcom_icc_node qhs_mss_cfg = { 89 .name = "qhs_mss_cfg", 90 .channels = 1, 91 .buswidth = 4, 92 }; 93 94 static struct qcom_icc_node qhs_pcie_0_cfg = { 95 .name = "qhs_pcie_0_cfg", 96 .channels = 1, 97 .buswidth = 4, 98 }; 99 100 static struct qcom_icc_node qhs_prng = { 101 .name = "qhs_prng", 102 .channels = 1, 103 .buswidth = 4, 104 }; 105 106 static struct qcom_icc_node qhs_qdss_cfg = { 107 .name = "qhs_qdss_cfg", 108 .channels = 1, 109 .buswidth = 4, 110 }; 111 112 static struct qcom_icc_node qhs_qspi = { 113 .name = "qhs_qspi", 114 .channels = 1, 115 .buswidth = 4, 116 }; 117 118 static struct qcom_icc_node qhs_qup1 = { 119 .name = "qhs_qup1", 120 .channels = 1, 121 .buswidth = 4, 122 }; 123 124 static struct qcom_icc_node qhs_qup2 = { 125 .name = "qhs_qup2", 126 .channels = 1, 127 .buswidth = 4, 128 }; 129 130 static struct qcom_icc_node qhs_sdc2 = { 131 .name = "qhs_sdc2", 132 .channels = 1, 133 .buswidth = 4, 134 }; 135 136 static struct qcom_icc_node qhs_tcsr = { 137 .name = "qhs_tcsr", 138 .channels = 1, 139 .buswidth = 4, 140 }; 141 142 static struct qcom_icc_node qhs_tlmm = { 143 .name = "qhs_tlmm", 144 .channels = 1, 145 .buswidth = 4, 146 }; 147 148 static struct qcom_icc_node qhs_ufs_mem_cfg = { 149 .name = "qhs_ufs_mem_cfg", 150 .channels = 1, 151 .buswidth = 4, 152 }; 153 154 static struct qcom_icc_node qhs_usb3_0 = { 155 .name = "qhs_usb3_0", 156 .channels = 1, 157 .buswidth = 4, 158 }; 159 160 static struct qcom_icc_node qhs_venus_cfg = { 161 .name = "qhs_venus_cfg", 162 .channels = 1, 163 .buswidth = 4, 164 }; 165 166 static struct qcom_icc_node qhs_vsense_ctrl_cfg = { 167 .name = "qhs_vsense_ctrl_cfg", 168 .channels = 1, 169 .buswidth = 4, 170 }; 171 172 static struct qcom_icc_node xs_qdss_stm = { 173 .name = "xs_qdss_stm", 174 .channels = 1, 175 .buswidth = 4, 176 }; 177 178 static struct qcom_icc_node xs_sys_tcu_cfg = { 179 .name = "xs_sys_tcu_cfg", 180 .channels = 1, 181 .buswidth = 8, 182 }; 183 184 static struct qcom_icc_node qhs_aoss = { 185 .name = "qhs_aoss", 186 .channels = 1, 187 .buswidth = 4, 188 }; 189 190 static struct qcom_icc_node qhs_ipa = { 191 .name = "qhs_ipa", 192 .channels = 1, 193 .buswidth = 4, 194 }; 195 196 static struct qcom_icc_node qhs_ipc_router = { 197 .name = "qhs_ipc_router", 198 .channels = 1, 199 .buswidth = 4, 200 }; 201 202 static struct qcom_icc_node qhs_soccp = { 203 .name = "qhs_soccp", 204 .channels = 1, 205 .buswidth = 4, 206 }; 207 208 static struct qcom_icc_node qhs_tme_cfg = { 209 .name = "qhs_tme_cfg", 210 .channels = 1, 211 .buswidth = 4, 212 }; 213 214 static struct qcom_icc_node qss_apss = { 215 .name = "qss_apss", 216 .channels = 1, 217 .buswidth = 4, 218 }; 219 220 static struct qcom_icc_node qss_ddrss_cfg = { 221 .name = "qss_ddrss_cfg", 222 .channels = 1, 223 .buswidth = 4, 224 }; 225 226 static struct qcom_icc_node qxs_boot_imem = { 227 .name = "qxs_boot_imem", 228 .channels = 1, 229 .buswidth = 16, 230 }; 231 232 static struct qcom_icc_node qxs_imem = { 233 .name = "qxs_imem", 234 .channels = 1, 235 .buswidth = 8, 236 }; 237 238 static struct qcom_icc_node qxs_modem_boot_imem = { 239 .name = "qxs_modem_boot_imem", 240 .channels = 1, 241 .buswidth = 8, 242 }; 243 244 static struct qcom_icc_node srvc_cnoc_main = { 245 .name = "srvc_cnoc_main", 246 .channels = 1, 247 .buswidth = 4, 248 }; 249 250 static struct qcom_icc_node xs_pcie_0 = { 251 .name = "xs_pcie_0", 252 .channels = 1, 253 .buswidth = 8, 254 }; 255 256 static struct qcom_icc_node xs_pcie_1 = { 257 .name = "xs_pcie_1", 258 .channels = 1, 259 .buswidth = 8, 260 }; 261 262 static struct qcom_icc_node ebi = { 263 .name = "ebi", 264 .channels = 4, 265 .buswidth = 4, 266 }; 267 268 static struct qcom_icc_node srvc_mnoc_sf = { 269 .name = "srvc_mnoc_sf", 270 .channels = 1, 271 .buswidth = 4, 272 }; 273 274 static struct qcom_icc_node srvc_mnoc_hf = { 275 .name = "srvc_mnoc_hf", 276 .channels = 1, 277 .buswidth = 4, 278 }; 279 280 static struct qcom_icc_node srvc_pcie_aggre_noc = { 281 .name = "srvc_pcie_aggre_noc", 282 .channels = 1, 283 .buswidth = 4, 284 }; 285 286 static struct qcom_icc_node qup1_core_master = { 287 .name = "qup1_core_master", 288 .channels = 1, 289 .buswidth = 4, 290 .num_links = 1, 291 .link_nodes = { &qup1_core_slave }, 292 }; 293 294 static struct qcom_icc_node qup2_core_master = { 295 .name = "qup2_core_master", 296 .channels = 1, 297 .buswidth = 4, 298 .num_links = 1, 299 .link_nodes = { &qup2_core_slave }, 300 }; 301 302 static struct qcom_icc_node qnm_gemnoc_pcie = { 303 .name = "qnm_gemnoc_pcie", 304 .channels = 1, 305 .buswidth = 16, 306 .num_links = 2, 307 .link_nodes = { &xs_pcie_0, &xs_pcie_1 }, 308 }; 309 310 static struct qcom_icc_node llcc_mc = { 311 .name = "llcc_mc", 312 .channels = 4, 313 .buswidth = 4, 314 .num_links = 1, 315 .link_nodes = { &ebi }, 316 }; 317 318 static struct qcom_icc_node qsm_sf_mnoc_cfg = { 319 .name = "qsm_sf_mnoc_cfg", 320 .channels = 1, 321 .buswidth = 4, 322 .num_links = 1, 323 .link_nodes = { &srvc_mnoc_sf }, 324 }; 325 326 static struct qcom_icc_node qsm_hf_mnoc_cfg = { 327 .name = "qsm_hf_mnoc_cfg", 328 .channels = 1, 329 .buswidth = 4, 330 .num_links = 1, 331 .link_nodes = { &srvc_mnoc_hf }, 332 }; 333 334 static struct qcom_icc_node qsm_pcie_anoc_cfg = { 335 .name = "qsm_pcie_anoc_cfg", 336 .channels = 1, 337 .buswidth = 4, 338 .num_links = 1, 339 .link_nodes = { &srvc_pcie_aggre_noc }, 340 }; 341 342 static struct qcom_icc_node qss_mnoc_hf_cfg = { 343 .name = "qss_mnoc_hf_cfg", 344 .channels = 1, 345 .buswidth = 4, 346 .num_links = 1, 347 .link_nodes = { &qsm_hf_mnoc_cfg }, 348 }; 349 350 static struct qcom_icc_node qss_mnoc_sf_cfg = { 351 .name = "qss_mnoc_sf_cfg", 352 .channels = 1, 353 .buswidth = 4, 354 .num_links = 1, 355 .link_nodes = { &qsm_sf_mnoc_cfg }, 356 }; 357 358 static struct qcom_icc_node qss_pcie_anoc_cfg = { 359 .name = "qss_pcie_anoc_cfg", 360 .channels = 1, 361 .buswidth = 4, 362 .num_links = 1, 363 .link_nodes = { &qsm_pcie_anoc_cfg }, 364 }; 365 366 static struct qcom_icc_node qns_llcc = { 367 .name = "qns_llcc", 368 .channels = 2, 369 .buswidth = 16, 370 .num_links = 1, 371 .link_nodes = { &llcc_mc }, 372 }; 373 374 static struct qcom_icc_node qns_pcie = { 375 .name = "qns_pcie", 376 .channels = 1, 377 .buswidth = 16, 378 .num_links = 1, 379 .link_nodes = { &qnm_gemnoc_pcie }, 380 }; 381 382 static struct qcom_icc_node qsm_cfg = { 383 .name = "qsm_cfg", 384 .channels = 1, 385 .buswidth = 4, 386 .num_links = 29, 387 .link_nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1, 388 &qhs_camera_cfg, &qhs_clk_ctl, 389 &qhs_crypto0_cfg, &qhs_display_cfg, 390 &qhs_gpuss_cfg, &qhs_i3c_ibi0_cfg, 391 &qhs_i3c_ibi1_cfg, &qhs_imem_cfg, 392 &qhs_mss_cfg, &qhs_pcie_0_cfg, 393 &qhs_prng, &qhs_qdss_cfg, 394 &qhs_qspi, &qhs_qup1, 395 &qhs_qup2, &qhs_sdc2, 396 &qhs_tcsr, &qhs_tlmm, 397 &qhs_ufs_mem_cfg, &qhs_usb3_0, 398 &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, 399 &qss_mnoc_hf_cfg, &qss_mnoc_sf_cfg, 400 &qss_pcie_anoc_cfg, &xs_qdss_stm, 401 &xs_sys_tcu_cfg }, 402 }; 403 404 static struct qcom_icc_node xm_gic = { 405 .name = "xm_gic", 406 .channels = 1, 407 .buswidth = 8, 408 .qosbox = &(const struct qcom_icc_qosbox) { 409 .num_ports = 1, 410 .port_offsets = { 0x15d000 }, 411 .prio = 4, 412 .urg_fwd = 0, 413 .prio_fwd_disable = 1, 414 }, 415 .num_links = 1, 416 .link_nodes = { &qns_llcc }, 417 }; 418 419 static struct qcom_icc_node qss_cfg = { 420 .name = "qss_cfg", 421 .channels = 1, 422 .buswidth = 4, 423 .num_links = 1, 424 .link_nodes = { &qsm_cfg }, 425 }; 426 427 static struct qcom_icc_node qnm_gemnoc_cnoc = { 428 .name = "qnm_gemnoc_cnoc", 429 .channels = 1, 430 .buswidth = 16, 431 .num_links = 12, 432 .link_nodes = { &qhs_aoss, &qhs_ipa, 433 &qhs_ipc_router, &qhs_soccp, 434 &qhs_tme_cfg, &qss_apss, 435 &qss_cfg, &qss_ddrss_cfg, 436 &qxs_boot_imem, &qxs_imem, 437 &qxs_modem_boot_imem, &srvc_cnoc_main }, 438 }; 439 440 static struct qcom_icc_node qns_gem_noc_cnoc = { 441 .name = "qns_gem_noc_cnoc", 442 .channels = 1, 443 .buswidth = 16, 444 .num_links = 1, 445 .link_nodes = { &qnm_gemnoc_cnoc }, 446 }; 447 448 static struct qcom_icc_qosbox alm_gpu_tcu_qos = { 449 .num_ports = 1, 450 .port_offsets = { 0x155000 }, 451 .prio = 1, 452 .urg_fwd = 0, 453 .prio_fwd_disable = 1, 454 }; 455 456 static struct qcom_icc_node alm_gpu_tcu = { 457 .name = "alm_gpu_tcu", 458 .channels = 1, 459 .buswidth = 8, 460 .qosbox = &alm_gpu_tcu_qos, 461 .num_links = 2, 462 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 463 }; 464 465 static struct qcom_icc_qosbox alm_sys_tcu_qos = { 466 .num_ports = 1, 467 .port_offsets = { 0x157000 }, 468 .prio = 6, 469 .urg_fwd = 0, 470 .prio_fwd_disable = 1, 471 }; 472 473 static struct qcom_icc_node alm_sys_tcu = { 474 .name = "alm_sys_tcu", 475 .channels = 1, 476 .buswidth = 8, 477 .qosbox = &alm_sys_tcu_qos, 478 .num_links = 2, 479 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 480 }; 481 482 static struct qcom_icc_node chm_apps = { 483 .name = "chm_apps", 484 .channels = 3, 485 .buswidth = 32, 486 .num_links = 3, 487 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 488 &qns_pcie }, 489 }; 490 491 static struct qcom_icc_qosbox qnm_gpu_qos = { 492 .num_ports = 2, 493 .port_offsets = { 0x31000, 0xb1000 }, 494 .prio = 0, 495 .urg_fwd = 1, 496 .prio_fwd_disable = 1, 497 }; 498 499 static struct qcom_icc_node qnm_gpu = { 500 .name = "qnm_gpu", 501 .channels = 2, 502 .buswidth = 32, 503 .qosbox = &qnm_gpu_qos, 504 .num_links = 2, 505 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 506 }; 507 508 static struct qcom_icc_qosbox qnm_lpass_gemnoc_qos = { 509 .num_ports = 1, 510 .port_offsets = { 0x159000 }, 511 .prio = 0, 512 .urg_fwd = 1, 513 .prio_fwd_disable = 0, 514 }; 515 516 static struct qcom_icc_node qnm_lpass_gemnoc = { 517 .name = "qnm_lpass_gemnoc", 518 .channels = 1, 519 .buswidth = 16, 520 .qosbox = &qnm_lpass_gemnoc_qos, 521 .num_links = 3, 522 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 523 &qns_pcie }, 524 }; 525 526 static struct qcom_icc_node qnm_mdsp = { 527 .name = "qnm_mdsp", 528 .channels = 1, 529 .buswidth = 16, 530 .num_links = 3, 531 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 532 &qns_pcie }, 533 }; 534 535 static struct qcom_icc_qosbox qnm_mnoc_hf_qos = { 536 .num_ports = 2, 537 .port_offsets = { 0x33000, 0xb3000 }, 538 .prio = 0, 539 .urg_fwd = 1, 540 .prio_fwd_disable = 0, 541 }; 542 543 static struct qcom_icc_node qnm_mnoc_hf = { 544 .name = "qnm_mnoc_hf", 545 .channels = 2, 546 .buswidth = 32, 547 .qosbox = &qnm_mnoc_hf_qos, 548 .num_links = 2, 549 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 550 }; 551 552 static struct qcom_icc_qosbox qnm_mnoc_sf_qos = { 553 .num_ports = 2, 554 .port_offsets = { 0x35000, 0xb5000 }, 555 .prio = 0, 556 .urg_fwd = 0, 557 .prio_fwd_disable = 0, 558 }; 559 560 static struct qcom_icc_node qnm_mnoc_sf = { 561 .name = "qnm_mnoc_sf", 562 .channels = 2, 563 .buswidth = 32, 564 .qosbox = &qnm_mnoc_sf_qos, 565 .num_links = 2, 566 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 567 }; 568 569 static struct qcom_icc_qosbox qnm_nsp_gemnoc_qos = { 570 .num_ports = 2, 571 .port_offsets = { 0x37000, 0xb7000 }, 572 .prio = 0, 573 .urg_fwd = 1, 574 .prio_fwd_disable = 1, 575 }; 576 577 static struct qcom_icc_node qnm_nsp_gemnoc = { 578 .name = "qnm_nsp_gemnoc", 579 .channels = 2, 580 .buswidth = 32, 581 .qosbox = &qnm_nsp_gemnoc_qos, 582 .num_links = 3, 583 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 584 &qns_pcie }, 585 }; 586 587 static struct qcom_icc_qosbox qnm_pcie_qos = { 588 .num_ports = 1, 589 .port_offsets = { 0x15b000 }, 590 .prio = 2, 591 .urg_fwd = 1, 592 .prio_fwd_disable = 0, 593 }; 594 595 static struct qcom_icc_node qnm_pcie = { 596 .name = "qnm_pcie", 597 .channels = 1, 598 .buswidth = 16, 599 .qosbox = &qnm_pcie_qos, 600 .num_links = 2, 601 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc }, 602 }; 603 604 static struct qcom_icc_node qnm_snoc_sf = { 605 .name = "qnm_snoc_sf", 606 .channels = 1, 607 .buswidth = 16, 608 .qosbox = &(const struct qcom_icc_qosbox) { 609 .num_ports = 1, 610 .port_offsets = { 0x15f000 }, 611 .prio = 0, 612 .urg_fwd = 1, 613 .prio_fwd_disable = 0, 614 }, 615 .num_links = 3, 616 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 617 &qns_pcie }, 618 }; 619 620 static struct qcom_icc_node qxm_wlan_q6 = { 621 .name = "qxm_wlan_q6", 622 .channels = 1, 623 .buswidth = 8, 624 .num_links = 3, 625 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc, 626 &qns_pcie }, 627 }; 628 629 static struct qcom_icc_node qns_lpass_ag_noc_gemnoc = { 630 .name = "qns_lpass_ag_noc_gemnoc", 631 .channels = 1, 632 .buswidth = 16, 633 .num_links = 1, 634 .link_nodes = { &qnm_lpass_gemnoc }, 635 }; 636 637 static struct qcom_icc_node qns_mem_noc_sf = { 638 .name = "qns_mem_noc_sf", 639 .channels = 2, 640 .buswidth = 32, 641 .num_links = 1, 642 .link_nodes = { &qnm_mnoc_sf }, 643 }; 644 645 static struct qcom_icc_node qns_mem_noc_hf = { 646 .name = "qns_mem_noc_hf", 647 .channels = 2, 648 .buswidth = 32, 649 .num_links = 1, 650 .link_nodes = { &qnm_mnoc_hf }, 651 }; 652 653 static struct qcom_icc_node qns_nsp_gemnoc = { 654 .name = "qns_nsp_gemnoc", 655 .channels = 2, 656 .buswidth = 32, 657 .num_links = 1, 658 .link_nodes = { &qnm_nsp_gemnoc }, 659 }; 660 661 static struct qcom_icc_node qns_pcie_mem_noc = { 662 .name = "qns_pcie_mem_noc", 663 .channels = 1, 664 .buswidth = 16, 665 .num_links = 1, 666 .link_nodes = { &qnm_pcie }, 667 }; 668 669 static struct qcom_icc_node qns_gemnoc_sf = { 670 .name = "qns_gemnoc_sf", 671 .channels = 1, 672 .buswidth = 16, 673 .num_links = 1, 674 .link_nodes = { &qnm_snoc_sf }, 675 }; 676 677 static struct qcom_icc_node qnm_lpiaon_noc = { 678 .name = "qnm_lpiaon_noc", 679 .channels = 1, 680 .buswidth = 16, 681 .num_links = 1, 682 .link_nodes = { &qns_lpass_ag_noc_gemnoc }, 683 }; 684 685 static struct qcom_icc_qosbox qnm_camnoc_nrt_icp_sf_qos = { 686 .num_ports = 1, 687 .port_offsets = { 0x25000 }, 688 .prio = 4, 689 .urg_fwd = 0, 690 .prio_fwd_disable = 1, 691 }; 692 693 static struct qcom_icc_node qnm_camnoc_nrt_icp_sf = { 694 .name = "qnm_camnoc_nrt_icp_sf", 695 .channels = 1, 696 .buswidth = 8, 697 .qosbox = &qnm_camnoc_nrt_icp_sf_qos, 698 .num_links = 1, 699 .link_nodes = { &qns_mem_noc_sf }, 700 }; 701 702 static struct qcom_icc_node qnm_camnoc_rt_cdm_sf = { 703 .name = "qnm_camnoc_rt_cdm_sf", 704 .channels = 1, 705 .buswidth = 8, 706 .qosbox = &(const struct qcom_icc_qosbox) { 707 .num_ports = 1, 708 .port_offsets = { 0x2c000 }, 709 .prio = 2, 710 .urg_fwd = 0, 711 .prio_fwd_disable = 1, 712 }, 713 .num_links = 1, 714 .link_nodes = { &qns_mem_noc_sf }, 715 }; 716 717 static struct qcom_icc_node qnm_camnoc_sf = { 718 .name = "qnm_camnoc_sf", 719 .channels = 2, 720 .buswidth = 32, 721 .qosbox = &(const struct qcom_icc_qosbox) { 722 .num_ports = 2, 723 .port_offsets = { 0x26000, 0x27000 }, 724 .prio = 0, 725 .urg_fwd = 1, 726 .prio_fwd_disable = 0, 727 }, 728 .num_links = 1, 729 .link_nodes = { &qns_mem_noc_sf }, 730 }; 731 732 static struct qcom_icc_node qnm_video_mvp = { 733 .name = "qnm_video_mvp", 734 .channels = 1, 735 .buswidth = 32, 736 .qosbox = &(const struct qcom_icc_qosbox) { 737 .num_ports = 1, 738 .port_offsets = { 0x28000 }, 739 .prio = 0, 740 .urg_fwd = 1, 741 .prio_fwd_disable = 0, 742 }, 743 .num_links = 1, 744 .link_nodes = { &qns_mem_noc_sf }, 745 }; 746 747 static struct qcom_icc_node qnm_video_v_cpu = { 748 .name = "qnm_video_v_cpu", 749 .channels = 1, 750 .buswidth = 8, 751 .qosbox = &(const struct qcom_icc_qosbox) { 752 .num_ports = 1, 753 .port_offsets = { 0x2b000 }, 754 .prio = 4, 755 .urg_fwd = 0, 756 .prio_fwd_disable = 1, 757 }, 758 .num_links = 1, 759 .link_nodes = { &qns_mem_noc_sf }, 760 }; 761 762 static struct qcom_icc_node qnm_camnoc_hf = { 763 .name = "qnm_camnoc_hf", 764 .channels = 2, 765 .buswidth = 32, 766 .qosbox = &(const struct qcom_icc_qosbox) { 767 .num_ports = 2, 768 .port_offsets = { 0x64000, 0x65000 }, 769 .prio = 0, 770 .urg_fwd = 1, 771 .prio_fwd_disable = 0, 772 }, 773 .num_links = 1, 774 .link_nodes = { &qns_mem_noc_hf }, 775 }; 776 777 static struct qcom_icc_node qnm_mdp = { 778 .name = "qnm_mdp", 779 .channels = 2, 780 .buswidth = 32, 781 .qosbox = &(const struct qcom_icc_qosbox) { 782 .num_ports = 2, 783 .port_offsets = { 0x66000, 0x67000 }, 784 .prio = 0, 785 .urg_fwd = 1, 786 .prio_fwd_disable = 0, 787 }, 788 .num_links = 1, 789 .link_nodes = { &qns_mem_noc_hf }, 790 }; 791 792 static struct qcom_icc_node qxm_nsp = { 793 .name = "qxm_nsp", 794 .channels = 2, 795 .buswidth = 32, 796 .num_links = 1, 797 .link_nodes = { &qns_nsp_gemnoc }, 798 }; 799 800 static struct qcom_icc_node xm_pcie3_0 = { 801 .name = "xm_pcie3_0", 802 .channels = 1, 803 .buswidth = 8, 804 .qosbox = &(const struct qcom_icc_qosbox) { 805 .num_ports = 1, 806 .port_offsets = { 0xb000 }, 807 .prio = 3, 808 .urg_fwd = 0, 809 .prio_fwd_disable = 1, 810 }, 811 .num_links = 1, 812 .link_nodes = { &qns_pcie_mem_noc }, 813 }; 814 815 static struct qcom_icc_node xm_pcie3_1 = { 816 .name = "xm_pcie3_1", 817 .channels = 1, 818 .buswidth = 8, 819 .qosbox = &(const struct qcom_icc_qosbox) { 820 .num_ports = 1, 821 .port_offsets = { 0xc000 }, 822 .prio = 3, 823 .urg_fwd = 0, 824 .prio_fwd_disable = 1, 825 }, 826 .num_links = 1, 827 .link_nodes = { &qns_pcie_mem_noc }, 828 }; 829 830 static struct qcom_icc_node qnm_aggre1_noc = { 831 .name = "qnm_aggre1_noc", 832 .channels = 1, 833 .buswidth = 16, 834 .num_links = 1, 835 .link_nodes = { &qns_gemnoc_sf }, 836 }; 837 838 static struct qcom_icc_node qnm_aggre2_noc = { 839 .name = "qnm_aggre2_noc", 840 .channels = 1, 841 .buswidth = 16, 842 .num_links = 1, 843 .link_nodes = { &qns_gemnoc_sf }, 844 }; 845 846 static struct qcom_icc_node qnm_cnoc_data = { 847 .name = "qnm_cnoc_data", 848 .channels = 1, 849 .buswidth = 8, 850 .qosbox = &(const struct qcom_icc_qosbox) { 851 .num_ports = 1, 852 .port_offsets = { 0x1d000 }, 853 .prio = 2, 854 .urg_fwd = 0, 855 .prio_fwd_disable = 1, 856 }, 857 .num_links = 1, 858 .link_nodes = { &qns_gemnoc_sf }, 859 }; 860 861 static struct qcom_icc_node qnm_nsinoc_snoc = { 862 .name = "qnm_nsinoc_snoc", 863 .channels = 1, 864 .buswidth = 8, 865 .qosbox = &(const struct qcom_icc_qosbox) { 866 .num_ports = 1, 867 .port_offsets = { 0x1c000 }, 868 .prio = 2, 869 .urg_fwd = 0, 870 .prio_fwd_disable = 1, 871 }, 872 .num_links = 1, 873 .link_nodes = { &qns_gemnoc_sf }, 874 }; 875 876 static struct qcom_icc_node qns_a1noc_snoc = { 877 .name = "qns_a1noc_snoc", 878 .channels = 1, 879 .buswidth = 16, 880 .num_links = 1, 881 .link_nodes = { &qnm_aggre1_noc }, 882 }; 883 884 static struct qcom_icc_node qns_a2noc_snoc = { 885 .name = "qns_a2noc_snoc", 886 .channels = 1, 887 .buswidth = 16, 888 .num_links = 1, 889 .link_nodes = { &qnm_aggre2_noc }, 890 }; 891 892 static struct qcom_icc_node qns_lpass_aggnoc = { 893 .name = "qns_lpass_aggnoc", 894 .channels = 1, 895 .buswidth = 16, 896 .num_links = 1, 897 .link_nodes = { &qnm_lpiaon_noc }, 898 }; 899 900 static struct qcom_icc_node qhm_qspi = { 901 .name = "qhm_qspi", 902 .channels = 1, 903 .buswidth = 4, 904 .qosbox = &(const struct qcom_icc_qosbox) { 905 .num_ports = 1, 906 .port_offsets = { 0xc000 }, 907 .prio = 2, 908 .urg_fwd = 0, 909 .prio_fwd_disable = 1, 910 }, 911 .num_links = 1, 912 .link_nodes = { &qns_a1noc_snoc }, 913 }; 914 915 static struct qcom_icc_node qhm_qup1 = { 916 .name = "qhm_qup1", 917 .channels = 1, 918 .buswidth = 4, 919 .qosbox = &(const struct qcom_icc_qosbox) { 920 .num_ports = 1, 921 .port_offsets = { 0xd000 }, 922 .prio = 2, 923 .urg_fwd = 0, 924 .prio_fwd_disable = 1, 925 }, 926 .num_links = 1, 927 .link_nodes = { &qns_a1noc_snoc }, 928 }; 929 930 static struct qcom_icc_node xm_ufs_mem = { 931 .name = "xm_ufs_mem", 932 .channels = 1, 933 .buswidth = 16, 934 .qosbox = &(const struct qcom_icc_qosbox) { 935 .num_ports = 1, 936 .port_offsets = { 0xf000 }, 937 .prio = 2, 938 .urg_fwd = 0, 939 .prio_fwd_disable = 1, 940 }, 941 .num_links = 1, 942 .link_nodes = { &qns_a1noc_snoc }, 943 }; 944 945 static struct qcom_icc_node xm_usb3_0 = { 946 .name = "xm_usb3_0", 947 .channels = 1, 948 .buswidth = 8, 949 .qosbox = &(const struct qcom_icc_qosbox) { 950 .num_ports = 1, 951 .port_offsets = { 0x10000 }, 952 .prio = 2, 953 .urg_fwd = 0, 954 .prio_fwd_disable = 1, 955 }, 956 .num_links = 1, 957 .link_nodes = { &qns_a1noc_snoc }, 958 }; 959 960 static struct qcom_icc_node qhm_qup2 = { 961 .name = "qhm_qup2", 962 .channels = 1, 963 .buswidth = 4, 964 .qosbox = &(const struct qcom_icc_qosbox) { 965 .num_ports = 1, 966 .port_offsets = { 0x14000 }, 967 .prio = 2, 968 .urg_fwd = 0, 969 .prio_fwd_disable = 1, 970 }, 971 .num_links = 1, 972 .link_nodes = { &qns_a2noc_snoc }, 973 }; 974 975 static struct qcom_icc_node qxm_crypto = { 976 .name = "qxm_crypto", 977 .channels = 1, 978 .buswidth = 8, 979 .qosbox = &(const struct qcom_icc_qosbox) { 980 .num_ports = 1, 981 .port_offsets = { 0x15000 }, 982 .prio = 2, 983 .urg_fwd = 0, 984 .prio_fwd_disable = 1, 985 }, 986 .num_links = 1, 987 .link_nodes = { &qns_a2noc_snoc }, 988 }; 989 990 static struct qcom_icc_node qxm_ipa = { 991 .name = "qxm_ipa", 992 .channels = 1, 993 .buswidth = 8, 994 .qosbox = &(const struct qcom_icc_qosbox) { 995 .num_ports = 1, 996 .port_offsets = { 0x16000 }, 997 .prio = 2, 998 .urg_fwd = 0, 999 .prio_fwd_disable = 1, 1000 }, 1001 .num_links = 1, 1002 .link_nodes = { &qns_a2noc_snoc }, 1003 }; 1004 1005 static struct qcom_icc_node qxm_soccp = { 1006 .name = "qxm_soccp", 1007 .channels = 1, 1008 .buswidth = 8, 1009 .qosbox = &(const struct qcom_icc_qosbox) { 1010 .num_ports = 1, 1011 .port_offsets = { 0x1a000 }, 1012 .prio = 2, 1013 .urg_fwd = 0, 1014 .prio_fwd_disable = 1, 1015 }, 1016 .num_links = 1, 1017 .link_nodes = { &qns_a2noc_snoc }, 1018 }; 1019 1020 static struct qcom_icc_node xm_qdss_etr_0 = { 1021 .name = "xm_qdss_etr_0", 1022 .channels = 1, 1023 .buswidth = 8, 1024 .qosbox = &(const struct qcom_icc_qosbox) { 1025 .num_ports = 1, 1026 .port_offsets = { 0x17000 }, 1027 .prio = 2, 1028 .urg_fwd = 0, 1029 .prio_fwd_disable = 1, 1030 }, 1031 .num_links = 1, 1032 .link_nodes = { &qns_a2noc_snoc }, 1033 }; 1034 1035 static struct qcom_icc_node xm_qdss_etr_1 = { 1036 .name = "xm_qdss_etr_1", 1037 .channels = 1, 1038 .buswidth = 8, 1039 .qosbox = &(const struct qcom_icc_qosbox) { 1040 .num_ports = 1, 1041 .port_offsets = { 0x18000 }, 1042 .prio = 2, 1043 .urg_fwd = 0, 1044 .prio_fwd_disable = 1, 1045 }, 1046 .num_links = 1, 1047 .link_nodes = { &qns_a2noc_snoc }, 1048 }; 1049 1050 static struct qcom_icc_node xm_sdc1 = { 1051 .name = "xm_sdc1", 1052 .channels = 1, 1053 .buswidth = 8, 1054 .qosbox = &(const struct qcom_icc_qosbox) { 1055 .num_ports = 1, 1056 .port_offsets = { 0x13000 }, 1057 .prio = 2, 1058 .urg_fwd = 0, 1059 .prio_fwd_disable = 1, 1060 }, 1061 .num_links = 1, 1062 .link_nodes = { &qns_a2noc_snoc }, 1063 }; 1064 1065 static struct qcom_icc_node xm_sdc2 = { 1066 .name = "xm_sdc2", 1067 .channels = 1, 1068 .buswidth = 8, 1069 .qosbox = &(const struct qcom_icc_qosbox) { 1070 .num_ports = 1, 1071 .port_offsets = { 0x19000 }, 1072 .prio = 2, 1073 .urg_fwd = 0, 1074 .prio_fwd_disable = 1, 1075 }, 1076 .num_links = 1, 1077 .link_nodes = { &qns_a2noc_snoc }, 1078 }; 1079 1080 static struct qcom_icc_node qnm_lpass_lpinoc = { 1081 .name = "qnm_lpass_lpinoc", 1082 .channels = 1, 1083 .buswidth = 16, 1084 .num_links = 1, 1085 .link_nodes = { &qns_lpass_aggnoc }, 1086 }; 1087 1088 static struct qcom_icc_node qns_lpi_aon_noc = { 1089 .name = "qns_lpi_aon_noc", 1090 .channels = 1, 1091 .buswidth = 16, 1092 .num_links = 1, 1093 .link_nodes = { &qnm_lpass_lpinoc }, 1094 }; 1095 1096 static struct qcom_icc_node qxm_lpinoc_dsp_axim = { 1097 .name = "qxm_lpinoc_dsp_axim", 1098 .channels = 1, 1099 .buswidth = 16, 1100 .num_links = 1, 1101 .link_nodes = { &qns_lpi_aon_noc }, 1102 }; 1103 1104 static struct qcom_icc_bcm bcm_ce0 = { 1105 .name = "CE0", 1106 .num_nodes = 1, 1107 .nodes = { &qxm_crypto }, 1108 }; 1109 1110 static struct qcom_icc_bcm bcm_cn0 = { 1111 .name = "CN0", 1112 .enable_mask = BIT(0), 1113 .keepalive = true, 1114 .num_nodes = 43, 1115 .nodes = { &qsm_cfg, &qhs_ahb2phy0, 1116 &qhs_ahb2phy1, &qhs_camera_cfg, 1117 &qhs_clk_ctl, &qhs_crypto0_cfg, 1118 &qhs_gpuss_cfg, &qhs_i3c_ibi0_cfg, 1119 &qhs_i3c_ibi1_cfg, &qhs_imem_cfg, 1120 &qhs_mss_cfg, &qhs_pcie_0_cfg, 1121 &qhs_prng, &qhs_qdss_cfg, 1122 &qhs_qspi, &qhs_sdc2, 1123 &qhs_tcsr, &qhs_tlmm, 1124 &qhs_ufs_mem_cfg, &qhs_usb3_0, 1125 &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, 1126 &qss_mnoc_hf_cfg, &qss_mnoc_sf_cfg, 1127 &qss_pcie_anoc_cfg, &xs_qdss_stm, 1128 &xs_sys_tcu_cfg, &qnm_gemnoc_cnoc, 1129 &qnm_gemnoc_pcie, &qhs_aoss, 1130 &qhs_ipa, &qhs_ipc_router, 1131 &qhs_soccp, &qhs_tme_cfg, 1132 &qss_apss, &qss_cfg, 1133 &qss_ddrss_cfg, &qxs_boot_imem, 1134 &qxs_imem, &qxs_modem_boot_imem, 1135 &srvc_cnoc_main, &xs_pcie_0, 1136 &xs_pcie_1 }, 1137 }; 1138 1139 static struct qcom_icc_bcm bcm_cn1 = { 1140 .name = "CN1", 1141 .num_nodes = 3, 1142 .nodes = { &qhs_display_cfg, &qhs_qup1, 1143 &qhs_qup2 }, 1144 }; 1145 1146 static struct qcom_icc_bcm bcm_co0 = { 1147 .name = "CO0", 1148 .enable_mask = BIT(0), 1149 .num_nodes = 2, 1150 .nodes = { &qxm_nsp, &qns_nsp_gemnoc }, 1151 }; 1152 1153 static struct qcom_icc_bcm bcm_lp0 = { 1154 .name = "LP0", 1155 .num_nodes = 2, 1156 .nodes = { &qnm_lpass_lpinoc, &qns_lpass_aggnoc }, 1157 }; 1158 1159 static struct qcom_icc_bcm bcm_mc0 = { 1160 .name = "MC0", 1161 .keepalive = true, 1162 .num_nodes = 1, 1163 .nodes = { &ebi }, 1164 }; 1165 1166 static struct qcom_icc_bcm bcm_mm0 = { 1167 .name = "MM0", 1168 .num_nodes = 1, 1169 .nodes = { &qns_mem_noc_hf }, 1170 }; 1171 1172 static struct qcom_icc_bcm bcm_mm1 = { 1173 .name = "MM1", 1174 .enable_mask = BIT(0), 1175 .num_nodes = 7, 1176 .nodes = { &qnm_camnoc_nrt_icp_sf, &qnm_camnoc_rt_cdm_sf, 1177 &qnm_camnoc_sf, &qnm_video_mvp, 1178 &qnm_video_v_cpu, &qnm_camnoc_hf, 1179 &qns_mem_noc_sf }, 1180 }; 1181 1182 static struct qcom_icc_bcm bcm_qup1 = { 1183 .name = "QUP1", 1184 .vote_scale = 1, 1185 .keepalive = true, 1186 .num_nodes = 1, 1187 .nodes = { &qup1_core_slave }, 1188 }; 1189 1190 static struct qcom_icc_bcm bcm_qup2 = { 1191 .name = "QUP2", 1192 .vote_scale = 1, 1193 .keepalive = true, 1194 .num_nodes = 1, 1195 .nodes = { &qup2_core_slave }, 1196 }; 1197 1198 static struct qcom_icc_bcm bcm_sh0 = { 1199 .name = "SH0", 1200 .keepalive = true, 1201 .num_nodes = 1, 1202 .nodes = { &qns_llcc }, 1203 }; 1204 1205 static struct qcom_icc_bcm bcm_sh1 = { 1206 .name = "SH1", 1207 .enable_mask = BIT(0), 1208 .num_nodes = 14, 1209 .nodes = { &alm_gpu_tcu, &alm_sys_tcu, 1210 &chm_apps, &qnm_gpu, 1211 &qnm_mdsp, &qnm_mnoc_hf, 1212 &qnm_mnoc_sf, &qnm_nsp_gemnoc, 1213 &qnm_pcie, &qnm_snoc_sf, 1214 &qxm_wlan_q6, &xm_gic, 1215 &qns_gem_noc_cnoc, &qns_pcie }, 1216 }; 1217 1218 static struct qcom_icc_bcm bcm_sn0 = { 1219 .name = "SN0", 1220 .keepalive = true, 1221 .num_nodes = 1, 1222 .nodes = { &qns_gemnoc_sf }, 1223 }; 1224 1225 static struct qcom_icc_bcm bcm_sn2 = { 1226 .name = "SN2", 1227 .num_nodes = 1, 1228 .nodes = { &qnm_aggre1_noc }, 1229 }; 1230 1231 static struct qcom_icc_bcm bcm_sn3 = { 1232 .name = "SN3", 1233 .num_nodes = 1, 1234 .nodes = { &qnm_aggre2_noc }, 1235 }; 1236 1237 static struct qcom_icc_bcm bcm_sn4 = { 1238 .name = "SN4", 1239 .num_nodes = 1, 1240 .nodes = { &qns_pcie_mem_noc }, 1241 }; 1242 1243 static struct qcom_icc_node * const aggre1_noc_nodes[] = { 1244 [MASTER_QSPI_0] = &qhm_qspi, 1245 [MASTER_QUP_1] = &qhm_qup1, 1246 [MASTER_UFS_MEM] = &xm_ufs_mem, 1247 [MASTER_USB3_0] = &xm_usb3_0, 1248 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc, 1249 }; 1250 1251 static const struct qcom_icc_desc eliza_aggre1_noc = { 1252 .nodes = aggre1_noc_nodes, 1253 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes), 1254 .qos_requires_clocks = true, 1255 }; 1256 1257 static struct qcom_icc_bcm * const aggre2_noc_bcms[] = { 1258 &bcm_ce0, 1259 }; 1260 1261 static struct qcom_icc_node * const aggre2_noc_nodes[] = { 1262 [MASTER_QUP_2] = &qhm_qup2, 1263 [MASTER_CRYPTO] = &qxm_crypto, 1264 [MASTER_IPA] = &qxm_ipa, 1265 [MASTER_SOCCP_AGGR_NOC] = &qxm_soccp, 1266 [MASTER_QDSS_ETR] = &xm_qdss_etr_0, 1267 [MASTER_QDSS_ETR_1] = &xm_qdss_etr_1, 1268 [MASTER_SDCC_1] = &xm_sdc1, 1269 [MASTER_SDCC_2] = &xm_sdc2, 1270 [SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc, 1271 }; 1272 1273 static const struct qcom_icc_desc eliza_aggre2_noc = { 1274 .nodes = aggre2_noc_nodes, 1275 .num_nodes = ARRAY_SIZE(aggre2_noc_nodes), 1276 .bcms = aggre2_noc_bcms, 1277 .num_bcms = ARRAY_SIZE(aggre2_noc_bcms), 1278 .qos_requires_clocks = true, 1279 }; 1280 1281 static struct qcom_icc_bcm * const clk_virt_bcms[] = { 1282 &bcm_qup1, 1283 &bcm_qup2, 1284 }; 1285 1286 static struct qcom_icc_node * const clk_virt_nodes[] = { 1287 [MASTER_QUP_CORE_1] = &qup1_core_master, 1288 [MASTER_QUP_CORE_2] = &qup2_core_master, 1289 [SLAVE_QUP_CORE_1] = &qup1_core_slave, 1290 [SLAVE_QUP_CORE_2] = &qup2_core_slave, 1291 }; 1292 1293 static const struct qcom_icc_desc eliza_clk_virt = { 1294 .nodes = clk_virt_nodes, 1295 .num_nodes = ARRAY_SIZE(clk_virt_nodes), 1296 .bcms = clk_virt_bcms, 1297 .num_bcms = ARRAY_SIZE(clk_virt_bcms), 1298 }; 1299 1300 static struct qcom_icc_bcm * const cnoc_cfg_bcms[] = { 1301 &bcm_cn0, 1302 &bcm_cn1, 1303 }; 1304 1305 static struct qcom_icc_node * const cnoc_cfg_nodes[] = { 1306 [MASTER_CNOC_CFG] = &qsm_cfg, 1307 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0, 1308 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1, 1309 [SLAVE_CAMERA_CFG] = &qhs_camera_cfg, 1310 [SLAVE_CLK_CTL] = &qhs_clk_ctl, 1311 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg, 1312 [SLAVE_DISPLAY_CFG] = &qhs_display_cfg, 1313 [SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg, 1314 [SLAVE_I3C_IBI0_CFG] = &qhs_i3c_ibi0_cfg, 1315 [SLAVE_I3C_IBI1_CFG] = &qhs_i3c_ibi1_cfg, 1316 [SLAVE_IMEM_CFG] = &qhs_imem_cfg, 1317 [SLAVE_CNOC_MSS] = &qhs_mss_cfg, 1318 [SLAVE_PCIE_0_CFG] = &qhs_pcie_0_cfg, 1319 [SLAVE_PRNG] = &qhs_prng, 1320 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg, 1321 [SLAVE_QSPI_0] = &qhs_qspi, 1322 [SLAVE_QUP_1] = &qhs_qup1, 1323 [SLAVE_QUP_2] = &qhs_qup2, 1324 [SLAVE_SDCC_2] = &qhs_sdc2, 1325 [SLAVE_TCSR] = &qhs_tcsr, 1326 [SLAVE_TLMM] = &qhs_tlmm, 1327 [SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg, 1328 [SLAVE_USB3_0] = &qhs_usb3_0, 1329 [SLAVE_VENUS_CFG] = &qhs_venus_cfg, 1330 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg, 1331 [SLAVE_CNOC_MNOC_HF_CFG] = &qss_mnoc_hf_cfg, 1332 [SLAVE_CNOC_MNOC_SF_CFG] = &qss_mnoc_sf_cfg, 1333 [SLAVE_PCIE_ANOC_CFG] = &qss_pcie_anoc_cfg, 1334 [SLAVE_QDSS_STM] = &xs_qdss_stm, 1335 [SLAVE_TCU] = &xs_sys_tcu_cfg, 1336 }; 1337 1338 static const struct qcom_icc_desc eliza_cnoc_cfg = { 1339 .nodes = cnoc_cfg_nodes, 1340 .num_nodes = ARRAY_SIZE(cnoc_cfg_nodes), 1341 .bcms = cnoc_cfg_bcms, 1342 .num_bcms = ARRAY_SIZE(cnoc_cfg_bcms), 1343 }; 1344 1345 static struct qcom_icc_bcm * const cnoc_main_bcms[] = { 1346 &bcm_cn0, 1347 }; 1348 1349 static struct qcom_icc_node * const cnoc_main_nodes[] = { 1350 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc, 1351 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie, 1352 [SLAVE_AOSS] = &qhs_aoss, 1353 [SLAVE_IPA_CFG] = &qhs_ipa, 1354 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router, 1355 [SLAVE_SOCCP] = &qhs_soccp, 1356 [SLAVE_TME_CFG] = &qhs_tme_cfg, 1357 [SLAVE_APPSS] = &qss_apss, 1358 [SLAVE_CNOC_CFG] = &qss_cfg, 1359 [SLAVE_DDRSS_CFG] = &qss_ddrss_cfg, 1360 [SLAVE_BOOT_IMEM] = &qxs_boot_imem, 1361 [SLAVE_IMEM] = &qxs_imem, 1362 [SLAVE_BOOT_IMEM_2] = &qxs_modem_boot_imem, 1363 [SLAVE_SERVICE_CNOC] = &srvc_cnoc_main, 1364 [SLAVE_PCIE_0] = &xs_pcie_0, 1365 [SLAVE_PCIE_1] = &xs_pcie_1, 1366 }; 1367 1368 static const struct qcom_icc_desc eliza_cnoc_main = { 1369 .nodes = cnoc_main_nodes, 1370 .num_nodes = ARRAY_SIZE(cnoc_main_nodes), 1371 .bcms = cnoc_main_bcms, 1372 .num_bcms = ARRAY_SIZE(cnoc_main_bcms), 1373 }; 1374 1375 static struct qcom_icc_bcm * const gem_noc_bcms[] = { 1376 &bcm_sh0, 1377 &bcm_sh1, 1378 }; 1379 1380 static struct qcom_icc_node * const gem_noc_nodes[] = { 1381 [MASTER_GPU_TCU] = &alm_gpu_tcu, 1382 [MASTER_SYS_TCU] = &alm_sys_tcu, 1383 [MASTER_APPSS_PROC] = &chm_apps, 1384 [MASTER_GFX3D] = &qnm_gpu, 1385 [MASTER_LPASS_GEM_NOC] = &qnm_lpass_gemnoc, 1386 [MASTER_MSS_PROC] = &qnm_mdsp, 1387 [MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf, 1388 [MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf, 1389 [MASTER_COMPUTE_NOC] = &qnm_nsp_gemnoc, 1390 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie, 1391 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf, 1392 [MASTER_WLAN_Q6] = &qxm_wlan_q6, 1393 [MASTER_GIC] = &xm_gic, 1394 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, 1395 [SLAVE_LLCC] = &qns_llcc, 1396 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, 1397 }; 1398 1399 static const struct qcom_icc_desc eliza_gem_noc = { 1400 .nodes = gem_noc_nodes, 1401 .num_nodes = ARRAY_SIZE(gem_noc_nodes), 1402 .bcms = gem_noc_bcms, 1403 .num_bcms = ARRAY_SIZE(gem_noc_bcms), 1404 }; 1405 1406 static struct qcom_icc_node * const lpass_ag_noc_nodes[] = { 1407 [MASTER_LPIAON_NOC] = &qnm_lpiaon_noc, 1408 [SLAVE_LPASS_GEM_NOC] = &qns_lpass_ag_noc_gemnoc, 1409 }; 1410 1411 static const struct qcom_icc_desc eliza_lpass_ag_noc = { 1412 .nodes = lpass_ag_noc_nodes, 1413 .num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes), 1414 }; 1415 1416 static struct qcom_icc_bcm * const lpass_lpiaon_noc_bcms[] = { 1417 &bcm_lp0, 1418 }; 1419 1420 static struct qcom_icc_node * const lpass_lpiaon_noc_nodes[] = { 1421 [MASTER_LPASS_LPINOC] = &qnm_lpass_lpinoc, 1422 [SLAVE_LPIAON_NOC_LPASS_AG_NOC] = &qns_lpass_aggnoc, 1423 }; 1424 1425 static const struct qcom_icc_desc eliza_lpass_lpiaon_noc = { 1426 .nodes = lpass_lpiaon_noc_nodes, 1427 .num_nodes = ARRAY_SIZE(lpass_lpiaon_noc_nodes), 1428 .bcms = lpass_lpiaon_noc_bcms, 1429 .num_bcms = ARRAY_SIZE(lpass_lpiaon_noc_bcms), 1430 }; 1431 1432 static struct qcom_icc_node * const lpass_lpicx_noc_nodes[] = { 1433 [MASTER_LPASS_PROC] = &qxm_lpinoc_dsp_axim, 1434 [SLAVE_LPICX_NOC_LPIAON_NOC] = &qns_lpi_aon_noc, 1435 }; 1436 1437 static const struct qcom_icc_desc eliza_lpass_lpicx_noc = { 1438 .nodes = lpass_lpicx_noc_nodes, 1439 .num_nodes = ARRAY_SIZE(lpass_lpicx_noc_nodes), 1440 }; 1441 1442 static struct qcom_icc_bcm * const mc_virt_bcms[] = { 1443 &bcm_mc0, 1444 }; 1445 1446 static struct qcom_icc_node * const mc_virt_nodes[] = { 1447 [MASTER_LLCC] = &llcc_mc, 1448 [SLAVE_EBI1] = &ebi, 1449 }; 1450 1451 static const struct qcom_icc_desc eliza_mc_virt = { 1452 .nodes = mc_virt_nodes, 1453 .num_nodes = ARRAY_SIZE(mc_virt_nodes), 1454 .bcms = mc_virt_bcms, 1455 .num_bcms = ARRAY_SIZE(mc_virt_bcms), 1456 }; 1457 1458 static struct qcom_icc_bcm * const mmss_noc_bcms[] = { 1459 &bcm_mm0, 1460 &bcm_mm1, 1461 }; 1462 1463 static struct qcom_icc_node * const mmss_noc_nodes[] = { 1464 [MASTER_CAMNOC_NRT_ICP_SF] = &qnm_camnoc_nrt_icp_sf, 1465 [MASTER_CAMNOC_RT_CDM_SF] = &qnm_camnoc_rt_cdm_sf, 1466 [MASTER_CAMNOC_SF] = &qnm_camnoc_sf, 1467 [MASTER_VIDEO_MVP] = &qnm_video_mvp, 1468 [MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu, 1469 [MASTER_CNOC_MNOC_SF_CFG] = &qsm_sf_mnoc_cfg, 1470 [MASTER_CAMNOC_HF] = &qnm_camnoc_hf, 1471 [MASTER_MDP] = &qnm_mdp, 1472 [MASTER_CNOC_MNOC_HF_CFG] = &qsm_hf_mnoc_cfg, 1473 [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, 1474 [SLAVE_SERVICE_MNOC_SF] = &srvc_mnoc_sf, 1475 [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, 1476 [SLAVE_SERVICE_MNOC_HF] = &srvc_mnoc_hf, 1477 }; 1478 1479 static const struct qcom_icc_desc eliza_mmss_noc = { 1480 .nodes = mmss_noc_nodes, 1481 .num_nodes = ARRAY_SIZE(mmss_noc_nodes), 1482 .bcms = mmss_noc_bcms, 1483 .num_bcms = ARRAY_SIZE(mmss_noc_bcms), 1484 }; 1485 1486 static struct qcom_icc_bcm * const nsp_noc_bcms[] = { 1487 &bcm_co0, 1488 }; 1489 1490 static struct qcom_icc_node * const nsp_noc_nodes[] = { 1491 [MASTER_CDSP_PROC] = &qxm_nsp, 1492 [SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc, 1493 }; 1494 1495 static const struct qcom_icc_desc eliza_nsp_noc = { 1496 .nodes = nsp_noc_nodes, 1497 .num_nodes = ARRAY_SIZE(nsp_noc_nodes), 1498 .bcms = nsp_noc_bcms, 1499 .num_bcms = ARRAY_SIZE(nsp_noc_bcms), 1500 }; 1501 1502 static struct qcom_icc_bcm * const pcie_anoc_bcms[] = { 1503 &bcm_sn4, 1504 }; 1505 1506 static struct qcom_icc_node * const pcie_anoc_nodes[] = { 1507 [MASTER_PCIE_ANOC_CFG] = &qsm_pcie_anoc_cfg, 1508 [MASTER_PCIE_0] = &xm_pcie3_0, 1509 [MASTER_PCIE_1] = &xm_pcie3_1, 1510 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, 1511 [SLAVE_SERVICE_PCIE_ANOC] = &srvc_pcie_aggre_noc, 1512 }; 1513 1514 static const struct qcom_icc_desc eliza_pcie_anoc = { 1515 .nodes = pcie_anoc_nodes, 1516 .num_nodes = ARRAY_SIZE(pcie_anoc_nodes), 1517 .bcms = pcie_anoc_bcms, 1518 .num_bcms = ARRAY_SIZE(pcie_anoc_bcms), 1519 .qos_requires_clocks = true, 1520 }; 1521 1522 static struct qcom_icc_bcm * const system_noc_bcms[] = { 1523 &bcm_sn0, 1524 &bcm_sn2, 1525 &bcm_sn3, 1526 }; 1527 1528 static struct qcom_icc_node * const system_noc_nodes[] = { 1529 [MASTER_A1NOC_SNOC] = &qnm_aggre1_noc, 1530 [MASTER_A2NOC_SNOC] = &qnm_aggre2_noc, 1531 [MASTER_CNOC_SNOC] = &qnm_cnoc_data, 1532 [MASTER_NSINOC_SNOC] = &qnm_nsinoc_snoc, 1533 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf, 1534 }; 1535 1536 static const struct qcom_icc_desc eliza_system_noc = { 1537 .nodes = system_noc_nodes, 1538 .num_nodes = ARRAY_SIZE(system_noc_nodes), 1539 .bcms = system_noc_bcms, 1540 .num_bcms = ARRAY_SIZE(system_noc_bcms), 1541 }; 1542 1543 static const struct of_device_id qnoc_of_match[] = { 1544 { .compatible = "qcom,eliza-aggre1-noc", .data = &eliza_aggre1_noc }, 1545 { .compatible = "qcom,eliza-aggre2-noc", .data = &eliza_aggre2_noc }, 1546 { .compatible = "qcom,eliza-clk-virt", .data = &eliza_clk_virt }, 1547 { .compatible = "qcom,eliza-cnoc-cfg", .data = &eliza_cnoc_cfg }, 1548 { .compatible = "qcom,eliza-cnoc-main", .data = &eliza_cnoc_main }, 1549 { .compatible = "qcom,eliza-gem-noc", .data = &eliza_gem_noc }, 1550 { .compatible = "qcom,eliza-lpass-ag-noc", .data = &eliza_lpass_ag_noc }, 1551 { .compatible = "qcom,eliza-lpass-lpiaon-noc", .data = &eliza_lpass_lpiaon_noc }, 1552 { .compatible = "qcom,eliza-lpass-lpicx-noc", .data = &eliza_lpass_lpicx_noc }, 1553 { .compatible = "qcom,eliza-mc-virt", .data = &eliza_mc_virt }, 1554 { .compatible = "qcom,eliza-mmss-noc", .data = &eliza_mmss_noc }, 1555 { .compatible = "qcom,eliza-nsp-noc", .data = &eliza_nsp_noc }, 1556 { .compatible = "qcom,eliza-pcie-anoc", .data = &eliza_pcie_anoc }, 1557 { .compatible = "qcom,eliza-system-noc", .data = &eliza_system_noc }, 1558 { } 1559 }; 1560 MODULE_DEVICE_TABLE(of, qnoc_of_match); 1561 1562 static struct platform_driver qnoc_driver = { 1563 .probe = qcom_icc_rpmh_probe, 1564 .remove = qcom_icc_rpmh_remove, 1565 .driver = { 1566 .name = "qnoc-eliza", 1567 .of_match_table = qnoc_of_match, 1568 .sync_state = icc_sync_state, 1569 }, 1570 }; 1571 1572 static int __init qnoc_driver_init(void) 1573 { 1574 return platform_driver_register(&qnoc_driver); 1575 } 1576 core_initcall(qnoc_driver_init); 1577 1578 static void __exit qnoc_driver_exit(void) 1579 { 1580 platform_driver_unregister(&qnoc_driver); 1581 } 1582 module_exit(qnoc_driver_exit); 1583 1584 MODULE_DESCRIPTION(" Qualcomm Eliza NoC driver"); 1585 MODULE_LICENSE("GPL"); 1586