1 /* 2 * i8042 keyboard and mouse controller driver for Linux 3 * 4 * Copyright (c) 1999-2004 Vojtech Pavlik 5 */ 6 7 /* 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License version 2 as published by 10 * the Free Software Foundation. 11 */ 12 13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 14 15 #include <linux/types.h> 16 #include <linux/delay.h> 17 #include <linux/module.h> 18 #include <linux/interrupt.h> 19 #include <linux/ioport.h> 20 #include <linux/init.h> 21 #include <linux/serio.h> 22 #include <linux/err.h> 23 #include <linux/rcupdate.h> 24 #include <linux/platform_device.h> 25 #include <linux/i8042.h> 26 #include <linux/slab.h> 27 #include <linux/suspend.h> 28 29 #include <asm/io.h> 30 31 MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>"); 32 MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver"); 33 MODULE_LICENSE("GPL"); 34 35 static bool i8042_nokbd; 36 module_param_named(nokbd, i8042_nokbd, bool, 0); 37 MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port."); 38 39 static bool i8042_noaux; 40 module_param_named(noaux, i8042_noaux, bool, 0); 41 MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port."); 42 43 static bool i8042_nomux; 44 module_param_named(nomux, i8042_nomux, bool, 0); 45 MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing controller is present."); 46 47 static bool i8042_unlock; 48 module_param_named(unlock, i8042_unlock, bool, 0); 49 MODULE_PARM_DESC(unlock, "Ignore keyboard lock."); 50 51 enum i8042_controller_reset_mode { 52 I8042_RESET_NEVER, 53 I8042_RESET_ALWAYS, 54 I8042_RESET_ON_S2RAM, 55 #define I8042_RESET_DEFAULT I8042_RESET_ON_S2RAM 56 }; 57 static enum i8042_controller_reset_mode i8042_reset = I8042_RESET_DEFAULT; 58 static int i8042_set_reset(const char *val, const struct kernel_param *kp) 59 { 60 enum i8042_controller_reset_mode *arg = kp->arg; 61 int error; 62 bool reset; 63 64 if (val) { 65 error = kstrtobool(val, &reset); 66 if (error) 67 return error; 68 } else { 69 reset = true; 70 } 71 72 *arg = reset ? I8042_RESET_ALWAYS : I8042_RESET_NEVER; 73 return 0; 74 } 75 76 static const struct kernel_param_ops param_ops_reset_param = { 77 .flags = KERNEL_PARAM_OPS_FL_NOARG, 78 .set = i8042_set_reset, 79 }; 80 #define param_check_reset_param(name, p) \ 81 __param_check(name, p, enum i8042_controller_reset_mode) 82 module_param_named(reset, i8042_reset, reset_param, 0); 83 MODULE_PARM_DESC(reset, "Reset controller on resume, cleanup or both"); 84 85 static bool i8042_direct; 86 module_param_named(direct, i8042_direct, bool, 0); 87 MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode."); 88 89 static bool i8042_dumbkbd; 90 module_param_named(dumbkbd, i8042_dumbkbd, bool, 0); 91 MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard"); 92 93 static bool i8042_noloop; 94 module_param_named(noloop, i8042_noloop, bool, 0); 95 MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port"); 96 97 static bool i8042_notimeout; 98 module_param_named(notimeout, i8042_notimeout, bool, 0); 99 MODULE_PARM_DESC(notimeout, "Ignore timeouts signalled by i8042"); 100 101 static bool i8042_kbdreset; 102 module_param_named(kbdreset, i8042_kbdreset, bool, 0); 103 MODULE_PARM_DESC(kbdreset, "Reset device connected to KBD port"); 104 105 #ifdef CONFIG_X86 106 static bool i8042_dritek; 107 module_param_named(dritek, i8042_dritek, bool, 0); 108 MODULE_PARM_DESC(dritek, "Force enable the Dritek keyboard extension"); 109 #endif 110 111 #ifdef CONFIG_PNP 112 static bool i8042_nopnp; 113 module_param_named(nopnp, i8042_nopnp, bool, 0); 114 MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings"); 115 #endif 116 117 #define DEBUG 118 #ifdef DEBUG 119 static bool i8042_debug; 120 module_param_named(debug, i8042_debug, bool, 0600); 121 MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off"); 122 123 static bool i8042_unmask_kbd_data; 124 module_param_named(unmask_kbd_data, i8042_unmask_kbd_data, bool, 0600); 125 MODULE_PARM_DESC(unmask_kbd_data, "Unconditional enable (may reveal sensitive data) of normally sanitize-filtered kbd data traffic debug log [pre-condition: i8042.debug=1 enabled]"); 126 #endif 127 128 static bool i8042_bypass_aux_irq_test; 129 static char i8042_kbd_firmware_id[128]; 130 static char i8042_aux_firmware_id[128]; 131 132 #include "i8042.h" 133 134 /* 135 * i8042_lock protects serialization between i8042_command and 136 * the interrupt handler. 137 */ 138 static DEFINE_SPINLOCK(i8042_lock); 139 140 /* 141 * Writers to AUX and KBD ports as well as users issuing i8042_command 142 * directly should acquire i8042_mutex (by means of calling 143 * i8042_lock_chip() and i8042_unlock_ship() helpers) to ensure that 144 * they do not disturb each other (unfortunately in many i8042 145 * implementations write to one of the ports will immediately abort 146 * command that is being processed by another port). 147 */ 148 static DEFINE_MUTEX(i8042_mutex); 149 150 struct i8042_port { 151 struct serio *serio; 152 int irq; 153 bool exists; 154 bool driver_bound; 155 signed char mux; 156 }; 157 158 #define I8042_KBD_PORT_NO 0 159 #define I8042_AUX_PORT_NO 1 160 #define I8042_MUX_PORT_NO 2 161 #define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2) 162 163 static struct i8042_port i8042_ports[I8042_NUM_PORTS]; 164 165 static unsigned char i8042_initial_ctr; 166 static unsigned char i8042_ctr; 167 static bool i8042_mux_present; 168 static bool i8042_kbd_irq_registered; 169 static bool i8042_aux_irq_registered; 170 static unsigned char i8042_suppress_kbd_ack; 171 static struct platform_device *i8042_platform_device; 172 static struct notifier_block i8042_kbd_bind_notifier_block; 173 174 static irqreturn_t i8042_interrupt(int irq, void *dev_id); 175 static bool (*i8042_platform_filter)(unsigned char data, unsigned char str, 176 struct serio *serio); 177 178 void i8042_lock_chip(void) 179 { 180 mutex_lock(&i8042_mutex); 181 } 182 EXPORT_SYMBOL(i8042_lock_chip); 183 184 void i8042_unlock_chip(void) 185 { 186 mutex_unlock(&i8042_mutex); 187 } 188 EXPORT_SYMBOL(i8042_unlock_chip); 189 190 int i8042_install_filter(bool (*filter)(unsigned char data, unsigned char str, 191 struct serio *serio)) 192 { 193 unsigned long flags; 194 int ret = 0; 195 196 spin_lock_irqsave(&i8042_lock, flags); 197 198 if (i8042_platform_filter) { 199 ret = -EBUSY; 200 goto out; 201 } 202 203 i8042_platform_filter = filter; 204 205 out: 206 spin_unlock_irqrestore(&i8042_lock, flags); 207 return ret; 208 } 209 EXPORT_SYMBOL(i8042_install_filter); 210 211 int i8042_remove_filter(bool (*filter)(unsigned char data, unsigned char str, 212 struct serio *port)) 213 { 214 unsigned long flags; 215 int ret = 0; 216 217 spin_lock_irqsave(&i8042_lock, flags); 218 219 if (i8042_platform_filter != filter) { 220 ret = -EINVAL; 221 goto out; 222 } 223 224 i8042_platform_filter = NULL; 225 226 out: 227 spin_unlock_irqrestore(&i8042_lock, flags); 228 return ret; 229 } 230 EXPORT_SYMBOL(i8042_remove_filter); 231 232 /* 233 * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to 234 * be ready for reading values from it / writing values to it. 235 * Called always with i8042_lock held. 236 */ 237 238 static int i8042_wait_read(void) 239 { 240 int i = 0; 241 242 while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) { 243 udelay(50); 244 i++; 245 } 246 return -(i == I8042_CTL_TIMEOUT); 247 } 248 249 static int i8042_wait_write(void) 250 { 251 int i = 0; 252 253 while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) { 254 udelay(50); 255 i++; 256 } 257 return -(i == I8042_CTL_TIMEOUT); 258 } 259 260 /* 261 * i8042_flush() flushes all data that may be in the keyboard and mouse buffers 262 * of the i8042 down the toilet. 263 */ 264 265 static int i8042_flush(void) 266 { 267 unsigned long flags; 268 unsigned char data, str; 269 int count = 0; 270 int retval = 0; 271 272 spin_lock_irqsave(&i8042_lock, flags); 273 274 while ((str = i8042_read_status()) & I8042_STR_OBF) { 275 if (count++ < I8042_BUFFER_SIZE) { 276 udelay(50); 277 data = i8042_read_data(); 278 dbg("%02x <- i8042 (flush, %s)\n", 279 data, str & I8042_STR_AUXDATA ? "aux" : "kbd"); 280 } else { 281 retval = -EIO; 282 break; 283 } 284 } 285 286 spin_unlock_irqrestore(&i8042_lock, flags); 287 288 return retval; 289 } 290 291 /* 292 * i8042_command() executes a command on the i8042. It also sends the input 293 * parameter(s) of the commands to it, and receives the output value(s). The 294 * parameters are to be stored in the param array, and the output is placed 295 * into the same array. The number of the parameters and output values is 296 * encoded in bits 8-11 of the command number. 297 */ 298 299 static int __i8042_command(unsigned char *param, int command) 300 { 301 int i, error; 302 303 if (i8042_noloop && command == I8042_CMD_AUX_LOOP) 304 return -1; 305 306 error = i8042_wait_write(); 307 if (error) 308 return error; 309 310 dbg("%02x -> i8042 (command)\n", command & 0xff); 311 i8042_write_command(command & 0xff); 312 313 for (i = 0; i < ((command >> 12) & 0xf); i++) { 314 error = i8042_wait_write(); 315 if (error) { 316 dbg(" -- i8042 (wait write timeout)\n"); 317 return error; 318 } 319 dbg("%02x -> i8042 (parameter)\n", param[i]); 320 i8042_write_data(param[i]); 321 } 322 323 for (i = 0; i < ((command >> 8) & 0xf); i++) { 324 error = i8042_wait_read(); 325 if (error) { 326 dbg(" -- i8042 (wait read timeout)\n"); 327 return error; 328 } 329 330 if (command == I8042_CMD_AUX_LOOP && 331 !(i8042_read_status() & I8042_STR_AUXDATA)) { 332 dbg(" -- i8042 (auxerr)\n"); 333 return -1; 334 } 335 336 param[i] = i8042_read_data(); 337 dbg("%02x <- i8042 (return)\n", param[i]); 338 } 339 340 return 0; 341 } 342 343 int i8042_command(unsigned char *param, int command) 344 { 345 unsigned long flags; 346 int retval; 347 348 spin_lock_irqsave(&i8042_lock, flags); 349 retval = __i8042_command(param, command); 350 spin_unlock_irqrestore(&i8042_lock, flags); 351 352 return retval; 353 } 354 EXPORT_SYMBOL(i8042_command); 355 356 /* 357 * i8042_kbd_write() sends a byte out through the keyboard interface. 358 */ 359 360 static int i8042_kbd_write(struct serio *port, unsigned char c) 361 { 362 unsigned long flags; 363 int retval = 0; 364 365 spin_lock_irqsave(&i8042_lock, flags); 366 367 if (!(retval = i8042_wait_write())) { 368 dbg("%02x -> i8042 (kbd-data)\n", c); 369 i8042_write_data(c); 370 } 371 372 spin_unlock_irqrestore(&i8042_lock, flags); 373 374 return retval; 375 } 376 377 /* 378 * i8042_aux_write() sends a byte out through the aux interface. 379 */ 380 381 static int i8042_aux_write(struct serio *serio, unsigned char c) 382 { 383 struct i8042_port *port = serio->port_data; 384 385 return i8042_command(&c, port->mux == -1 ? 386 I8042_CMD_AUX_SEND : 387 I8042_CMD_MUX_SEND + port->mux); 388 } 389 390 391 /* 392 * i8042_port_close attempts to clear AUX or KBD port state by disabling 393 * and then re-enabling it. 394 */ 395 396 static void i8042_port_close(struct serio *serio) 397 { 398 int irq_bit; 399 int disable_bit; 400 const char *port_name; 401 402 if (serio == i8042_ports[I8042_AUX_PORT_NO].serio) { 403 irq_bit = I8042_CTR_AUXINT; 404 disable_bit = I8042_CTR_AUXDIS; 405 port_name = "AUX"; 406 } else { 407 irq_bit = I8042_CTR_KBDINT; 408 disable_bit = I8042_CTR_KBDDIS; 409 port_name = "KBD"; 410 } 411 412 i8042_ctr &= ~irq_bit; 413 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 414 pr_warn("Can't write CTR while closing %s port\n", port_name); 415 416 udelay(50); 417 418 i8042_ctr &= ~disable_bit; 419 i8042_ctr |= irq_bit; 420 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 421 pr_err("Can't reactivate %s port\n", port_name); 422 423 /* 424 * See if there is any data appeared while we were messing with 425 * port state. 426 */ 427 i8042_interrupt(0, NULL); 428 } 429 430 /* 431 * i8042_start() is called by serio core when port is about to finish 432 * registering. It will mark port as existing so i8042_interrupt can 433 * start sending data through it. 434 */ 435 static int i8042_start(struct serio *serio) 436 { 437 struct i8042_port *port = serio->port_data; 438 439 port->exists = true; 440 mb(); 441 return 0; 442 } 443 444 /* 445 * i8042_stop() marks serio port as non-existing so i8042_interrupt 446 * will not try to send data to the port that is about to go away. 447 * The function is called by serio core as part of unregister procedure. 448 */ 449 static void i8042_stop(struct serio *serio) 450 { 451 struct i8042_port *port = serio->port_data; 452 453 port->exists = false; 454 455 /* 456 * We synchronize with both AUX and KBD IRQs because there is 457 * a (very unlikely) chance that AUX IRQ is raised for KBD port 458 * and vice versa. 459 */ 460 synchronize_irq(I8042_AUX_IRQ); 461 synchronize_irq(I8042_KBD_IRQ); 462 port->serio = NULL; 463 } 464 465 /* 466 * i8042_filter() filters out unwanted bytes from the input data stream. 467 * It is called from i8042_interrupt and thus is running with interrupts 468 * off and i8042_lock held. 469 */ 470 static bool i8042_filter(unsigned char data, unsigned char str, 471 struct serio *serio) 472 { 473 if (unlikely(i8042_suppress_kbd_ack)) { 474 if ((~str & I8042_STR_AUXDATA) && 475 (data == 0xfa || data == 0xfe)) { 476 i8042_suppress_kbd_ack--; 477 dbg("Extra keyboard ACK - filtered out\n"); 478 return true; 479 } 480 } 481 482 if (i8042_platform_filter && i8042_platform_filter(data, str, serio)) { 483 dbg("Filtered out by platform filter\n"); 484 return true; 485 } 486 487 return false; 488 } 489 490 /* 491 * i8042_interrupt() is the most important function in this driver - 492 * it handles the interrupts from the i8042, and sends incoming bytes 493 * to the upper layers. 494 */ 495 496 static irqreturn_t i8042_interrupt(int irq, void *dev_id) 497 { 498 struct i8042_port *port; 499 struct serio *serio; 500 unsigned long flags; 501 unsigned char str, data; 502 unsigned int dfl; 503 unsigned int port_no; 504 bool filtered; 505 int ret = 1; 506 507 spin_lock_irqsave(&i8042_lock, flags); 508 509 str = i8042_read_status(); 510 if (unlikely(~str & I8042_STR_OBF)) { 511 spin_unlock_irqrestore(&i8042_lock, flags); 512 if (irq) 513 dbg("Interrupt %d, without any data\n", irq); 514 ret = 0; 515 goto out; 516 } 517 518 data = i8042_read_data(); 519 520 if (i8042_mux_present && (str & I8042_STR_AUXDATA)) { 521 static unsigned long last_transmit; 522 static unsigned char last_str; 523 524 dfl = 0; 525 if (str & I8042_STR_MUXERR) { 526 dbg("MUX error, status is %02x, data is %02x\n", 527 str, data); 528 /* 529 * When MUXERR condition is signalled the data register can only contain 530 * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately 531 * it is not always the case. Some KBCs also report 0xfc when there is 532 * nothing connected to the port while others sometimes get confused which 533 * port the data came from and signal error leaving the data intact. They 534 * _do not_ revert to legacy mode (actually I've never seen KBC reverting 535 * to legacy mode yet, when we see one we'll add proper handling). 536 * Anyway, we process 0xfc, 0xfd, 0xfe and 0xff as timeouts, and for the 537 * rest assume that the data came from the same serio last byte 538 * was transmitted (if transmission happened not too long ago). 539 */ 540 541 switch (data) { 542 default: 543 if (time_before(jiffies, last_transmit + HZ/10)) { 544 str = last_str; 545 break; 546 } 547 /* fall through - report timeout */ 548 case 0xfc: 549 case 0xfd: 550 case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break; 551 case 0xff: dfl = SERIO_PARITY; data = 0xfe; break; 552 } 553 } 554 555 port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3); 556 last_str = str; 557 last_transmit = jiffies; 558 } else { 559 560 dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) | 561 ((str & I8042_STR_TIMEOUT && !i8042_notimeout) ? SERIO_TIMEOUT : 0); 562 563 port_no = (str & I8042_STR_AUXDATA) ? 564 I8042_AUX_PORT_NO : I8042_KBD_PORT_NO; 565 } 566 567 port = &i8042_ports[port_no]; 568 serio = port->exists ? port->serio : NULL; 569 570 filter_dbg(port->driver_bound, data, "<- i8042 (interrupt, %d, %d%s%s)\n", 571 port_no, irq, 572 dfl & SERIO_PARITY ? ", bad parity" : "", 573 dfl & SERIO_TIMEOUT ? ", timeout" : ""); 574 575 filtered = i8042_filter(data, str, serio); 576 577 spin_unlock_irqrestore(&i8042_lock, flags); 578 579 if (likely(port->exists && !filtered)) 580 serio_interrupt(serio, data, dfl); 581 582 out: 583 return IRQ_RETVAL(ret); 584 } 585 586 /* 587 * i8042_enable_kbd_port enables keyboard port on chip 588 */ 589 590 static int i8042_enable_kbd_port(void) 591 { 592 i8042_ctr &= ~I8042_CTR_KBDDIS; 593 i8042_ctr |= I8042_CTR_KBDINT; 594 595 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 596 i8042_ctr &= ~I8042_CTR_KBDINT; 597 i8042_ctr |= I8042_CTR_KBDDIS; 598 pr_err("Failed to enable KBD port\n"); 599 return -EIO; 600 } 601 602 return 0; 603 } 604 605 /* 606 * i8042_enable_aux_port enables AUX (mouse) port on chip 607 */ 608 609 static int i8042_enable_aux_port(void) 610 { 611 i8042_ctr &= ~I8042_CTR_AUXDIS; 612 i8042_ctr |= I8042_CTR_AUXINT; 613 614 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 615 i8042_ctr &= ~I8042_CTR_AUXINT; 616 i8042_ctr |= I8042_CTR_AUXDIS; 617 pr_err("Failed to enable AUX port\n"); 618 return -EIO; 619 } 620 621 return 0; 622 } 623 624 /* 625 * i8042_enable_mux_ports enables 4 individual AUX ports after 626 * the controller has been switched into Multiplexed mode 627 */ 628 629 static int i8042_enable_mux_ports(void) 630 { 631 unsigned char param; 632 int i; 633 634 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { 635 i8042_command(¶m, I8042_CMD_MUX_PFX + i); 636 i8042_command(¶m, I8042_CMD_AUX_ENABLE); 637 } 638 639 return i8042_enable_aux_port(); 640 } 641 642 /* 643 * i8042_set_mux_mode checks whether the controller has an 644 * active multiplexor and puts the chip into Multiplexed (true) 645 * or Legacy (false) mode. 646 */ 647 648 static int i8042_set_mux_mode(bool multiplex, unsigned char *mux_version) 649 { 650 651 unsigned char param, val; 652 /* 653 * Get rid of bytes in the queue. 654 */ 655 656 i8042_flush(); 657 658 /* 659 * Internal loopback test - send three bytes, they should come back from the 660 * mouse interface, the last should be version. 661 */ 662 663 param = val = 0xf0; 664 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) 665 return -1; 666 param = val = multiplex ? 0x56 : 0xf6; 667 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) 668 return -1; 669 param = val = multiplex ? 0xa4 : 0xa5; 670 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == val) 671 return -1; 672 673 /* 674 * Workaround for interference with USB Legacy emulation 675 * that causes a v10.12 MUX to be found. 676 */ 677 if (param == 0xac) 678 return -1; 679 680 if (mux_version) 681 *mux_version = param; 682 683 return 0; 684 } 685 686 /* 687 * i8042_check_mux() checks whether the controller supports the PS/2 Active 688 * Multiplexing specification by Synaptics, Phoenix, Insyde and 689 * LCS/Telegraphics. 690 */ 691 692 static int __init i8042_check_mux(void) 693 { 694 unsigned char mux_version; 695 696 if (i8042_set_mux_mode(true, &mux_version)) 697 return -1; 698 699 pr_info("Detected active multiplexing controller, rev %d.%d\n", 700 (mux_version >> 4) & 0xf, mux_version & 0xf); 701 702 /* 703 * Disable all muxed ports by disabling AUX. 704 */ 705 i8042_ctr |= I8042_CTR_AUXDIS; 706 i8042_ctr &= ~I8042_CTR_AUXINT; 707 708 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 709 pr_err("Failed to disable AUX port, can't use MUX\n"); 710 return -EIO; 711 } 712 713 i8042_mux_present = true; 714 715 return 0; 716 } 717 718 /* 719 * The following is used to test AUX IRQ delivery. 720 */ 721 static struct completion i8042_aux_irq_delivered __initdata; 722 static bool i8042_irq_being_tested __initdata; 723 724 static irqreturn_t __init i8042_aux_test_irq(int irq, void *dev_id) 725 { 726 unsigned long flags; 727 unsigned char str, data; 728 int ret = 0; 729 730 spin_lock_irqsave(&i8042_lock, flags); 731 str = i8042_read_status(); 732 if (str & I8042_STR_OBF) { 733 data = i8042_read_data(); 734 dbg("%02x <- i8042 (aux_test_irq, %s)\n", 735 data, str & I8042_STR_AUXDATA ? "aux" : "kbd"); 736 if (i8042_irq_being_tested && 737 data == 0xa5 && (str & I8042_STR_AUXDATA)) 738 complete(&i8042_aux_irq_delivered); 739 ret = 1; 740 } 741 spin_unlock_irqrestore(&i8042_lock, flags); 742 743 return IRQ_RETVAL(ret); 744 } 745 746 /* 747 * i8042_toggle_aux - enables or disables AUX port on i8042 via command and 748 * verifies success by readinng CTR. Used when testing for presence of AUX 749 * port. 750 */ 751 static int __init i8042_toggle_aux(bool on) 752 { 753 unsigned char param; 754 int i; 755 756 if (i8042_command(¶m, 757 on ? I8042_CMD_AUX_ENABLE : I8042_CMD_AUX_DISABLE)) 758 return -1; 759 760 /* some chips need some time to set the I8042_CTR_AUXDIS bit */ 761 for (i = 0; i < 100; i++) { 762 udelay(50); 763 764 if (i8042_command(¶m, I8042_CMD_CTL_RCTR)) 765 return -1; 766 767 if (!(param & I8042_CTR_AUXDIS) == on) 768 return 0; 769 } 770 771 return -1; 772 } 773 774 /* 775 * i8042_check_aux() applies as much paranoia as it can at detecting 776 * the presence of an AUX interface. 777 */ 778 779 static int __init i8042_check_aux(void) 780 { 781 int retval = -1; 782 bool irq_registered = false; 783 bool aux_loop_broken = false; 784 unsigned long flags; 785 unsigned char param; 786 787 /* 788 * Get rid of bytes in the queue. 789 */ 790 791 i8042_flush(); 792 793 /* 794 * Internal loopback test - filters out AT-type i8042's. Unfortunately 795 * SiS screwed up and their 5597 doesn't support the LOOP command even 796 * though it has an AUX port. 797 */ 798 799 param = 0x5a; 800 retval = i8042_command(¶m, I8042_CMD_AUX_LOOP); 801 if (retval || param != 0x5a) { 802 803 /* 804 * External connection test - filters out AT-soldered PS/2 i8042's 805 * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error 806 * 0xfa - no error on some notebooks which ignore the spec 807 * Because it's common for chipsets to return error on perfectly functioning 808 * AUX ports, we test for this only when the LOOP command failed. 809 */ 810 811 if (i8042_command(¶m, I8042_CMD_AUX_TEST) || 812 (param && param != 0xfa && param != 0xff)) 813 return -1; 814 815 /* 816 * If AUX_LOOP completed without error but returned unexpected data 817 * mark it as broken 818 */ 819 if (!retval) 820 aux_loop_broken = true; 821 } 822 823 /* 824 * Bit assignment test - filters out PS/2 i8042's in AT mode 825 */ 826 827 if (i8042_toggle_aux(false)) { 828 pr_warn("Failed to disable AUX port, but continuing anyway... Is this a SiS?\n"); 829 pr_warn("If AUX port is really absent please use the 'i8042.noaux' option\n"); 830 } 831 832 if (i8042_toggle_aux(true)) 833 return -1; 834 835 /* 836 * Reset keyboard (needed on some laptops to successfully detect 837 * touchpad, e.g., some Gigabyte laptop models with Elantech 838 * touchpads). 839 */ 840 if (i8042_kbdreset) { 841 pr_warn("Attempting to reset device connected to KBD port\n"); 842 i8042_kbd_write(NULL, (unsigned char) 0xff); 843 } 844 845 /* 846 * Test AUX IRQ delivery to make sure BIOS did not grab the IRQ and 847 * used it for a PCI card or somethig else. 848 */ 849 850 if (i8042_noloop || i8042_bypass_aux_irq_test || aux_loop_broken) { 851 /* 852 * Without LOOP command we can't test AUX IRQ delivery. Assume the port 853 * is working and hope we are right. 854 */ 855 retval = 0; 856 goto out; 857 } 858 859 if (request_irq(I8042_AUX_IRQ, i8042_aux_test_irq, IRQF_SHARED, 860 "i8042", i8042_platform_device)) 861 goto out; 862 863 irq_registered = true; 864 865 if (i8042_enable_aux_port()) 866 goto out; 867 868 spin_lock_irqsave(&i8042_lock, flags); 869 870 init_completion(&i8042_aux_irq_delivered); 871 i8042_irq_being_tested = true; 872 873 param = 0xa5; 874 retval = __i8042_command(¶m, I8042_CMD_AUX_LOOP & 0xf0ff); 875 876 spin_unlock_irqrestore(&i8042_lock, flags); 877 878 if (retval) 879 goto out; 880 881 if (wait_for_completion_timeout(&i8042_aux_irq_delivered, 882 msecs_to_jiffies(250)) == 0) { 883 /* 884 * AUX IRQ was never delivered so we need to flush the controller to 885 * get rid of the byte we put there; otherwise keyboard may not work. 886 */ 887 dbg(" -- i8042 (aux irq test timeout)\n"); 888 i8042_flush(); 889 retval = -1; 890 } 891 892 out: 893 894 /* 895 * Disable the interface. 896 */ 897 898 i8042_ctr |= I8042_CTR_AUXDIS; 899 i8042_ctr &= ~I8042_CTR_AUXINT; 900 901 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 902 retval = -1; 903 904 if (irq_registered) 905 free_irq(I8042_AUX_IRQ, i8042_platform_device); 906 907 return retval; 908 } 909 910 static int i8042_controller_check(void) 911 { 912 if (i8042_flush()) { 913 pr_info("No controller found\n"); 914 return -ENODEV; 915 } 916 917 return 0; 918 } 919 920 static int i8042_controller_selftest(void) 921 { 922 unsigned char param; 923 int i = 0; 924 925 /* 926 * We try this 5 times; on some really fragile systems this does not 927 * take the first time... 928 */ 929 do { 930 931 if (i8042_command(¶m, I8042_CMD_CTL_TEST)) { 932 pr_err("i8042 controller selftest timeout\n"); 933 return -ENODEV; 934 } 935 936 if (param == I8042_RET_CTL_TEST) 937 return 0; 938 939 dbg("i8042 controller selftest: %#x != %#x\n", 940 param, I8042_RET_CTL_TEST); 941 msleep(50); 942 } while (i++ < 5); 943 944 #ifdef CONFIG_X86 945 /* 946 * On x86, we don't fail entire i8042 initialization if controller 947 * reset fails in hopes that keyboard port will still be functional 948 * and user will still get a working keyboard. This is especially 949 * important on netbooks. On other arches we trust hardware more. 950 */ 951 pr_info("giving up on controller selftest, continuing anyway...\n"); 952 return 0; 953 #else 954 pr_err("i8042 controller selftest failed\n"); 955 return -EIO; 956 #endif 957 } 958 959 /* 960 * i8042_controller init initializes the i8042 controller, and, 961 * most importantly, sets it into non-xlated mode if that's 962 * desired. 963 */ 964 965 static int i8042_controller_init(void) 966 { 967 unsigned long flags; 968 int n = 0; 969 unsigned char ctr[2]; 970 971 /* 972 * Save the CTR for restore on unload / reboot. 973 */ 974 975 do { 976 if (n >= 10) { 977 pr_err("Unable to get stable CTR read\n"); 978 return -EIO; 979 } 980 981 if (n != 0) 982 udelay(50); 983 984 if (i8042_command(&ctr[n++ % 2], I8042_CMD_CTL_RCTR)) { 985 pr_err("Can't read CTR while initializing i8042\n"); 986 return -EIO; 987 } 988 989 } while (n < 2 || ctr[0] != ctr[1]); 990 991 i8042_initial_ctr = i8042_ctr = ctr[0]; 992 993 /* 994 * Disable the keyboard interface and interrupt. 995 */ 996 997 i8042_ctr |= I8042_CTR_KBDDIS; 998 i8042_ctr &= ~I8042_CTR_KBDINT; 999 1000 /* 1001 * Handle keylock. 1002 */ 1003 1004 spin_lock_irqsave(&i8042_lock, flags); 1005 if (~i8042_read_status() & I8042_STR_KEYLOCK) { 1006 if (i8042_unlock) 1007 i8042_ctr |= I8042_CTR_IGNKEYLOCK; 1008 else 1009 pr_warn("Warning: Keylock active\n"); 1010 } 1011 spin_unlock_irqrestore(&i8042_lock, flags); 1012 1013 /* 1014 * If the chip is configured into nontranslated mode by the BIOS, don't 1015 * bother enabling translating and be happy. 1016 */ 1017 1018 if (~i8042_ctr & I8042_CTR_XLATE) 1019 i8042_direct = true; 1020 1021 /* 1022 * Set nontranslated mode for the kbd interface if requested by an option. 1023 * After this the kbd interface becomes a simple serial in/out, like the aux 1024 * interface is. We don't do this by default, since it can confuse notebook 1025 * BIOSes. 1026 */ 1027 1028 if (i8042_direct) 1029 i8042_ctr &= ~I8042_CTR_XLATE; 1030 1031 /* 1032 * Write CTR back. 1033 */ 1034 1035 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 1036 pr_err("Can't write CTR while initializing i8042\n"); 1037 return -EIO; 1038 } 1039 1040 /* 1041 * Flush whatever accumulated while we were disabling keyboard port. 1042 */ 1043 1044 i8042_flush(); 1045 1046 return 0; 1047 } 1048 1049 1050 /* 1051 * Reset the controller and reset CRT to the original value set by BIOS. 1052 */ 1053 1054 static void i8042_controller_reset(bool s2r_wants_reset) 1055 { 1056 i8042_flush(); 1057 1058 /* 1059 * Disable both KBD and AUX interfaces so they don't get in the way 1060 */ 1061 1062 i8042_ctr |= I8042_CTR_KBDDIS | I8042_CTR_AUXDIS; 1063 i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT); 1064 1065 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 1066 pr_warn("Can't write CTR while resetting\n"); 1067 1068 /* 1069 * Disable MUX mode if present. 1070 */ 1071 1072 if (i8042_mux_present) 1073 i8042_set_mux_mode(false, NULL); 1074 1075 /* 1076 * Reset the controller if requested. 1077 */ 1078 1079 if (i8042_reset == I8042_RESET_ALWAYS || 1080 (i8042_reset == I8042_RESET_ON_S2RAM && s2r_wants_reset)) { 1081 i8042_controller_selftest(); 1082 } 1083 1084 /* 1085 * Restore the original control register setting. 1086 */ 1087 1088 if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR)) 1089 pr_warn("Can't restore CTR\n"); 1090 } 1091 1092 1093 /* 1094 * i8042_panic_blink() will turn the keyboard LEDs on or off and is called 1095 * when kernel panics. Flashing LEDs is useful for users running X who may 1096 * not see the console and will help distinguishing panics from "real" 1097 * lockups. 1098 * 1099 * Note that DELAY has a limit of 10ms so we will not get stuck here 1100 * waiting for KBC to free up even if KBD interrupt is off 1101 */ 1102 1103 #define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0) 1104 1105 static long i8042_panic_blink(int state) 1106 { 1107 long delay = 0; 1108 char led; 1109 1110 led = (state) ? 0x01 | 0x04 : 0; 1111 while (i8042_read_status() & I8042_STR_IBF) 1112 DELAY; 1113 dbg("%02x -> i8042 (panic blink)\n", 0xed); 1114 i8042_suppress_kbd_ack = 2; 1115 i8042_write_data(0xed); /* set leds */ 1116 DELAY; 1117 while (i8042_read_status() & I8042_STR_IBF) 1118 DELAY; 1119 DELAY; 1120 dbg("%02x -> i8042 (panic blink)\n", led); 1121 i8042_write_data(led); 1122 DELAY; 1123 return delay; 1124 } 1125 1126 #undef DELAY 1127 1128 #ifdef CONFIG_X86 1129 static void i8042_dritek_enable(void) 1130 { 1131 unsigned char param = 0x90; 1132 int error; 1133 1134 error = i8042_command(¶m, 0x1059); 1135 if (error) 1136 pr_warn("Failed to enable DRITEK extension: %d\n", error); 1137 } 1138 #endif 1139 1140 #ifdef CONFIG_PM 1141 1142 /* 1143 * Here we try to reset everything back to a state we had 1144 * before suspending. 1145 */ 1146 1147 static int i8042_controller_resume(bool s2r_wants_reset) 1148 { 1149 int error; 1150 1151 error = i8042_controller_check(); 1152 if (error) 1153 return error; 1154 1155 if (i8042_reset == I8042_RESET_ALWAYS || 1156 (i8042_reset == I8042_RESET_ON_S2RAM && s2r_wants_reset)) { 1157 error = i8042_controller_selftest(); 1158 if (error) 1159 return error; 1160 } 1161 1162 /* 1163 * Restore original CTR value and disable all ports 1164 */ 1165 1166 i8042_ctr = i8042_initial_ctr; 1167 if (i8042_direct) 1168 i8042_ctr &= ~I8042_CTR_XLATE; 1169 i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS; 1170 i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT); 1171 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 1172 pr_warn("Can't write CTR to resume, retrying...\n"); 1173 msleep(50); 1174 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 1175 pr_err("CTR write retry failed\n"); 1176 return -EIO; 1177 } 1178 } 1179 1180 1181 #ifdef CONFIG_X86 1182 if (i8042_dritek) 1183 i8042_dritek_enable(); 1184 #endif 1185 1186 if (i8042_mux_present) { 1187 if (i8042_set_mux_mode(true, NULL) || i8042_enable_mux_ports()) 1188 pr_warn("failed to resume active multiplexor, mouse won't work\n"); 1189 } else if (i8042_ports[I8042_AUX_PORT_NO].serio) 1190 i8042_enable_aux_port(); 1191 1192 if (i8042_ports[I8042_KBD_PORT_NO].serio) 1193 i8042_enable_kbd_port(); 1194 1195 i8042_interrupt(0, NULL); 1196 1197 return 0; 1198 } 1199 1200 /* 1201 * Here we try to restore the original BIOS settings to avoid 1202 * upsetting it. 1203 */ 1204 1205 static int i8042_pm_suspend(struct device *dev) 1206 { 1207 int i; 1208 1209 if (pm_suspend_via_firmware()) 1210 i8042_controller_reset(true); 1211 1212 /* Set up serio interrupts for system wakeup. */ 1213 for (i = 0; i < I8042_NUM_PORTS; i++) { 1214 struct serio *serio = i8042_ports[i].serio; 1215 1216 if (serio && device_may_wakeup(&serio->dev)) 1217 enable_irq_wake(i8042_ports[i].irq); 1218 } 1219 1220 return 0; 1221 } 1222 1223 static int i8042_pm_resume_noirq(struct device *dev) 1224 { 1225 if (!pm_resume_via_firmware()) 1226 i8042_interrupt(0, NULL); 1227 1228 return 0; 1229 } 1230 1231 static int i8042_pm_resume(struct device *dev) 1232 { 1233 bool want_reset; 1234 int i; 1235 1236 for (i = 0; i < I8042_NUM_PORTS; i++) { 1237 struct serio *serio = i8042_ports[i].serio; 1238 1239 if (serio && device_may_wakeup(&serio->dev)) 1240 disable_irq_wake(i8042_ports[i].irq); 1241 } 1242 1243 /* 1244 * If platform firmware was not going to be involved in suspend, we did 1245 * not restore the controller state to whatever it had been at boot 1246 * time, so we do not need to do anything. 1247 */ 1248 if (!pm_suspend_via_firmware()) 1249 return 0; 1250 1251 /* 1252 * We only need to reset the controller if we are resuming after handing 1253 * off control to the platform firmware, otherwise we can simply restore 1254 * the mode. 1255 */ 1256 want_reset = pm_resume_via_firmware(); 1257 1258 return i8042_controller_resume(want_reset); 1259 } 1260 1261 static int i8042_pm_thaw(struct device *dev) 1262 { 1263 i8042_interrupt(0, NULL); 1264 1265 return 0; 1266 } 1267 1268 static int i8042_pm_reset(struct device *dev) 1269 { 1270 i8042_controller_reset(false); 1271 1272 return 0; 1273 } 1274 1275 static int i8042_pm_restore(struct device *dev) 1276 { 1277 return i8042_controller_resume(false); 1278 } 1279 1280 static const struct dev_pm_ops i8042_pm_ops = { 1281 .suspend = i8042_pm_suspend, 1282 .resume_noirq = i8042_pm_resume_noirq, 1283 .resume = i8042_pm_resume, 1284 .thaw = i8042_pm_thaw, 1285 .poweroff = i8042_pm_reset, 1286 .restore = i8042_pm_restore, 1287 }; 1288 1289 #endif /* CONFIG_PM */ 1290 1291 /* 1292 * We need to reset the 8042 back to original mode on system shutdown, 1293 * because otherwise BIOSes will be confused. 1294 */ 1295 1296 static void i8042_shutdown(struct platform_device *dev) 1297 { 1298 i8042_controller_reset(false); 1299 } 1300 1301 static int __init i8042_create_kbd_port(void) 1302 { 1303 struct serio *serio; 1304 struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO]; 1305 1306 serio = kzalloc(sizeof(struct serio), GFP_KERNEL); 1307 if (!serio) 1308 return -ENOMEM; 1309 1310 serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL; 1311 serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write; 1312 serio->start = i8042_start; 1313 serio->stop = i8042_stop; 1314 serio->close = i8042_port_close; 1315 serio->ps2_cmd_mutex = &i8042_mutex; 1316 serio->port_data = port; 1317 serio->dev.parent = &i8042_platform_device->dev; 1318 strlcpy(serio->name, "i8042 KBD port", sizeof(serio->name)); 1319 strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys)); 1320 strlcpy(serio->firmware_id, i8042_kbd_firmware_id, 1321 sizeof(serio->firmware_id)); 1322 1323 port->serio = serio; 1324 port->irq = I8042_KBD_IRQ; 1325 1326 return 0; 1327 } 1328 1329 static int __init i8042_create_aux_port(int idx) 1330 { 1331 struct serio *serio; 1332 int port_no = idx < 0 ? I8042_AUX_PORT_NO : I8042_MUX_PORT_NO + idx; 1333 struct i8042_port *port = &i8042_ports[port_no]; 1334 1335 serio = kzalloc(sizeof(struct serio), GFP_KERNEL); 1336 if (!serio) 1337 return -ENOMEM; 1338 1339 serio->id.type = SERIO_8042; 1340 serio->write = i8042_aux_write; 1341 serio->start = i8042_start; 1342 serio->stop = i8042_stop; 1343 serio->ps2_cmd_mutex = &i8042_mutex; 1344 serio->port_data = port; 1345 serio->dev.parent = &i8042_platform_device->dev; 1346 if (idx < 0) { 1347 strlcpy(serio->name, "i8042 AUX port", sizeof(serio->name)); 1348 strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys)); 1349 strlcpy(serio->firmware_id, i8042_aux_firmware_id, 1350 sizeof(serio->firmware_id)); 1351 serio->close = i8042_port_close; 1352 } else { 1353 snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx); 1354 snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1); 1355 strlcpy(serio->firmware_id, i8042_aux_firmware_id, 1356 sizeof(serio->firmware_id)); 1357 } 1358 1359 port->serio = serio; 1360 port->mux = idx; 1361 port->irq = I8042_AUX_IRQ; 1362 1363 return 0; 1364 } 1365 1366 static void __init i8042_free_kbd_port(void) 1367 { 1368 kfree(i8042_ports[I8042_KBD_PORT_NO].serio); 1369 i8042_ports[I8042_KBD_PORT_NO].serio = NULL; 1370 } 1371 1372 static void __init i8042_free_aux_ports(void) 1373 { 1374 int i; 1375 1376 for (i = I8042_AUX_PORT_NO; i < I8042_NUM_PORTS; i++) { 1377 kfree(i8042_ports[i].serio); 1378 i8042_ports[i].serio = NULL; 1379 } 1380 } 1381 1382 static void __init i8042_register_ports(void) 1383 { 1384 int i; 1385 1386 for (i = 0; i < I8042_NUM_PORTS; i++) { 1387 struct serio *serio = i8042_ports[i].serio; 1388 1389 if (serio) { 1390 printk(KERN_INFO "serio: %s at %#lx,%#lx irq %d\n", 1391 serio->name, 1392 (unsigned long) I8042_DATA_REG, 1393 (unsigned long) I8042_COMMAND_REG, 1394 i8042_ports[i].irq); 1395 serio_register_port(serio); 1396 device_set_wakeup_capable(&serio->dev, true); 1397 } 1398 } 1399 } 1400 1401 static void i8042_unregister_ports(void) 1402 { 1403 int i; 1404 1405 for (i = 0; i < I8042_NUM_PORTS; i++) { 1406 if (i8042_ports[i].serio) { 1407 serio_unregister_port(i8042_ports[i].serio); 1408 i8042_ports[i].serio = NULL; 1409 } 1410 } 1411 } 1412 1413 static void i8042_free_irqs(void) 1414 { 1415 if (i8042_aux_irq_registered) 1416 free_irq(I8042_AUX_IRQ, i8042_platform_device); 1417 if (i8042_kbd_irq_registered) 1418 free_irq(I8042_KBD_IRQ, i8042_platform_device); 1419 1420 i8042_aux_irq_registered = i8042_kbd_irq_registered = false; 1421 } 1422 1423 static int __init i8042_setup_aux(void) 1424 { 1425 int (*aux_enable)(void); 1426 int error; 1427 int i; 1428 1429 if (i8042_check_aux()) 1430 return -ENODEV; 1431 1432 if (i8042_nomux || i8042_check_mux()) { 1433 error = i8042_create_aux_port(-1); 1434 if (error) 1435 goto err_free_ports; 1436 aux_enable = i8042_enable_aux_port; 1437 } else { 1438 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { 1439 error = i8042_create_aux_port(i); 1440 if (error) 1441 goto err_free_ports; 1442 } 1443 aux_enable = i8042_enable_mux_ports; 1444 } 1445 1446 error = request_irq(I8042_AUX_IRQ, i8042_interrupt, IRQF_SHARED, 1447 "i8042", i8042_platform_device); 1448 if (error) 1449 goto err_free_ports; 1450 1451 if (aux_enable()) 1452 goto err_free_irq; 1453 1454 i8042_aux_irq_registered = true; 1455 return 0; 1456 1457 err_free_irq: 1458 free_irq(I8042_AUX_IRQ, i8042_platform_device); 1459 err_free_ports: 1460 i8042_free_aux_ports(); 1461 return error; 1462 } 1463 1464 static int __init i8042_setup_kbd(void) 1465 { 1466 int error; 1467 1468 error = i8042_create_kbd_port(); 1469 if (error) 1470 return error; 1471 1472 error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED, 1473 "i8042", i8042_platform_device); 1474 if (error) 1475 goto err_free_port; 1476 1477 error = i8042_enable_kbd_port(); 1478 if (error) 1479 goto err_free_irq; 1480 1481 i8042_kbd_irq_registered = true; 1482 return 0; 1483 1484 err_free_irq: 1485 free_irq(I8042_KBD_IRQ, i8042_platform_device); 1486 err_free_port: 1487 i8042_free_kbd_port(); 1488 return error; 1489 } 1490 1491 static int i8042_kbd_bind_notifier(struct notifier_block *nb, 1492 unsigned long action, void *data) 1493 { 1494 struct device *dev = data; 1495 struct serio *serio = to_serio_port(dev); 1496 struct i8042_port *port = serio->port_data; 1497 1498 if (serio != i8042_ports[I8042_KBD_PORT_NO].serio) 1499 return 0; 1500 1501 switch (action) { 1502 case BUS_NOTIFY_BOUND_DRIVER: 1503 port->driver_bound = true; 1504 break; 1505 1506 case BUS_NOTIFY_UNBIND_DRIVER: 1507 port->driver_bound = false; 1508 break; 1509 } 1510 1511 return 0; 1512 } 1513 1514 static int __init i8042_probe(struct platform_device *dev) 1515 { 1516 int error; 1517 1518 i8042_platform_device = dev; 1519 1520 if (i8042_reset == I8042_RESET_ALWAYS) { 1521 error = i8042_controller_selftest(); 1522 if (error) 1523 return error; 1524 } 1525 1526 error = i8042_controller_init(); 1527 if (error) 1528 return error; 1529 1530 #ifdef CONFIG_X86 1531 if (i8042_dritek) 1532 i8042_dritek_enable(); 1533 #endif 1534 1535 if (!i8042_noaux) { 1536 error = i8042_setup_aux(); 1537 if (error && error != -ENODEV && error != -EBUSY) 1538 goto out_fail; 1539 } 1540 1541 if (!i8042_nokbd) { 1542 error = i8042_setup_kbd(); 1543 if (error) 1544 goto out_fail; 1545 } 1546 /* 1547 * Ok, everything is ready, let's register all serio ports 1548 */ 1549 i8042_register_ports(); 1550 1551 return 0; 1552 1553 out_fail: 1554 i8042_free_aux_ports(); /* in case KBD failed but AUX not */ 1555 i8042_free_irqs(); 1556 i8042_controller_reset(false); 1557 i8042_platform_device = NULL; 1558 1559 return error; 1560 } 1561 1562 static int i8042_remove(struct platform_device *dev) 1563 { 1564 i8042_unregister_ports(); 1565 i8042_free_irqs(); 1566 i8042_controller_reset(false); 1567 i8042_platform_device = NULL; 1568 1569 return 0; 1570 } 1571 1572 static struct platform_driver i8042_driver = { 1573 .driver = { 1574 .name = "i8042", 1575 #ifdef CONFIG_PM 1576 .pm = &i8042_pm_ops, 1577 #endif 1578 }, 1579 .remove = i8042_remove, 1580 .shutdown = i8042_shutdown, 1581 }; 1582 1583 static struct notifier_block i8042_kbd_bind_notifier_block = { 1584 .notifier_call = i8042_kbd_bind_notifier, 1585 }; 1586 1587 static int __init i8042_init(void) 1588 { 1589 struct platform_device *pdev; 1590 int err; 1591 1592 dbg_init(); 1593 1594 err = i8042_platform_init(); 1595 if (err) 1596 return err; 1597 1598 err = i8042_controller_check(); 1599 if (err) 1600 goto err_platform_exit; 1601 1602 pdev = platform_create_bundle(&i8042_driver, i8042_probe, NULL, 0, NULL, 0); 1603 if (IS_ERR(pdev)) { 1604 err = PTR_ERR(pdev); 1605 goto err_platform_exit; 1606 } 1607 1608 bus_register_notifier(&serio_bus, &i8042_kbd_bind_notifier_block); 1609 panic_blink = i8042_panic_blink; 1610 1611 return 0; 1612 1613 err_platform_exit: 1614 i8042_platform_exit(); 1615 return err; 1616 } 1617 1618 static void __exit i8042_exit(void) 1619 { 1620 platform_device_unregister(i8042_platform_device); 1621 platform_driver_unregister(&i8042_driver); 1622 i8042_platform_exit(); 1623 1624 bus_unregister_notifier(&serio_bus, &i8042_kbd_bind_notifier_block); 1625 panic_blink = NULL; 1626 } 1627 1628 module_init(i8042_init); 1629 module_exit(i8042_exit); 1630