1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * i8042 keyboard and mouse controller driver for Linux 4 * 5 * Copyright (c) 1999-2004 Vojtech Pavlik 6 */ 7 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/types.h> 12 #include <linux/delay.h> 13 #include <linux/export.h> 14 #include <linux/module.h> 15 #include <linux/interrupt.h> 16 #include <linux/ioport.h> 17 #include <linux/init.h> 18 #include <linux/serio.h> 19 #include <linux/err.h> 20 #include <linux/rcupdate.h> 21 #include <linux/platform_device.h> 22 #include <linux/i8042.h> 23 #include <linux/slab.h> 24 #include <linux/suspend.h> 25 #include <linux/property.h> 26 27 #include <asm/io.h> 28 29 MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>"); 30 MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver"); 31 MODULE_LICENSE("GPL"); 32 33 static bool i8042_nokbd; 34 module_param_named(nokbd, i8042_nokbd, bool, 0); 35 MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port."); 36 37 static bool i8042_noaux; 38 module_param_named(noaux, i8042_noaux, bool, 0); 39 MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port."); 40 41 static bool i8042_nomux; 42 module_param_named(nomux, i8042_nomux, bool, 0); 43 MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing controller is present."); 44 45 static bool i8042_unlock; 46 module_param_named(unlock, i8042_unlock, bool, 0); 47 MODULE_PARM_DESC(unlock, "Ignore keyboard lock."); 48 49 static bool i8042_probe_defer; 50 module_param_named(probe_defer, i8042_probe_defer, bool, 0); 51 MODULE_PARM_DESC(probe_defer, "Allow deferred probing."); 52 53 enum i8042_controller_reset_mode { 54 I8042_RESET_NEVER, 55 I8042_RESET_ALWAYS, 56 I8042_RESET_ON_S2RAM, 57 #define I8042_RESET_DEFAULT I8042_RESET_ON_S2RAM 58 }; 59 static enum i8042_controller_reset_mode i8042_reset = I8042_RESET_DEFAULT; 60 static int i8042_set_reset(const char *val, const struct kernel_param *kp) 61 { 62 enum i8042_controller_reset_mode *arg = kp->arg; 63 int error; 64 bool reset; 65 66 if (val) { 67 error = kstrtobool(val, &reset); 68 if (error) 69 return error; 70 } else { 71 reset = true; 72 } 73 74 *arg = reset ? I8042_RESET_ALWAYS : I8042_RESET_NEVER; 75 return 0; 76 } 77 78 static const struct kernel_param_ops param_ops_reset_param = { 79 .flags = KERNEL_PARAM_OPS_FL_NOARG, 80 .set = i8042_set_reset, 81 }; 82 #define param_check_reset_param(name, p) \ 83 __param_check(name, p, enum i8042_controller_reset_mode) 84 module_param_named(reset, i8042_reset, reset_param, 0); 85 MODULE_PARM_DESC(reset, "Reset controller on resume, cleanup or both"); 86 87 static bool i8042_direct; 88 module_param_named(direct, i8042_direct, bool, 0); 89 MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode."); 90 91 static bool i8042_dumbkbd; 92 module_param_named(dumbkbd, i8042_dumbkbd, bool, 0); 93 MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard"); 94 95 static bool i8042_noloop; 96 module_param_named(noloop, i8042_noloop, bool, 0); 97 MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port"); 98 99 static bool i8042_notimeout; 100 module_param_named(notimeout, i8042_notimeout, bool, 0); 101 MODULE_PARM_DESC(notimeout, "Ignore timeouts signalled by i8042"); 102 103 static bool i8042_kbdreset; 104 module_param_named(kbdreset, i8042_kbdreset, bool, 0); 105 MODULE_PARM_DESC(kbdreset, "Reset device connected to KBD port"); 106 107 #ifdef CONFIG_X86 108 static bool i8042_dritek; 109 module_param_named(dritek, i8042_dritek, bool, 0); 110 MODULE_PARM_DESC(dritek, "Force enable the Dritek keyboard extension"); 111 #endif 112 113 #ifdef CONFIG_PNP 114 static bool i8042_nopnp; 115 module_param_named(nopnp, i8042_nopnp, bool, 0); 116 MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings"); 117 #endif 118 119 static bool i8042_forcenorestore; 120 module_param_named(forcenorestore, i8042_forcenorestore, bool, 0); 121 MODULE_PARM_DESC(forcenorestore, "Force no restore on s3 resume, copying s2idle behaviour"); 122 123 #define DEBUG 124 #ifdef DEBUG 125 static bool i8042_debug; 126 module_param_named(debug, i8042_debug, bool, 0600); 127 MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off"); 128 129 static bool i8042_unmask_kbd_data; 130 module_param_named(unmask_kbd_data, i8042_unmask_kbd_data, bool, 0600); 131 MODULE_PARM_DESC(unmask_kbd_data, "Unconditional enable (may reveal sensitive data) of normally sanitize-filtered kbd data traffic debug log [pre-condition: i8042.debug=1 enabled]"); 132 #endif 133 134 static bool i8042_present; 135 static bool i8042_bypass_aux_irq_test; 136 static char i8042_kbd_firmware_id[128]; 137 static char i8042_aux_firmware_id[128]; 138 static struct fwnode_handle *i8042_kbd_fwnode; 139 140 #include "i8042.h" 141 142 /* 143 * i8042_lock protects serialization between i8042_command and 144 * the interrupt handler. 145 */ 146 static DEFINE_SPINLOCK(i8042_lock); 147 148 /* 149 * Writers to AUX and KBD ports as well as users issuing i8042_command 150 * directly should acquire i8042_mutex (by means of calling 151 * i8042_lock_chip() and i8042_unlock_chip() helpers) to ensure that 152 * they do not disturb each other (unfortunately in many i8042 153 * implementations write to one of the ports will immediately abort 154 * command that is being processed by another port). 155 */ 156 static DEFINE_MUTEX(i8042_mutex); 157 158 struct i8042_port { 159 struct serio *serio; 160 int irq; 161 bool exists; 162 bool driver_bound; 163 signed char mux; 164 }; 165 166 #define I8042_KBD_PORT_NO 0 167 #define I8042_AUX_PORT_NO 1 168 #define I8042_MUX_PORT_NO 2 169 #define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2) 170 171 static struct i8042_port i8042_ports[I8042_NUM_PORTS]; 172 173 static unsigned char i8042_initial_ctr; 174 static unsigned char i8042_ctr; 175 static bool i8042_mux_present; 176 static bool i8042_kbd_irq_registered; 177 static bool i8042_aux_irq_registered; 178 static unsigned char i8042_suppress_kbd_ack; 179 static struct platform_device *i8042_platform_device; 180 static struct notifier_block i8042_kbd_bind_notifier_block; 181 182 static bool i8042_handle_data(int irq); 183 static i8042_filter_t i8042_platform_filter; 184 static void *i8042_platform_filter_context; 185 186 void i8042_lock_chip(void) 187 { 188 mutex_lock(&i8042_mutex); 189 } 190 EXPORT_SYMBOL(i8042_lock_chip); 191 192 void i8042_unlock_chip(void) 193 { 194 mutex_unlock(&i8042_mutex); 195 } 196 EXPORT_SYMBOL(i8042_unlock_chip); 197 198 int i8042_install_filter(i8042_filter_t filter, void *context) 199 { 200 guard(spinlock_irqsave)(&i8042_lock); 201 202 if (i8042_platform_filter) 203 return -EBUSY; 204 205 i8042_platform_filter = filter; 206 i8042_platform_filter_context = context; 207 return 0; 208 } 209 EXPORT_SYMBOL(i8042_install_filter); 210 211 int i8042_remove_filter(i8042_filter_t filter) 212 { 213 guard(spinlock_irqsave)(&i8042_lock); 214 215 if (i8042_platform_filter != filter) 216 return -EINVAL; 217 218 i8042_platform_filter = NULL; 219 i8042_platform_filter_context = NULL; 220 return 0; 221 } 222 EXPORT_SYMBOL(i8042_remove_filter); 223 224 /* 225 * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to 226 * be ready for reading values from it / writing values to it. 227 * Called always with i8042_lock held. 228 */ 229 230 static int i8042_wait_read(void) 231 { 232 int i = 0; 233 234 while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) { 235 udelay(50); 236 i++; 237 } 238 return -(i == I8042_CTL_TIMEOUT); 239 } 240 241 static int i8042_wait_write(void) 242 { 243 int i = 0; 244 245 while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) { 246 udelay(50); 247 i++; 248 } 249 return -(i == I8042_CTL_TIMEOUT); 250 } 251 252 /* 253 * i8042_flush() flushes all data that may be in the keyboard and mouse buffers 254 * of the i8042 down the toilet. 255 */ 256 257 static int i8042_flush(void) 258 { 259 unsigned char data, str; 260 int count = 0; 261 262 guard(spinlock_irqsave)(&i8042_lock); 263 264 while ((str = i8042_read_status()) & I8042_STR_OBF) { 265 if (count++ >= I8042_BUFFER_SIZE) 266 return -EIO; 267 268 udelay(50); 269 data = i8042_read_data(); 270 dbg("%02x <- i8042 (flush, %s)\n", 271 data, str & I8042_STR_AUXDATA ? "aux" : "kbd"); 272 } 273 274 return 0; 275 } 276 277 /* 278 * i8042_command() executes a command on the i8042. It also sends the input 279 * parameter(s) of the commands to it, and receives the output value(s). The 280 * parameters are to be stored in the param array, and the output is placed 281 * into the same array. The number of the parameters and output values is 282 * encoded in bits 8-11 of the command number. 283 */ 284 285 static int __i8042_command(unsigned char *param, int command) 286 { 287 int i, error; 288 289 if (i8042_noloop && command == I8042_CMD_AUX_LOOP) 290 return -1; 291 292 error = i8042_wait_write(); 293 if (error) 294 return error; 295 296 dbg("%02x -> i8042 (command)\n", command & 0xff); 297 i8042_write_command(command & 0xff); 298 299 for (i = 0; i < ((command >> 12) & 0xf); i++) { 300 error = i8042_wait_write(); 301 if (error) { 302 dbg(" -- i8042 (wait write timeout)\n"); 303 return error; 304 } 305 dbg("%02x -> i8042 (parameter)\n", param[i]); 306 i8042_write_data(param[i]); 307 } 308 309 for (i = 0; i < ((command >> 8) & 0xf); i++) { 310 error = i8042_wait_read(); 311 if (error) { 312 dbg(" -- i8042 (wait read timeout)\n"); 313 return error; 314 } 315 316 if (command == I8042_CMD_AUX_LOOP && 317 !(i8042_read_status() & I8042_STR_AUXDATA)) { 318 dbg(" -- i8042 (auxerr)\n"); 319 return -1; 320 } 321 322 param[i] = i8042_read_data(); 323 dbg("%02x <- i8042 (return)\n", param[i]); 324 } 325 326 return 0; 327 } 328 329 int i8042_command(unsigned char *param, int command) 330 { 331 if (!i8042_present) 332 return -1; 333 334 guard(spinlock_irqsave)(&i8042_lock); 335 336 return __i8042_command(param, command); 337 } 338 EXPORT_SYMBOL(i8042_command); 339 340 /* 341 * i8042_kbd_write() sends a byte out through the keyboard interface. 342 */ 343 344 static int i8042_kbd_write(struct serio *port, unsigned char c) 345 { 346 int error; 347 348 guard(spinlock_irqsave)(&i8042_lock); 349 350 error = i8042_wait_write(); 351 if (error) 352 return error; 353 354 dbg("%02x -> i8042 (kbd-data)\n", c); 355 i8042_write_data(c); 356 357 return 0; 358 } 359 360 /* 361 * i8042_aux_write() sends a byte out through the aux interface. 362 */ 363 364 static int i8042_aux_write(struct serio *serio, unsigned char c) 365 { 366 struct i8042_port *port = serio->port_data; 367 368 return i8042_command(&c, port->mux == -1 ? 369 I8042_CMD_AUX_SEND : 370 I8042_CMD_MUX_SEND + port->mux); 371 } 372 373 374 /* 375 * i8042_port_close attempts to clear AUX or KBD port state by disabling 376 * and then re-enabling it. 377 */ 378 379 static void i8042_port_close(struct serio *serio) 380 { 381 int irq_bit; 382 int disable_bit; 383 const char *port_name; 384 385 if (serio == i8042_ports[I8042_AUX_PORT_NO].serio) { 386 irq_bit = I8042_CTR_AUXINT; 387 disable_bit = I8042_CTR_AUXDIS; 388 port_name = "AUX"; 389 } else { 390 irq_bit = I8042_CTR_KBDINT; 391 disable_bit = I8042_CTR_KBDDIS; 392 port_name = "KBD"; 393 } 394 395 i8042_ctr &= ~irq_bit; 396 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 397 pr_warn("Can't write CTR while closing %s port\n", port_name); 398 399 udelay(50); 400 401 i8042_ctr &= ~disable_bit; 402 i8042_ctr |= irq_bit; 403 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 404 pr_err("Can't reactivate %s port\n", port_name); 405 406 /* 407 * See if there is any data appeared while we were messing with 408 * port state. 409 */ 410 i8042_handle_data(0); 411 } 412 413 /* 414 * i8042_start() is called by serio core when port is about to finish 415 * registering. It will mark port as existing so i8042_interrupt can 416 * start sending data through it. 417 */ 418 static int i8042_start(struct serio *serio) 419 { 420 struct i8042_port *port = serio->port_data; 421 422 device_set_wakeup_capable(&serio->dev, true); 423 424 /* 425 * On platforms using suspend-to-idle, allow the keyboard to 426 * wake up the system from sleep by enabling keyboard wakeups 427 * by default. This is consistent with keyboard wakeup 428 * behavior on many platforms using suspend-to-RAM (ACPI S3) 429 * by default. 430 */ 431 if (pm_suspend_default_s2idle() && 432 serio == i8042_ports[I8042_KBD_PORT_NO].serio) { 433 device_set_wakeup_enable(&serio->dev, true); 434 } 435 436 guard(spinlock_irq)(&i8042_lock); 437 port->exists = true; 438 439 return 0; 440 } 441 442 /* 443 * i8042_stop() marks serio port as non-existing so i8042_interrupt 444 * will not try to send data to the port that is about to go away. 445 * The function is called by serio core as part of unregister procedure. 446 */ 447 static void i8042_stop(struct serio *serio) 448 { 449 struct i8042_port *port = serio->port_data; 450 451 scoped_guard(spinlock_irq, &i8042_lock) { 452 port->exists = false; 453 port->serio = NULL; 454 } 455 456 /* 457 * We need to make sure that interrupt handler finishes using 458 * our serio port before we return from this function. 459 * We synchronize with both AUX and KBD IRQs because there is 460 * a (very unlikely) chance that AUX IRQ is raised for KBD port 461 * and vice versa. 462 */ 463 synchronize_irq(I8042_AUX_IRQ); 464 synchronize_irq(I8042_KBD_IRQ); 465 } 466 467 /* 468 * i8042_filter() filters out unwanted bytes from the input data stream. 469 * It is called from i8042_interrupt and thus is running with interrupts 470 * off and i8042_lock held. 471 */ 472 static bool i8042_filter(unsigned char data, unsigned char str, 473 struct serio *serio) 474 { 475 if (unlikely(i8042_suppress_kbd_ack)) { 476 if ((~str & I8042_STR_AUXDATA) && 477 (data == 0xfa || data == 0xfe)) { 478 i8042_suppress_kbd_ack--; 479 dbg("Extra keyboard ACK - filtered out\n"); 480 return true; 481 } 482 } 483 484 if (!i8042_platform_filter) 485 return false; 486 487 if (i8042_platform_filter(data, str, serio, i8042_platform_filter_context)) { 488 dbg("Filtered out by platform filter\n"); 489 return true; 490 } 491 492 return false; 493 } 494 495 /* 496 * i8042_handle_mux() handles case when data is coming from one of 497 * the multiplexed ports. It would be simple if not for quirks with 498 * handling errors: 499 * 500 * When MUXERR condition is signalled the data register can only contain 501 * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately 502 * it is not always the case. Some KBCs also report 0xfc when there is 503 * nothing connected to the port while others sometimes get confused which 504 * port the data came from and signal error leaving the data intact. They 505 * _do not_ revert to legacy mode (actually I've never seen KBC reverting 506 * to legacy mode yet, when we see one we'll add proper handling). 507 * Anyway, we process 0xfc, 0xfd, 0xfe and 0xff as timeouts, and for the 508 * rest assume that the data came from the same serio last byte 509 * was transmitted (if transmission happened not too long ago). 510 */ 511 static int i8042_handle_mux(u8 str, u8 *data, unsigned int *dfl) 512 { 513 static unsigned long last_transmit; 514 static unsigned long last_port; 515 unsigned int mux_port; 516 517 mux_port = (str >> 6) & 3; 518 *dfl = 0; 519 520 if (str & I8042_STR_MUXERR) { 521 dbg("MUX error, status is %02x, data is %02x\n", 522 str, *data); 523 524 switch (*data) { 525 default: 526 if (time_before(jiffies, last_transmit + HZ/10)) { 527 mux_port = last_port; 528 break; 529 } 530 fallthrough; /* report timeout */ 531 case 0xfc: 532 case 0xfd: 533 case 0xfe: 534 *dfl = SERIO_TIMEOUT; 535 *data = 0xfe; 536 break; 537 case 0xff: 538 *dfl = SERIO_PARITY; 539 *data = 0xfe; 540 break; 541 } 542 } 543 544 last_port = mux_port; 545 last_transmit = jiffies; 546 547 return I8042_MUX_PORT_NO + mux_port; 548 } 549 550 /* 551 * i8042_handle_data() is the most important function in this driver - 552 * it reads the data from the i8042, determines its destination serio 553 * port, and sends received byte to the upper layers. 554 * 555 * Returns true if there was data waiting, false otherwise. 556 */ 557 static bool i8042_handle_data(int irq) 558 { 559 struct i8042_port *port; 560 struct serio *serio; 561 unsigned char str, data; 562 unsigned int dfl; 563 unsigned int port_no; 564 bool filtered; 565 566 scoped_guard(spinlock_irqsave, &i8042_lock) { 567 str = i8042_read_status(); 568 if (unlikely(~str & I8042_STR_OBF)) 569 return false; 570 571 data = i8042_read_data(); 572 573 if (i8042_mux_present && (str & I8042_STR_AUXDATA)) { 574 port_no = i8042_handle_mux(str, &data, &dfl); 575 } else { 576 577 dfl = (str & I8042_STR_PARITY) ? SERIO_PARITY : 0; 578 if ((str & I8042_STR_TIMEOUT) && !i8042_notimeout) 579 dfl |= SERIO_TIMEOUT; 580 581 port_no = (str & I8042_STR_AUXDATA) ? 582 I8042_AUX_PORT_NO : I8042_KBD_PORT_NO; 583 } 584 585 port = &i8042_ports[port_no]; 586 serio = port->exists ? port->serio : NULL; 587 588 filter_dbg(port->driver_bound, 589 data, "<- i8042 (interrupt, %d, %d%s%s)\n", 590 port_no, irq, 591 dfl & SERIO_PARITY ? ", bad parity" : "", 592 dfl & SERIO_TIMEOUT ? ", timeout" : ""); 593 594 filtered = i8042_filter(data, str, serio); 595 } 596 597 if (likely(serio && !filtered)) 598 serio_interrupt(serio, data, dfl); 599 600 return true; 601 } 602 603 static irqreturn_t i8042_interrupt(int irq, void *dev_id) 604 { 605 if (unlikely(!i8042_handle_data(irq))) { 606 dbg("Interrupt %d, without any data\n", irq); 607 return IRQ_NONE; 608 } 609 610 return IRQ_HANDLED; 611 } 612 613 /* 614 * i8042_enable_kbd_port enables keyboard port on chip 615 */ 616 617 static int i8042_enable_kbd_port(void) 618 { 619 i8042_ctr &= ~I8042_CTR_KBDDIS; 620 i8042_ctr |= I8042_CTR_KBDINT; 621 622 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 623 i8042_ctr &= ~I8042_CTR_KBDINT; 624 i8042_ctr |= I8042_CTR_KBDDIS; 625 pr_err("Failed to enable KBD port\n"); 626 return -EIO; 627 } 628 629 return 0; 630 } 631 632 /* 633 * i8042_enable_aux_port enables AUX (mouse) port on chip 634 */ 635 636 static int i8042_enable_aux_port(void) 637 { 638 i8042_ctr &= ~I8042_CTR_AUXDIS; 639 i8042_ctr |= I8042_CTR_AUXINT; 640 641 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 642 i8042_ctr &= ~I8042_CTR_AUXINT; 643 i8042_ctr |= I8042_CTR_AUXDIS; 644 pr_err("Failed to enable AUX port\n"); 645 return -EIO; 646 } 647 648 return 0; 649 } 650 651 /* 652 * i8042_enable_mux_ports enables 4 individual AUX ports after 653 * the controller has been switched into Multiplexed mode 654 */ 655 656 static int i8042_enable_mux_ports(void) 657 { 658 unsigned char param; 659 int i; 660 661 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { 662 i8042_command(¶m, I8042_CMD_MUX_PFX + i); 663 i8042_command(¶m, I8042_CMD_AUX_ENABLE); 664 } 665 666 return i8042_enable_aux_port(); 667 } 668 669 /* 670 * i8042_set_mux_mode checks whether the controller has an 671 * active multiplexor and puts the chip into Multiplexed (true) 672 * or Legacy (false) mode. 673 */ 674 675 static int i8042_set_mux_mode(bool multiplex, unsigned char *mux_version) 676 { 677 678 unsigned char param, val; 679 /* 680 * Get rid of bytes in the queue. 681 */ 682 683 i8042_flush(); 684 685 /* 686 * Internal loopback test - send three bytes, they should come back from the 687 * mouse interface, the last should be version. 688 */ 689 690 param = val = 0xf0; 691 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) 692 return -1; 693 param = val = multiplex ? 0x56 : 0xf6; 694 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) 695 return -1; 696 param = val = multiplex ? 0xa4 : 0xa5; 697 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == val) 698 return -1; 699 700 /* 701 * Workaround for interference with USB Legacy emulation 702 * that causes a v10.12 MUX to be found. 703 */ 704 if (param == 0xac) 705 return -1; 706 707 if (mux_version) 708 *mux_version = param; 709 710 return 0; 711 } 712 713 /* 714 * i8042_check_mux() checks whether the controller supports the PS/2 Active 715 * Multiplexing specification by Synaptics, Phoenix, Insyde and 716 * LCS/Telegraphics. 717 */ 718 719 static int i8042_check_mux(void) 720 { 721 unsigned char mux_version; 722 723 if (i8042_set_mux_mode(true, &mux_version)) 724 return -1; 725 726 pr_info("Detected active multiplexing controller, rev %d.%d\n", 727 (mux_version >> 4) & 0xf, mux_version & 0xf); 728 729 /* 730 * Disable all muxed ports by disabling AUX. 731 */ 732 i8042_ctr |= I8042_CTR_AUXDIS; 733 i8042_ctr &= ~I8042_CTR_AUXINT; 734 735 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 736 pr_err("Failed to disable AUX port, can't use MUX\n"); 737 return -EIO; 738 } 739 740 i8042_mux_present = true; 741 742 return 0; 743 } 744 745 /* 746 * The following is used to test AUX IRQ delivery. 747 */ 748 static struct completion i8042_aux_irq_delivered; 749 static bool i8042_irq_being_tested; 750 751 static irqreturn_t i8042_aux_test_irq(int irq, void *dev_id) 752 { 753 unsigned char str, data; 754 755 guard(spinlock_irqsave)(&i8042_lock); 756 757 str = i8042_read_status(); 758 if (!(str & I8042_STR_OBF)) 759 return IRQ_NONE; 760 761 data = i8042_read_data(); 762 dbg("%02x <- i8042 (aux_test_irq, %s)\n", 763 data, str & I8042_STR_AUXDATA ? "aux" : "kbd"); 764 765 if (i8042_irq_being_tested && data == 0xa5 && (str & I8042_STR_AUXDATA)) 766 complete(&i8042_aux_irq_delivered); 767 768 return IRQ_HANDLED; 769 } 770 771 /* 772 * i8042_toggle_aux - enables or disables AUX port on i8042 via command and 773 * verifies success by readinng CTR. Used when testing for presence of AUX 774 * port. 775 */ 776 static int i8042_toggle_aux(bool on) 777 { 778 unsigned char param; 779 int i; 780 781 if (i8042_command(¶m, 782 on ? I8042_CMD_AUX_ENABLE : I8042_CMD_AUX_DISABLE)) 783 return -1; 784 785 /* some chips need some time to set the I8042_CTR_AUXDIS bit */ 786 for (i = 0; i < 100; i++) { 787 udelay(50); 788 789 if (i8042_command(¶m, I8042_CMD_CTL_RCTR)) 790 return -1; 791 792 if (!(param & I8042_CTR_AUXDIS) == on) 793 return 0; 794 } 795 796 return -1; 797 } 798 799 /* 800 * i8042_check_aux() applies as much paranoia as it can at detecting 801 * the presence of an AUX interface. 802 */ 803 804 static int i8042_check_aux(void) 805 { 806 int retval = -1; 807 bool irq_registered = false; 808 bool aux_loop_broken = false; 809 unsigned char param; 810 811 /* 812 * Get rid of bytes in the queue. 813 */ 814 815 i8042_flush(); 816 817 /* 818 * Internal loopback test - filters out AT-type i8042's. Unfortunately 819 * SiS screwed up and their 5597 doesn't support the LOOP command even 820 * though it has an AUX port. 821 */ 822 823 param = 0x5a; 824 retval = i8042_command(¶m, I8042_CMD_AUX_LOOP); 825 if (retval || param != 0x5a) { 826 827 /* 828 * External connection test - filters out AT-soldered PS/2 i8042's 829 * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error 830 * 0xfa - no error on some notebooks which ignore the spec 831 * Because it's common for chipsets to return error on perfectly functioning 832 * AUX ports, we test for this only when the LOOP command failed. 833 */ 834 835 if (i8042_command(¶m, I8042_CMD_AUX_TEST) || 836 (param && param != 0xfa && param != 0xff)) 837 return -1; 838 839 /* 840 * If AUX_LOOP completed without error but returned unexpected data 841 * mark it as broken 842 */ 843 if (!retval) 844 aux_loop_broken = true; 845 } 846 847 /* 848 * Bit assignment test - filters out PS/2 i8042's in AT mode 849 */ 850 851 if (i8042_toggle_aux(false)) { 852 pr_warn("Failed to disable AUX port, but continuing anyway... Is this a SiS?\n"); 853 pr_warn("If AUX port is really absent please use the 'i8042.noaux' option\n"); 854 } 855 856 if (i8042_toggle_aux(true)) 857 return -1; 858 859 /* 860 * Reset keyboard (needed on some laptops to successfully detect 861 * touchpad, e.g., some Gigabyte laptop models with Elantech 862 * touchpads). 863 */ 864 if (i8042_kbdreset) { 865 pr_warn("Attempting to reset device connected to KBD port\n"); 866 i8042_kbd_write(NULL, (unsigned char) 0xff); 867 } 868 869 /* 870 * Test AUX IRQ delivery to make sure BIOS did not grab the IRQ and 871 * used it for a PCI card or somethig else. 872 */ 873 874 if (i8042_noloop || i8042_bypass_aux_irq_test || aux_loop_broken) { 875 /* 876 * Without LOOP command we can't test AUX IRQ delivery. Assume the port 877 * is working and hope we are right. 878 */ 879 retval = 0; 880 goto out; 881 } 882 883 if (request_irq(I8042_AUX_IRQ, i8042_aux_test_irq, IRQF_SHARED, 884 "i8042", i8042_platform_device)) 885 goto out; 886 887 irq_registered = true; 888 889 if (i8042_enable_aux_port()) 890 goto out; 891 892 scoped_guard(spinlock_irqsave, &i8042_lock) { 893 init_completion(&i8042_aux_irq_delivered); 894 i8042_irq_being_tested = true; 895 896 param = 0xa5; 897 retval = __i8042_command(¶m, I8042_CMD_AUX_LOOP & 0xf0ff); 898 if (retval) 899 goto out; 900 } 901 902 if (wait_for_completion_timeout(&i8042_aux_irq_delivered, 903 msecs_to_jiffies(250)) == 0) { 904 /* 905 * AUX IRQ was never delivered so we need to flush the controller to 906 * get rid of the byte we put there; otherwise keyboard may not work. 907 */ 908 dbg(" -- i8042 (aux irq test timeout)\n"); 909 i8042_flush(); 910 retval = -1; 911 } 912 913 out: 914 915 /* 916 * Disable the interface. 917 */ 918 919 i8042_ctr |= I8042_CTR_AUXDIS; 920 i8042_ctr &= ~I8042_CTR_AUXINT; 921 922 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 923 retval = -1; 924 925 if (irq_registered) 926 free_irq(I8042_AUX_IRQ, i8042_platform_device); 927 928 return retval; 929 } 930 931 static int i8042_controller_check(void) 932 { 933 if (i8042_flush()) { 934 pr_info("No controller found\n"); 935 return -ENODEV; 936 } 937 938 return 0; 939 } 940 941 static int i8042_controller_selftest(void) 942 { 943 unsigned char param; 944 int i = 0; 945 946 /* 947 * We try this 5 times; on some really fragile systems this does not 948 * take the first time... 949 */ 950 do { 951 952 if (i8042_command(¶m, I8042_CMD_CTL_TEST)) { 953 pr_err("i8042 controller selftest timeout\n"); 954 return -ENODEV; 955 } 956 957 if (param == I8042_RET_CTL_TEST) 958 return 0; 959 960 dbg("i8042 controller selftest: %#x != %#x\n", 961 param, I8042_RET_CTL_TEST); 962 msleep(50); 963 } while (i++ < 5); 964 965 #ifdef CONFIG_X86 966 /* 967 * On x86, we don't fail entire i8042 initialization if controller 968 * reset fails in hopes that keyboard port will still be functional 969 * and user will still get a working keyboard. This is especially 970 * important on netbooks. On other arches we trust hardware more. 971 */ 972 pr_info("giving up on controller selftest, continuing anyway...\n"); 973 return 0; 974 #else 975 pr_err("i8042 controller selftest failed\n"); 976 return -EIO; 977 #endif 978 } 979 980 /* 981 * i8042_controller_init initializes the i8042 controller, and, 982 * most importantly, sets it into non-xlated mode if that's 983 * desired. 984 */ 985 986 static int i8042_controller_init(void) 987 { 988 int n = 0; 989 unsigned char ctr[2]; 990 991 /* 992 * Save the CTR for restore on unload / reboot. 993 */ 994 995 do { 996 if (n >= 10) { 997 pr_err("Unable to get stable CTR read\n"); 998 return -EIO; 999 } 1000 1001 if (n != 0) 1002 udelay(50); 1003 1004 if (i8042_command(&ctr[n++ % 2], I8042_CMD_CTL_RCTR)) { 1005 pr_err("Can't read CTR while initializing i8042\n"); 1006 return i8042_probe_defer ? -EPROBE_DEFER : -EIO; 1007 } 1008 1009 } while (n < 2 || ctr[0] != ctr[1]); 1010 1011 i8042_initial_ctr = i8042_ctr = ctr[0]; 1012 1013 /* 1014 * Disable the keyboard interface and interrupt. 1015 */ 1016 1017 i8042_ctr |= I8042_CTR_KBDDIS; 1018 i8042_ctr &= ~I8042_CTR_KBDINT; 1019 1020 /* 1021 * Handle keylock. 1022 */ 1023 1024 scoped_guard(spinlock_irqsave, &i8042_lock) { 1025 if (~i8042_read_status() & I8042_STR_KEYLOCK) { 1026 if (i8042_unlock) 1027 i8042_ctr |= I8042_CTR_IGNKEYLOCK; 1028 else 1029 pr_warn("Warning: Keylock active\n"); 1030 } 1031 } 1032 1033 /* 1034 * If the chip is configured into nontranslated mode by the BIOS, don't 1035 * bother enabling translating and be happy. 1036 */ 1037 1038 if (~i8042_ctr & I8042_CTR_XLATE) 1039 i8042_direct = true; 1040 1041 /* 1042 * Set nontranslated mode for the kbd interface if requested by an option. 1043 * After this the kbd interface becomes a simple serial in/out, like the aux 1044 * interface is. We don't do this by default, since it can confuse notebook 1045 * BIOSes. 1046 */ 1047 1048 if (i8042_direct) 1049 i8042_ctr &= ~I8042_CTR_XLATE; 1050 1051 /* 1052 * Write CTR back. 1053 */ 1054 1055 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 1056 pr_err("Can't write CTR while initializing i8042\n"); 1057 return -EIO; 1058 } 1059 1060 /* 1061 * Flush whatever accumulated while we were disabling keyboard port. 1062 */ 1063 1064 i8042_flush(); 1065 1066 return 0; 1067 } 1068 1069 1070 /* 1071 * Reset the controller and reset CRT to the original value set by BIOS. 1072 */ 1073 1074 static void i8042_controller_reset(bool s2r_wants_reset) 1075 { 1076 i8042_flush(); 1077 1078 /* 1079 * Disable both KBD and AUX interfaces so they don't get in the way 1080 */ 1081 1082 i8042_ctr |= I8042_CTR_KBDDIS | I8042_CTR_AUXDIS; 1083 i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT); 1084 1085 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 1086 pr_warn("Can't write CTR while resetting\n"); 1087 1088 /* 1089 * Disable MUX mode if present. 1090 */ 1091 1092 if (i8042_mux_present) 1093 i8042_set_mux_mode(false, NULL); 1094 1095 /* 1096 * Reset the controller if requested. 1097 */ 1098 1099 if (i8042_reset == I8042_RESET_ALWAYS || 1100 (i8042_reset == I8042_RESET_ON_S2RAM && s2r_wants_reset)) { 1101 i8042_controller_selftest(); 1102 } 1103 1104 /* 1105 * Restore the original control register setting. 1106 */ 1107 1108 if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR)) 1109 pr_warn("Can't restore CTR\n"); 1110 } 1111 1112 1113 /* 1114 * i8042_panic_blink() will turn the keyboard LEDs on or off and is called 1115 * when kernel panics. Flashing LEDs is useful for users running X who may 1116 * not see the console and will help distinguishing panics from "real" 1117 * lockups. 1118 * 1119 * Note that DELAY has a limit of 10ms so we will not get stuck here 1120 * waiting for KBC to free up even if KBD interrupt is off 1121 */ 1122 1123 #define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0) 1124 1125 static long i8042_panic_blink(int state) 1126 { 1127 long delay = 0; 1128 char led; 1129 1130 led = (state) ? 0x01 | 0x04 : 0; 1131 while (i8042_read_status() & I8042_STR_IBF) 1132 DELAY; 1133 dbg("%02x -> i8042 (panic blink)\n", 0xed); 1134 i8042_suppress_kbd_ack = 2; 1135 i8042_write_data(0xed); /* set leds */ 1136 DELAY; 1137 while (i8042_read_status() & I8042_STR_IBF) 1138 DELAY; 1139 DELAY; 1140 dbg("%02x -> i8042 (panic blink)\n", led); 1141 i8042_write_data(led); 1142 DELAY; 1143 return delay; 1144 } 1145 1146 #undef DELAY 1147 1148 #ifdef CONFIG_X86 1149 static void i8042_dritek_enable(void) 1150 { 1151 unsigned char param = 0x90; 1152 int error; 1153 1154 error = i8042_command(¶m, 0x1059); 1155 if (error) 1156 pr_warn("Failed to enable DRITEK extension: %d\n", error); 1157 } 1158 #endif 1159 1160 #ifdef CONFIG_PM 1161 1162 /* 1163 * Here we try to reset everything back to a state we had 1164 * before suspending. 1165 */ 1166 1167 static int i8042_controller_resume(bool s2r_wants_reset) 1168 { 1169 int error; 1170 1171 error = i8042_controller_check(); 1172 if (error) 1173 return error; 1174 1175 if (i8042_reset == I8042_RESET_ALWAYS || 1176 (i8042_reset == I8042_RESET_ON_S2RAM && s2r_wants_reset)) { 1177 error = i8042_controller_selftest(); 1178 if (error) 1179 return error; 1180 } 1181 1182 /* 1183 * Restore original CTR value and disable all ports 1184 */ 1185 1186 i8042_ctr = i8042_initial_ctr; 1187 if (i8042_direct) 1188 i8042_ctr &= ~I8042_CTR_XLATE; 1189 i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS; 1190 i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT); 1191 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 1192 pr_warn("Can't write CTR to resume, retrying...\n"); 1193 msleep(50); 1194 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 1195 pr_err("CTR write retry failed\n"); 1196 return -EIO; 1197 } 1198 } 1199 1200 1201 #ifdef CONFIG_X86 1202 if (i8042_dritek) 1203 i8042_dritek_enable(); 1204 #endif 1205 1206 if (i8042_mux_present) { 1207 if (i8042_set_mux_mode(true, NULL) || i8042_enable_mux_ports()) 1208 pr_warn("failed to resume active multiplexor, mouse won't work\n"); 1209 } else if (i8042_ports[I8042_AUX_PORT_NO].serio) { 1210 i8042_enable_aux_port(); 1211 } 1212 1213 if (i8042_ports[I8042_KBD_PORT_NO].serio) 1214 i8042_enable_kbd_port(); 1215 1216 i8042_handle_data(0); 1217 1218 return 0; 1219 } 1220 1221 /* 1222 * Here we try to restore the original BIOS settings to avoid 1223 * upsetting it. 1224 */ 1225 1226 static int i8042_pm_suspend(struct device *dev) 1227 { 1228 int i; 1229 1230 if (!i8042_forcenorestore && pm_suspend_via_firmware()) 1231 i8042_controller_reset(true); 1232 1233 /* Set up serio interrupts for system wakeup. */ 1234 for (i = 0; i < I8042_NUM_PORTS; i++) { 1235 struct serio *serio = i8042_ports[i].serio; 1236 1237 if (serio && device_may_wakeup(&serio->dev)) 1238 enable_irq_wake(i8042_ports[i].irq); 1239 } 1240 1241 return 0; 1242 } 1243 1244 static int i8042_pm_resume_noirq(struct device *dev) 1245 { 1246 if (i8042_forcenorestore || !pm_resume_via_firmware()) 1247 i8042_handle_data(0); 1248 1249 return 0; 1250 } 1251 1252 static int i8042_pm_resume(struct device *dev) 1253 { 1254 bool want_reset; 1255 int i; 1256 1257 for (i = 0; i < I8042_NUM_PORTS; i++) { 1258 struct serio *serio = i8042_ports[i].serio; 1259 1260 if (serio && device_may_wakeup(&serio->dev)) 1261 disable_irq_wake(i8042_ports[i].irq); 1262 } 1263 1264 /* 1265 * If platform firmware was not going to be involved in suspend, we did 1266 * not restore the controller state to whatever it had been at boot 1267 * time, so we do not need to do anything. 1268 */ 1269 if (i8042_forcenorestore || !pm_suspend_via_firmware()) 1270 return 0; 1271 1272 /* 1273 * We only need to reset the controller if we are resuming after handing 1274 * off control to the platform firmware, otherwise we can simply restore 1275 * the mode. 1276 */ 1277 want_reset = pm_resume_via_firmware(); 1278 1279 return i8042_controller_resume(want_reset); 1280 } 1281 1282 static int i8042_pm_thaw(struct device *dev) 1283 { 1284 i8042_handle_data(0); 1285 1286 return 0; 1287 } 1288 1289 static int i8042_pm_reset(struct device *dev) 1290 { 1291 i8042_controller_reset(false); 1292 1293 return 0; 1294 } 1295 1296 static int i8042_pm_restore(struct device *dev) 1297 { 1298 return i8042_controller_resume(false); 1299 } 1300 1301 static const struct dev_pm_ops i8042_pm_ops = { 1302 .suspend = i8042_pm_suspend, 1303 .resume_noirq = i8042_pm_resume_noirq, 1304 .resume = i8042_pm_resume, 1305 .thaw = i8042_pm_thaw, 1306 .poweroff = i8042_pm_reset, 1307 .restore = i8042_pm_restore, 1308 }; 1309 1310 #endif /* CONFIG_PM */ 1311 1312 /* 1313 * We need to reset the 8042 back to original mode on system shutdown, 1314 * because otherwise BIOSes will be confused. 1315 */ 1316 1317 static void i8042_shutdown(struct platform_device *dev) 1318 { 1319 i8042_controller_reset(false); 1320 } 1321 1322 static int i8042_create_kbd_port(void) 1323 { 1324 struct serio *serio; 1325 struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO]; 1326 1327 serio = kzalloc(sizeof(*serio), GFP_KERNEL); 1328 if (!serio) 1329 return -ENOMEM; 1330 1331 serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL; 1332 serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write; 1333 serio->start = i8042_start; 1334 serio->stop = i8042_stop; 1335 serio->close = i8042_port_close; 1336 serio->ps2_cmd_mutex = &i8042_mutex; 1337 serio->port_data = port; 1338 serio->dev.parent = &i8042_platform_device->dev; 1339 strscpy(serio->name, "i8042 KBD port", sizeof(serio->name)); 1340 strscpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys)); 1341 strscpy(serio->firmware_id, i8042_kbd_firmware_id, 1342 sizeof(serio->firmware_id)); 1343 set_primary_fwnode(&serio->dev, i8042_kbd_fwnode); 1344 1345 port->serio = serio; 1346 port->irq = I8042_KBD_IRQ; 1347 1348 return 0; 1349 } 1350 1351 static int i8042_create_aux_port(int idx) 1352 { 1353 struct serio *serio; 1354 int port_no = idx < 0 ? I8042_AUX_PORT_NO : I8042_MUX_PORT_NO + idx; 1355 struct i8042_port *port = &i8042_ports[port_no]; 1356 1357 serio = kzalloc(sizeof(*serio), GFP_KERNEL); 1358 if (!serio) 1359 return -ENOMEM; 1360 1361 serio->id.type = SERIO_8042; 1362 serio->write = i8042_aux_write; 1363 serio->start = i8042_start; 1364 serio->stop = i8042_stop; 1365 serio->ps2_cmd_mutex = &i8042_mutex; 1366 serio->port_data = port; 1367 serio->dev.parent = &i8042_platform_device->dev; 1368 if (idx < 0) { 1369 strscpy(serio->name, "i8042 AUX port", sizeof(serio->name)); 1370 strscpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys)); 1371 strscpy(serio->firmware_id, i8042_aux_firmware_id, 1372 sizeof(serio->firmware_id)); 1373 serio->close = i8042_port_close; 1374 } else { 1375 snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx); 1376 snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1); 1377 strscpy(serio->firmware_id, i8042_aux_firmware_id, 1378 sizeof(serio->firmware_id)); 1379 } 1380 1381 port->serio = serio; 1382 port->mux = idx; 1383 port->irq = I8042_AUX_IRQ; 1384 1385 return 0; 1386 } 1387 1388 static void i8042_free_kbd_port(void) 1389 { 1390 kfree(i8042_ports[I8042_KBD_PORT_NO].serio); 1391 i8042_ports[I8042_KBD_PORT_NO].serio = NULL; 1392 } 1393 1394 static void i8042_free_aux_ports(void) 1395 { 1396 int i; 1397 1398 for (i = I8042_AUX_PORT_NO; i < I8042_NUM_PORTS; i++) { 1399 kfree(i8042_ports[i].serio); 1400 i8042_ports[i].serio = NULL; 1401 } 1402 } 1403 1404 static void i8042_register_ports(void) 1405 { 1406 int i; 1407 1408 for (i = 0; i < I8042_NUM_PORTS; i++) { 1409 struct serio *serio = i8042_ports[i].serio; 1410 1411 if (!serio) 1412 continue; 1413 1414 printk(KERN_INFO "serio: %s at %#lx,%#lx irq %d\n", 1415 serio->name, 1416 (unsigned long) I8042_DATA_REG, 1417 (unsigned long) I8042_COMMAND_REG, 1418 i8042_ports[i].irq); 1419 serio_register_port(serio); 1420 } 1421 } 1422 1423 static void i8042_unregister_ports(void) 1424 { 1425 int i; 1426 1427 for (i = 0; i < I8042_NUM_PORTS; i++) { 1428 if (i8042_ports[i].serio) { 1429 serio_unregister_port(i8042_ports[i].serio); 1430 i8042_ports[i].serio = NULL; 1431 } 1432 } 1433 } 1434 1435 static void i8042_free_irqs(void) 1436 { 1437 if (i8042_aux_irq_registered) 1438 free_irq(I8042_AUX_IRQ, i8042_platform_device); 1439 if (i8042_kbd_irq_registered) 1440 free_irq(I8042_KBD_IRQ, i8042_platform_device); 1441 1442 i8042_aux_irq_registered = i8042_kbd_irq_registered = false; 1443 } 1444 1445 static int i8042_setup_aux(void) 1446 { 1447 int (*aux_enable)(void); 1448 int error; 1449 int i; 1450 1451 if (i8042_check_aux()) 1452 return -ENODEV; 1453 1454 if (i8042_nomux || i8042_check_mux()) { 1455 error = i8042_create_aux_port(-1); 1456 if (error) 1457 goto err_free_ports; 1458 aux_enable = i8042_enable_aux_port; 1459 } else { 1460 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { 1461 error = i8042_create_aux_port(i); 1462 if (error) 1463 goto err_free_ports; 1464 } 1465 aux_enable = i8042_enable_mux_ports; 1466 } 1467 1468 error = request_irq(I8042_AUX_IRQ, i8042_interrupt, IRQF_SHARED, 1469 "i8042", i8042_platform_device); 1470 if (error) 1471 goto err_free_ports; 1472 1473 error = aux_enable(); 1474 if (error) 1475 goto err_free_irq; 1476 1477 i8042_aux_irq_registered = true; 1478 return 0; 1479 1480 err_free_irq: 1481 free_irq(I8042_AUX_IRQ, i8042_platform_device); 1482 err_free_ports: 1483 i8042_free_aux_ports(); 1484 return error; 1485 } 1486 1487 static int i8042_setup_kbd(void) 1488 { 1489 int error; 1490 1491 error = i8042_create_kbd_port(); 1492 if (error) 1493 return error; 1494 1495 error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED, 1496 "i8042", i8042_platform_device); 1497 if (error) 1498 goto err_free_port; 1499 1500 error = i8042_enable_kbd_port(); 1501 if (error) 1502 goto err_free_irq; 1503 1504 i8042_kbd_irq_registered = true; 1505 return 0; 1506 1507 err_free_irq: 1508 free_irq(I8042_KBD_IRQ, i8042_platform_device); 1509 err_free_port: 1510 i8042_free_kbd_port(); 1511 return error; 1512 } 1513 1514 static int i8042_kbd_bind_notifier(struct notifier_block *nb, 1515 unsigned long action, void *data) 1516 { 1517 struct device *dev = data; 1518 struct serio *serio = to_serio_port(dev); 1519 struct i8042_port *port = serio->port_data; 1520 1521 if (serio != i8042_ports[I8042_KBD_PORT_NO].serio) 1522 return 0; 1523 1524 switch (action) { 1525 case BUS_NOTIFY_BOUND_DRIVER: 1526 port->driver_bound = true; 1527 break; 1528 1529 case BUS_NOTIFY_UNBIND_DRIVER: 1530 port->driver_bound = false; 1531 break; 1532 } 1533 1534 return 0; 1535 } 1536 1537 static int i8042_probe(struct platform_device *dev) 1538 { 1539 int error; 1540 1541 if (i8042_reset == I8042_RESET_ALWAYS) { 1542 error = i8042_controller_selftest(); 1543 if (error) 1544 return error; 1545 } 1546 1547 error = i8042_controller_init(); 1548 if (error) 1549 return error; 1550 1551 #ifdef CONFIG_X86 1552 if (i8042_dritek) 1553 i8042_dritek_enable(); 1554 #endif 1555 1556 if (!i8042_noaux) { 1557 error = i8042_setup_aux(); 1558 if (error && error != -ENODEV && error != -EBUSY) 1559 goto out_fail; 1560 } 1561 1562 if (!i8042_nokbd) { 1563 error = i8042_setup_kbd(); 1564 if (error) 1565 goto out_fail; 1566 } 1567 /* 1568 * Ok, everything is ready, let's register all serio ports 1569 */ 1570 i8042_register_ports(); 1571 1572 return 0; 1573 1574 out_fail: 1575 i8042_free_aux_ports(); /* in case KBD failed but AUX not */ 1576 i8042_free_irqs(); 1577 i8042_controller_reset(false); 1578 1579 return error; 1580 } 1581 1582 static void i8042_remove(struct platform_device *dev) 1583 { 1584 i8042_unregister_ports(); 1585 i8042_free_irqs(); 1586 i8042_controller_reset(false); 1587 } 1588 1589 static struct platform_driver i8042_driver = { 1590 .driver = { 1591 .name = "i8042", 1592 #ifdef CONFIG_PM 1593 .pm = &i8042_pm_ops, 1594 #endif 1595 }, 1596 .probe = i8042_probe, 1597 .remove = i8042_remove, 1598 .shutdown = i8042_shutdown, 1599 }; 1600 1601 static struct notifier_block i8042_kbd_bind_notifier_block = { 1602 .notifier_call = i8042_kbd_bind_notifier, 1603 }; 1604 1605 static int __init i8042_init(void) 1606 { 1607 int err; 1608 1609 dbg_init(); 1610 1611 err = i8042_platform_init(); 1612 if (err) 1613 return (err == -ENODEV) ? 0 : err; 1614 1615 err = i8042_controller_check(); 1616 if (err) 1617 goto err_platform_exit; 1618 1619 /* Set this before creating the dev to allow i8042_command to work right away */ 1620 i8042_present = true; 1621 1622 err = platform_driver_register(&i8042_driver); 1623 if (err) 1624 goto err_platform_exit; 1625 1626 i8042_platform_device = platform_device_alloc("i8042", -1); 1627 if (!i8042_platform_device) { 1628 err = -ENOMEM; 1629 goto err_unregister_driver; 1630 } 1631 1632 err = platform_device_add(i8042_platform_device); 1633 if (err) 1634 goto err_free_device; 1635 1636 bus_register_notifier(&serio_bus, &i8042_kbd_bind_notifier_block); 1637 panic_blink = i8042_panic_blink; 1638 1639 return 0; 1640 1641 err_free_device: 1642 platform_device_put(i8042_platform_device); 1643 err_unregister_driver: 1644 platform_driver_unregister(&i8042_driver); 1645 err_platform_exit: 1646 i8042_platform_exit(); 1647 return err; 1648 } 1649 1650 static void __exit i8042_exit(void) 1651 { 1652 if (!i8042_present) 1653 return; 1654 1655 platform_device_unregister(i8042_platform_device); 1656 platform_driver_unregister(&i8042_driver); 1657 i8042_platform_exit(); 1658 1659 bus_unregister_notifier(&serio_bus, &i8042_kbd_bind_notifier_block); 1660 panic_blink = NULL; 1661 } 1662 1663 module_init(i8042_init); 1664 module_exit(i8042_exit); 1665