1 /* 2 * i8042 keyboard and mouse controller driver for Linux 3 * 4 * Copyright (c) 1999-2004 Vojtech Pavlik 5 */ 6 7 /* 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License version 2 as published by 10 * the Free Software Foundation. 11 */ 12 13 #include <linux/types.h> 14 #include <linux/delay.h> 15 #include <linux/module.h> 16 #include <linux/interrupt.h> 17 #include <linux/ioport.h> 18 #include <linux/init.h> 19 #include <linux/serio.h> 20 #include <linux/err.h> 21 #include <linux/rcupdate.h> 22 #include <linux/platform_device.h> 23 #include <linux/i8042.h> 24 25 #include <asm/io.h> 26 27 MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>"); 28 MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver"); 29 MODULE_LICENSE("GPL"); 30 31 static unsigned int i8042_nokbd; 32 module_param_named(nokbd, i8042_nokbd, bool, 0); 33 MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port."); 34 35 static unsigned int i8042_noaux; 36 module_param_named(noaux, i8042_noaux, bool, 0); 37 MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port."); 38 39 static unsigned int i8042_nomux; 40 module_param_named(nomux, i8042_nomux, bool, 0); 41 MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing conrtoller is present."); 42 43 static unsigned int i8042_unlock; 44 module_param_named(unlock, i8042_unlock, bool, 0); 45 MODULE_PARM_DESC(unlock, "Ignore keyboard lock."); 46 47 static unsigned int i8042_reset; 48 module_param_named(reset, i8042_reset, bool, 0); 49 MODULE_PARM_DESC(reset, "Reset controller during init and cleanup."); 50 51 static unsigned int i8042_direct; 52 module_param_named(direct, i8042_direct, bool, 0); 53 MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode."); 54 55 static unsigned int i8042_dumbkbd; 56 module_param_named(dumbkbd, i8042_dumbkbd, bool, 0); 57 MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard"); 58 59 static unsigned int i8042_noloop; 60 module_param_named(noloop, i8042_noloop, bool, 0); 61 MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port"); 62 63 static unsigned int i8042_blink_frequency = 500; 64 module_param_named(panicblink, i8042_blink_frequency, uint, 0600); 65 MODULE_PARM_DESC(panicblink, "Frequency with which keyboard LEDs should blink when kernel panics"); 66 67 #ifdef CONFIG_X86 68 static unsigned int i8042_dritek; 69 module_param_named(dritek, i8042_dritek, bool, 0); 70 MODULE_PARM_DESC(dritek, "Force enable the Dritek keyboard extension"); 71 #endif 72 73 #ifdef CONFIG_PNP 74 static int i8042_nopnp; 75 module_param_named(nopnp, i8042_nopnp, bool, 0); 76 MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings"); 77 #endif 78 79 #define DEBUG 80 #ifdef DEBUG 81 static int i8042_debug; 82 module_param_named(debug, i8042_debug, bool, 0600); 83 MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off"); 84 #endif 85 86 #include "i8042.h" 87 88 static DEFINE_SPINLOCK(i8042_lock); 89 90 struct i8042_port { 91 struct serio *serio; 92 int irq; 93 unsigned char exists; 94 signed char mux; 95 }; 96 97 #define I8042_KBD_PORT_NO 0 98 #define I8042_AUX_PORT_NO 1 99 #define I8042_MUX_PORT_NO 2 100 #define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2) 101 102 static struct i8042_port i8042_ports[I8042_NUM_PORTS]; 103 104 static unsigned char i8042_initial_ctr; 105 static unsigned char i8042_ctr; 106 static unsigned char i8042_mux_present; 107 static unsigned char i8042_kbd_irq_registered; 108 static unsigned char i8042_aux_irq_registered; 109 static unsigned char i8042_suppress_kbd_ack; 110 static struct platform_device *i8042_platform_device; 111 112 static irqreturn_t i8042_interrupt(int irq, void *dev_id); 113 114 /* 115 * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to 116 * be ready for reading values from it / writing values to it. 117 * Called always with i8042_lock held. 118 */ 119 120 static int i8042_wait_read(void) 121 { 122 int i = 0; 123 124 while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) { 125 udelay(50); 126 i++; 127 } 128 return -(i == I8042_CTL_TIMEOUT); 129 } 130 131 static int i8042_wait_write(void) 132 { 133 int i = 0; 134 135 while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) { 136 udelay(50); 137 i++; 138 } 139 return -(i == I8042_CTL_TIMEOUT); 140 } 141 142 /* 143 * i8042_flush() flushes all data that may be in the keyboard and mouse buffers 144 * of the i8042 down the toilet. 145 */ 146 147 static int i8042_flush(void) 148 { 149 unsigned long flags; 150 unsigned char data, str; 151 int i = 0; 152 153 spin_lock_irqsave(&i8042_lock, flags); 154 155 while (((str = i8042_read_status()) & I8042_STR_OBF) && (i < I8042_BUFFER_SIZE)) { 156 udelay(50); 157 data = i8042_read_data(); 158 i++; 159 dbg("%02x <- i8042 (flush, %s)", data, 160 str & I8042_STR_AUXDATA ? "aux" : "kbd"); 161 } 162 163 spin_unlock_irqrestore(&i8042_lock, flags); 164 165 return i; 166 } 167 168 /* 169 * i8042_command() executes a command on the i8042. It also sends the input 170 * parameter(s) of the commands to it, and receives the output value(s). The 171 * parameters are to be stored in the param array, and the output is placed 172 * into the same array. The number of the parameters and output values is 173 * encoded in bits 8-11 of the command number. 174 */ 175 176 static int __i8042_command(unsigned char *param, int command) 177 { 178 int i, error; 179 180 if (i8042_noloop && command == I8042_CMD_AUX_LOOP) 181 return -1; 182 183 error = i8042_wait_write(); 184 if (error) 185 return error; 186 187 dbg("%02x -> i8042 (command)", command & 0xff); 188 i8042_write_command(command & 0xff); 189 190 for (i = 0; i < ((command >> 12) & 0xf); i++) { 191 error = i8042_wait_write(); 192 if (error) 193 return error; 194 dbg("%02x -> i8042 (parameter)", param[i]); 195 i8042_write_data(param[i]); 196 } 197 198 for (i = 0; i < ((command >> 8) & 0xf); i++) { 199 error = i8042_wait_read(); 200 if (error) { 201 dbg(" -- i8042 (timeout)"); 202 return error; 203 } 204 205 if (command == I8042_CMD_AUX_LOOP && 206 !(i8042_read_status() & I8042_STR_AUXDATA)) { 207 dbg(" -- i8042 (auxerr)"); 208 return -1; 209 } 210 211 param[i] = i8042_read_data(); 212 dbg("%02x <- i8042 (return)", param[i]); 213 } 214 215 return 0; 216 } 217 218 int i8042_command(unsigned char *param, int command) 219 { 220 unsigned long flags; 221 int retval; 222 223 spin_lock_irqsave(&i8042_lock, flags); 224 retval = __i8042_command(param, command); 225 spin_unlock_irqrestore(&i8042_lock, flags); 226 227 return retval; 228 } 229 EXPORT_SYMBOL(i8042_command); 230 231 /* 232 * i8042_kbd_write() sends a byte out through the keyboard interface. 233 */ 234 235 static int i8042_kbd_write(struct serio *port, unsigned char c) 236 { 237 unsigned long flags; 238 int retval = 0; 239 240 spin_lock_irqsave(&i8042_lock, flags); 241 242 if (!(retval = i8042_wait_write())) { 243 dbg("%02x -> i8042 (kbd-data)", c); 244 i8042_write_data(c); 245 } 246 247 spin_unlock_irqrestore(&i8042_lock, flags); 248 249 return retval; 250 } 251 252 /* 253 * i8042_aux_write() sends a byte out through the aux interface. 254 */ 255 256 static int i8042_aux_write(struct serio *serio, unsigned char c) 257 { 258 struct i8042_port *port = serio->port_data; 259 260 return i8042_command(&c, port->mux == -1 ? 261 I8042_CMD_AUX_SEND : 262 I8042_CMD_MUX_SEND + port->mux); 263 } 264 265 /* 266 * i8042_start() is called by serio core when port is about to finish 267 * registering. It will mark port as existing so i8042_interrupt can 268 * start sending data through it. 269 */ 270 static int i8042_start(struct serio *serio) 271 { 272 struct i8042_port *port = serio->port_data; 273 274 port->exists = 1; 275 mb(); 276 return 0; 277 } 278 279 /* 280 * i8042_stop() marks serio port as non-existing so i8042_interrupt 281 * will not try to send data to the port that is about to go away. 282 * The function is called by serio core as part of unregister procedure. 283 */ 284 static void i8042_stop(struct serio *serio) 285 { 286 struct i8042_port *port = serio->port_data; 287 288 port->exists = 0; 289 290 /* 291 * We synchronize with both AUX and KBD IRQs because there is 292 * a (very unlikely) chance that AUX IRQ is raised for KBD port 293 * and vice versa. 294 */ 295 synchronize_irq(I8042_AUX_IRQ); 296 synchronize_irq(I8042_KBD_IRQ); 297 port->serio = NULL; 298 } 299 300 /* 301 * i8042_interrupt() is the most important function in this driver - 302 * it handles the interrupts from the i8042, and sends incoming bytes 303 * to the upper layers. 304 */ 305 306 static irqreturn_t i8042_interrupt(int irq, void *dev_id) 307 { 308 struct i8042_port *port; 309 unsigned long flags; 310 unsigned char str, data; 311 unsigned int dfl; 312 unsigned int port_no; 313 int ret = 1; 314 315 spin_lock_irqsave(&i8042_lock, flags); 316 str = i8042_read_status(); 317 if (unlikely(~str & I8042_STR_OBF)) { 318 spin_unlock_irqrestore(&i8042_lock, flags); 319 if (irq) dbg("Interrupt %d, without any data", irq); 320 ret = 0; 321 goto out; 322 } 323 data = i8042_read_data(); 324 spin_unlock_irqrestore(&i8042_lock, flags); 325 326 if (i8042_mux_present && (str & I8042_STR_AUXDATA)) { 327 static unsigned long last_transmit; 328 static unsigned char last_str; 329 330 dfl = 0; 331 if (str & I8042_STR_MUXERR) { 332 dbg("MUX error, status is %02x, data is %02x", str, data); 333 /* 334 * When MUXERR condition is signalled the data register can only contain 335 * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately 336 * it is not always the case. Some KBCs also report 0xfc when there is 337 * nothing connected to the port while others sometimes get confused which 338 * port the data came from and signal error leaving the data intact. They 339 * _do not_ revert to legacy mode (actually I've never seen KBC reverting 340 * to legacy mode yet, when we see one we'll add proper handling). 341 * Anyway, we process 0xfc, 0xfd, 0xfe and 0xff as timeouts, and for the 342 * rest assume that the data came from the same serio last byte 343 * was transmitted (if transmission happened not too long ago). 344 */ 345 346 switch (data) { 347 default: 348 if (time_before(jiffies, last_transmit + HZ/10)) { 349 str = last_str; 350 break; 351 } 352 /* fall through - report timeout */ 353 case 0xfc: 354 case 0xfd: 355 case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break; 356 case 0xff: dfl = SERIO_PARITY; data = 0xfe; break; 357 } 358 } 359 360 port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3); 361 last_str = str; 362 last_transmit = jiffies; 363 } else { 364 365 dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) | 366 ((str & I8042_STR_TIMEOUT) ? SERIO_TIMEOUT : 0); 367 368 port_no = (str & I8042_STR_AUXDATA) ? 369 I8042_AUX_PORT_NO : I8042_KBD_PORT_NO; 370 } 371 372 port = &i8042_ports[port_no]; 373 374 dbg("%02x <- i8042 (interrupt, %d, %d%s%s)", 375 data, port_no, irq, 376 dfl & SERIO_PARITY ? ", bad parity" : "", 377 dfl & SERIO_TIMEOUT ? ", timeout" : ""); 378 379 if (unlikely(i8042_suppress_kbd_ack)) 380 if (port_no == I8042_KBD_PORT_NO && 381 (data == 0xfa || data == 0xfe)) { 382 i8042_suppress_kbd_ack--; 383 goto out; 384 } 385 386 if (likely(port->exists)) 387 serio_interrupt(port->serio, data, dfl); 388 389 out: 390 return IRQ_RETVAL(ret); 391 } 392 393 /* 394 * i8042_enable_kbd_port enables keybaord port on chip 395 */ 396 397 static int i8042_enable_kbd_port(void) 398 { 399 i8042_ctr &= ~I8042_CTR_KBDDIS; 400 i8042_ctr |= I8042_CTR_KBDINT; 401 402 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 403 i8042_ctr &= ~I8042_CTR_KBDINT; 404 i8042_ctr |= I8042_CTR_KBDDIS; 405 printk(KERN_ERR "i8042.c: Failed to enable KBD port.\n"); 406 return -EIO; 407 } 408 409 return 0; 410 } 411 412 /* 413 * i8042_enable_aux_port enables AUX (mouse) port on chip 414 */ 415 416 static int i8042_enable_aux_port(void) 417 { 418 i8042_ctr &= ~I8042_CTR_AUXDIS; 419 i8042_ctr |= I8042_CTR_AUXINT; 420 421 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 422 i8042_ctr &= ~I8042_CTR_AUXINT; 423 i8042_ctr |= I8042_CTR_AUXDIS; 424 printk(KERN_ERR "i8042.c: Failed to enable AUX port.\n"); 425 return -EIO; 426 } 427 428 return 0; 429 } 430 431 /* 432 * i8042_enable_mux_ports enables 4 individual AUX ports after 433 * the controller has been switched into Multiplexed mode 434 */ 435 436 static int i8042_enable_mux_ports(void) 437 { 438 unsigned char param; 439 int i; 440 441 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { 442 i8042_command(¶m, I8042_CMD_MUX_PFX + i); 443 i8042_command(¶m, I8042_CMD_AUX_ENABLE); 444 } 445 446 return i8042_enable_aux_port(); 447 } 448 449 /* 450 * i8042_set_mux_mode checks whether the controller has an active 451 * multiplexor and puts the chip into Multiplexed (1) or Legacy (0) mode. 452 */ 453 454 static int i8042_set_mux_mode(unsigned int mode, unsigned char *mux_version) 455 { 456 457 unsigned char param; 458 /* 459 * Get rid of bytes in the queue. 460 */ 461 462 i8042_flush(); 463 464 /* 465 * Internal loopback test - send three bytes, they should come back from the 466 * mouse interface, the last should be version. 467 */ 468 469 param = 0xf0; 470 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != 0xf0) 471 return -1; 472 param = mode ? 0x56 : 0xf6; 473 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != (mode ? 0x56 : 0xf6)) 474 return -1; 475 param = mode ? 0xa4 : 0xa5; 476 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == (mode ? 0xa4 : 0xa5)) 477 return -1; 478 479 if (mux_version) 480 *mux_version = param; 481 482 return 0; 483 } 484 485 /* 486 * i8042_check_mux() checks whether the controller supports the PS/2 Active 487 * Multiplexing specification by Synaptics, Phoenix, Insyde and 488 * LCS/Telegraphics. 489 */ 490 491 static int __devinit i8042_check_mux(void) 492 { 493 unsigned char mux_version; 494 495 if (i8042_set_mux_mode(1, &mux_version)) 496 return -1; 497 498 /* 499 * Workaround for interference with USB Legacy emulation 500 * that causes a v10.12 MUX to be found. 501 */ 502 if (mux_version == 0xAC) 503 return -1; 504 505 printk(KERN_INFO "i8042.c: Detected active multiplexing controller, rev %d.%d.\n", 506 (mux_version >> 4) & 0xf, mux_version & 0xf); 507 508 /* 509 * Disable all muxed ports by disabling AUX. 510 */ 511 i8042_ctr |= I8042_CTR_AUXDIS; 512 i8042_ctr &= ~I8042_CTR_AUXINT; 513 514 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 515 printk(KERN_ERR "i8042.c: Failed to disable AUX port, can't use MUX.\n"); 516 return -EIO; 517 } 518 519 i8042_mux_present = 1; 520 521 return 0; 522 } 523 524 /* 525 * The following is used to test AUX IRQ delivery. 526 */ 527 static struct completion i8042_aux_irq_delivered __devinitdata; 528 static int i8042_irq_being_tested __devinitdata; 529 530 static irqreturn_t __devinit i8042_aux_test_irq(int irq, void *dev_id) 531 { 532 unsigned long flags; 533 unsigned char str, data; 534 int ret = 0; 535 536 spin_lock_irqsave(&i8042_lock, flags); 537 str = i8042_read_status(); 538 if (str & I8042_STR_OBF) { 539 data = i8042_read_data(); 540 if (i8042_irq_being_tested && 541 data == 0xa5 && (str & I8042_STR_AUXDATA)) 542 complete(&i8042_aux_irq_delivered); 543 ret = 1; 544 } 545 spin_unlock_irqrestore(&i8042_lock, flags); 546 547 return IRQ_RETVAL(ret); 548 } 549 550 /* 551 * i8042_toggle_aux - enables or disables AUX port on i8042 via command and 552 * verifies success by readinng CTR. Used when testing for presence of AUX 553 * port. 554 */ 555 static int __devinit i8042_toggle_aux(int on) 556 { 557 unsigned char param; 558 int i; 559 560 if (i8042_command(¶m, 561 on ? I8042_CMD_AUX_ENABLE : I8042_CMD_AUX_DISABLE)) 562 return -1; 563 564 /* some chips need some time to set the I8042_CTR_AUXDIS bit */ 565 for (i = 0; i < 100; i++) { 566 udelay(50); 567 568 if (i8042_command(¶m, I8042_CMD_CTL_RCTR)) 569 return -1; 570 571 if (!(param & I8042_CTR_AUXDIS) == on) 572 return 0; 573 } 574 575 return -1; 576 } 577 578 /* 579 * i8042_check_aux() applies as much paranoia as it can at detecting 580 * the presence of an AUX interface. 581 */ 582 583 static int __devinit i8042_check_aux(void) 584 { 585 int retval = -1; 586 int irq_registered = 0; 587 int aux_loop_broken = 0; 588 unsigned long flags; 589 unsigned char param; 590 591 /* 592 * Get rid of bytes in the queue. 593 */ 594 595 i8042_flush(); 596 597 /* 598 * Internal loopback test - filters out AT-type i8042's. Unfortunately 599 * SiS screwed up and their 5597 doesn't support the LOOP command even 600 * though it has an AUX port. 601 */ 602 603 param = 0x5a; 604 retval = i8042_command(¶m, I8042_CMD_AUX_LOOP); 605 if (retval || param != 0x5a) { 606 607 /* 608 * External connection test - filters out AT-soldered PS/2 i8042's 609 * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error 610 * 0xfa - no error on some notebooks which ignore the spec 611 * Because it's common for chipsets to return error on perfectly functioning 612 * AUX ports, we test for this only when the LOOP command failed. 613 */ 614 615 if (i8042_command(¶m, I8042_CMD_AUX_TEST) || 616 (param && param != 0xfa && param != 0xff)) 617 return -1; 618 619 /* 620 * If AUX_LOOP completed without error but returned unexpected data 621 * mark it as broken 622 */ 623 if (!retval) 624 aux_loop_broken = 1; 625 } 626 627 /* 628 * Bit assignment test - filters out PS/2 i8042's in AT mode 629 */ 630 631 if (i8042_toggle_aux(0)) { 632 printk(KERN_WARNING "Failed to disable AUX port, but continuing anyway... Is this a SiS?\n"); 633 printk(KERN_WARNING "If AUX port is really absent please use the 'i8042.noaux' option.\n"); 634 } 635 636 if (i8042_toggle_aux(1)) 637 return -1; 638 639 /* 640 * Test AUX IRQ delivery to make sure BIOS did not grab the IRQ and 641 * used it for a PCI card or somethig else. 642 */ 643 644 if (i8042_noloop || aux_loop_broken) { 645 /* 646 * Without LOOP command we can't test AUX IRQ delivery. Assume the port 647 * is working and hope we are right. 648 */ 649 retval = 0; 650 goto out; 651 } 652 653 if (request_irq(I8042_AUX_IRQ, i8042_aux_test_irq, IRQF_SHARED, 654 "i8042", i8042_platform_device)) 655 goto out; 656 657 irq_registered = 1; 658 659 if (i8042_enable_aux_port()) 660 goto out; 661 662 spin_lock_irqsave(&i8042_lock, flags); 663 664 init_completion(&i8042_aux_irq_delivered); 665 i8042_irq_being_tested = 1; 666 667 param = 0xa5; 668 retval = __i8042_command(¶m, I8042_CMD_AUX_LOOP & 0xf0ff); 669 670 spin_unlock_irqrestore(&i8042_lock, flags); 671 672 if (retval) 673 goto out; 674 675 if (wait_for_completion_timeout(&i8042_aux_irq_delivered, 676 msecs_to_jiffies(250)) == 0) { 677 /* 678 * AUX IRQ was never delivered so we need to flush the controller to 679 * get rid of the byte we put there; otherwise keyboard may not work. 680 */ 681 i8042_flush(); 682 retval = -1; 683 } 684 685 out: 686 687 /* 688 * Disable the interface. 689 */ 690 691 i8042_ctr |= I8042_CTR_AUXDIS; 692 i8042_ctr &= ~I8042_CTR_AUXINT; 693 694 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 695 retval = -1; 696 697 if (irq_registered) 698 free_irq(I8042_AUX_IRQ, i8042_platform_device); 699 700 return retval; 701 } 702 703 static int i8042_controller_check(void) 704 { 705 if (i8042_flush() == I8042_BUFFER_SIZE) { 706 printk(KERN_ERR "i8042.c: No controller found.\n"); 707 return -ENODEV; 708 } 709 710 return 0; 711 } 712 713 static int i8042_controller_selftest(void) 714 { 715 unsigned char param; 716 int i = 0; 717 718 if (!i8042_reset) 719 return 0; 720 721 /* 722 * We try this 5 times; on some really fragile systems this does not 723 * take the first time... 724 */ 725 do { 726 727 if (i8042_command(¶m, I8042_CMD_CTL_TEST)) { 728 printk(KERN_ERR "i8042.c: i8042 controller self test timeout.\n"); 729 return -ENODEV; 730 } 731 732 if (param == I8042_RET_CTL_TEST) 733 return 0; 734 735 printk(KERN_ERR "i8042.c: i8042 controller selftest failed. (%#x != %#x)\n", 736 param, I8042_RET_CTL_TEST); 737 msleep(50); 738 } while (i++ < 5); 739 740 #ifdef CONFIG_X86 741 /* 742 * On x86, we don't fail entire i8042 initialization if controller 743 * reset fails in hopes that keyboard port will still be functional 744 * and user will still get a working keyboard. This is especially 745 * important on netbooks. On other arches we trust hardware more. 746 */ 747 printk(KERN_INFO 748 "i8042: giving up on controller selftest, continuing anyway...\n"); 749 return 0; 750 #else 751 return -EIO; 752 #endif 753 } 754 755 /* 756 * i8042_controller init initializes the i8042 controller, and, 757 * most importantly, sets it into non-xlated mode if that's 758 * desired. 759 */ 760 761 static int i8042_controller_init(void) 762 { 763 unsigned long flags; 764 765 /* 766 * Save the CTR for restoral on unload / reboot. 767 */ 768 769 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_RCTR)) { 770 printk(KERN_ERR "i8042.c: Can't read CTR while initializing i8042.\n"); 771 return -EIO; 772 } 773 774 i8042_initial_ctr = i8042_ctr; 775 776 /* 777 * Disable the keyboard interface and interrupt. 778 */ 779 780 i8042_ctr |= I8042_CTR_KBDDIS; 781 i8042_ctr &= ~I8042_CTR_KBDINT; 782 783 /* 784 * Handle keylock. 785 */ 786 787 spin_lock_irqsave(&i8042_lock, flags); 788 if (~i8042_read_status() & I8042_STR_KEYLOCK) { 789 if (i8042_unlock) 790 i8042_ctr |= I8042_CTR_IGNKEYLOCK; 791 else 792 printk(KERN_WARNING "i8042.c: Warning: Keylock active.\n"); 793 } 794 spin_unlock_irqrestore(&i8042_lock, flags); 795 796 /* 797 * If the chip is configured into nontranslated mode by the BIOS, don't 798 * bother enabling translating and be happy. 799 */ 800 801 if (~i8042_ctr & I8042_CTR_XLATE) 802 i8042_direct = 1; 803 804 /* 805 * Set nontranslated mode for the kbd interface if requested by an option. 806 * After this the kbd interface becomes a simple serial in/out, like the aux 807 * interface is. We don't do this by default, since it can confuse notebook 808 * BIOSes. 809 */ 810 811 if (i8042_direct) 812 i8042_ctr &= ~I8042_CTR_XLATE; 813 814 /* 815 * Write CTR back. 816 */ 817 818 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 819 printk(KERN_ERR "i8042.c: Can't write CTR while initializing i8042.\n"); 820 return -EIO; 821 } 822 823 return 0; 824 } 825 826 827 /* 828 * Reset the controller and reset CRT to the original value set by BIOS. 829 */ 830 831 static void i8042_controller_reset(void) 832 { 833 i8042_flush(); 834 835 /* 836 * Disable both KBD and AUX interfaces so they don't get in the way 837 */ 838 839 i8042_ctr |= I8042_CTR_KBDDIS | I8042_CTR_AUXDIS; 840 i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT); 841 842 /* 843 * Disable MUX mode if present. 844 */ 845 846 if (i8042_mux_present) 847 i8042_set_mux_mode(0, NULL); 848 849 /* 850 * Reset the controller if requested. 851 */ 852 853 i8042_controller_selftest(); 854 855 /* 856 * Restore the original control register setting. 857 */ 858 859 if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR)) 860 printk(KERN_WARNING "i8042.c: Can't restore CTR.\n"); 861 } 862 863 864 /* 865 * i8042_panic_blink() will flash the keyboard LEDs and is called when 866 * kernel panics. Flashing LEDs is useful for users running X who may 867 * not see the console and will help distingushing panics from "real" 868 * lockups. 869 * 870 * Note that DELAY has a limit of 10ms so we will not get stuck here 871 * waiting for KBC to free up even if KBD interrupt is off 872 */ 873 874 #define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0) 875 876 static long i8042_panic_blink(long count) 877 { 878 long delay = 0; 879 static long last_blink; 880 static char led; 881 882 /* 883 * We expect frequency to be about 1/2s. KDB uses about 1s. 884 * Make sure they are different. 885 */ 886 if (!i8042_blink_frequency) 887 return 0; 888 if (count - last_blink < i8042_blink_frequency) 889 return 0; 890 891 led ^= 0x01 | 0x04; 892 while (i8042_read_status() & I8042_STR_IBF) 893 DELAY; 894 dbg("%02x -> i8042 (panic blink)", 0xed); 895 i8042_suppress_kbd_ack = 2; 896 i8042_write_data(0xed); /* set leds */ 897 DELAY; 898 while (i8042_read_status() & I8042_STR_IBF) 899 DELAY; 900 DELAY; 901 dbg("%02x -> i8042 (panic blink)", led); 902 i8042_write_data(led); 903 DELAY; 904 last_blink = count; 905 return delay; 906 } 907 908 #undef DELAY 909 910 #ifdef CONFIG_X86 911 static void i8042_dritek_enable(void) 912 { 913 char param = 0x90; 914 int error; 915 916 error = i8042_command(¶m, 0x1059); 917 if (error) 918 printk(KERN_WARNING 919 "Failed to enable DRITEK extension: %d\n", 920 error); 921 } 922 #endif 923 924 #ifdef CONFIG_PM 925 926 static bool i8042_suspended; 927 928 /* 929 * Here we try to restore the original BIOS settings. We only want to 930 * do that once, when we really suspend, not when we taking memory 931 * snapshot for swsusp (in this case we'll perform required cleanup 932 * as part of shutdown process). 933 */ 934 935 static int i8042_suspend(struct platform_device *dev, pm_message_t state) 936 { 937 if (!i8042_suspended && state.event == PM_EVENT_SUSPEND) 938 i8042_controller_reset(); 939 940 i8042_suspended = state.event == PM_EVENT_SUSPEND || 941 state.event == PM_EVENT_FREEZE; 942 943 return 0; 944 } 945 946 947 /* 948 * Here we try to reset everything back to a state in which suspended 949 */ 950 951 static int i8042_resume(struct platform_device *dev) 952 { 953 int error; 954 955 /* 956 * Do not bother with restoring state if we haven't suspened yet 957 */ 958 if (!i8042_suspended) 959 return 0; 960 961 error = i8042_controller_check(); 962 if (error) 963 return error; 964 965 error = i8042_controller_selftest(); 966 if (error) 967 return error; 968 969 /* 970 * Restore original CTR value and disable all ports 971 */ 972 973 i8042_ctr = i8042_initial_ctr; 974 if (i8042_direct) 975 i8042_ctr &= ~I8042_CTR_XLATE; 976 i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS; 977 i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT); 978 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 979 printk(KERN_WARNING "i8042: Can't write CTR to resume, retrying...\n"); 980 msleep(50); 981 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 982 printk(KERN_ERR "i8042: CTR write retry failed\n"); 983 return -EIO; 984 } 985 } 986 987 988 #ifdef CONFIG_X86 989 if (i8042_dritek) 990 i8042_dritek_enable(); 991 #endif 992 993 if (i8042_mux_present) { 994 if (i8042_set_mux_mode(1, NULL) || i8042_enable_mux_ports()) 995 printk(KERN_WARNING 996 "i8042: failed to resume active multiplexor, " 997 "mouse won't work.\n"); 998 } else if (i8042_ports[I8042_AUX_PORT_NO].serio) 999 i8042_enable_aux_port(); 1000 1001 if (i8042_ports[I8042_KBD_PORT_NO].serio) 1002 i8042_enable_kbd_port(); 1003 1004 i8042_suspended = false; 1005 i8042_interrupt(0, NULL); 1006 1007 return 0; 1008 } 1009 #endif /* CONFIG_PM */ 1010 1011 /* 1012 * We need to reset the 8042 back to original mode on system shutdown, 1013 * because otherwise BIOSes will be confused. 1014 */ 1015 1016 static void i8042_shutdown(struct platform_device *dev) 1017 { 1018 i8042_controller_reset(); 1019 } 1020 1021 static int __devinit i8042_create_kbd_port(void) 1022 { 1023 struct serio *serio; 1024 struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO]; 1025 1026 serio = kzalloc(sizeof(struct serio), GFP_KERNEL); 1027 if (!serio) 1028 return -ENOMEM; 1029 1030 serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL; 1031 serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write; 1032 serio->start = i8042_start; 1033 serio->stop = i8042_stop; 1034 serio->port_data = port; 1035 serio->dev.parent = &i8042_platform_device->dev; 1036 strlcpy(serio->name, "i8042 KBD port", sizeof(serio->name)); 1037 strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys)); 1038 1039 port->serio = serio; 1040 port->irq = I8042_KBD_IRQ; 1041 1042 return 0; 1043 } 1044 1045 static int __devinit i8042_create_aux_port(int idx) 1046 { 1047 struct serio *serio; 1048 int port_no = idx < 0 ? I8042_AUX_PORT_NO : I8042_MUX_PORT_NO + idx; 1049 struct i8042_port *port = &i8042_ports[port_no]; 1050 1051 serio = kzalloc(sizeof(struct serio), GFP_KERNEL); 1052 if (!serio) 1053 return -ENOMEM; 1054 1055 serio->id.type = SERIO_8042; 1056 serio->write = i8042_aux_write; 1057 serio->start = i8042_start; 1058 serio->stop = i8042_stop; 1059 serio->port_data = port; 1060 serio->dev.parent = &i8042_platform_device->dev; 1061 if (idx < 0) { 1062 strlcpy(serio->name, "i8042 AUX port", sizeof(serio->name)); 1063 strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys)); 1064 } else { 1065 snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx); 1066 snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1); 1067 } 1068 1069 port->serio = serio; 1070 port->mux = idx; 1071 port->irq = I8042_AUX_IRQ; 1072 1073 return 0; 1074 } 1075 1076 static void __devinit i8042_free_kbd_port(void) 1077 { 1078 kfree(i8042_ports[I8042_KBD_PORT_NO].serio); 1079 i8042_ports[I8042_KBD_PORT_NO].serio = NULL; 1080 } 1081 1082 static void __devinit i8042_free_aux_ports(void) 1083 { 1084 int i; 1085 1086 for (i = I8042_AUX_PORT_NO; i < I8042_NUM_PORTS; i++) { 1087 kfree(i8042_ports[i].serio); 1088 i8042_ports[i].serio = NULL; 1089 } 1090 } 1091 1092 static void __devinit i8042_register_ports(void) 1093 { 1094 int i; 1095 1096 for (i = 0; i < I8042_NUM_PORTS; i++) { 1097 if (i8042_ports[i].serio) { 1098 printk(KERN_INFO "serio: %s at %#lx,%#lx irq %d\n", 1099 i8042_ports[i].serio->name, 1100 (unsigned long) I8042_DATA_REG, 1101 (unsigned long) I8042_COMMAND_REG, 1102 i8042_ports[i].irq); 1103 serio_register_port(i8042_ports[i].serio); 1104 } 1105 } 1106 } 1107 1108 static void __devexit i8042_unregister_ports(void) 1109 { 1110 int i; 1111 1112 for (i = 0; i < I8042_NUM_PORTS; i++) { 1113 if (i8042_ports[i].serio) { 1114 serio_unregister_port(i8042_ports[i].serio); 1115 i8042_ports[i].serio = NULL; 1116 } 1117 } 1118 } 1119 1120 static void i8042_free_irqs(void) 1121 { 1122 if (i8042_aux_irq_registered) 1123 free_irq(I8042_AUX_IRQ, i8042_platform_device); 1124 if (i8042_kbd_irq_registered) 1125 free_irq(I8042_KBD_IRQ, i8042_platform_device); 1126 1127 i8042_aux_irq_registered = i8042_kbd_irq_registered = 0; 1128 } 1129 1130 static int __devinit i8042_setup_aux(void) 1131 { 1132 int (*aux_enable)(void); 1133 int error; 1134 int i; 1135 1136 if (i8042_check_aux()) 1137 return -ENODEV; 1138 1139 if (i8042_nomux || i8042_check_mux()) { 1140 error = i8042_create_aux_port(-1); 1141 if (error) 1142 goto err_free_ports; 1143 aux_enable = i8042_enable_aux_port; 1144 } else { 1145 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { 1146 error = i8042_create_aux_port(i); 1147 if (error) 1148 goto err_free_ports; 1149 } 1150 aux_enable = i8042_enable_mux_ports; 1151 } 1152 1153 error = request_irq(I8042_AUX_IRQ, i8042_interrupt, IRQF_SHARED, 1154 "i8042", i8042_platform_device); 1155 if (error) 1156 goto err_free_ports; 1157 1158 if (aux_enable()) 1159 goto err_free_irq; 1160 1161 i8042_aux_irq_registered = 1; 1162 return 0; 1163 1164 err_free_irq: 1165 free_irq(I8042_AUX_IRQ, i8042_platform_device); 1166 err_free_ports: 1167 i8042_free_aux_ports(); 1168 return error; 1169 } 1170 1171 static int __devinit i8042_setup_kbd(void) 1172 { 1173 int error; 1174 1175 error = i8042_create_kbd_port(); 1176 if (error) 1177 return error; 1178 1179 error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED, 1180 "i8042", i8042_platform_device); 1181 if (error) 1182 goto err_free_port; 1183 1184 error = i8042_enable_kbd_port(); 1185 if (error) 1186 goto err_free_irq; 1187 1188 i8042_kbd_irq_registered = 1; 1189 return 0; 1190 1191 err_free_irq: 1192 free_irq(I8042_KBD_IRQ, i8042_platform_device); 1193 err_free_port: 1194 i8042_free_kbd_port(); 1195 return error; 1196 } 1197 1198 static int __devinit i8042_probe(struct platform_device *dev) 1199 { 1200 int error; 1201 1202 error = i8042_controller_selftest(); 1203 if (error) 1204 return error; 1205 1206 error = i8042_controller_init(); 1207 if (error) 1208 return error; 1209 1210 #ifdef CONFIG_X86 1211 if (i8042_dritek) 1212 i8042_dritek_enable(); 1213 #endif 1214 1215 if (!i8042_noaux) { 1216 error = i8042_setup_aux(); 1217 if (error && error != -ENODEV && error != -EBUSY) 1218 goto out_fail; 1219 } 1220 1221 if (!i8042_nokbd) { 1222 error = i8042_setup_kbd(); 1223 if (error) 1224 goto out_fail; 1225 } 1226 /* 1227 * Ok, everything is ready, let's register all serio ports 1228 */ 1229 i8042_register_ports(); 1230 1231 return 0; 1232 1233 out_fail: 1234 i8042_free_aux_ports(); /* in case KBD failed but AUX not */ 1235 i8042_free_irqs(); 1236 i8042_controller_reset(); 1237 1238 return error; 1239 } 1240 1241 static int __devexit i8042_remove(struct platform_device *dev) 1242 { 1243 i8042_unregister_ports(); 1244 i8042_free_irqs(); 1245 i8042_controller_reset(); 1246 1247 return 0; 1248 } 1249 1250 static struct platform_driver i8042_driver = { 1251 .driver = { 1252 .name = "i8042", 1253 .owner = THIS_MODULE, 1254 }, 1255 .probe = i8042_probe, 1256 .remove = __devexit_p(i8042_remove), 1257 .shutdown = i8042_shutdown, 1258 #ifdef CONFIG_PM 1259 .suspend = i8042_suspend, 1260 .resume = i8042_resume, 1261 #endif 1262 }; 1263 1264 static int __init i8042_init(void) 1265 { 1266 int err; 1267 1268 dbg_init(); 1269 1270 err = i8042_platform_init(); 1271 if (err) 1272 return err; 1273 1274 err = i8042_controller_check(); 1275 if (err) 1276 goto err_platform_exit; 1277 1278 err = platform_driver_register(&i8042_driver); 1279 if (err) 1280 goto err_platform_exit; 1281 1282 i8042_platform_device = platform_device_alloc("i8042", -1); 1283 if (!i8042_platform_device) { 1284 err = -ENOMEM; 1285 goto err_unregister_driver; 1286 } 1287 1288 err = platform_device_add(i8042_platform_device); 1289 if (err) 1290 goto err_free_device; 1291 1292 panic_blink = i8042_panic_blink; 1293 1294 return 0; 1295 1296 err_free_device: 1297 platform_device_put(i8042_platform_device); 1298 err_unregister_driver: 1299 platform_driver_unregister(&i8042_driver); 1300 err_platform_exit: 1301 i8042_platform_exit(); 1302 1303 return err; 1304 } 1305 1306 static void __exit i8042_exit(void) 1307 { 1308 platform_device_unregister(i8042_platform_device); 1309 platform_driver_unregister(&i8042_driver); 1310 i8042_platform_exit(); 1311 1312 panic_blink = NULL; 1313 } 1314 1315 module_init(i8042_init); 1316 module_exit(i8042_exit); 1317