1 /* 2 * i8042 keyboard and mouse controller driver for Linux 3 * 4 * Copyright (c) 1999-2004 Vojtech Pavlik 5 */ 6 7 /* 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License version 2 as published by 10 * the Free Software Foundation. 11 */ 12 13 #include <linux/types.h> 14 #include <linux/delay.h> 15 #include <linux/module.h> 16 #include <linux/interrupt.h> 17 #include <linux/ioport.h> 18 #include <linux/init.h> 19 #include <linux/serio.h> 20 #include <linux/err.h> 21 #include <linux/rcupdate.h> 22 #include <linux/platform_device.h> 23 #include <linux/i8042.h> 24 25 #include <asm/io.h> 26 27 MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>"); 28 MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver"); 29 MODULE_LICENSE("GPL"); 30 31 static bool i8042_nokbd; 32 module_param_named(nokbd, i8042_nokbd, bool, 0); 33 MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port."); 34 35 static bool i8042_noaux; 36 module_param_named(noaux, i8042_noaux, bool, 0); 37 MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port."); 38 39 static bool i8042_nomux; 40 module_param_named(nomux, i8042_nomux, bool, 0); 41 MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing conrtoller is present."); 42 43 static bool i8042_unlock; 44 module_param_named(unlock, i8042_unlock, bool, 0); 45 MODULE_PARM_DESC(unlock, "Ignore keyboard lock."); 46 47 static bool i8042_reset; 48 module_param_named(reset, i8042_reset, bool, 0); 49 MODULE_PARM_DESC(reset, "Reset controller during init and cleanup."); 50 51 static bool i8042_direct; 52 module_param_named(direct, i8042_direct, bool, 0); 53 MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode."); 54 55 static bool i8042_dumbkbd; 56 module_param_named(dumbkbd, i8042_dumbkbd, bool, 0); 57 MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard"); 58 59 static bool i8042_noloop; 60 module_param_named(noloop, i8042_noloop, bool, 0); 61 MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port"); 62 63 static unsigned int i8042_blink_frequency = 500; 64 module_param_named(panicblink, i8042_blink_frequency, uint, 0600); 65 MODULE_PARM_DESC(panicblink, "Frequency with which keyboard LEDs should blink when kernel panics"); 66 67 #ifdef CONFIG_X86 68 static bool i8042_dritek; 69 module_param_named(dritek, i8042_dritek, bool, 0); 70 MODULE_PARM_DESC(dritek, "Force enable the Dritek keyboard extension"); 71 #endif 72 73 #ifdef CONFIG_PNP 74 static bool i8042_nopnp; 75 module_param_named(nopnp, i8042_nopnp, bool, 0); 76 MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings"); 77 #endif 78 79 #define DEBUG 80 #ifdef DEBUG 81 static bool i8042_debug; 82 module_param_named(debug, i8042_debug, bool, 0600); 83 MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off"); 84 #endif 85 86 static bool i8042_bypass_aux_irq_test; 87 88 #include "i8042.h" 89 90 static DEFINE_SPINLOCK(i8042_lock); 91 92 struct i8042_port { 93 struct serio *serio; 94 int irq; 95 bool exists; 96 signed char mux; 97 }; 98 99 #define I8042_KBD_PORT_NO 0 100 #define I8042_AUX_PORT_NO 1 101 #define I8042_MUX_PORT_NO 2 102 #define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2) 103 104 static struct i8042_port i8042_ports[I8042_NUM_PORTS]; 105 106 static unsigned char i8042_initial_ctr; 107 static unsigned char i8042_ctr; 108 static bool i8042_mux_present; 109 static bool i8042_kbd_irq_registered; 110 static bool i8042_aux_irq_registered; 111 static unsigned char i8042_suppress_kbd_ack; 112 static struct platform_device *i8042_platform_device; 113 114 static irqreturn_t i8042_interrupt(int irq, void *dev_id); 115 116 /* 117 * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to 118 * be ready for reading values from it / writing values to it. 119 * Called always with i8042_lock held. 120 */ 121 122 static int i8042_wait_read(void) 123 { 124 int i = 0; 125 126 while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) { 127 udelay(50); 128 i++; 129 } 130 return -(i == I8042_CTL_TIMEOUT); 131 } 132 133 static int i8042_wait_write(void) 134 { 135 int i = 0; 136 137 while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) { 138 udelay(50); 139 i++; 140 } 141 return -(i == I8042_CTL_TIMEOUT); 142 } 143 144 /* 145 * i8042_flush() flushes all data that may be in the keyboard and mouse buffers 146 * of the i8042 down the toilet. 147 */ 148 149 static int i8042_flush(void) 150 { 151 unsigned long flags; 152 unsigned char data, str; 153 int i = 0; 154 155 spin_lock_irqsave(&i8042_lock, flags); 156 157 while (((str = i8042_read_status()) & I8042_STR_OBF) && (i < I8042_BUFFER_SIZE)) { 158 udelay(50); 159 data = i8042_read_data(); 160 i++; 161 dbg("%02x <- i8042 (flush, %s)", data, 162 str & I8042_STR_AUXDATA ? "aux" : "kbd"); 163 } 164 165 spin_unlock_irqrestore(&i8042_lock, flags); 166 167 return i; 168 } 169 170 /* 171 * i8042_command() executes a command on the i8042. It also sends the input 172 * parameter(s) of the commands to it, and receives the output value(s). The 173 * parameters are to be stored in the param array, and the output is placed 174 * into the same array. The number of the parameters and output values is 175 * encoded in bits 8-11 of the command number. 176 */ 177 178 static int __i8042_command(unsigned char *param, int command) 179 { 180 int i, error; 181 182 if (i8042_noloop && command == I8042_CMD_AUX_LOOP) 183 return -1; 184 185 error = i8042_wait_write(); 186 if (error) 187 return error; 188 189 dbg("%02x -> i8042 (command)", command & 0xff); 190 i8042_write_command(command & 0xff); 191 192 for (i = 0; i < ((command >> 12) & 0xf); i++) { 193 error = i8042_wait_write(); 194 if (error) 195 return error; 196 dbg("%02x -> i8042 (parameter)", param[i]); 197 i8042_write_data(param[i]); 198 } 199 200 for (i = 0; i < ((command >> 8) & 0xf); i++) { 201 error = i8042_wait_read(); 202 if (error) { 203 dbg(" -- i8042 (timeout)"); 204 return error; 205 } 206 207 if (command == I8042_CMD_AUX_LOOP && 208 !(i8042_read_status() & I8042_STR_AUXDATA)) { 209 dbg(" -- i8042 (auxerr)"); 210 return -1; 211 } 212 213 param[i] = i8042_read_data(); 214 dbg("%02x <- i8042 (return)", param[i]); 215 } 216 217 return 0; 218 } 219 220 int i8042_command(unsigned char *param, int command) 221 { 222 unsigned long flags; 223 int retval; 224 225 spin_lock_irqsave(&i8042_lock, flags); 226 retval = __i8042_command(param, command); 227 spin_unlock_irqrestore(&i8042_lock, flags); 228 229 return retval; 230 } 231 EXPORT_SYMBOL(i8042_command); 232 233 /* 234 * i8042_kbd_write() sends a byte out through the keyboard interface. 235 */ 236 237 static int i8042_kbd_write(struct serio *port, unsigned char c) 238 { 239 unsigned long flags; 240 int retval = 0; 241 242 spin_lock_irqsave(&i8042_lock, flags); 243 244 if (!(retval = i8042_wait_write())) { 245 dbg("%02x -> i8042 (kbd-data)", c); 246 i8042_write_data(c); 247 } 248 249 spin_unlock_irqrestore(&i8042_lock, flags); 250 251 return retval; 252 } 253 254 /* 255 * i8042_aux_write() sends a byte out through the aux interface. 256 */ 257 258 static int i8042_aux_write(struct serio *serio, unsigned char c) 259 { 260 struct i8042_port *port = serio->port_data; 261 262 return i8042_command(&c, port->mux == -1 ? 263 I8042_CMD_AUX_SEND : 264 I8042_CMD_MUX_SEND + port->mux); 265 } 266 267 268 /* 269 * i8042_aux_close attempts to clear AUX or KBD port state by disabling 270 * and then re-enabling it. 271 */ 272 273 static void i8042_port_close(struct serio *serio) 274 { 275 int irq_bit; 276 int disable_bit; 277 const char *port_name; 278 279 if (serio == i8042_ports[I8042_AUX_PORT_NO].serio) { 280 irq_bit = I8042_CTR_AUXINT; 281 disable_bit = I8042_CTR_AUXDIS; 282 port_name = "AUX"; 283 } else { 284 irq_bit = I8042_CTR_KBDINT; 285 disable_bit = I8042_CTR_KBDDIS; 286 port_name = "KBD"; 287 } 288 289 i8042_ctr &= ~irq_bit; 290 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 291 printk(KERN_WARNING 292 "i8042.c: Can't write CTR while closing %s port.\n", 293 port_name); 294 295 udelay(50); 296 297 i8042_ctr &= ~disable_bit; 298 i8042_ctr |= irq_bit; 299 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 300 printk(KERN_ERR "i8042.c: Can't reactivate %s port.\n", 301 port_name); 302 303 /* 304 * See if there is any data appeared while we were messing with 305 * port state. 306 */ 307 i8042_interrupt(0, NULL); 308 } 309 310 /* 311 * i8042_start() is called by serio core when port is about to finish 312 * registering. It will mark port as existing so i8042_interrupt can 313 * start sending data through it. 314 */ 315 static int i8042_start(struct serio *serio) 316 { 317 struct i8042_port *port = serio->port_data; 318 319 port->exists = true; 320 mb(); 321 return 0; 322 } 323 324 /* 325 * i8042_stop() marks serio port as non-existing so i8042_interrupt 326 * will not try to send data to the port that is about to go away. 327 * The function is called by serio core as part of unregister procedure. 328 */ 329 static void i8042_stop(struct serio *serio) 330 { 331 struct i8042_port *port = serio->port_data; 332 333 port->exists = false; 334 335 /* 336 * We synchronize with both AUX and KBD IRQs because there is 337 * a (very unlikely) chance that AUX IRQ is raised for KBD port 338 * and vice versa. 339 */ 340 synchronize_irq(I8042_AUX_IRQ); 341 synchronize_irq(I8042_KBD_IRQ); 342 port->serio = NULL; 343 } 344 345 /* 346 * i8042_interrupt() is the most important function in this driver - 347 * it handles the interrupts from the i8042, and sends incoming bytes 348 * to the upper layers. 349 */ 350 351 static irqreturn_t i8042_interrupt(int irq, void *dev_id) 352 { 353 struct i8042_port *port; 354 unsigned long flags; 355 unsigned char str, data; 356 unsigned int dfl; 357 unsigned int port_no; 358 int ret = 1; 359 360 spin_lock_irqsave(&i8042_lock, flags); 361 str = i8042_read_status(); 362 if (unlikely(~str & I8042_STR_OBF)) { 363 spin_unlock_irqrestore(&i8042_lock, flags); 364 if (irq) dbg("Interrupt %d, without any data", irq); 365 ret = 0; 366 goto out; 367 } 368 data = i8042_read_data(); 369 spin_unlock_irqrestore(&i8042_lock, flags); 370 371 if (i8042_mux_present && (str & I8042_STR_AUXDATA)) { 372 static unsigned long last_transmit; 373 static unsigned char last_str; 374 375 dfl = 0; 376 if (str & I8042_STR_MUXERR) { 377 dbg("MUX error, status is %02x, data is %02x", str, data); 378 /* 379 * When MUXERR condition is signalled the data register can only contain 380 * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately 381 * it is not always the case. Some KBCs also report 0xfc when there is 382 * nothing connected to the port while others sometimes get confused which 383 * port the data came from and signal error leaving the data intact. They 384 * _do not_ revert to legacy mode (actually I've never seen KBC reverting 385 * to legacy mode yet, when we see one we'll add proper handling). 386 * Anyway, we process 0xfc, 0xfd, 0xfe and 0xff as timeouts, and for the 387 * rest assume that the data came from the same serio last byte 388 * was transmitted (if transmission happened not too long ago). 389 */ 390 391 switch (data) { 392 default: 393 if (time_before(jiffies, last_transmit + HZ/10)) { 394 str = last_str; 395 break; 396 } 397 /* fall through - report timeout */ 398 case 0xfc: 399 case 0xfd: 400 case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break; 401 case 0xff: dfl = SERIO_PARITY; data = 0xfe; break; 402 } 403 } 404 405 port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3); 406 last_str = str; 407 last_transmit = jiffies; 408 } else { 409 410 dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) | 411 ((str & I8042_STR_TIMEOUT) ? SERIO_TIMEOUT : 0); 412 413 port_no = (str & I8042_STR_AUXDATA) ? 414 I8042_AUX_PORT_NO : I8042_KBD_PORT_NO; 415 } 416 417 port = &i8042_ports[port_no]; 418 419 dbg("%02x <- i8042 (interrupt, %d, %d%s%s)", 420 data, port_no, irq, 421 dfl & SERIO_PARITY ? ", bad parity" : "", 422 dfl & SERIO_TIMEOUT ? ", timeout" : ""); 423 424 if (unlikely(i8042_suppress_kbd_ack)) 425 if (port_no == I8042_KBD_PORT_NO && 426 (data == 0xfa || data == 0xfe)) { 427 i8042_suppress_kbd_ack--; 428 goto out; 429 } 430 431 if (likely(port->exists)) 432 serio_interrupt(port->serio, data, dfl); 433 434 out: 435 return IRQ_RETVAL(ret); 436 } 437 438 /* 439 * i8042_enable_kbd_port enables keyboard port on chip 440 */ 441 442 static int i8042_enable_kbd_port(void) 443 { 444 i8042_ctr &= ~I8042_CTR_KBDDIS; 445 i8042_ctr |= I8042_CTR_KBDINT; 446 447 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 448 i8042_ctr &= ~I8042_CTR_KBDINT; 449 i8042_ctr |= I8042_CTR_KBDDIS; 450 printk(KERN_ERR "i8042.c: Failed to enable KBD port.\n"); 451 return -EIO; 452 } 453 454 return 0; 455 } 456 457 /* 458 * i8042_enable_aux_port enables AUX (mouse) port on chip 459 */ 460 461 static int i8042_enable_aux_port(void) 462 { 463 i8042_ctr &= ~I8042_CTR_AUXDIS; 464 i8042_ctr |= I8042_CTR_AUXINT; 465 466 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 467 i8042_ctr &= ~I8042_CTR_AUXINT; 468 i8042_ctr |= I8042_CTR_AUXDIS; 469 printk(KERN_ERR "i8042.c: Failed to enable AUX port.\n"); 470 return -EIO; 471 } 472 473 return 0; 474 } 475 476 /* 477 * i8042_enable_mux_ports enables 4 individual AUX ports after 478 * the controller has been switched into Multiplexed mode 479 */ 480 481 static int i8042_enable_mux_ports(void) 482 { 483 unsigned char param; 484 int i; 485 486 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { 487 i8042_command(¶m, I8042_CMD_MUX_PFX + i); 488 i8042_command(¶m, I8042_CMD_AUX_ENABLE); 489 } 490 491 return i8042_enable_aux_port(); 492 } 493 494 /* 495 * i8042_set_mux_mode checks whether the controller has an 496 * active multiplexor and puts the chip into Multiplexed (true) 497 * or Legacy (false) mode. 498 */ 499 500 static int i8042_set_mux_mode(bool multiplex, unsigned char *mux_version) 501 { 502 503 unsigned char param, val; 504 /* 505 * Get rid of bytes in the queue. 506 */ 507 508 i8042_flush(); 509 510 /* 511 * Internal loopback test - send three bytes, they should come back from the 512 * mouse interface, the last should be version. 513 */ 514 515 param = val = 0xf0; 516 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) 517 return -1; 518 param = val = multiplex ? 0x56 : 0xf6; 519 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) 520 return -1; 521 param = val = multiplex ? 0xa4 : 0xa5; 522 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == val) 523 return -1; 524 525 /* 526 * Workaround for interference with USB Legacy emulation 527 * that causes a v10.12 MUX to be found. 528 */ 529 if (param == 0xac) 530 return -1; 531 532 if (mux_version) 533 *mux_version = param; 534 535 return 0; 536 } 537 538 /* 539 * i8042_check_mux() checks whether the controller supports the PS/2 Active 540 * Multiplexing specification by Synaptics, Phoenix, Insyde and 541 * LCS/Telegraphics. 542 */ 543 544 static int __init i8042_check_mux(void) 545 { 546 unsigned char mux_version; 547 548 if (i8042_set_mux_mode(true, &mux_version)) 549 return -1; 550 551 printk(KERN_INFO "i8042.c: Detected active multiplexing controller, rev %d.%d.\n", 552 (mux_version >> 4) & 0xf, mux_version & 0xf); 553 554 /* 555 * Disable all muxed ports by disabling AUX. 556 */ 557 i8042_ctr |= I8042_CTR_AUXDIS; 558 i8042_ctr &= ~I8042_CTR_AUXINT; 559 560 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 561 printk(KERN_ERR "i8042.c: Failed to disable AUX port, can't use MUX.\n"); 562 return -EIO; 563 } 564 565 i8042_mux_present = true; 566 567 return 0; 568 } 569 570 /* 571 * The following is used to test AUX IRQ delivery. 572 */ 573 static struct completion i8042_aux_irq_delivered __initdata; 574 static bool i8042_irq_being_tested __initdata; 575 576 static irqreturn_t __init i8042_aux_test_irq(int irq, void *dev_id) 577 { 578 unsigned long flags; 579 unsigned char str, data; 580 int ret = 0; 581 582 spin_lock_irqsave(&i8042_lock, flags); 583 str = i8042_read_status(); 584 if (str & I8042_STR_OBF) { 585 data = i8042_read_data(); 586 if (i8042_irq_being_tested && 587 data == 0xa5 && (str & I8042_STR_AUXDATA)) 588 complete(&i8042_aux_irq_delivered); 589 ret = 1; 590 } 591 spin_unlock_irqrestore(&i8042_lock, flags); 592 593 return IRQ_RETVAL(ret); 594 } 595 596 /* 597 * i8042_toggle_aux - enables or disables AUX port on i8042 via command and 598 * verifies success by readinng CTR. Used when testing for presence of AUX 599 * port. 600 */ 601 static int __init i8042_toggle_aux(bool on) 602 { 603 unsigned char param; 604 int i; 605 606 if (i8042_command(¶m, 607 on ? I8042_CMD_AUX_ENABLE : I8042_CMD_AUX_DISABLE)) 608 return -1; 609 610 /* some chips need some time to set the I8042_CTR_AUXDIS bit */ 611 for (i = 0; i < 100; i++) { 612 udelay(50); 613 614 if (i8042_command(¶m, I8042_CMD_CTL_RCTR)) 615 return -1; 616 617 if (!(param & I8042_CTR_AUXDIS) == on) 618 return 0; 619 } 620 621 return -1; 622 } 623 624 /* 625 * i8042_check_aux() applies as much paranoia as it can at detecting 626 * the presence of an AUX interface. 627 */ 628 629 static int __init i8042_check_aux(void) 630 { 631 int retval = -1; 632 bool irq_registered = false; 633 bool aux_loop_broken = false; 634 unsigned long flags; 635 unsigned char param; 636 637 /* 638 * Get rid of bytes in the queue. 639 */ 640 641 i8042_flush(); 642 643 /* 644 * Internal loopback test - filters out AT-type i8042's. Unfortunately 645 * SiS screwed up and their 5597 doesn't support the LOOP command even 646 * though it has an AUX port. 647 */ 648 649 param = 0x5a; 650 retval = i8042_command(¶m, I8042_CMD_AUX_LOOP); 651 if (retval || param != 0x5a) { 652 653 /* 654 * External connection test - filters out AT-soldered PS/2 i8042's 655 * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error 656 * 0xfa - no error on some notebooks which ignore the spec 657 * Because it's common for chipsets to return error on perfectly functioning 658 * AUX ports, we test for this only when the LOOP command failed. 659 */ 660 661 if (i8042_command(¶m, I8042_CMD_AUX_TEST) || 662 (param && param != 0xfa && param != 0xff)) 663 return -1; 664 665 /* 666 * If AUX_LOOP completed without error but returned unexpected data 667 * mark it as broken 668 */ 669 if (!retval) 670 aux_loop_broken = true; 671 } 672 673 /* 674 * Bit assignment test - filters out PS/2 i8042's in AT mode 675 */ 676 677 if (i8042_toggle_aux(false)) { 678 printk(KERN_WARNING "Failed to disable AUX port, but continuing anyway... Is this a SiS?\n"); 679 printk(KERN_WARNING "If AUX port is really absent please use the 'i8042.noaux' option.\n"); 680 } 681 682 if (i8042_toggle_aux(true)) 683 return -1; 684 685 /* 686 * Test AUX IRQ delivery to make sure BIOS did not grab the IRQ and 687 * used it for a PCI card or somethig else. 688 */ 689 690 if (i8042_noloop || i8042_bypass_aux_irq_test || aux_loop_broken) { 691 /* 692 * Without LOOP command we can't test AUX IRQ delivery. Assume the port 693 * is working and hope we are right. 694 */ 695 retval = 0; 696 goto out; 697 } 698 699 if (request_irq(I8042_AUX_IRQ, i8042_aux_test_irq, IRQF_SHARED, 700 "i8042", i8042_platform_device)) 701 goto out; 702 703 irq_registered = true; 704 705 if (i8042_enable_aux_port()) 706 goto out; 707 708 spin_lock_irqsave(&i8042_lock, flags); 709 710 init_completion(&i8042_aux_irq_delivered); 711 i8042_irq_being_tested = true; 712 713 param = 0xa5; 714 retval = __i8042_command(¶m, I8042_CMD_AUX_LOOP & 0xf0ff); 715 716 spin_unlock_irqrestore(&i8042_lock, flags); 717 718 if (retval) 719 goto out; 720 721 if (wait_for_completion_timeout(&i8042_aux_irq_delivered, 722 msecs_to_jiffies(250)) == 0) { 723 /* 724 * AUX IRQ was never delivered so we need to flush the controller to 725 * get rid of the byte we put there; otherwise keyboard may not work. 726 */ 727 i8042_flush(); 728 retval = -1; 729 } 730 731 out: 732 733 /* 734 * Disable the interface. 735 */ 736 737 i8042_ctr |= I8042_CTR_AUXDIS; 738 i8042_ctr &= ~I8042_CTR_AUXINT; 739 740 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 741 retval = -1; 742 743 if (irq_registered) 744 free_irq(I8042_AUX_IRQ, i8042_platform_device); 745 746 return retval; 747 } 748 749 static int i8042_controller_check(void) 750 { 751 if (i8042_flush() == I8042_BUFFER_SIZE) { 752 printk(KERN_ERR "i8042.c: No controller found.\n"); 753 return -ENODEV; 754 } 755 756 return 0; 757 } 758 759 static int i8042_controller_selftest(void) 760 { 761 unsigned char param; 762 int i = 0; 763 764 if (!i8042_reset) 765 return 0; 766 767 /* 768 * We try this 5 times; on some really fragile systems this does not 769 * take the first time... 770 */ 771 do { 772 773 if (i8042_command(¶m, I8042_CMD_CTL_TEST)) { 774 printk(KERN_ERR "i8042.c: i8042 controller self test timeout.\n"); 775 return -ENODEV; 776 } 777 778 if (param == I8042_RET_CTL_TEST) 779 return 0; 780 781 printk(KERN_ERR "i8042.c: i8042 controller selftest failed. (%#x != %#x)\n", 782 param, I8042_RET_CTL_TEST); 783 msleep(50); 784 } while (i++ < 5); 785 786 #ifdef CONFIG_X86 787 /* 788 * On x86, we don't fail entire i8042 initialization if controller 789 * reset fails in hopes that keyboard port will still be functional 790 * and user will still get a working keyboard. This is especially 791 * important on netbooks. On other arches we trust hardware more. 792 */ 793 printk(KERN_INFO 794 "i8042: giving up on controller selftest, continuing anyway...\n"); 795 return 0; 796 #else 797 return -EIO; 798 #endif 799 } 800 801 /* 802 * i8042_controller init initializes the i8042 controller, and, 803 * most importantly, sets it into non-xlated mode if that's 804 * desired. 805 */ 806 807 static int i8042_controller_init(void) 808 { 809 unsigned long flags; 810 811 /* 812 * Save the CTR for restoral on unload / reboot. 813 */ 814 815 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_RCTR)) { 816 printk(KERN_ERR "i8042.c: Can't read CTR while initializing i8042.\n"); 817 return -EIO; 818 } 819 820 i8042_initial_ctr = i8042_ctr; 821 822 /* 823 * Disable the keyboard interface and interrupt. 824 */ 825 826 i8042_ctr |= I8042_CTR_KBDDIS; 827 i8042_ctr &= ~I8042_CTR_KBDINT; 828 829 /* 830 * Handle keylock. 831 */ 832 833 spin_lock_irqsave(&i8042_lock, flags); 834 if (~i8042_read_status() & I8042_STR_KEYLOCK) { 835 if (i8042_unlock) 836 i8042_ctr |= I8042_CTR_IGNKEYLOCK; 837 else 838 printk(KERN_WARNING "i8042.c: Warning: Keylock active.\n"); 839 } 840 spin_unlock_irqrestore(&i8042_lock, flags); 841 842 /* 843 * If the chip is configured into nontranslated mode by the BIOS, don't 844 * bother enabling translating and be happy. 845 */ 846 847 if (~i8042_ctr & I8042_CTR_XLATE) 848 i8042_direct = true; 849 850 /* 851 * Set nontranslated mode for the kbd interface if requested by an option. 852 * After this the kbd interface becomes a simple serial in/out, like the aux 853 * interface is. We don't do this by default, since it can confuse notebook 854 * BIOSes. 855 */ 856 857 if (i8042_direct) 858 i8042_ctr &= ~I8042_CTR_XLATE; 859 860 /* 861 * Write CTR back. 862 */ 863 864 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 865 printk(KERN_ERR "i8042.c: Can't write CTR while initializing i8042.\n"); 866 return -EIO; 867 } 868 869 return 0; 870 } 871 872 873 /* 874 * Reset the controller and reset CRT to the original value set by BIOS. 875 */ 876 877 static void i8042_controller_reset(void) 878 { 879 i8042_flush(); 880 881 /* 882 * Disable both KBD and AUX interfaces so they don't get in the way 883 */ 884 885 i8042_ctr |= I8042_CTR_KBDDIS | I8042_CTR_AUXDIS; 886 i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT); 887 888 if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR)) 889 printk(KERN_WARNING "i8042.c: Can't write CTR while resetting.\n"); 890 891 /* 892 * Disable MUX mode if present. 893 */ 894 895 if (i8042_mux_present) 896 i8042_set_mux_mode(false, NULL); 897 898 /* 899 * Reset the controller if requested. 900 */ 901 902 i8042_controller_selftest(); 903 904 /* 905 * Restore the original control register setting. 906 */ 907 908 if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR)) 909 printk(KERN_WARNING "i8042.c: Can't restore CTR.\n"); 910 } 911 912 913 /* 914 * i8042_panic_blink() will flash the keyboard LEDs and is called when 915 * kernel panics. Flashing LEDs is useful for users running X who may 916 * not see the console and will help distingushing panics from "real" 917 * lockups. 918 * 919 * Note that DELAY has a limit of 10ms so we will not get stuck here 920 * waiting for KBC to free up even if KBD interrupt is off 921 */ 922 923 #define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0) 924 925 static long i8042_panic_blink(long count) 926 { 927 long delay = 0; 928 static long last_blink; 929 static char led; 930 931 /* 932 * We expect frequency to be about 1/2s. KDB uses about 1s. 933 * Make sure they are different. 934 */ 935 if (!i8042_blink_frequency) 936 return 0; 937 if (count - last_blink < i8042_blink_frequency) 938 return 0; 939 940 led ^= 0x01 | 0x04; 941 while (i8042_read_status() & I8042_STR_IBF) 942 DELAY; 943 dbg("%02x -> i8042 (panic blink)", 0xed); 944 i8042_suppress_kbd_ack = 2; 945 i8042_write_data(0xed); /* set leds */ 946 DELAY; 947 while (i8042_read_status() & I8042_STR_IBF) 948 DELAY; 949 DELAY; 950 dbg("%02x -> i8042 (panic blink)", led); 951 i8042_write_data(led); 952 DELAY; 953 last_blink = count; 954 return delay; 955 } 956 957 #undef DELAY 958 959 #ifdef CONFIG_X86 960 static void i8042_dritek_enable(void) 961 { 962 char param = 0x90; 963 int error; 964 965 error = i8042_command(¶m, 0x1059); 966 if (error) 967 printk(KERN_WARNING 968 "Failed to enable DRITEK extension: %d\n", 969 error); 970 } 971 #endif 972 973 #ifdef CONFIG_PM 974 975 /* 976 * Here we try to restore the original BIOS settings to avoid 977 * upsetting it. 978 */ 979 980 static int i8042_pm_reset(struct device *dev) 981 { 982 i8042_controller_reset(); 983 984 return 0; 985 } 986 987 /* 988 * Here we try to reset everything back to a state we had 989 * before suspending. 990 */ 991 992 static int i8042_pm_restore(struct device *dev) 993 { 994 int error; 995 996 error = i8042_controller_check(); 997 if (error) 998 return error; 999 1000 error = i8042_controller_selftest(); 1001 if (error) 1002 return error; 1003 1004 /* 1005 * Restore original CTR value and disable all ports 1006 */ 1007 1008 i8042_ctr = i8042_initial_ctr; 1009 if (i8042_direct) 1010 i8042_ctr &= ~I8042_CTR_XLATE; 1011 i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS; 1012 i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT); 1013 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 1014 printk(KERN_WARNING "i8042: Can't write CTR to resume, retrying...\n"); 1015 msleep(50); 1016 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 1017 printk(KERN_ERR "i8042: CTR write retry failed\n"); 1018 return -EIO; 1019 } 1020 } 1021 1022 1023 #ifdef CONFIG_X86 1024 if (i8042_dritek) 1025 i8042_dritek_enable(); 1026 #endif 1027 1028 if (i8042_mux_present) { 1029 if (i8042_set_mux_mode(true, NULL) || i8042_enable_mux_ports()) 1030 printk(KERN_WARNING 1031 "i8042: failed to resume active multiplexor, " 1032 "mouse won't work.\n"); 1033 } else if (i8042_ports[I8042_AUX_PORT_NO].serio) 1034 i8042_enable_aux_port(); 1035 1036 if (i8042_ports[I8042_KBD_PORT_NO].serio) 1037 i8042_enable_kbd_port(); 1038 1039 i8042_interrupt(0, NULL); 1040 1041 return 0; 1042 } 1043 1044 static const struct dev_pm_ops i8042_pm_ops = { 1045 .suspend = i8042_pm_reset, 1046 .resume = i8042_pm_restore, 1047 .poweroff = i8042_pm_reset, 1048 .restore = i8042_pm_restore, 1049 }; 1050 1051 #endif /* CONFIG_PM */ 1052 1053 /* 1054 * We need to reset the 8042 back to original mode on system shutdown, 1055 * because otherwise BIOSes will be confused. 1056 */ 1057 1058 static void i8042_shutdown(struct platform_device *dev) 1059 { 1060 i8042_controller_reset(); 1061 } 1062 1063 static int __init i8042_create_kbd_port(void) 1064 { 1065 struct serio *serio; 1066 struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO]; 1067 1068 serio = kzalloc(sizeof(struct serio), GFP_KERNEL); 1069 if (!serio) 1070 return -ENOMEM; 1071 1072 serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL; 1073 serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write; 1074 serio->start = i8042_start; 1075 serio->stop = i8042_stop; 1076 serio->close = i8042_port_close; 1077 serio->port_data = port; 1078 serio->dev.parent = &i8042_platform_device->dev; 1079 strlcpy(serio->name, "i8042 KBD port", sizeof(serio->name)); 1080 strlcpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys)); 1081 1082 port->serio = serio; 1083 port->irq = I8042_KBD_IRQ; 1084 1085 return 0; 1086 } 1087 1088 static int __init i8042_create_aux_port(int idx) 1089 { 1090 struct serio *serio; 1091 int port_no = idx < 0 ? I8042_AUX_PORT_NO : I8042_MUX_PORT_NO + idx; 1092 struct i8042_port *port = &i8042_ports[port_no]; 1093 1094 serio = kzalloc(sizeof(struct serio), GFP_KERNEL); 1095 if (!serio) 1096 return -ENOMEM; 1097 1098 serio->id.type = SERIO_8042; 1099 serio->write = i8042_aux_write; 1100 serio->start = i8042_start; 1101 serio->stop = i8042_stop; 1102 serio->port_data = port; 1103 serio->dev.parent = &i8042_platform_device->dev; 1104 if (idx < 0) { 1105 strlcpy(serio->name, "i8042 AUX port", sizeof(serio->name)); 1106 strlcpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys)); 1107 serio->close = i8042_port_close; 1108 } else { 1109 snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx); 1110 snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1); 1111 } 1112 1113 port->serio = serio; 1114 port->mux = idx; 1115 port->irq = I8042_AUX_IRQ; 1116 1117 return 0; 1118 } 1119 1120 static void __init i8042_free_kbd_port(void) 1121 { 1122 kfree(i8042_ports[I8042_KBD_PORT_NO].serio); 1123 i8042_ports[I8042_KBD_PORT_NO].serio = NULL; 1124 } 1125 1126 static void __init i8042_free_aux_ports(void) 1127 { 1128 int i; 1129 1130 for (i = I8042_AUX_PORT_NO; i < I8042_NUM_PORTS; i++) { 1131 kfree(i8042_ports[i].serio); 1132 i8042_ports[i].serio = NULL; 1133 } 1134 } 1135 1136 static void __init i8042_register_ports(void) 1137 { 1138 int i; 1139 1140 for (i = 0; i < I8042_NUM_PORTS; i++) { 1141 if (i8042_ports[i].serio) { 1142 printk(KERN_INFO "serio: %s at %#lx,%#lx irq %d\n", 1143 i8042_ports[i].serio->name, 1144 (unsigned long) I8042_DATA_REG, 1145 (unsigned long) I8042_COMMAND_REG, 1146 i8042_ports[i].irq); 1147 serio_register_port(i8042_ports[i].serio); 1148 } 1149 } 1150 } 1151 1152 static void __devexit i8042_unregister_ports(void) 1153 { 1154 int i; 1155 1156 for (i = 0; i < I8042_NUM_PORTS; i++) { 1157 if (i8042_ports[i].serio) { 1158 serio_unregister_port(i8042_ports[i].serio); 1159 i8042_ports[i].serio = NULL; 1160 } 1161 } 1162 } 1163 1164 static void i8042_free_irqs(void) 1165 { 1166 if (i8042_aux_irq_registered) 1167 free_irq(I8042_AUX_IRQ, i8042_platform_device); 1168 if (i8042_kbd_irq_registered) 1169 free_irq(I8042_KBD_IRQ, i8042_platform_device); 1170 1171 i8042_aux_irq_registered = i8042_kbd_irq_registered = false; 1172 } 1173 1174 static int __init i8042_setup_aux(void) 1175 { 1176 int (*aux_enable)(void); 1177 int error; 1178 int i; 1179 1180 if (i8042_check_aux()) 1181 return -ENODEV; 1182 1183 if (i8042_nomux || i8042_check_mux()) { 1184 error = i8042_create_aux_port(-1); 1185 if (error) 1186 goto err_free_ports; 1187 aux_enable = i8042_enable_aux_port; 1188 } else { 1189 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { 1190 error = i8042_create_aux_port(i); 1191 if (error) 1192 goto err_free_ports; 1193 } 1194 aux_enable = i8042_enable_mux_ports; 1195 } 1196 1197 error = request_irq(I8042_AUX_IRQ, i8042_interrupt, IRQF_SHARED, 1198 "i8042", i8042_platform_device); 1199 if (error) 1200 goto err_free_ports; 1201 1202 if (aux_enable()) 1203 goto err_free_irq; 1204 1205 i8042_aux_irq_registered = true; 1206 return 0; 1207 1208 err_free_irq: 1209 free_irq(I8042_AUX_IRQ, i8042_platform_device); 1210 err_free_ports: 1211 i8042_free_aux_ports(); 1212 return error; 1213 } 1214 1215 static int __init i8042_setup_kbd(void) 1216 { 1217 int error; 1218 1219 error = i8042_create_kbd_port(); 1220 if (error) 1221 return error; 1222 1223 error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED, 1224 "i8042", i8042_platform_device); 1225 if (error) 1226 goto err_free_port; 1227 1228 error = i8042_enable_kbd_port(); 1229 if (error) 1230 goto err_free_irq; 1231 1232 i8042_kbd_irq_registered = true; 1233 return 0; 1234 1235 err_free_irq: 1236 free_irq(I8042_KBD_IRQ, i8042_platform_device); 1237 err_free_port: 1238 i8042_free_kbd_port(); 1239 return error; 1240 } 1241 1242 static int __init i8042_probe(struct platform_device *dev) 1243 { 1244 int error; 1245 1246 error = i8042_controller_selftest(); 1247 if (error) 1248 return error; 1249 1250 error = i8042_controller_init(); 1251 if (error) 1252 return error; 1253 1254 #ifdef CONFIG_X86 1255 if (i8042_dritek) 1256 i8042_dritek_enable(); 1257 #endif 1258 1259 if (!i8042_noaux) { 1260 error = i8042_setup_aux(); 1261 if (error && error != -ENODEV && error != -EBUSY) 1262 goto out_fail; 1263 } 1264 1265 if (!i8042_nokbd) { 1266 error = i8042_setup_kbd(); 1267 if (error) 1268 goto out_fail; 1269 } 1270 /* 1271 * Ok, everything is ready, let's register all serio ports 1272 */ 1273 i8042_register_ports(); 1274 1275 return 0; 1276 1277 out_fail: 1278 i8042_free_aux_ports(); /* in case KBD failed but AUX not */ 1279 i8042_free_irqs(); 1280 i8042_controller_reset(); 1281 1282 return error; 1283 } 1284 1285 static int __devexit i8042_remove(struct platform_device *dev) 1286 { 1287 i8042_unregister_ports(); 1288 i8042_free_irqs(); 1289 i8042_controller_reset(); 1290 1291 return 0; 1292 } 1293 1294 static struct platform_driver i8042_driver = { 1295 .driver = { 1296 .name = "i8042", 1297 .owner = THIS_MODULE, 1298 #ifdef CONFIG_PM 1299 .pm = &i8042_pm_ops, 1300 #endif 1301 }, 1302 .remove = __devexit_p(i8042_remove), 1303 .shutdown = i8042_shutdown, 1304 }; 1305 1306 static int __init i8042_init(void) 1307 { 1308 int err; 1309 1310 dbg_init(); 1311 1312 err = i8042_platform_init(); 1313 if (err) 1314 return err; 1315 1316 err = i8042_controller_check(); 1317 if (err) 1318 goto err_platform_exit; 1319 1320 i8042_platform_device = platform_device_alloc("i8042", -1); 1321 if (!i8042_platform_device) { 1322 err = -ENOMEM; 1323 goto err_platform_exit; 1324 } 1325 1326 err = platform_device_add(i8042_platform_device); 1327 if (err) 1328 goto err_free_device; 1329 1330 err = platform_driver_probe(&i8042_driver, i8042_probe); 1331 if (err) 1332 goto err_del_device; 1333 1334 panic_blink = i8042_panic_blink; 1335 1336 return 0; 1337 1338 err_del_device: 1339 platform_device_del(i8042_platform_device); 1340 err_free_device: 1341 platform_device_put(i8042_platform_device); 1342 err_platform_exit: 1343 i8042_platform_exit(); 1344 1345 return err; 1346 } 1347 1348 static void __exit i8042_exit(void) 1349 { 1350 platform_driver_unregister(&i8042_driver); 1351 platform_device_unregister(i8042_platform_device); 1352 i8042_platform_exit(); 1353 1354 panic_blink = NULL; 1355 } 1356 1357 module_init(i8042_init); 1358 module_exit(i8042_exit); 1359