1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Azoteq IQS7222A/B/C Capacitive Touch Controller 4 * 5 * Copyright (C) 2022 Jeff LaBundy <jeff@labundy.com> 6 */ 7 8 #include <linux/bits.h> 9 #include <linux/delay.h> 10 #include <linux/device.h> 11 #include <linux/err.h> 12 #include <linux/gpio/consumer.h> 13 #include <linux/i2c.h> 14 #include <linux/input.h> 15 #include <linux/interrupt.h> 16 #include <linux/kernel.h> 17 #include <linux/ktime.h> 18 #include <linux/module.h> 19 #include <linux/of_device.h> 20 #include <linux/property.h> 21 #include <linux/slab.h> 22 #include <asm/unaligned.h> 23 24 #define IQS7222_PROD_NUM 0x00 25 #define IQS7222_PROD_NUM_A 840 26 #define IQS7222_PROD_NUM_B 698 27 #define IQS7222_PROD_NUM_C 863 28 29 #define IQS7222_SYS_STATUS 0x10 30 #define IQS7222_SYS_STATUS_RESET BIT(3) 31 #define IQS7222_SYS_STATUS_ATI_ERROR BIT(1) 32 #define IQS7222_SYS_STATUS_ATI_ACTIVE BIT(0) 33 34 #define IQS7222_CHAN_SETUP_0_REF_MODE_MASK GENMASK(15, 14) 35 #define IQS7222_CHAN_SETUP_0_REF_MODE_FOLLOW BIT(15) 36 #define IQS7222_CHAN_SETUP_0_REF_MODE_REF BIT(14) 37 #define IQS7222_CHAN_SETUP_0_CHAN_EN BIT(8) 38 39 #define IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK GENMASK(2, 0) 40 #define IQS7222_SLDR_SETUP_2_RES_MASK GENMASK(15, 8) 41 #define IQS7222_SLDR_SETUP_2_RES_SHIFT 8 42 #define IQS7222_SLDR_SETUP_2_TOP_SPEED_MASK GENMASK(7, 0) 43 44 #define IQS7222_GPIO_SETUP_0_GPIO_EN BIT(0) 45 46 #define IQS7222_SYS_SETUP 0xD0 47 #define IQS7222_SYS_SETUP_INTF_MODE_MASK GENMASK(7, 6) 48 #define IQS7222_SYS_SETUP_INTF_MODE_TOUCH BIT(7) 49 #define IQS7222_SYS_SETUP_INTF_MODE_EVENT BIT(6) 50 #define IQS7222_SYS_SETUP_PWR_MODE_MASK GENMASK(5, 4) 51 #define IQS7222_SYS_SETUP_PWR_MODE_AUTO IQS7222_SYS_SETUP_PWR_MODE_MASK 52 #define IQS7222_SYS_SETUP_REDO_ATI BIT(2) 53 #define IQS7222_SYS_SETUP_ACK_RESET BIT(0) 54 55 #define IQS7222_EVENT_MASK_ATI BIT(12) 56 #define IQS7222_EVENT_MASK_SLDR BIT(10) 57 #define IQS7222_EVENT_MASK_TOUCH BIT(1) 58 #define IQS7222_EVENT_MASK_PROX BIT(0) 59 60 #define IQS7222_COMMS_HOLD BIT(0) 61 #define IQS7222_COMMS_ERROR 0xEEEE 62 #define IQS7222_COMMS_RETRY_MS 50 63 #define IQS7222_COMMS_TIMEOUT_MS 100 64 #define IQS7222_RESET_TIMEOUT_MS 250 65 #define IQS7222_ATI_TIMEOUT_MS 2000 66 67 #define IQS7222_MAX_COLS_STAT 8 68 #define IQS7222_MAX_COLS_CYCLE 3 69 #define IQS7222_MAX_COLS_GLBL 3 70 #define IQS7222_MAX_COLS_BTN 3 71 #define IQS7222_MAX_COLS_CHAN 6 72 #define IQS7222_MAX_COLS_FILT 2 73 #define IQS7222_MAX_COLS_SLDR 11 74 #define IQS7222_MAX_COLS_GPIO 3 75 #define IQS7222_MAX_COLS_SYS 13 76 77 #define IQS7222_MAX_CHAN 20 78 #define IQS7222_MAX_SLDR 2 79 80 #define IQS7222_NUM_RETRIES 5 81 #define IQS7222_REG_OFFSET 0x100 82 83 enum iqs7222_reg_key_id { 84 IQS7222_REG_KEY_NONE, 85 IQS7222_REG_KEY_PROX, 86 IQS7222_REG_KEY_TOUCH, 87 IQS7222_REG_KEY_DEBOUNCE, 88 IQS7222_REG_KEY_TAP, 89 IQS7222_REG_KEY_TAP_LEGACY, 90 IQS7222_REG_KEY_AXIAL, 91 IQS7222_REG_KEY_AXIAL_LEGACY, 92 IQS7222_REG_KEY_WHEEL, 93 IQS7222_REG_KEY_NO_WHEEL, 94 IQS7222_REG_KEY_RESERVED 95 }; 96 97 enum iqs7222_reg_grp_id { 98 IQS7222_REG_GRP_STAT, 99 IQS7222_REG_GRP_FILT, 100 IQS7222_REG_GRP_CYCLE, 101 IQS7222_REG_GRP_GLBL, 102 IQS7222_REG_GRP_BTN, 103 IQS7222_REG_GRP_CHAN, 104 IQS7222_REG_GRP_SLDR, 105 IQS7222_REG_GRP_GPIO, 106 IQS7222_REG_GRP_SYS, 107 IQS7222_NUM_REG_GRPS 108 }; 109 110 static const char * const iqs7222_reg_grp_names[IQS7222_NUM_REG_GRPS] = { 111 [IQS7222_REG_GRP_CYCLE] = "cycle", 112 [IQS7222_REG_GRP_CHAN] = "channel", 113 [IQS7222_REG_GRP_SLDR] = "slider", 114 [IQS7222_REG_GRP_GPIO] = "gpio", 115 }; 116 117 static const unsigned int iqs7222_max_cols[IQS7222_NUM_REG_GRPS] = { 118 [IQS7222_REG_GRP_STAT] = IQS7222_MAX_COLS_STAT, 119 [IQS7222_REG_GRP_CYCLE] = IQS7222_MAX_COLS_CYCLE, 120 [IQS7222_REG_GRP_GLBL] = IQS7222_MAX_COLS_GLBL, 121 [IQS7222_REG_GRP_BTN] = IQS7222_MAX_COLS_BTN, 122 [IQS7222_REG_GRP_CHAN] = IQS7222_MAX_COLS_CHAN, 123 [IQS7222_REG_GRP_FILT] = IQS7222_MAX_COLS_FILT, 124 [IQS7222_REG_GRP_SLDR] = IQS7222_MAX_COLS_SLDR, 125 [IQS7222_REG_GRP_GPIO] = IQS7222_MAX_COLS_GPIO, 126 [IQS7222_REG_GRP_SYS] = IQS7222_MAX_COLS_SYS, 127 }; 128 129 static const unsigned int iqs7222_gpio_links[] = { 2, 5, 6, }; 130 131 struct iqs7222_event_desc { 132 const char *name; 133 u16 mask; 134 u16 val; 135 u16 enable; 136 enum iqs7222_reg_key_id reg_key; 137 }; 138 139 static const struct iqs7222_event_desc iqs7222_kp_events[] = { 140 { 141 .name = "event-prox", 142 .enable = IQS7222_EVENT_MASK_PROX, 143 .reg_key = IQS7222_REG_KEY_PROX, 144 }, 145 { 146 .name = "event-touch", 147 .enable = IQS7222_EVENT_MASK_TOUCH, 148 .reg_key = IQS7222_REG_KEY_TOUCH, 149 }, 150 }; 151 152 static const struct iqs7222_event_desc iqs7222_sl_events[] = { 153 { .name = "event-press", }, 154 { 155 .name = "event-tap", 156 .mask = BIT(0), 157 .val = BIT(0), 158 .enable = BIT(0), 159 .reg_key = IQS7222_REG_KEY_TAP, 160 }, 161 { 162 .name = "event-swipe-pos", 163 .mask = BIT(5) | BIT(1), 164 .val = BIT(1), 165 .enable = BIT(1), 166 .reg_key = IQS7222_REG_KEY_AXIAL, 167 }, 168 { 169 .name = "event-swipe-neg", 170 .mask = BIT(5) | BIT(1), 171 .val = BIT(5) | BIT(1), 172 .enable = BIT(1), 173 .reg_key = IQS7222_REG_KEY_AXIAL, 174 }, 175 { 176 .name = "event-flick-pos", 177 .mask = BIT(5) | BIT(2), 178 .val = BIT(2), 179 .enable = BIT(2), 180 .reg_key = IQS7222_REG_KEY_AXIAL, 181 }, 182 { 183 .name = "event-flick-neg", 184 .mask = BIT(5) | BIT(2), 185 .val = BIT(5) | BIT(2), 186 .enable = BIT(2), 187 .reg_key = IQS7222_REG_KEY_AXIAL, 188 }, 189 }; 190 191 struct iqs7222_reg_grp_desc { 192 u16 base; 193 int num_row; 194 int num_col; 195 }; 196 197 struct iqs7222_dev_desc { 198 u16 prod_num; 199 u16 fw_major; 200 u16 fw_minor; 201 u16 sldr_res; 202 u16 touch_link; 203 u16 wheel_enable; 204 int allow_offset; 205 int event_offset; 206 int comms_offset; 207 bool legacy_gesture; 208 struct iqs7222_reg_grp_desc reg_grps[IQS7222_NUM_REG_GRPS]; 209 }; 210 211 static const struct iqs7222_dev_desc iqs7222_devs[] = { 212 { 213 .prod_num = IQS7222_PROD_NUM_A, 214 .fw_major = 1, 215 .fw_minor = 13, 216 .sldr_res = U8_MAX * 16, 217 .touch_link = 1768, 218 .allow_offset = 9, 219 .event_offset = 10, 220 .comms_offset = 12, 221 .reg_grps = { 222 [IQS7222_REG_GRP_STAT] = { 223 .base = IQS7222_SYS_STATUS, 224 .num_row = 1, 225 .num_col = 8, 226 }, 227 [IQS7222_REG_GRP_CYCLE] = { 228 .base = 0x8000, 229 .num_row = 7, 230 .num_col = 3, 231 }, 232 [IQS7222_REG_GRP_GLBL] = { 233 .base = 0x8700, 234 .num_row = 1, 235 .num_col = 3, 236 }, 237 [IQS7222_REG_GRP_BTN] = { 238 .base = 0x9000, 239 .num_row = 12, 240 .num_col = 3, 241 }, 242 [IQS7222_REG_GRP_CHAN] = { 243 .base = 0xA000, 244 .num_row = 12, 245 .num_col = 6, 246 }, 247 [IQS7222_REG_GRP_FILT] = { 248 .base = 0xAC00, 249 .num_row = 1, 250 .num_col = 2, 251 }, 252 [IQS7222_REG_GRP_SLDR] = { 253 .base = 0xB000, 254 .num_row = 2, 255 .num_col = 11, 256 }, 257 [IQS7222_REG_GRP_GPIO] = { 258 .base = 0xC000, 259 .num_row = 1, 260 .num_col = 3, 261 }, 262 [IQS7222_REG_GRP_SYS] = { 263 .base = IQS7222_SYS_SETUP, 264 .num_row = 1, 265 .num_col = 13, 266 }, 267 }, 268 }, 269 { 270 .prod_num = IQS7222_PROD_NUM_A, 271 .fw_major = 1, 272 .fw_minor = 12, 273 .sldr_res = U8_MAX * 16, 274 .touch_link = 1768, 275 .allow_offset = 9, 276 .event_offset = 10, 277 .comms_offset = 12, 278 .legacy_gesture = true, 279 .reg_grps = { 280 [IQS7222_REG_GRP_STAT] = { 281 .base = IQS7222_SYS_STATUS, 282 .num_row = 1, 283 .num_col = 8, 284 }, 285 [IQS7222_REG_GRP_CYCLE] = { 286 .base = 0x8000, 287 .num_row = 7, 288 .num_col = 3, 289 }, 290 [IQS7222_REG_GRP_GLBL] = { 291 .base = 0x8700, 292 .num_row = 1, 293 .num_col = 3, 294 }, 295 [IQS7222_REG_GRP_BTN] = { 296 .base = 0x9000, 297 .num_row = 12, 298 .num_col = 3, 299 }, 300 [IQS7222_REG_GRP_CHAN] = { 301 .base = 0xA000, 302 .num_row = 12, 303 .num_col = 6, 304 }, 305 [IQS7222_REG_GRP_FILT] = { 306 .base = 0xAC00, 307 .num_row = 1, 308 .num_col = 2, 309 }, 310 [IQS7222_REG_GRP_SLDR] = { 311 .base = 0xB000, 312 .num_row = 2, 313 .num_col = 11, 314 }, 315 [IQS7222_REG_GRP_GPIO] = { 316 .base = 0xC000, 317 .num_row = 1, 318 .num_col = 3, 319 }, 320 [IQS7222_REG_GRP_SYS] = { 321 .base = IQS7222_SYS_SETUP, 322 .num_row = 1, 323 .num_col = 13, 324 }, 325 }, 326 }, 327 { 328 .prod_num = IQS7222_PROD_NUM_B, 329 .fw_major = 1, 330 .fw_minor = 43, 331 .event_offset = 10, 332 .comms_offset = 11, 333 .reg_grps = { 334 [IQS7222_REG_GRP_STAT] = { 335 .base = IQS7222_SYS_STATUS, 336 .num_row = 1, 337 .num_col = 6, 338 }, 339 [IQS7222_REG_GRP_CYCLE] = { 340 .base = 0x8000, 341 .num_row = 10, 342 .num_col = 2, 343 }, 344 [IQS7222_REG_GRP_GLBL] = { 345 .base = 0x8A00, 346 .num_row = 1, 347 .num_col = 3, 348 }, 349 [IQS7222_REG_GRP_BTN] = { 350 .base = 0x9000, 351 .num_row = 20, 352 .num_col = 2, 353 }, 354 [IQS7222_REG_GRP_CHAN] = { 355 .base = 0xB000, 356 .num_row = 20, 357 .num_col = 4, 358 }, 359 [IQS7222_REG_GRP_FILT] = { 360 .base = 0xC400, 361 .num_row = 1, 362 .num_col = 2, 363 }, 364 [IQS7222_REG_GRP_SYS] = { 365 .base = IQS7222_SYS_SETUP, 366 .num_row = 1, 367 .num_col = 13, 368 }, 369 }, 370 }, 371 { 372 .prod_num = IQS7222_PROD_NUM_B, 373 .fw_major = 1, 374 .fw_minor = 27, 375 .reg_grps = { 376 [IQS7222_REG_GRP_STAT] = { 377 .base = IQS7222_SYS_STATUS, 378 .num_row = 1, 379 .num_col = 6, 380 }, 381 [IQS7222_REG_GRP_CYCLE] = { 382 .base = 0x8000, 383 .num_row = 10, 384 .num_col = 2, 385 }, 386 [IQS7222_REG_GRP_GLBL] = { 387 .base = 0x8A00, 388 .num_row = 1, 389 .num_col = 3, 390 }, 391 [IQS7222_REG_GRP_BTN] = { 392 .base = 0x9000, 393 .num_row = 20, 394 .num_col = 2, 395 }, 396 [IQS7222_REG_GRP_CHAN] = { 397 .base = 0xB000, 398 .num_row = 20, 399 .num_col = 4, 400 }, 401 [IQS7222_REG_GRP_FILT] = { 402 .base = 0xC400, 403 .num_row = 1, 404 .num_col = 2, 405 }, 406 [IQS7222_REG_GRP_SYS] = { 407 .base = IQS7222_SYS_SETUP, 408 .num_row = 1, 409 .num_col = 10, 410 }, 411 }, 412 }, 413 { 414 .prod_num = IQS7222_PROD_NUM_C, 415 .fw_major = 2, 416 .fw_minor = 6, 417 .sldr_res = U16_MAX, 418 .touch_link = 1686, 419 .wheel_enable = BIT(3), 420 .event_offset = 9, 421 .comms_offset = 10, 422 .reg_grps = { 423 [IQS7222_REG_GRP_STAT] = { 424 .base = IQS7222_SYS_STATUS, 425 .num_row = 1, 426 .num_col = 6, 427 }, 428 [IQS7222_REG_GRP_CYCLE] = { 429 .base = 0x8000, 430 .num_row = 5, 431 .num_col = 3, 432 }, 433 [IQS7222_REG_GRP_GLBL] = { 434 .base = 0x8500, 435 .num_row = 1, 436 .num_col = 3, 437 }, 438 [IQS7222_REG_GRP_BTN] = { 439 .base = 0x9000, 440 .num_row = 10, 441 .num_col = 3, 442 }, 443 [IQS7222_REG_GRP_CHAN] = { 444 .base = 0xA000, 445 .num_row = 10, 446 .num_col = 6, 447 }, 448 [IQS7222_REG_GRP_FILT] = { 449 .base = 0xAA00, 450 .num_row = 1, 451 .num_col = 2, 452 }, 453 [IQS7222_REG_GRP_SLDR] = { 454 .base = 0xB000, 455 .num_row = 2, 456 .num_col = 10, 457 }, 458 [IQS7222_REG_GRP_GPIO] = { 459 .base = 0xC000, 460 .num_row = 3, 461 .num_col = 3, 462 }, 463 [IQS7222_REG_GRP_SYS] = { 464 .base = IQS7222_SYS_SETUP, 465 .num_row = 1, 466 .num_col = 12, 467 }, 468 }, 469 }, 470 { 471 .prod_num = IQS7222_PROD_NUM_C, 472 .fw_major = 1, 473 .fw_minor = 13, 474 .sldr_res = U16_MAX, 475 .touch_link = 1674, 476 .wheel_enable = BIT(3), 477 .event_offset = 9, 478 .comms_offset = 10, 479 .reg_grps = { 480 [IQS7222_REG_GRP_STAT] = { 481 .base = IQS7222_SYS_STATUS, 482 .num_row = 1, 483 .num_col = 6, 484 }, 485 [IQS7222_REG_GRP_CYCLE] = { 486 .base = 0x8000, 487 .num_row = 5, 488 .num_col = 3, 489 }, 490 [IQS7222_REG_GRP_GLBL] = { 491 .base = 0x8500, 492 .num_row = 1, 493 .num_col = 3, 494 }, 495 [IQS7222_REG_GRP_BTN] = { 496 .base = 0x9000, 497 .num_row = 10, 498 .num_col = 3, 499 }, 500 [IQS7222_REG_GRP_CHAN] = { 501 .base = 0xA000, 502 .num_row = 10, 503 .num_col = 6, 504 }, 505 [IQS7222_REG_GRP_FILT] = { 506 .base = 0xAA00, 507 .num_row = 1, 508 .num_col = 2, 509 }, 510 [IQS7222_REG_GRP_SLDR] = { 511 .base = 0xB000, 512 .num_row = 2, 513 .num_col = 10, 514 }, 515 [IQS7222_REG_GRP_GPIO] = { 516 .base = 0xC000, 517 .num_row = 1, 518 .num_col = 3, 519 }, 520 [IQS7222_REG_GRP_SYS] = { 521 .base = IQS7222_SYS_SETUP, 522 .num_row = 1, 523 .num_col = 11, 524 }, 525 }, 526 }, 527 }; 528 529 struct iqs7222_prop_desc { 530 const char *name; 531 enum iqs7222_reg_grp_id reg_grp; 532 enum iqs7222_reg_key_id reg_key; 533 int reg_offset; 534 int reg_shift; 535 int reg_width; 536 int val_pitch; 537 int val_min; 538 int val_max; 539 bool invert; 540 const char *label; 541 }; 542 543 static const struct iqs7222_prop_desc iqs7222_props[] = { 544 { 545 .name = "azoteq,conv-period", 546 .reg_grp = IQS7222_REG_GRP_CYCLE, 547 .reg_offset = 0, 548 .reg_shift = 8, 549 .reg_width = 8, 550 .label = "conversion period", 551 }, 552 { 553 .name = "azoteq,conv-frac", 554 .reg_grp = IQS7222_REG_GRP_CYCLE, 555 .reg_offset = 0, 556 .reg_shift = 0, 557 .reg_width = 8, 558 .label = "conversion frequency fractional divider", 559 }, 560 { 561 .name = "azoteq,rx-float-inactive", 562 .reg_grp = IQS7222_REG_GRP_CYCLE, 563 .reg_offset = 1, 564 .reg_shift = 6, 565 .reg_width = 1, 566 .invert = true, 567 }, 568 { 569 .name = "azoteq,dead-time-enable", 570 .reg_grp = IQS7222_REG_GRP_CYCLE, 571 .reg_offset = 1, 572 .reg_shift = 5, 573 .reg_width = 1, 574 }, 575 { 576 .name = "azoteq,tx-freq-fosc", 577 .reg_grp = IQS7222_REG_GRP_CYCLE, 578 .reg_offset = 1, 579 .reg_shift = 4, 580 .reg_width = 1, 581 }, 582 { 583 .name = "azoteq,vbias-enable", 584 .reg_grp = IQS7222_REG_GRP_CYCLE, 585 .reg_offset = 1, 586 .reg_shift = 3, 587 .reg_width = 1, 588 }, 589 { 590 .name = "azoteq,sense-mode", 591 .reg_grp = IQS7222_REG_GRP_CYCLE, 592 .reg_offset = 1, 593 .reg_shift = 0, 594 .reg_width = 3, 595 .val_max = 3, 596 .label = "sensing mode", 597 }, 598 { 599 .name = "azoteq,iref-enable", 600 .reg_grp = IQS7222_REG_GRP_CYCLE, 601 .reg_offset = 2, 602 .reg_shift = 10, 603 .reg_width = 1, 604 }, 605 { 606 .name = "azoteq,iref-level", 607 .reg_grp = IQS7222_REG_GRP_CYCLE, 608 .reg_offset = 2, 609 .reg_shift = 4, 610 .reg_width = 4, 611 .label = "current reference level", 612 }, 613 { 614 .name = "azoteq,iref-trim", 615 .reg_grp = IQS7222_REG_GRP_CYCLE, 616 .reg_offset = 2, 617 .reg_shift = 0, 618 .reg_width = 4, 619 .label = "current reference trim", 620 }, 621 { 622 .name = "azoteq,max-counts", 623 .reg_grp = IQS7222_REG_GRP_GLBL, 624 .reg_offset = 0, 625 .reg_shift = 13, 626 .reg_width = 2, 627 .label = "maximum counts", 628 }, 629 { 630 .name = "azoteq,auto-mode", 631 .reg_grp = IQS7222_REG_GRP_GLBL, 632 .reg_offset = 0, 633 .reg_shift = 2, 634 .reg_width = 2, 635 .label = "number of conversions", 636 }, 637 { 638 .name = "azoteq,ati-frac-div-fine", 639 .reg_grp = IQS7222_REG_GRP_GLBL, 640 .reg_offset = 1, 641 .reg_shift = 9, 642 .reg_width = 5, 643 .label = "ATI fine fractional divider", 644 }, 645 { 646 .name = "azoteq,ati-frac-div-coarse", 647 .reg_grp = IQS7222_REG_GRP_GLBL, 648 .reg_offset = 1, 649 .reg_shift = 0, 650 .reg_width = 5, 651 .label = "ATI coarse fractional divider", 652 }, 653 { 654 .name = "azoteq,ati-comp-select", 655 .reg_grp = IQS7222_REG_GRP_GLBL, 656 .reg_offset = 2, 657 .reg_shift = 0, 658 .reg_width = 10, 659 .label = "ATI compensation selection", 660 }, 661 { 662 .name = "azoteq,ati-band", 663 .reg_grp = IQS7222_REG_GRP_CHAN, 664 .reg_offset = 0, 665 .reg_shift = 12, 666 .reg_width = 2, 667 .label = "ATI band", 668 }, 669 { 670 .name = "azoteq,global-halt", 671 .reg_grp = IQS7222_REG_GRP_CHAN, 672 .reg_offset = 0, 673 .reg_shift = 11, 674 .reg_width = 1, 675 }, 676 { 677 .name = "azoteq,invert-enable", 678 .reg_grp = IQS7222_REG_GRP_CHAN, 679 .reg_offset = 0, 680 .reg_shift = 10, 681 .reg_width = 1, 682 }, 683 { 684 .name = "azoteq,dual-direction", 685 .reg_grp = IQS7222_REG_GRP_CHAN, 686 .reg_offset = 0, 687 .reg_shift = 9, 688 .reg_width = 1, 689 }, 690 { 691 .name = "azoteq,samp-cap-double", 692 .reg_grp = IQS7222_REG_GRP_CHAN, 693 .reg_offset = 0, 694 .reg_shift = 3, 695 .reg_width = 1, 696 }, 697 { 698 .name = "azoteq,vref-half", 699 .reg_grp = IQS7222_REG_GRP_CHAN, 700 .reg_offset = 0, 701 .reg_shift = 2, 702 .reg_width = 1, 703 }, 704 { 705 .name = "azoteq,proj-bias", 706 .reg_grp = IQS7222_REG_GRP_CHAN, 707 .reg_offset = 0, 708 .reg_shift = 0, 709 .reg_width = 2, 710 .label = "projected bias current", 711 }, 712 { 713 .name = "azoteq,ati-target", 714 .reg_grp = IQS7222_REG_GRP_CHAN, 715 .reg_offset = 1, 716 .reg_shift = 8, 717 .reg_width = 8, 718 .val_pitch = 8, 719 .label = "ATI target", 720 }, 721 { 722 .name = "azoteq,ati-base", 723 .reg_grp = IQS7222_REG_GRP_CHAN, 724 .reg_offset = 1, 725 .reg_shift = 3, 726 .reg_width = 5, 727 .val_pitch = 16, 728 .label = "ATI base", 729 }, 730 { 731 .name = "azoteq,ati-mode", 732 .reg_grp = IQS7222_REG_GRP_CHAN, 733 .reg_offset = 1, 734 .reg_shift = 0, 735 .reg_width = 3, 736 .val_max = 5, 737 .label = "ATI mode", 738 }, 739 { 740 .name = "azoteq,ati-frac-div-fine", 741 .reg_grp = IQS7222_REG_GRP_CHAN, 742 .reg_offset = 2, 743 .reg_shift = 9, 744 .reg_width = 5, 745 .label = "ATI fine fractional divider", 746 }, 747 { 748 .name = "azoteq,ati-frac-mult-coarse", 749 .reg_grp = IQS7222_REG_GRP_CHAN, 750 .reg_offset = 2, 751 .reg_shift = 5, 752 .reg_width = 4, 753 .label = "ATI coarse fractional multiplier", 754 }, 755 { 756 .name = "azoteq,ati-frac-div-coarse", 757 .reg_grp = IQS7222_REG_GRP_CHAN, 758 .reg_offset = 2, 759 .reg_shift = 0, 760 .reg_width = 5, 761 .label = "ATI coarse fractional divider", 762 }, 763 { 764 .name = "azoteq,ati-comp-div", 765 .reg_grp = IQS7222_REG_GRP_CHAN, 766 .reg_offset = 3, 767 .reg_shift = 11, 768 .reg_width = 5, 769 .label = "ATI compensation divider", 770 }, 771 { 772 .name = "azoteq,ati-comp-select", 773 .reg_grp = IQS7222_REG_GRP_CHAN, 774 .reg_offset = 3, 775 .reg_shift = 0, 776 .reg_width = 10, 777 .label = "ATI compensation selection", 778 }, 779 { 780 .name = "azoteq,debounce-exit", 781 .reg_grp = IQS7222_REG_GRP_BTN, 782 .reg_key = IQS7222_REG_KEY_DEBOUNCE, 783 .reg_offset = 0, 784 .reg_shift = 12, 785 .reg_width = 4, 786 .label = "debounce exit factor", 787 }, 788 { 789 .name = "azoteq,debounce-enter", 790 .reg_grp = IQS7222_REG_GRP_BTN, 791 .reg_key = IQS7222_REG_KEY_DEBOUNCE, 792 .reg_offset = 0, 793 .reg_shift = 8, 794 .reg_width = 4, 795 .label = "debounce entrance factor", 796 }, 797 { 798 .name = "azoteq,thresh", 799 .reg_grp = IQS7222_REG_GRP_BTN, 800 .reg_key = IQS7222_REG_KEY_PROX, 801 .reg_offset = 0, 802 .reg_shift = 0, 803 .reg_width = 8, 804 .val_max = 127, 805 .label = "threshold", 806 }, 807 { 808 .name = "azoteq,thresh", 809 .reg_grp = IQS7222_REG_GRP_BTN, 810 .reg_key = IQS7222_REG_KEY_TOUCH, 811 .reg_offset = 1, 812 .reg_shift = 0, 813 .reg_width = 8, 814 .label = "threshold", 815 }, 816 { 817 .name = "azoteq,hyst", 818 .reg_grp = IQS7222_REG_GRP_BTN, 819 .reg_key = IQS7222_REG_KEY_TOUCH, 820 .reg_offset = 1, 821 .reg_shift = 8, 822 .reg_width = 8, 823 .label = "hysteresis", 824 }, 825 { 826 .name = "azoteq,lta-beta-lp", 827 .reg_grp = IQS7222_REG_GRP_FILT, 828 .reg_offset = 0, 829 .reg_shift = 12, 830 .reg_width = 4, 831 .label = "low-power mode long-term average beta", 832 }, 833 { 834 .name = "azoteq,lta-beta-np", 835 .reg_grp = IQS7222_REG_GRP_FILT, 836 .reg_offset = 0, 837 .reg_shift = 8, 838 .reg_width = 4, 839 .label = "normal-power mode long-term average beta", 840 }, 841 { 842 .name = "azoteq,counts-beta-lp", 843 .reg_grp = IQS7222_REG_GRP_FILT, 844 .reg_offset = 0, 845 .reg_shift = 4, 846 .reg_width = 4, 847 .label = "low-power mode counts beta", 848 }, 849 { 850 .name = "azoteq,counts-beta-np", 851 .reg_grp = IQS7222_REG_GRP_FILT, 852 .reg_offset = 0, 853 .reg_shift = 0, 854 .reg_width = 4, 855 .label = "normal-power mode counts beta", 856 }, 857 { 858 .name = "azoteq,lta-fast-beta-lp", 859 .reg_grp = IQS7222_REG_GRP_FILT, 860 .reg_offset = 1, 861 .reg_shift = 4, 862 .reg_width = 4, 863 .label = "low-power mode long-term average fast beta", 864 }, 865 { 866 .name = "azoteq,lta-fast-beta-np", 867 .reg_grp = IQS7222_REG_GRP_FILT, 868 .reg_offset = 1, 869 .reg_shift = 0, 870 .reg_width = 4, 871 .label = "normal-power mode long-term average fast beta", 872 }, 873 { 874 .name = "azoteq,lower-cal", 875 .reg_grp = IQS7222_REG_GRP_SLDR, 876 .reg_offset = 0, 877 .reg_shift = 8, 878 .reg_width = 8, 879 .label = "lower calibration", 880 }, 881 { 882 .name = "azoteq,static-beta", 883 .reg_grp = IQS7222_REG_GRP_SLDR, 884 .reg_key = IQS7222_REG_KEY_NO_WHEEL, 885 .reg_offset = 0, 886 .reg_shift = 6, 887 .reg_width = 1, 888 }, 889 { 890 .name = "azoteq,bottom-beta", 891 .reg_grp = IQS7222_REG_GRP_SLDR, 892 .reg_key = IQS7222_REG_KEY_NO_WHEEL, 893 .reg_offset = 0, 894 .reg_shift = 3, 895 .reg_width = 3, 896 .label = "bottom beta", 897 }, 898 { 899 .name = "azoteq,static-beta", 900 .reg_grp = IQS7222_REG_GRP_SLDR, 901 .reg_key = IQS7222_REG_KEY_WHEEL, 902 .reg_offset = 0, 903 .reg_shift = 7, 904 .reg_width = 1, 905 }, 906 { 907 .name = "azoteq,bottom-beta", 908 .reg_grp = IQS7222_REG_GRP_SLDR, 909 .reg_key = IQS7222_REG_KEY_WHEEL, 910 .reg_offset = 0, 911 .reg_shift = 4, 912 .reg_width = 3, 913 .label = "bottom beta", 914 }, 915 { 916 .name = "azoteq,bottom-speed", 917 .reg_grp = IQS7222_REG_GRP_SLDR, 918 .reg_offset = 1, 919 .reg_shift = 8, 920 .reg_width = 8, 921 .label = "bottom speed", 922 }, 923 { 924 .name = "azoteq,upper-cal", 925 .reg_grp = IQS7222_REG_GRP_SLDR, 926 .reg_offset = 1, 927 .reg_shift = 0, 928 .reg_width = 8, 929 .label = "upper calibration", 930 }, 931 { 932 .name = "azoteq,gesture-max-ms", 933 .reg_grp = IQS7222_REG_GRP_SLDR, 934 .reg_key = IQS7222_REG_KEY_TAP, 935 .reg_offset = 9, 936 .reg_shift = 8, 937 .reg_width = 8, 938 .val_pitch = 16, 939 .label = "maximum gesture time", 940 }, 941 { 942 .name = "azoteq,gesture-max-ms", 943 .reg_grp = IQS7222_REG_GRP_SLDR, 944 .reg_key = IQS7222_REG_KEY_TAP_LEGACY, 945 .reg_offset = 9, 946 .reg_shift = 8, 947 .reg_width = 8, 948 .val_pitch = 4, 949 .label = "maximum gesture time", 950 }, 951 { 952 .name = "azoteq,gesture-min-ms", 953 .reg_grp = IQS7222_REG_GRP_SLDR, 954 .reg_key = IQS7222_REG_KEY_TAP, 955 .reg_offset = 9, 956 .reg_shift = 3, 957 .reg_width = 5, 958 .val_pitch = 16, 959 .label = "minimum gesture time", 960 }, 961 { 962 .name = "azoteq,gesture-min-ms", 963 .reg_grp = IQS7222_REG_GRP_SLDR, 964 .reg_key = IQS7222_REG_KEY_TAP_LEGACY, 965 .reg_offset = 9, 966 .reg_shift = 3, 967 .reg_width = 5, 968 .val_pitch = 4, 969 .label = "minimum gesture time", 970 }, 971 { 972 .name = "azoteq,gesture-dist", 973 .reg_grp = IQS7222_REG_GRP_SLDR, 974 .reg_key = IQS7222_REG_KEY_AXIAL, 975 .reg_offset = 10, 976 .reg_shift = 8, 977 .reg_width = 8, 978 .val_pitch = 16, 979 .label = "gesture distance", 980 }, 981 { 982 .name = "azoteq,gesture-dist", 983 .reg_grp = IQS7222_REG_GRP_SLDR, 984 .reg_key = IQS7222_REG_KEY_AXIAL_LEGACY, 985 .reg_offset = 10, 986 .reg_shift = 8, 987 .reg_width = 8, 988 .val_pitch = 16, 989 .label = "gesture distance", 990 }, 991 { 992 .name = "azoteq,gesture-max-ms", 993 .reg_grp = IQS7222_REG_GRP_SLDR, 994 .reg_key = IQS7222_REG_KEY_AXIAL, 995 .reg_offset = 10, 996 .reg_shift = 0, 997 .reg_width = 8, 998 .val_pitch = 16, 999 .label = "maximum gesture time", 1000 }, 1001 { 1002 .name = "azoteq,gesture-max-ms", 1003 .reg_grp = IQS7222_REG_GRP_SLDR, 1004 .reg_key = IQS7222_REG_KEY_AXIAL_LEGACY, 1005 .reg_offset = 10, 1006 .reg_shift = 0, 1007 .reg_width = 8, 1008 .val_pitch = 4, 1009 .label = "maximum gesture time", 1010 }, 1011 { 1012 .name = "drive-open-drain", 1013 .reg_grp = IQS7222_REG_GRP_GPIO, 1014 .reg_offset = 0, 1015 .reg_shift = 1, 1016 .reg_width = 1, 1017 }, 1018 { 1019 .name = "azoteq,timeout-ati-ms", 1020 .reg_grp = IQS7222_REG_GRP_SYS, 1021 .reg_offset = 1, 1022 .reg_shift = 0, 1023 .reg_width = 16, 1024 .val_pitch = 500, 1025 .label = "ATI error timeout", 1026 }, 1027 { 1028 .name = "azoteq,rate-ati-ms", 1029 .reg_grp = IQS7222_REG_GRP_SYS, 1030 .reg_offset = 2, 1031 .reg_shift = 0, 1032 .reg_width = 16, 1033 .label = "ATI report rate", 1034 }, 1035 { 1036 .name = "azoteq,timeout-np-ms", 1037 .reg_grp = IQS7222_REG_GRP_SYS, 1038 .reg_offset = 3, 1039 .reg_shift = 0, 1040 .reg_width = 16, 1041 .label = "normal-power mode timeout", 1042 }, 1043 { 1044 .name = "azoteq,rate-np-ms", 1045 .reg_grp = IQS7222_REG_GRP_SYS, 1046 .reg_offset = 4, 1047 .reg_shift = 0, 1048 .reg_width = 16, 1049 .val_max = 3000, 1050 .label = "normal-power mode report rate", 1051 }, 1052 { 1053 .name = "azoteq,timeout-lp-ms", 1054 .reg_grp = IQS7222_REG_GRP_SYS, 1055 .reg_offset = 5, 1056 .reg_shift = 0, 1057 .reg_width = 16, 1058 .label = "low-power mode timeout", 1059 }, 1060 { 1061 .name = "azoteq,rate-lp-ms", 1062 .reg_grp = IQS7222_REG_GRP_SYS, 1063 .reg_offset = 6, 1064 .reg_shift = 0, 1065 .reg_width = 16, 1066 .val_max = 3000, 1067 .label = "low-power mode report rate", 1068 }, 1069 { 1070 .name = "azoteq,timeout-ulp-ms", 1071 .reg_grp = IQS7222_REG_GRP_SYS, 1072 .reg_offset = 7, 1073 .reg_shift = 0, 1074 .reg_width = 16, 1075 .label = "ultra-low-power mode timeout", 1076 }, 1077 { 1078 .name = "azoteq,rate-ulp-ms", 1079 .reg_grp = IQS7222_REG_GRP_SYS, 1080 .reg_offset = 8, 1081 .reg_shift = 0, 1082 .reg_width = 16, 1083 .val_max = 3000, 1084 .label = "ultra-low-power mode report rate", 1085 }, 1086 }; 1087 1088 struct iqs7222_private { 1089 const struct iqs7222_dev_desc *dev_desc; 1090 struct gpio_desc *reset_gpio; 1091 struct gpio_desc *irq_gpio; 1092 struct i2c_client *client; 1093 struct input_dev *keypad; 1094 unsigned int kp_type[IQS7222_MAX_CHAN][ARRAY_SIZE(iqs7222_kp_events)]; 1095 unsigned int kp_code[IQS7222_MAX_CHAN][ARRAY_SIZE(iqs7222_kp_events)]; 1096 unsigned int sl_code[IQS7222_MAX_SLDR][ARRAY_SIZE(iqs7222_sl_events)]; 1097 unsigned int sl_axis[IQS7222_MAX_SLDR]; 1098 u16 cycle_setup[IQS7222_MAX_CHAN / 2][IQS7222_MAX_COLS_CYCLE]; 1099 u16 glbl_setup[IQS7222_MAX_COLS_GLBL]; 1100 u16 btn_setup[IQS7222_MAX_CHAN][IQS7222_MAX_COLS_BTN]; 1101 u16 chan_setup[IQS7222_MAX_CHAN][IQS7222_MAX_COLS_CHAN]; 1102 u16 filt_setup[IQS7222_MAX_COLS_FILT]; 1103 u16 sldr_setup[IQS7222_MAX_SLDR][IQS7222_MAX_COLS_SLDR]; 1104 u16 gpio_setup[ARRAY_SIZE(iqs7222_gpio_links)][IQS7222_MAX_COLS_GPIO]; 1105 u16 sys_setup[IQS7222_MAX_COLS_SYS]; 1106 }; 1107 1108 static u16 *iqs7222_setup(struct iqs7222_private *iqs7222, 1109 enum iqs7222_reg_grp_id reg_grp, int row) 1110 { 1111 switch (reg_grp) { 1112 case IQS7222_REG_GRP_CYCLE: 1113 return iqs7222->cycle_setup[row]; 1114 1115 case IQS7222_REG_GRP_GLBL: 1116 return iqs7222->glbl_setup; 1117 1118 case IQS7222_REG_GRP_BTN: 1119 return iqs7222->btn_setup[row]; 1120 1121 case IQS7222_REG_GRP_CHAN: 1122 return iqs7222->chan_setup[row]; 1123 1124 case IQS7222_REG_GRP_FILT: 1125 return iqs7222->filt_setup; 1126 1127 case IQS7222_REG_GRP_SLDR: 1128 return iqs7222->sldr_setup[row]; 1129 1130 case IQS7222_REG_GRP_GPIO: 1131 return iqs7222->gpio_setup[row]; 1132 1133 case IQS7222_REG_GRP_SYS: 1134 return iqs7222->sys_setup; 1135 1136 default: 1137 return NULL; 1138 } 1139 } 1140 1141 static int iqs7222_irq_poll(struct iqs7222_private *iqs7222, u16 timeout_ms) 1142 { 1143 ktime_t irq_timeout = ktime_add_ms(ktime_get(), timeout_ms); 1144 int ret; 1145 1146 do { 1147 usleep_range(1000, 1100); 1148 1149 ret = gpiod_get_value_cansleep(iqs7222->irq_gpio); 1150 if (ret < 0) 1151 return ret; 1152 else if (ret > 0) 1153 return 0; 1154 } while (ktime_compare(ktime_get(), irq_timeout) < 0); 1155 1156 return -EBUSY; 1157 } 1158 1159 static int iqs7222_hard_reset(struct iqs7222_private *iqs7222) 1160 { 1161 struct i2c_client *client = iqs7222->client; 1162 int error; 1163 1164 if (!iqs7222->reset_gpio) 1165 return 0; 1166 1167 gpiod_set_value_cansleep(iqs7222->reset_gpio, 1); 1168 usleep_range(1000, 1100); 1169 1170 gpiod_set_value_cansleep(iqs7222->reset_gpio, 0); 1171 1172 error = iqs7222_irq_poll(iqs7222, IQS7222_RESET_TIMEOUT_MS); 1173 if (error) 1174 dev_err(&client->dev, "Failed to reset device: %d\n", error); 1175 1176 return error; 1177 } 1178 1179 static int iqs7222_force_comms(struct iqs7222_private *iqs7222) 1180 { 1181 u8 msg_buf[] = { 0xFF, }; 1182 int ret; 1183 1184 /* 1185 * The device cannot communicate until it asserts its interrupt (RDY) 1186 * pin. Attempts to do so while RDY is deasserted return an ACK; how- 1187 * ever all write data is ignored, and all read data returns 0xEE. 1188 * 1189 * Unsolicited communication must be preceded by a special force com- 1190 * munication command, after which the device eventually asserts its 1191 * RDY pin and agrees to communicate. 1192 * 1193 * Regardless of whether communication is forced or the result of an 1194 * interrupt, the device automatically deasserts its RDY pin once it 1195 * detects an I2C stop condition, or a timeout expires. 1196 */ 1197 ret = gpiod_get_value_cansleep(iqs7222->irq_gpio); 1198 if (ret < 0) 1199 return ret; 1200 else if (ret > 0) 1201 return 0; 1202 1203 ret = i2c_master_send(iqs7222->client, msg_buf, sizeof(msg_buf)); 1204 if (ret < (int)sizeof(msg_buf)) { 1205 if (ret >= 0) 1206 ret = -EIO; 1207 1208 /* 1209 * The datasheet states that the host must wait to retry any 1210 * failed attempt to communicate over I2C. 1211 */ 1212 msleep(IQS7222_COMMS_RETRY_MS); 1213 return ret; 1214 } 1215 1216 return iqs7222_irq_poll(iqs7222, IQS7222_COMMS_TIMEOUT_MS); 1217 } 1218 1219 static int iqs7222_read_burst(struct iqs7222_private *iqs7222, 1220 u16 reg, void *val, u16 num_val) 1221 { 1222 u8 reg_buf[sizeof(__be16)]; 1223 int ret, i; 1224 struct i2c_client *client = iqs7222->client; 1225 struct i2c_msg msg[] = { 1226 { 1227 .addr = client->addr, 1228 .flags = 0, 1229 .len = reg > U8_MAX ? sizeof(reg) : sizeof(u8), 1230 .buf = reg_buf, 1231 }, 1232 { 1233 .addr = client->addr, 1234 .flags = I2C_M_RD, 1235 .len = num_val * sizeof(__le16), 1236 .buf = (u8 *)val, 1237 }, 1238 }; 1239 1240 if (reg > U8_MAX) 1241 put_unaligned_be16(reg, reg_buf); 1242 else 1243 *reg_buf = (u8)reg; 1244 1245 /* 1246 * The following loop protects against an edge case in which the RDY 1247 * pin is automatically deasserted just as the read is initiated. In 1248 * that case, the read must be retried using forced communication. 1249 */ 1250 for (i = 0; i < IQS7222_NUM_RETRIES; i++) { 1251 ret = iqs7222_force_comms(iqs7222); 1252 if (ret < 0) 1253 continue; 1254 1255 ret = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg)); 1256 if (ret < (int)ARRAY_SIZE(msg)) { 1257 if (ret >= 0) 1258 ret = -EIO; 1259 1260 msleep(IQS7222_COMMS_RETRY_MS); 1261 continue; 1262 } 1263 1264 if (get_unaligned_le16(msg[1].buf) == IQS7222_COMMS_ERROR) { 1265 ret = -ENODATA; 1266 continue; 1267 } 1268 1269 ret = 0; 1270 break; 1271 } 1272 1273 /* 1274 * The following delay ensures the device has deasserted the RDY pin 1275 * following the I2C stop condition. 1276 */ 1277 usleep_range(50, 100); 1278 1279 if (ret < 0) 1280 dev_err(&client->dev, 1281 "Failed to read from address 0x%04X: %d\n", reg, ret); 1282 1283 return ret; 1284 } 1285 1286 static int iqs7222_read_word(struct iqs7222_private *iqs7222, u16 reg, u16 *val) 1287 { 1288 __le16 val_buf; 1289 int error; 1290 1291 error = iqs7222_read_burst(iqs7222, reg, &val_buf, 1); 1292 if (error) 1293 return error; 1294 1295 *val = le16_to_cpu(val_buf); 1296 1297 return 0; 1298 } 1299 1300 static int iqs7222_write_burst(struct iqs7222_private *iqs7222, 1301 u16 reg, const void *val, u16 num_val) 1302 { 1303 int reg_len = reg > U8_MAX ? sizeof(reg) : sizeof(u8); 1304 int val_len = num_val * sizeof(__le16); 1305 int msg_len = reg_len + val_len; 1306 int ret, i; 1307 struct i2c_client *client = iqs7222->client; 1308 u8 *msg_buf; 1309 1310 msg_buf = kzalloc(msg_len, GFP_KERNEL); 1311 if (!msg_buf) 1312 return -ENOMEM; 1313 1314 if (reg > U8_MAX) 1315 put_unaligned_be16(reg, msg_buf); 1316 else 1317 *msg_buf = (u8)reg; 1318 1319 memcpy(msg_buf + reg_len, val, val_len); 1320 1321 /* 1322 * The following loop protects against an edge case in which the RDY 1323 * pin is automatically asserted just before the force communication 1324 * command is sent. 1325 * 1326 * In that case, the subsequent I2C stop condition tricks the device 1327 * into preemptively deasserting the RDY pin and the command must be 1328 * sent again. 1329 */ 1330 for (i = 0; i < IQS7222_NUM_RETRIES; i++) { 1331 ret = iqs7222_force_comms(iqs7222); 1332 if (ret < 0) 1333 continue; 1334 1335 ret = i2c_master_send(client, msg_buf, msg_len); 1336 if (ret < msg_len) { 1337 if (ret >= 0) 1338 ret = -EIO; 1339 1340 msleep(IQS7222_COMMS_RETRY_MS); 1341 continue; 1342 } 1343 1344 ret = 0; 1345 break; 1346 } 1347 1348 kfree(msg_buf); 1349 1350 usleep_range(50, 100); 1351 1352 if (ret < 0) 1353 dev_err(&client->dev, 1354 "Failed to write to address 0x%04X: %d\n", reg, ret); 1355 1356 return ret; 1357 } 1358 1359 static int iqs7222_write_word(struct iqs7222_private *iqs7222, u16 reg, u16 val) 1360 { 1361 __le16 val_buf = cpu_to_le16(val); 1362 1363 return iqs7222_write_burst(iqs7222, reg, &val_buf, 1); 1364 } 1365 1366 static int iqs7222_ati_trigger(struct iqs7222_private *iqs7222) 1367 { 1368 struct i2c_client *client = iqs7222->client; 1369 ktime_t ati_timeout; 1370 u16 sys_status = 0; 1371 u16 sys_setup; 1372 int error, i; 1373 1374 /* 1375 * The reserved fields of the system setup register may have changed 1376 * as a result of other registers having been written. As such, read 1377 * the register's latest value to avoid unexpected behavior when the 1378 * register is written in the loop that follows. 1379 */ 1380 error = iqs7222_read_word(iqs7222, IQS7222_SYS_SETUP, &sys_setup); 1381 if (error) 1382 return error; 1383 1384 sys_setup &= ~IQS7222_SYS_SETUP_INTF_MODE_MASK; 1385 sys_setup &= ~IQS7222_SYS_SETUP_PWR_MODE_MASK; 1386 1387 for (i = 0; i < IQS7222_NUM_RETRIES; i++) { 1388 /* 1389 * Trigger ATI from streaming and normal-power modes so that 1390 * the RDY pin continues to be asserted during ATI. 1391 */ 1392 error = iqs7222_write_word(iqs7222, IQS7222_SYS_SETUP, 1393 sys_setup | 1394 IQS7222_SYS_SETUP_REDO_ATI); 1395 if (error) 1396 return error; 1397 1398 ati_timeout = ktime_add_ms(ktime_get(), IQS7222_ATI_TIMEOUT_MS); 1399 1400 do { 1401 error = iqs7222_irq_poll(iqs7222, 1402 IQS7222_COMMS_TIMEOUT_MS); 1403 if (error) 1404 continue; 1405 1406 error = iqs7222_read_word(iqs7222, IQS7222_SYS_STATUS, 1407 &sys_status); 1408 if (error) 1409 return error; 1410 1411 if (sys_status & IQS7222_SYS_STATUS_RESET) 1412 return 0; 1413 1414 if (sys_status & IQS7222_SYS_STATUS_ATI_ERROR) 1415 break; 1416 1417 if (sys_status & IQS7222_SYS_STATUS_ATI_ACTIVE) 1418 continue; 1419 1420 /* 1421 * Use stream-in-touch mode if either slider reports 1422 * absolute position. 1423 */ 1424 sys_setup |= test_bit(EV_ABS, iqs7222->keypad->evbit) 1425 ? IQS7222_SYS_SETUP_INTF_MODE_TOUCH 1426 : IQS7222_SYS_SETUP_INTF_MODE_EVENT; 1427 sys_setup |= IQS7222_SYS_SETUP_PWR_MODE_AUTO; 1428 1429 return iqs7222_write_word(iqs7222, IQS7222_SYS_SETUP, 1430 sys_setup); 1431 } while (ktime_compare(ktime_get(), ati_timeout) < 0); 1432 1433 dev_err(&client->dev, 1434 "ATI attempt %d of %d failed with status 0x%02X, %s\n", 1435 i + 1, IQS7222_NUM_RETRIES, (u8)sys_status, 1436 i + 1 < IQS7222_NUM_RETRIES ? "retrying" : "stopping"); 1437 } 1438 1439 return -ETIMEDOUT; 1440 } 1441 1442 static int iqs7222_dev_init(struct iqs7222_private *iqs7222, int dir) 1443 { 1444 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc; 1445 int comms_offset = dev_desc->comms_offset; 1446 int error, i, j, k; 1447 1448 /* 1449 * Acknowledge reset before writing any registers in case the device 1450 * suffers a spurious reset during initialization. Because this step 1451 * may change the reserved fields of the second filter beta register, 1452 * its cache must be updated. 1453 * 1454 * Writing the second filter beta register, in turn, may clobber the 1455 * system status register. As such, the filter beta register pair is 1456 * written first to protect against this hazard. 1457 */ 1458 if (dir == WRITE) { 1459 u16 reg = dev_desc->reg_grps[IQS7222_REG_GRP_FILT].base + 1; 1460 u16 filt_setup; 1461 1462 error = iqs7222_write_word(iqs7222, IQS7222_SYS_SETUP, 1463 iqs7222->sys_setup[0] | 1464 IQS7222_SYS_SETUP_ACK_RESET); 1465 if (error) 1466 return error; 1467 1468 error = iqs7222_read_word(iqs7222, reg, &filt_setup); 1469 if (error) 1470 return error; 1471 1472 iqs7222->filt_setup[1] &= GENMASK(7, 0); 1473 iqs7222->filt_setup[1] |= (filt_setup & ~GENMASK(7, 0)); 1474 } 1475 1476 /* 1477 * Take advantage of the stop-bit disable function, if available, to 1478 * save the trouble of having to reopen a communication window after 1479 * each burst read or write. 1480 */ 1481 if (comms_offset) { 1482 u16 comms_setup; 1483 1484 error = iqs7222_read_word(iqs7222, 1485 IQS7222_SYS_SETUP + comms_offset, 1486 &comms_setup); 1487 if (error) 1488 return error; 1489 1490 error = iqs7222_write_word(iqs7222, 1491 IQS7222_SYS_SETUP + comms_offset, 1492 comms_setup | IQS7222_COMMS_HOLD); 1493 if (error) 1494 return error; 1495 } 1496 1497 for (i = 0; i < IQS7222_NUM_REG_GRPS; i++) { 1498 int num_row = dev_desc->reg_grps[i].num_row; 1499 int num_col = dev_desc->reg_grps[i].num_col; 1500 u16 reg = dev_desc->reg_grps[i].base; 1501 __le16 *val_buf; 1502 u16 *val; 1503 1504 if (!num_col) 1505 continue; 1506 1507 val = iqs7222_setup(iqs7222, i, 0); 1508 if (!val) 1509 continue; 1510 1511 val_buf = kcalloc(num_col, sizeof(__le16), GFP_KERNEL); 1512 if (!val_buf) 1513 return -ENOMEM; 1514 1515 for (j = 0; j < num_row; j++) { 1516 switch (dir) { 1517 case READ: 1518 error = iqs7222_read_burst(iqs7222, reg, 1519 val_buf, num_col); 1520 for (k = 0; k < num_col; k++) 1521 val[k] = le16_to_cpu(val_buf[k]); 1522 break; 1523 1524 case WRITE: 1525 for (k = 0; k < num_col; k++) 1526 val_buf[k] = cpu_to_le16(val[k]); 1527 error = iqs7222_write_burst(iqs7222, reg, 1528 val_buf, num_col); 1529 break; 1530 1531 default: 1532 error = -EINVAL; 1533 } 1534 1535 if (error) 1536 break; 1537 1538 reg += IQS7222_REG_OFFSET; 1539 val += iqs7222_max_cols[i]; 1540 } 1541 1542 kfree(val_buf); 1543 1544 if (error) 1545 return error; 1546 } 1547 1548 if (comms_offset) { 1549 u16 comms_setup; 1550 1551 error = iqs7222_read_word(iqs7222, 1552 IQS7222_SYS_SETUP + comms_offset, 1553 &comms_setup); 1554 if (error) 1555 return error; 1556 1557 error = iqs7222_write_word(iqs7222, 1558 IQS7222_SYS_SETUP + comms_offset, 1559 comms_setup & ~IQS7222_COMMS_HOLD); 1560 if (error) 1561 return error; 1562 } 1563 1564 if (dir == READ) 1565 return 0; 1566 1567 return iqs7222_ati_trigger(iqs7222); 1568 } 1569 1570 static int iqs7222_dev_info(struct iqs7222_private *iqs7222) 1571 { 1572 struct i2c_client *client = iqs7222->client; 1573 bool prod_num_valid = false; 1574 __le16 dev_id[3]; 1575 int error, i; 1576 1577 error = iqs7222_read_burst(iqs7222, IQS7222_PROD_NUM, dev_id, 1578 ARRAY_SIZE(dev_id)); 1579 if (error) 1580 return error; 1581 1582 for (i = 0; i < ARRAY_SIZE(iqs7222_devs); i++) { 1583 if (le16_to_cpu(dev_id[0]) != iqs7222_devs[i].prod_num) 1584 continue; 1585 1586 prod_num_valid = true; 1587 1588 if (le16_to_cpu(dev_id[1]) < iqs7222_devs[i].fw_major) 1589 continue; 1590 1591 if (le16_to_cpu(dev_id[2]) < iqs7222_devs[i].fw_minor) 1592 continue; 1593 1594 iqs7222->dev_desc = &iqs7222_devs[i]; 1595 return 0; 1596 } 1597 1598 if (prod_num_valid) 1599 dev_err(&client->dev, "Unsupported firmware revision: %u.%u\n", 1600 le16_to_cpu(dev_id[1]), le16_to_cpu(dev_id[2])); 1601 else 1602 dev_err(&client->dev, "Unrecognized product number: %u\n", 1603 le16_to_cpu(dev_id[0])); 1604 1605 return -EINVAL; 1606 } 1607 1608 static int iqs7222_gpio_select(struct iqs7222_private *iqs7222, 1609 struct fwnode_handle *child_node, 1610 int child_enable, u16 child_link) 1611 { 1612 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc; 1613 struct i2c_client *client = iqs7222->client; 1614 int num_gpio = dev_desc->reg_grps[IQS7222_REG_GRP_GPIO].num_row; 1615 int error, count, i; 1616 unsigned int gpio_sel[ARRAY_SIZE(iqs7222_gpio_links)]; 1617 1618 if (!num_gpio) 1619 return 0; 1620 1621 if (!fwnode_property_present(child_node, "azoteq,gpio-select")) 1622 return 0; 1623 1624 count = fwnode_property_count_u32(child_node, "azoteq,gpio-select"); 1625 if (count > num_gpio) { 1626 dev_err(&client->dev, "Invalid number of %s GPIOs\n", 1627 fwnode_get_name(child_node)); 1628 return -EINVAL; 1629 } else if (count < 0) { 1630 dev_err(&client->dev, "Failed to count %s GPIOs: %d\n", 1631 fwnode_get_name(child_node), count); 1632 return count; 1633 } 1634 1635 error = fwnode_property_read_u32_array(child_node, 1636 "azoteq,gpio-select", 1637 gpio_sel, count); 1638 if (error) { 1639 dev_err(&client->dev, "Failed to read %s GPIOs: %d\n", 1640 fwnode_get_name(child_node), error); 1641 return error; 1642 } 1643 1644 for (i = 0; i < count; i++) { 1645 u16 *gpio_setup; 1646 1647 if (gpio_sel[i] >= num_gpio) { 1648 dev_err(&client->dev, "Invalid %s GPIO: %u\n", 1649 fwnode_get_name(child_node), gpio_sel[i]); 1650 return -EINVAL; 1651 } 1652 1653 gpio_setup = iqs7222->gpio_setup[gpio_sel[i]]; 1654 1655 if (gpio_setup[2] && child_link != gpio_setup[2]) { 1656 dev_err(&client->dev, 1657 "Conflicting GPIO %u event types\n", 1658 gpio_sel[i]); 1659 return -EINVAL; 1660 } 1661 1662 gpio_setup[0] |= IQS7222_GPIO_SETUP_0_GPIO_EN; 1663 gpio_setup[1] |= child_enable; 1664 gpio_setup[2] = child_link; 1665 } 1666 1667 return 0; 1668 } 1669 1670 static int iqs7222_parse_props(struct iqs7222_private *iqs7222, 1671 struct fwnode_handle *reg_grp_node, 1672 int reg_grp_index, 1673 enum iqs7222_reg_grp_id reg_grp, 1674 enum iqs7222_reg_key_id reg_key) 1675 { 1676 u16 *setup = iqs7222_setup(iqs7222, reg_grp, reg_grp_index); 1677 struct i2c_client *client = iqs7222->client; 1678 int i; 1679 1680 if (!setup) 1681 return 0; 1682 1683 for (i = 0; i < ARRAY_SIZE(iqs7222_props); i++) { 1684 const char *name = iqs7222_props[i].name; 1685 int reg_offset = iqs7222_props[i].reg_offset; 1686 int reg_shift = iqs7222_props[i].reg_shift; 1687 int reg_width = iqs7222_props[i].reg_width; 1688 int val_pitch = iqs7222_props[i].val_pitch ? : 1; 1689 int val_min = iqs7222_props[i].val_min; 1690 int val_max = iqs7222_props[i].val_max; 1691 bool invert = iqs7222_props[i].invert; 1692 const char *label = iqs7222_props[i].label ? : name; 1693 unsigned int val; 1694 int error; 1695 1696 if (iqs7222_props[i].reg_grp != reg_grp || 1697 iqs7222_props[i].reg_key != reg_key) 1698 continue; 1699 1700 /* 1701 * Boolean register fields are one bit wide; they are forcibly 1702 * reset to provide a means to undo changes by a bootloader if 1703 * necessary. 1704 * 1705 * Scalar fields, on the other hand, are left untouched unless 1706 * their corresponding properties are present. 1707 */ 1708 if (reg_width == 1) { 1709 if (invert) 1710 setup[reg_offset] |= BIT(reg_shift); 1711 else 1712 setup[reg_offset] &= ~BIT(reg_shift); 1713 } 1714 1715 if (!fwnode_property_present(reg_grp_node, name)) 1716 continue; 1717 1718 if (reg_width == 1) { 1719 if (invert) 1720 setup[reg_offset] &= ~BIT(reg_shift); 1721 else 1722 setup[reg_offset] |= BIT(reg_shift); 1723 1724 continue; 1725 } 1726 1727 error = fwnode_property_read_u32(reg_grp_node, name, &val); 1728 if (error) { 1729 dev_err(&client->dev, "Failed to read %s %s: %d\n", 1730 fwnode_get_name(reg_grp_node), label, error); 1731 return error; 1732 } 1733 1734 if (!val_max) 1735 val_max = GENMASK(reg_width - 1, 0) * val_pitch; 1736 1737 if (val < val_min || val > val_max) { 1738 dev_err(&client->dev, "Invalid %s %s: %u\n", 1739 fwnode_get_name(reg_grp_node), label, val); 1740 return -EINVAL; 1741 } 1742 1743 setup[reg_offset] &= ~GENMASK(reg_shift + reg_width - 1, 1744 reg_shift); 1745 setup[reg_offset] |= (val / val_pitch << reg_shift); 1746 } 1747 1748 return 0; 1749 } 1750 1751 static int iqs7222_parse_event(struct iqs7222_private *iqs7222, 1752 struct fwnode_handle *event_node, 1753 int reg_grp_index, 1754 enum iqs7222_reg_grp_id reg_grp, 1755 enum iqs7222_reg_key_id reg_key, 1756 u16 event_enable, u16 event_link, 1757 unsigned int *event_type, 1758 unsigned int *event_code) 1759 { 1760 struct i2c_client *client = iqs7222->client; 1761 int error; 1762 1763 error = iqs7222_parse_props(iqs7222, event_node, reg_grp_index, 1764 reg_grp, reg_key); 1765 if (error) 1766 return error; 1767 1768 error = iqs7222_gpio_select(iqs7222, event_node, event_enable, 1769 event_link); 1770 if (error) 1771 return error; 1772 1773 error = fwnode_property_read_u32(event_node, "linux,code", event_code); 1774 if (error == -EINVAL) { 1775 return 0; 1776 } else if (error) { 1777 dev_err(&client->dev, "Failed to read %s code: %d\n", 1778 fwnode_get_name(event_node), error); 1779 return error; 1780 } 1781 1782 if (!event_type) { 1783 input_set_capability(iqs7222->keypad, EV_KEY, *event_code); 1784 return 0; 1785 } 1786 1787 error = fwnode_property_read_u32(event_node, "linux,input-type", 1788 event_type); 1789 if (error == -EINVAL) { 1790 *event_type = EV_KEY; 1791 } else if (error) { 1792 dev_err(&client->dev, "Failed to read %s input type: %d\n", 1793 fwnode_get_name(event_node), error); 1794 return error; 1795 } else if (*event_type != EV_KEY && *event_type != EV_SW) { 1796 dev_err(&client->dev, "Invalid %s input type: %d\n", 1797 fwnode_get_name(event_node), *event_type); 1798 return -EINVAL; 1799 } 1800 1801 input_set_capability(iqs7222->keypad, *event_type, *event_code); 1802 1803 return 0; 1804 } 1805 1806 static int iqs7222_parse_cycle(struct iqs7222_private *iqs7222, 1807 struct fwnode_handle *cycle_node, int cycle_index) 1808 { 1809 u16 *cycle_setup = iqs7222->cycle_setup[cycle_index]; 1810 struct i2c_client *client = iqs7222->client; 1811 unsigned int pins[9]; 1812 int error, count, i; 1813 1814 /* 1815 * Each channel shares a cycle with one other channel; the mapping of 1816 * channels to cycles is fixed. Properties defined for a cycle impact 1817 * both channels tied to the cycle. 1818 * 1819 * Unlike channels which are restricted to a select range of CRx pins 1820 * based on channel number, any cycle can claim any of the device's 9 1821 * CTx pins (CTx0-8). 1822 */ 1823 if (!fwnode_property_present(cycle_node, "azoteq,tx-enable")) 1824 return 0; 1825 1826 count = fwnode_property_count_u32(cycle_node, "azoteq,tx-enable"); 1827 if (count < 0) { 1828 dev_err(&client->dev, "Failed to count %s CTx pins: %d\n", 1829 fwnode_get_name(cycle_node), count); 1830 return count; 1831 } else if (count > ARRAY_SIZE(pins)) { 1832 dev_err(&client->dev, "Invalid number of %s CTx pins\n", 1833 fwnode_get_name(cycle_node)); 1834 return -EINVAL; 1835 } 1836 1837 error = fwnode_property_read_u32_array(cycle_node, "azoteq,tx-enable", 1838 pins, count); 1839 if (error) { 1840 dev_err(&client->dev, "Failed to read %s CTx pins: %d\n", 1841 fwnode_get_name(cycle_node), error); 1842 return error; 1843 } 1844 1845 cycle_setup[1] &= ~GENMASK(7 + ARRAY_SIZE(pins) - 1, 7); 1846 1847 for (i = 0; i < count; i++) { 1848 if (pins[i] > 8) { 1849 dev_err(&client->dev, "Invalid %s CTx pin: %u\n", 1850 fwnode_get_name(cycle_node), pins[i]); 1851 return -EINVAL; 1852 } 1853 1854 cycle_setup[1] |= BIT(pins[i] + 7); 1855 } 1856 1857 return 0; 1858 } 1859 1860 static int iqs7222_parse_chan(struct iqs7222_private *iqs7222, 1861 struct fwnode_handle *chan_node, int chan_index) 1862 { 1863 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc; 1864 struct i2c_client *client = iqs7222->client; 1865 int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row; 1866 int ext_chan = rounddown(num_chan, 10); 1867 int error, i; 1868 u16 *chan_setup = iqs7222->chan_setup[chan_index]; 1869 u16 *sys_setup = iqs7222->sys_setup; 1870 unsigned int val; 1871 1872 if (dev_desc->allow_offset && 1873 fwnode_property_present(chan_node, "azoteq,ulp-allow")) 1874 sys_setup[dev_desc->allow_offset] &= ~BIT(chan_index); 1875 1876 chan_setup[0] |= IQS7222_CHAN_SETUP_0_CHAN_EN; 1877 1878 /* 1879 * The reference channel function allows for differential measurements 1880 * and is only available in the case of IQS7222A or IQS7222C. 1881 */ 1882 if (dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_col > 4 && 1883 fwnode_property_present(chan_node, "azoteq,ref-select")) { 1884 u16 *ref_setup; 1885 1886 error = fwnode_property_read_u32(chan_node, "azoteq,ref-select", 1887 &val); 1888 if (error) { 1889 dev_err(&client->dev, 1890 "Failed to read %s reference channel: %d\n", 1891 fwnode_get_name(chan_node), error); 1892 return error; 1893 } 1894 1895 if (val >= ext_chan) { 1896 dev_err(&client->dev, 1897 "Invalid %s reference channel: %u\n", 1898 fwnode_get_name(chan_node), val); 1899 return -EINVAL; 1900 } 1901 1902 ref_setup = iqs7222->chan_setup[val]; 1903 1904 /* 1905 * Configure the current channel as a follower of the selected 1906 * reference channel. 1907 */ 1908 chan_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_FOLLOW; 1909 chan_setup[4] = val * 42 + 1048; 1910 1911 error = fwnode_property_read_u32(chan_node, "azoteq,ref-weight", 1912 &val); 1913 if (!error) { 1914 if (val > U16_MAX) { 1915 dev_err(&client->dev, 1916 "Invalid %s reference weight: %u\n", 1917 fwnode_get_name(chan_node), val); 1918 return -EINVAL; 1919 } 1920 1921 chan_setup[5] = val; 1922 } else if (error != -EINVAL) { 1923 dev_err(&client->dev, 1924 "Failed to read %s reference weight: %d\n", 1925 fwnode_get_name(chan_node), error); 1926 return error; 1927 } 1928 1929 /* 1930 * Configure the selected channel as a reference channel which 1931 * serves the current channel. 1932 */ 1933 ref_setup[0] |= IQS7222_CHAN_SETUP_0_REF_MODE_REF; 1934 ref_setup[5] |= BIT(chan_index); 1935 1936 ref_setup[4] = dev_desc->touch_link; 1937 if (fwnode_property_present(chan_node, "azoteq,use-prox")) 1938 ref_setup[4] -= 2; 1939 } 1940 1941 if (fwnode_property_present(chan_node, "azoteq,rx-enable")) { 1942 /* 1943 * Each channel can claim up to 4 CRx pins. The first half of 1944 * the channels can use CRx0-3, while the second half can use 1945 * CRx4-7. 1946 */ 1947 unsigned int pins[4]; 1948 int count; 1949 1950 count = fwnode_property_count_u32(chan_node, 1951 "azoteq,rx-enable"); 1952 if (count < 0) { 1953 dev_err(&client->dev, 1954 "Failed to count %s CRx pins: %d\n", 1955 fwnode_get_name(chan_node), count); 1956 return count; 1957 } else if (count > ARRAY_SIZE(pins)) { 1958 dev_err(&client->dev, 1959 "Invalid number of %s CRx pins\n", 1960 fwnode_get_name(chan_node)); 1961 return -EINVAL; 1962 } 1963 1964 error = fwnode_property_read_u32_array(chan_node, 1965 "azoteq,rx-enable", 1966 pins, count); 1967 if (error) { 1968 dev_err(&client->dev, 1969 "Failed to read %s CRx pins: %d\n", 1970 fwnode_get_name(chan_node), error); 1971 return error; 1972 } 1973 1974 chan_setup[0] &= ~GENMASK(4 + ARRAY_SIZE(pins) - 1, 4); 1975 1976 for (i = 0; i < count; i++) { 1977 int min_crx = chan_index < ext_chan / 2 ? 0 : 4; 1978 1979 if (pins[i] < min_crx || pins[i] > min_crx + 3) { 1980 dev_err(&client->dev, 1981 "Invalid %s CRx pin: %u\n", 1982 fwnode_get_name(chan_node), pins[i]); 1983 return -EINVAL; 1984 } 1985 1986 chan_setup[0] |= BIT(pins[i] + 4 - min_crx); 1987 } 1988 } 1989 1990 for (i = 0; i < ARRAY_SIZE(iqs7222_kp_events); i++) { 1991 const char *event_name = iqs7222_kp_events[i].name; 1992 u16 event_enable = iqs7222_kp_events[i].enable; 1993 struct fwnode_handle *event_node; 1994 1995 event_node = fwnode_get_named_child_node(chan_node, event_name); 1996 if (!event_node) 1997 continue; 1998 1999 error = fwnode_property_read_u32(event_node, 2000 "azoteq,timeout-press-ms", 2001 &val); 2002 if (!error) { 2003 /* 2004 * The IQS7222B employs a global pair of press timeout 2005 * registers as opposed to channel-specific registers. 2006 */ 2007 u16 *setup = dev_desc->reg_grps 2008 [IQS7222_REG_GRP_BTN].num_col > 2 ? 2009 &iqs7222->btn_setup[chan_index][2] : 2010 &sys_setup[9]; 2011 2012 if (val > U8_MAX * 500) { 2013 dev_err(&client->dev, 2014 "Invalid %s press timeout: %u\n", 2015 fwnode_get_name(event_node), val); 2016 fwnode_handle_put(event_node); 2017 return -EINVAL; 2018 } 2019 2020 *setup &= ~(U8_MAX << i * 8); 2021 *setup |= (val / 500 << i * 8); 2022 } else if (error != -EINVAL) { 2023 dev_err(&client->dev, 2024 "Failed to read %s press timeout: %d\n", 2025 fwnode_get_name(event_node), error); 2026 fwnode_handle_put(event_node); 2027 return error; 2028 } 2029 2030 error = iqs7222_parse_event(iqs7222, event_node, chan_index, 2031 IQS7222_REG_GRP_BTN, 2032 iqs7222_kp_events[i].reg_key, 2033 BIT(chan_index), 2034 dev_desc->touch_link - (i ? 0 : 2), 2035 &iqs7222->kp_type[chan_index][i], 2036 &iqs7222->kp_code[chan_index][i]); 2037 fwnode_handle_put(event_node); 2038 if (error) 2039 return error; 2040 2041 if (!dev_desc->event_offset) 2042 continue; 2043 2044 sys_setup[dev_desc->event_offset] |= event_enable; 2045 } 2046 2047 /* 2048 * The following call handles a special pair of properties that apply 2049 * to a channel node, but reside within the button (event) group. 2050 */ 2051 return iqs7222_parse_props(iqs7222, chan_node, chan_index, 2052 IQS7222_REG_GRP_BTN, 2053 IQS7222_REG_KEY_DEBOUNCE); 2054 } 2055 2056 static int iqs7222_parse_sldr(struct iqs7222_private *iqs7222, 2057 struct fwnode_handle *sldr_node, int sldr_index) 2058 { 2059 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc; 2060 struct i2c_client *client = iqs7222->client; 2061 int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row; 2062 int ext_chan = rounddown(num_chan, 10); 2063 int count, error, reg_offset, i; 2064 u16 *event_mask = &iqs7222->sys_setup[dev_desc->event_offset]; 2065 u16 *sldr_setup = iqs7222->sldr_setup[sldr_index]; 2066 unsigned int chan_sel[4], val; 2067 2068 /* 2069 * Each slider can be spread across 3 to 4 channels. It is possible to 2070 * select only 2 channels, but doing so prevents the slider from using 2071 * the specified resolution. 2072 */ 2073 count = fwnode_property_count_u32(sldr_node, "azoteq,channel-select"); 2074 if (count < 0) { 2075 dev_err(&client->dev, "Failed to count %s channels: %d\n", 2076 fwnode_get_name(sldr_node), count); 2077 return count; 2078 } else if (count < 3 || count > ARRAY_SIZE(chan_sel)) { 2079 dev_err(&client->dev, "Invalid number of %s channels\n", 2080 fwnode_get_name(sldr_node)); 2081 return -EINVAL; 2082 } 2083 2084 error = fwnode_property_read_u32_array(sldr_node, 2085 "azoteq,channel-select", 2086 chan_sel, count); 2087 if (error) { 2088 dev_err(&client->dev, "Failed to read %s channels: %d\n", 2089 fwnode_get_name(sldr_node), error); 2090 return error; 2091 } 2092 2093 /* 2094 * Resolution and top speed, if small enough, are packed into a single 2095 * register. Otherwise, each occupies its own register and the rest of 2096 * the slider-related register addresses are offset by one. 2097 */ 2098 reg_offset = dev_desc->sldr_res < U16_MAX ? 0 : 1; 2099 2100 sldr_setup[0] |= count; 2101 sldr_setup[3 + reg_offset] &= ~GENMASK(ext_chan - 1, 0); 2102 2103 for (i = 0; i < ARRAY_SIZE(chan_sel); i++) { 2104 sldr_setup[5 + reg_offset + i] = 0; 2105 if (i >= count) 2106 continue; 2107 2108 if (chan_sel[i] >= ext_chan) { 2109 dev_err(&client->dev, "Invalid %s channel: %u\n", 2110 fwnode_get_name(sldr_node), chan_sel[i]); 2111 return -EINVAL; 2112 } 2113 2114 /* 2115 * The following fields indicate which channels participate in 2116 * the slider, as well as each channel's relative placement. 2117 */ 2118 sldr_setup[3 + reg_offset] |= BIT(chan_sel[i]); 2119 sldr_setup[5 + reg_offset + i] = chan_sel[i] * 42 + 1080; 2120 } 2121 2122 sldr_setup[4 + reg_offset] = dev_desc->touch_link; 2123 if (fwnode_property_present(sldr_node, "azoteq,use-prox")) 2124 sldr_setup[4 + reg_offset] -= 2; 2125 2126 error = fwnode_property_read_u32(sldr_node, "azoteq,slider-size", &val); 2127 if (!error) { 2128 if (val > dev_desc->sldr_res) { 2129 dev_err(&client->dev, "Invalid %s size: %u\n", 2130 fwnode_get_name(sldr_node), val); 2131 return -EINVAL; 2132 } 2133 2134 if (reg_offset) { 2135 sldr_setup[3] = val; 2136 } else { 2137 sldr_setup[2] &= ~IQS7222_SLDR_SETUP_2_RES_MASK; 2138 sldr_setup[2] |= (val / 16 << 2139 IQS7222_SLDR_SETUP_2_RES_SHIFT); 2140 } 2141 } else if (error != -EINVAL) { 2142 dev_err(&client->dev, "Failed to read %s size: %d\n", 2143 fwnode_get_name(sldr_node), error); 2144 return error; 2145 } 2146 2147 if (!(reg_offset ? sldr_setup[3] 2148 : sldr_setup[2] & IQS7222_SLDR_SETUP_2_RES_MASK)) { 2149 dev_err(&client->dev, "Undefined %s size\n", 2150 fwnode_get_name(sldr_node)); 2151 return -EINVAL; 2152 } 2153 2154 error = fwnode_property_read_u32(sldr_node, "azoteq,top-speed", &val); 2155 if (!error) { 2156 if (val > (reg_offset ? U16_MAX : U8_MAX * 4)) { 2157 dev_err(&client->dev, "Invalid %s top speed: %u\n", 2158 fwnode_get_name(sldr_node), val); 2159 return -EINVAL; 2160 } 2161 2162 if (reg_offset) { 2163 sldr_setup[2] = val; 2164 } else { 2165 sldr_setup[2] &= ~IQS7222_SLDR_SETUP_2_TOP_SPEED_MASK; 2166 sldr_setup[2] |= (val / 4); 2167 } 2168 } else if (error != -EINVAL) { 2169 dev_err(&client->dev, "Failed to read %s top speed: %d\n", 2170 fwnode_get_name(sldr_node), error); 2171 return error; 2172 } 2173 2174 error = fwnode_property_read_u32(sldr_node, "linux,axis", &val); 2175 if (!error) { 2176 u16 sldr_max = sldr_setup[3] - 1; 2177 2178 if (!reg_offset) { 2179 sldr_max = sldr_setup[2]; 2180 2181 sldr_max &= IQS7222_SLDR_SETUP_2_RES_MASK; 2182 sldr_max >>= IQS7222_SLDR_SETUP_2_RES_SHIFT; 2183 2184 sldr_max = sldr_max * 16 - 1; 2185 } 2186 2187 input_set_abs_params(iqs7222->keypad, val, 0, sldr_max, 0, 0); 2188 iqs7222->sl_axis[sldr_index] = val; 2189 } else if (error != -EINVAL) { 2190 dev_err(&client->dev, "Failed to read %s axis: %d\n", 2191 fwnode_get_name(sldr_node), error); 2192 return error; 2193 } 2194 2195 if (dev_desc->wheel_enable) { 2196 sldr_setup[0] &= ~dev_desc->wheel_enable; 2197 if (iqs7222->sl_axis[sldr_index] == ABS_WHEEL) 2198 sldr_setup[0] |= dev_desc->wheel_enable; 2199 } 2200 2201 /* 2202 * The absence of a register offset makes it safe to assume the device 2203 * supports gestures, each of which is first disabled until explicitly 2204 * enabled. 2205 */ 2206 if (!reg_offset) 2207 for (i = 0; i < ARRAY_SIZE(iqs7222_sl_events); i++) 2208 sldr_setup[9] &= ~iqs7222_sl_events[i].enable; 2209 2210 for (i = 0; i < ARRAY_SIZE(iqs7222_sl_events); i++) { 2211 const char *event_name = iqs7222_sl_events[i].name; 2212 struct fwnode_handle *event_node; 2213 enum iqs7222_reg_key_id reg_key; 2214 2215 event_node = fwnode_get_named_child_node(sldr_node, event_name); 2216 if (!event_node) 2217 continue; 2218 2219 /* 2220 * Depending on the device, gestures are either offered using 2221 * one of two timing resolutions, or are not supported at all. 2222 */ 2223 if (reg_offset) 2224 reg_key = IQS7222_REG_KEY_RESERVED; 2225 else if (dev_desc->legacy_gesture && 2226 iqs7222_sl_events[i].reg_key == IQS7222_REG_KEY_TAP) 2227 reg_key = IQS7222_REG_KEY_TAP_LEGACY; 2228 else if (dev_desc->legacy_gesture && 2229 iqs7222_sl_events[i].reg_key == IQS7222_REG_KEY_AXIAL) 2230 reg_key = IQS7222_REG_KEY_AXIAL_LEGACY; 2231 else 2232 reg_key = iqs7222_sl_events[i].reg_key; 2233 2234 /* 2235 * The press/release event does not expose a direct GPIO link, 2236 * but one can be emulated by tying each of the participating 2237 * channels to the same GPIO. 2238 */ 2239 error = iqs7222_parse_event(iqs7222, event_node, sldr_index, 2240 IQS7222_REG_GRP_SLDR, reg_key, 2241 i ? iqs7222_sl_events[i].enable 2242 : sldr_setup[3 + reg_offset], 2243 i ? 1568 + sldr_index * 30 2244 : sldr_setup[4 + reg_offset], 2245 NULL, 2246 &iqs7222->sl_code[sldr_index][i]); 2247 fwnode_handle_put(event_node); 2248 if (error) 2249 return error; 2250 2251 if (!reg_offset) 2252 sldr_setup[9] |= iqs7222_sl_events[i].enable; 2253 2254 if (!dev_desc->event_offset) 2255 continue; 2256 2257 /* 2258 * The press/release event is determined based on whether the 2259 * coordinate field reports 0xFFFF and solely relies on touch 2260 * or proximity interrupts to be unmasked. 2261 */ 2262 if (i && !reg_offset) 2263 *event_mask |= (IQS7222_EVENT_MASK_SLDR << sldr_index); 2264 else if (sldr_setup[4 + reg_offset] == dev_desc->touch_link) 2265 *event_mask |= IQS7222_EVENT_MASK_TOUCH; 2266 else 2267 *event_mask |= IQS7222_EVENT_MASK_PROX; 2268 } 2269 2270 /* 2271 * The following call handles a special pair of properties that shift 2272 * to make room for a wheel enable control in the case of IQS7222C. 2273 */ 2274 return iqs7222_parse_props(iqs7222, sldr_node, sldr_index, 2275 IQS7222_REG_GRP_SLDR, 2276 dev_desc->wheel_enable ? 2277 IQS7222_REG_KEY_WHEEL : 2278 IQS7222_REG_KEY_NO_WHEEL); 2279 } 2280 2281 static int (*iqs7222_parse_extra[IQS7222_NUM_REG_GRPS]) 2282 (struct iqs7222_private *iqs7222, 2283 struct fwnode_handle *reg_grp_node, 2284 int reg_grp_index) = { 2285 [IQS7222_REG_GRP_CYCLE] = iqs7222_parse_cycle, 2286 [IQS7222_REG_GRP_CHAN] = iqs7222_parse_chan, 2287 [IQS7222_REG_GRP_SLDR] = iqs7222_parse_sldr, 2288 }; 2289 2290 static int iqs7222_parse_reg_grp(struct iqs7222_private *iqs7222, 2291 enum iqs7222_reg_grp_id reg_grp, 2292 int reg_grp_index) 2293 { 2294 struct i2c_client *client = iqs7222->client; 2295 struct fwnode_handle *reg_grp_node; 2296 int error; 2297 2298 if (iqs7222_reg_grp_names[reg_grp]) { 2299 char reg_grp_name[16]; 2300 2301 snprintf(reg_grp_name, sizeof(reg_grp_name), "%s-%d", 2302 iqs7222_reg_grp_names[reg_grp], reg_grp_index); 2303 2304 reg_grp_node = device_get_named_child_node(&client->dev, 2305 reg_grp_name); 2306 } else { 2307 reg_grp_node = fwnode_handle_get(dev_fwnode(&client->dev)); 2308 } 2309 2310 if (!reg_grp_node) 2311 return 0; 2312 2313 error = iqs7222_parse_props(iqs7222, reg_grp_node, reg_grp_index, 2314 reg_grp, IQS7222_REG_KEY_NONE); 2315 2316 if (!error && iqs7222_parse_extra[reg_grp]) 2317 error = iqs7222_parse_extra[reg_grp](iqs7222, reg_grp_node, 2318 reg_grp_index); 2319 2320 fwnode_handle_put(reg_grp_node); 2321 2322 return error; 2323 } 2324 2325 static int iqs7222_parse_all(struct iqs7222_private *iqs7222) 2326 { 2327 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc; 2328 const struct iqs7222_reg_grp_desc *reg_grps = dev_desc->reg_grps; 2329 u16 *sys_setup = iqs7222->sys_setup; 2330 int error, i, j; 2331 2332 if (dev_desc->allow_offset) 2333 sys_setup[dev_desc->allow_offset] = U16_MAX; 2334 2335 if (dev_desc->event_offset) 2336 sys_setup[dev_desc->event_offset] = IQS7222_EVENT_MASK_ATI; 2337 2338 for (i = 0; i < reg_grps[IQS7222_REG_GRP_GPIO].num_row; i++) { 2339 u16 *gpio_setup = iqs7222->gpio_setup[i]; 2340 2341 gpio_setup[0] &= ~IQS7222_GPIO_SETUP_0_GPIO_EN; 2342 gpio_setup[1] = 0; 2343 gpio_setup[2] = 0; 2344 2345 if (reg_grps[IQS7222_REG_GRP_GPIO].num_row == 1) 2346 continue; 2347 2348 /* 2349 * The IQS7222C exposes multiple GPIO and must be informed 2350 * as to which GPIO this group represents. 2351 */ 2352 for (j = 0; j < ARRAY_SIZE(iqs7222_gpio_links); j++) 2353 gpio_setup[0] &= ~BIT(iqs7222_gpio_links[j]); 2354 2355 gpio_setup[0] |= BIT(iqs7222_gpio_links[i]); 2356 } 2357 2358 for (i = 0; i < reg_grps[IQS7222_REG_GRP_CHAN].num_row; i++) { 2359 u16 *chan_setup = iqs7222->chan_setup[i]; 2360 2361 chan_setup[0] &= ~IQS7222_CHAN_SETUP_0_REF_MODE_MASK; 2362 chan_setup[0] &= ~IQS7222_CHAN_SETUP_0_CHAN_EN; 2363 2364 chan_setup[5] = 0; 2365 } 2366 2367 for (i = 0; i < reg_grps[IQS7222_REG_GRP_SLDR].num_row; i++) { 2368 u16 *sldr_setup = iqs7222->sldr_setup[i]; 2369 2370 sldr_setup[0] &= ~IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK; 2371 } 2372 2373 for (i = 0; i < IQS7222_NUM_REG_GRPS; i++) { 2374 for (j = 0; j < reg_grps[i].num_row; j++) { 2375 error = iqs7222_parse_reg_grp(iqs7222, i, j); 2376 if (error) 2377 return error; 2378 } 2379 } 2380 2381 return 0; 2382 } 2383 2384 static int iqs7222_report(struct iqs7222_private *iqs7222) 2385 { 2386 const struct iqs7222_dev_desc *dev_desc = iqs7222->dev_desc; 2387 struct i2c_client *client = iqs7222->client; 2388 int num_chan = dev_desc->reg_grps[IQS7222_REG_GRP_CHAN].num_row; 2389 int num_stat = dev_desc->reg_grps[IQS7222_REG_GRP_STAT].num_col; 2390 int error, i, j; 2391 __le16 status[IQS7222_MAX_COLS_STAT]; 2392 2393 error = iqs7222_read_burst(iqs7222, IQS7222_SYS_STATUS, status, 2394 num_stat); 2395 if (error) 2396 return error; 2397 2398 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_RESET) { 2399 dev_err(&client->dev, "Unexpected device reset\n"); 2400 return iqs7222_dev_init(iqs7222, WRITE); 2401 } 2402 2403 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_ATI_ERROR) { 2404 dev_err(&client->dev, "Unexpected ATI error\n"); 2405 return iqs7222_ati_trigger(iqs7222); 2406 } 2407 2408 if (le16_to_cpu(status[0]) & IQS7222_SYS_STATUS_ATI_ACTIVE) 2409 return 0; 2410 2411 for (i = 0; i < num_chan; i++) { 2412 u16 *chan_setup = iqs7222->chan_setup[i]; 2413 2414 if (!(chan_setup[0] & IQS7222_CHAN_SETUP_0_CHAN_EN)) 2415 continue; 2416 2417 for (j = 0; j < ARRAY_SIZE(iqs7222_kp_events); j++) { 2418 /* 2419 * Proximity state begins at offset 2 and spills into 2420 * offset 3 for devices with more than 16 channels. 2421 * 2422 * Touch state begins at the first offset immediately 2423 * following proximity state. 2424 */ 2425 int k = 2 + j * (num_chan > 16 ? 2 : 1); 2426 u16 state = le16_to_cpu(status[k + i / 16]); 2427 2428 if (!iqs7222->kp_type[i][j]) 2429 continue; 2430 2431 input_event(iqs7222->keypad, 2432 iqs7222->kp_type[i][j], 2433 iqs7222->kp_code[i][j], 2434 !!(state & BIT(i % 16))); 2435 } 2436 } 2437 2438 for (i = 0; i < dev_desc->reg_grps[IQS7222_REG_GRP_SLDR].num_row; i++) { 2439 u16 *sldr_setup = iqs7222->sldr_setup[i]; 2440 u16 sldr_pos = le16_to_cpu(status[4 + i]); 2441 u16 state = le16_to_cpu(status[6 + i]); 2442 2443 if (!(sldr_setup[0] & IQS7222_SLDR_SETUP_0_CHAN_CNT_MASK)) 2444 continue; 2445 2446 if (sldr_pos < dev_desc->sldr_res) 2447 input_report_abs(iqs7222->keypad, iqs7222->sl_axis[i], 2448 sldr_pos); 2449 2450 input_report_key(iqs7222->keypad, iqs7222->sl_code[i][0], 2451 sldr_pos < dev_desc->sldr_res); 2452 2453 /* 2454 * A maximum resolution indicates the device does not support 2455 * gestures, in which case the remaining fields are ignored. 2456 */ 2457 if (dev_desc->sldr_res == U16_MAX) 2458 continue; 2459 2460 if (!(le16_to_cpu(status[1]) & IQS7222_EVENT_MASK_SLDR << i)) 2461 continue; 2462 2463 /* 2464 * Skip the press/release event, as it does not have separate 2465 * status fields and is handled separately. 2466 */ 2467 for (j = 1; j < ARRAY_SIZE(iqs7222_sl_events); j++) { 2468 u16 mask = iqs7222_sl_events[j].mask; 2469 u16 val = iqs7222_sl_events[j].val; 2470 2471 input_report_key(iqs7222->keypad, 2472 iqs7222->sl_code[i][j], 2473 (state & mask) == val); 2474 } 2475 2476 input_sync(iqs7222->keypad); 2477 2478 for (j = 1; j < ARRAY_SIZE(iqs7222_sl_events); j++) 2479 input_report_key(iqs7222->keypad, 2480 iqs7222->sl_code[i][j], 0); 2481 } 2482 2483 input_sync(iqs7222->keypad); 2484 2485 return 0; 2486 } 2487 2488 static irqreturn_t iqs7222_irq(int irq, void *context) 2489 { 2490 struct iqs7222_private *iqs7222 = context; 2491 2492 return iqs7222_report(iqs7222) ? IRQ_NONE : IRQ_HANDLED; 2493 } 2494 2495 static int iqs7222_probe(struct i2c_client *client) 2496 { 2497 struct iqs7222_private *iqs7222; 2498 unsigned long irq_flags; 2499 int error, irq; 2500 2501 iqs7222 = devm_kzalloc(&client->dev, sizeof(*iqs7222), GFP_KERNEL); 2502 if (!iqs7222) 2503 return -ENOMEM; 2504 2505 i2c_set_clientdata(client, iqs7222); 2506 iqs7222->client = client; 2507 2508 iqs7222->keypad = devm_input_allocate_device(&client->dev); 2509 if (!iqs7222->keypad) 2510 return -ENOMEM; 2511 2512 iqs7222->keypad->name = client->name; 2513 iqs7222->keypad->id.bustype = BUS_I2C; 2514 2515 /* 2516 * The RDY pin behaves as an interrupt, but must also be polled ahead 2517 * of unsolicited I2C communication. As such, it is first opened as a 2518 * GPIO and then passed to gpiod_to_irq() to register the interrupt. 2519 */ 2520 iqs7222->irq_gpio = devm_gpiod_get(&client->dev, "irq", GPIOD_IN); 2521 if (IS_ERR(iqs7222->irq_gpio)) { 2522 error = PTR_ERR(iqs7222->irq_gpio); 2523 dev_err(&client->dev, "Failed to request IRQ GPIO: %d\n", 2524 error); 2525 return error; 2526 } 2527 2528 iqs7222->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", 2529 GPIOD_OUT_HIGH); 2530 if (IS_ERR(iqs7222->reset_gpio)) { 2531 error = PTR_ERR(iqs7222->reset_gpio); 2532 dev_err(&client->dev, "Failed to request reset GPIO: %d\n", 2533 error); 2534 return error; 2535 } 2536 2537 error = iqs7222_hard_reset(iqs7222); 2538 if (error) 2539 return error; 2540 2541 error = iqs7222_dev_info(iqs7222); 2542 if (error) 2543 return error; 2544 2545 error = iqs7222_dev_init(iqs7222, READ); 2546 if (error) 2547 return error; 2548 2549 error = iqs7222_parse_all(iqs7222); 2550 if (error) 2551 return error; 2552 2553 error = iqs7222_dev_init(iqs7222, WRITE); 2554 if (error) 2555 return error; 2556 2557 error = iqs7222_report(iqs7222); 2558 if (error) 2559 return error; 2560 2561 error = input_register_device(iqs7222->keypad); 2562 if (error) { 2563 dev_err(&client->dev, "Failed to register device: %d\n", error); 2564 return error; 2565 } 2566 2567 irq = gpiod_to_irq(iqs7222->irq_gpio); 2568 if (irq < 0) 2569 return irq; 2570 2571 irq_flags = gpiod_is_active_low(iqs7222->irq_gpio) ? IRQF_TRIGGER_LOW 2572 : IRQF_TRIGGER_HIGH; 2573 irq_flags |= IRQF_ONESHOT; 2574 2575 error = devm_request_threaded_irq(&client->dev, irq, NULL, iqs7222_irq, 2576 irq_flags, client->name, iqs7222); 2577 if (error) 2578 dev_err(&client->dev, "Failed to request IRQ: %d\n", error); 2579 2580 return error; 2581 } 2582 2583 static const struct of_device_id iqs7222_of_match[] = { 2584 { .compatible = "azoteq,iqs7222a" }, 2585 { .compatible = "azoteq,iqs7222b" }, 2586 { .compatible = "azoteq,iqs7222c" }, 2587 { } 2588 }; 2589 MODULE_DEVICE_TABLE(of, iqs7222_of_match); 2590 2591 static struct i2c_driver iqs7222_i2c_driver = { 2592 .driver = { 2593 .name = "iqs7222", 2594 .of_match_table = iqs7222_of_match, 2595 }, 2596 .probe = iqs7222_probe, 2597 }; 2598 module_i2c_driver(iqs7222_i2c_driver); 2599 2600 MODULE_AUTHOR("Jeff LaBundy <jeff@labundy.com>"); 2601 MODULE_DESCRIPTION("Azoteq IQS7222A/B/C Capacitive Touch Controller"); 2602 MODULE_LICENSE("GPL"); 2603