1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2025 Griffin Kroah-Hartman <griffin.kroah@fairphone.com> 4 * 5 * Partially based on vendor driver: 6 * Copyright (c) 2021 AWINIC Technology CO., LTD 7 * 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/bits.h> 12 #include <linux/delay.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/i2c.h> 15 #include <linux/input.h> 16 #include <linux/module.h> 17 #include <linux/regmap.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/types.h> 20 21 #define AW86927_RSTCFG_REG 0x00 22 #define AW86927_RSTCFG_SOFTRST 0xaa 23 24 #define AW86927_SYSINT_REG 0x02 25 #define AW86927_SYSINT_BST_SCPI BIT(7) 26 #define AW86927_SYSINT_BST_OVPI BIT(6) 27 #define AW86927_SYSINT_UVLI BIT(5) 28 #define AW86927_SYSINT_FF_AEI BIT(4) 29 #define AW86927_SYSINT_FF_AFI BIT(3) 30 #define AW86927_SYSINT_OCDI BIT(2) 31 #define AW86927_SYSINT_OTI BIT(1) 32 #define AW86927_SYSINT_DONEI BIT(0) 33 34 #define AW86927_SYSINTM_REG 0x03 35 #define AW86927_SYSINTM_BST_OVPM BIT(6) 36 #define AW86927_SYSINTM_FF_AEM BIT(4) 37 #define AW86927_SYSINTM_FF_AFM BIT(3) 38 #define AW86927_SYSINTM_DONEM BIT(0) 39 40 #define AW86927_PLAYCFG1_REG 0x06 41 #define AW86927_PLAYCFG1_BST_MODE_MASK GENMASK(7, 7) 42 #define AW86927_PLAYCFG1_BST_MODE_BYPASS 0 43 #define AW86927_PLAYCFG1_BST_VOUT_VREFSET_MASK GENMASK(6, 0) 44 #define AW86927_PLAYCFG1_BST_8500MV 0x50 45 46 #define AW86938_PLAYCFG1_REG 0x06 47 #define AW86938_PLAYCFG1_BST_MODE_MASK GENMASK(5, 5) 48 #define AW86938_PLAYCFG1_BST_MODE_BYPASS 0 49 #define AW86938_PLAYCFG1_BST_VOUT_VREFSET_MASK GENMASK(4, 0) 50 #define AW86938_PLAYCFG1_BST_7000MV 0x11 51 52 #define AW86927_PLAYCFG2_REG 0x07 53 54 #define AW86927_PLAYCFG3_REG 0x08 55 #define AW86927_PLAYCFG3_AUTO_BST_MASK GENMASK(4, 4) 56 #define AW86927_PLAYCFG3_AUTO_BST_ENABLE 1 57 #define AW86927_PLAYCFG3_AUTO_BST_DISABLE 0 58 #define AW86927_PLAYCFG3_PLAY_MODE_MASK GENMASK(1, 0) 59 #define AW86927_PLAYCFG3_PLAY_MODE_RAM 0 60 61 #define AW86927_PLAYCFG4_REG 0x09 62 #define AW86927_PLAYCFG4_STOP BIT(1) 63 #define AW86927_PLAYCFG4_GO BIT(0) 64 65 #define AW86927_WAVCFG1_REG 0x0a 66 #define AW86927_WAVCFG1_WAVSEQ1_MASK GENMASK(6, 0) 67 68 #define AW86927_WAVCFG2_REG 0x0b 69 #define AW86927_WAVCFG2_WAVSEQ2_MASK GENMASK(6, 0) 70 71 #define AW86927_WAVCFG9_REG 0x12 72 #define AW86927_WAVCFG9_SEQ1LOOP_MASK GENMASK(7, 4) 73 #define AW86927_WAVCFG9_SEQ1LOOP_INFINITELY 0x0f 74 75 #define AW86927_CONTCFG1_REG 0x18 76 #define AW86927_CONTCFG1_BRK_BST_MD_MASK GENMASK(6, 6) 77 78 #define AW86927_CONTCFG5_REG 0x1c 79 #define AW86927_CONTCFG5_BST_BRK_GAIN_MASK GENMASK(7, 4) 80 #define AW86927_CONTCFG5_BRK_GAIN_MASK GENMASK(3, 0) 81 82 #define AW86927_CONTCFG10_REG 0x21 83 #define AW86927_CONTCFG10_BRK_TIME_MASK GENMASK(7, 0) 84 #define AW86927_CONTCFG10_BRK_TIME_DEFAULT 8 85 86 #define AW86927_CONTCFG13_REG 0x24 87 #define AW86927_CONTCFG13_TSET_MASK GENMASK(7, 4) 88 #define AW86927_CONTCFG13_BEME_SET_MASK GENMASK(3, 0) 89 90 #define AW86927_BASEADDRH_REG 0x2d 91 #define AW86927_BASEADDRL_REG 0x2e 92 93 #define AW86927_GLBRD5_REG 0x3f 94 #define AW86927_GLBRD5_STATE_MASK GENMASK(3, 0) 95 #define AW86927_GLBRD5_STATE_STANDBY 0 96 97 #define AW86927_RAMADDRH_REG 0x40 98 99 #define AW86927_RAMADDRL_REG 0x41 100 101 #define AW86927_RAMDATA_REG 0x42 102 103 #define AW86927_SYSCTRL3_REG 0x45 104 #define AW86927_SYSCTRL3_STANDBY_MASK GENMASK(5, 5) 105 #define AW86927_SYSCTRL3_STANDBY_ON 1 106 #define AW86927_SYSCTRL3_STANDBY_OFF 0 107 #define AW86927_SYSCTRL3_EN_RAMINIT_MASK GENMASK(2, 2) 108 #define AW86927_SYSCTRL3_EN_RAMINIT_ON 1 109 #define AW86927_SYSCTRL3_EN_RAMINIT_OFF 0 110 111 #define AW86927_SYSCTRL4_REG 0x46 112 #define AW86927_SYSCTRL4_WAVDAT_MODE_MASK GENMASK(6, 5) 113 #define AW86927_SYSCTRL4_WAVDAT_24K 0 114 #define AW86927_SYSCTRL4_INT_EDGE_MODE_MASK GENMASK(4, 4) 115 #define AW86927_SYSCTRL4_INT_EDGE_MODE_POS 0 116 #define AW86927_SYSCTRL4_INT_MODE_MASK GENMASK(3, 3) 117 #define AW86927_SYSCTRL4_INT_MODE_EDGE 1 118 #define AW86927_SYSCTRL4_GAIN_BYPASS_MASK GENMASK(0, 0) 119 120 #define AW86927_PWMCFG1_REG 0x48 121 #define AW86927_PWMCFG1_PRC_EN_MASK GENMASK(7, 7) 122 #define AW86927_PWMCFG1_PRC_DISABLE 0 123 124 #define AW86927_PWMCFG3_REG 0x4a 125 #define AW86927_PWMCFG3_PR_EN_MASK GENMASK(7, 7) 126 #define AW86927_PWMCFG3_PRCTIME_MASK GENMASK(6, 0) 127 128 #define AW86927_PWMCFG4_REG 0x4b 129 #define AW86927_PWMCFG4_PRTIME_MASK GENMASK(7, 0) 130 131 #define AW86927_VBATCTRL_REG 0x4c 132 #define AW86927_VBATCTRL_VBAT_MODE_MASK GENMASK(6, 6) 133 #define AW86927_VBATCTRL_VBAT_MODE_SW 0 134 135 #define AW86927_DETCFG1_REG 0x4d 136 #define AW86927_DETCFG1_DET_GO_MASK GENMASK(1, 0) 137 #define AW86927_DETCFG1_DET_GO_DET_SEQ0 1 138 #define AW86927_DETCFG1_DET_GO_NA 0 139 140 #define AW86927_DETCFG2_REG 0x4e 141 #define AW86927_DETCFG2_DET_SEQ0_MASK GENMASK(6, 3) 142 #define AW86927_DETCFG2_DET_SEQ0_VBAT 0 143 #define AW86927_DETCFG2_D2S_GAIN_MASK GENMASK(2, 0) 144 #define AW86927_DETCFG2_D2S_GAIN_10 4 145 146 #define AW86927_CHIPIDH_REG 0x57 147 #define AW86927_CHIPIDL_REG 0x58 148 #define AW86927_CHIPID 0x9270 149 #define AW86938_CHIPID 0x9380 150 151 #define AW86927_TMCFG_REG 0x5b 152 #define AW86927_TMCFG_UNLOCK 0x7d 153 #define AW86927_TMCFG_LOCK 0x00 154 155 #define AW86927_ANACFG11_REG 0x70 156 157 #define AW86927_ANACFG12_REG 0x71 158 #define AW86927_ANACFG12_BST_SKIP_MASK GENMASK(7, 7) 159 #define AW86927_ANACFG12_BST_SKIP_SHUTDOWN 1 160 161 #define AW86927_ANACFG13_REG 0x72 162 #define AW86927_ANACFG13_BST_PC_MASK GENMASK(7, 4) 163 #define AW86927_ANACFG13_BST_PEAKCUR_3P45A 6 164 165 #define AW86927_ANACFG15_REG 0x74 166 #define AW86927_ANACFG15_BST_PEAK_MODE_MASK GENMASK(7, 7) 167 #define AW86927_ANACFG15_BST_PEAK_BACK 1 168 169 #define AW86927_ANACFG16_REG 0x75 170 #define AW86927_ANACFG16_BST_SRC_MASK GENMASK(4, 4) 171 #define AW86927_ANACFG16_BST_SRC_3NS 0 172 173 /* default value of base addr */ 174 #define AW86927_RAM_BASE_ADDR 0x800 175 #define AW86927_BASEADDRH_VAL 0x08 176 #define AW86927_BASEADDRL_VAL 0x00 177 178 enum aw86927_work_mode { 179 AW86927_STANDBY_MODE, 180 AW86927_RAM_MODE, 181 }; 182 183 enum aw86927_model { 184 AW86927, 185 AW86938, 186 }; 187 188 struct aw86927_data { 189 enum aw86927_model model; 190 struct work_struct play_work; 191 struct device *dev; 192 struct input_dev *input_dev; 193 struct i2c_client *client; 194 struct regmap *regmap; 195 struct gpio_desc *reset_gpio; 196 u16 level; 197 }; 198 199 static const struct regmap_config aw86927_regmap_config = { 200 .reg_bits = 8, 201 .val_bits = 8, 202 .cache_type = REGCACHE_NONE, 203 .max_register = 0x80, 204 }; 205 206 /* 207 * Sine wave representing the magnitude of the drive to be used. 208 * Data is encoded in two's complement. 209 * round(84 * sin(x / 16.25)) 210 */ 211 static const u8 aw86927_waveform[] = { 212 0x00, 0x05, 0x0a, 0x0f, 0x14, 0x1a, 0x1f, 0x23, 0x28, 0x2d, 0x31, 0x35, 213 0x39, 0x3d, 0x41, 0x44, 0x47, 0x4a, 0x4c, 0x4f, 0x51, 0x52, 0x53, 0x54, 214 0x55, 0x55, 0x55, 0x55, 0x55, 0x54, 0x52, 0x51, 0x4f, 0x4d, 0x4a, 0x47, 215 0x44, 0x41, 0x3d, 0x3a, 0x36, 0x31, 0x2d, 0x28, 0x24, 0x1f, 0x1a, 0x15, 216 0x10, 0x0a, 0x05, 0x00, 0xfc, 0xf6, 0xf1, 0xec, 0xe7, 0xe2, 0xdd, 0xd8, 217 0xd4, 0xcf, 0xcb, 0xc7, 0xc3, 0xbf, 0xbc, 0xb9, 0xb6, 0xb4, 0xb1, 0xb0, 218 0xae, 0xad, 0xac, 0xab, 0xab, 0xab, 0xab, 0xab, 0xac, 0xae, 0xaf, 0xb1, 219 0xb3, 0xb6, 0xb8, 0xbc, 0xbf, 0xc2, 0xc6, 0xca, 0xce, 0xd3, 0xd7, 0xdc, 220 0xe1, 0xe6, 0xeb, 0xf0, 0xf5, 0xfb 221 }; 222 223 struct aw86927_sram_waveform_header { 224 u8 version; 225 __be16 start_address; 226 __be16 end_address; 227 } __packed; 228 229 static const struct aw86927_sram_waveform_header sram_waveform_header = { 230 .version = 0x01, 231 .start_address = cpu_to_be16(AW86927_RAM_BASE_ADDR + 232 sizeof(struct aw86927_sram_waveform_header)), 233 .end_address = cpu_to_be16(AW86927_RAM_BASE_ADDR + 234 sizeof(struct aw86927_sram_waveform_header) + 235 ARRAY_SIZE(aw86927_waveform) - 1), 236 }; 237 238 static int aw86927_wait_enter_standby(struct aw86927_data *haptics) 239 { 240 unsigned int reg_val; 241 int err; 242 243 err = regmap_read_poll_timeout(haptics->regmap, AW86927_GLBRD5_REG, reg_val, 244 (FIELD_GET(AW86927_GLBRD5_STATE_MASK, reg_val) == 245 AW86927_GLBRD5_STATE_STANDBY), 246 2500, 2500 * 100); 247 248 if (err) { 249 dev_err(haptics->dev, "did not enter standby: %d\n", err); 250 return err; 251 } 252 return 0; 253 } 254 255 static int aw86927_play_mode(struct aw86927_data *haptics, u8 play_mode) 256 { 257 int err; 258 259 switch (play_mode) { 260 case AW86927_STANDBY_MODE: 261 /* Briefly toggle standby, then toggle back to standby off */ 262 err = regmap_update_bits(haptics->regmap, 263 AW86927_SYSCTRL3_REG, 264 AW86927_SYSCTRL3_STANDBY_MASK, 265 FIELD_PREP(AW86927_SYSCTRL3_STANDBY_MASK, 266 AW86927_SYSCTRL3_STANDBY_ON)); 267 if (err) 268 return err; 269 270 err = regmap_update_bits(haptics->regmap, 271 AW86927_SYSCTRL3_REG, 272 AW86927_SYSCTRL3_STANDBY_MASK, 273 FIELD_PREP(AW86927_SYSCTRL3_STANDBY_MASK, 274 AW86927_SYSCTRL3_STANDBY_OFF)); 275 if (err) 276 return err; 277 278 break; 279 280 case AW86927_RAM_MODE: 281 err = regmap_update_bits(haptics->regmap, 282 AW86927_PLAYCFG3_REG, 283 AW86927_PLAYCFG3_PLAY_MODE_MASK, 284 FIELD_PREP(AW86927_PLAYCFG3_PLAY_MODE_MASK, 285 AW86927_PLAYCFG3_PLAY_MODE_RAM)); 286 if (err) 287 return err; 288 289 err = regmap_update_bits(haptics->regmap, 290 AW86927_PLAYCFG1_REG, 291 AW86927_PLAYCFG1_BST_MODE_MASK, 292 FIELD_PREP(AW86927_PLAYCFG1_BST_MODE_MASK, 293 AW86927_PLAYCFG1_BST_MODE_BYPASS)); 294 if (err) 295 return err; 296 297 err = regmap_update_bits(haptics->regmap, 298 AW86927_VBATCTRL_REG, 299 AW86927_VBATCTRL_VBAT_MODE_MASK, 300 FIELD_PREP(AW86927_VBATCTRL_VBAT_MODE_MASK, 301 AW86927_VBATCTRL_VBAT_MODE_SW)); 302 if (err) 303 return err; 304 305 break; 306 } 307 308 return 0; 309 } 310 311 static int aw86927_stop(struct aw86927_data *haptics) 312 { 313 int err; 314 315 err = regmap_write(haptics->regmap, AW86927_PLAYCFG4_REG, AW86927_PLAYCFG4_STOP); 316 if (err) { 317 dev_err(haptics->dev, "Failed to stop playback: %d\n", err); 318 return err; 319 } 320 321 err = aw86927_wait_enter_standby(haptics); 322 if (err) { 323 dev_err(haptics->dev, "Failed to enter standby, trying to force it\n"); 324 err = aw86927_play_mode(haptics, AW86927_STANDBY_MODE); 325 if (err) 326 return err; 327 } 328 329 return 0; 330 } 331 332 static int aw86927_haptics_play(struct input_dev *dev, void *data, struct ff_effect *effect) 333 { 334 struct aw86927_data *haptics = input_get_drvdata(dev); 335 int level; 336 337 level = effect->u.rumble.strong_magnitude; 338 if (!level) 339 level = effect->u.rumble.weak_magnitude; 340 341 /* If level does not change, don't restart playback */ 342 if (haptics->level == level) 343 return 0; 344 345 haptics->level = level; 346 347 schedule_work(&haptics->play_work); 348 349 return 0; 350 } 351 352 static int aw86927_play_sine(struct aw86927_data *haptics) 353 { 354 int err; 355 356 err = aw86927_stop(haptics); 357 if (err) 358 return err; 359 360 err = aw86927_play_mode(haptics, AW86927_RAM_MODE); 361 if (err) 362 return err; 363 364 err = regmap_update_bits(haptics->regmap, AW86927_PLAYCFG3_REG, 365 AW86927_PLAYCFG3_AUTO_BST_MASK, 366 FIELD_PREP(AW86927_PLAYCFG3_AUTO_BST_MASK, 367 AW86927_PLAYCFG3_AUTO_BST_ENABLE)); 368 if (err) 369 return err; 370 371 /* Set waveseq 1 to the first wave */ 372 err = regmap_update_bits(haptics->regmap, AW86927_WAVCFG1_REG, 373 AW86927_WAVCFG1_WAVSEQ1_MASK, 374 FIELD_PREP(AW86927_WAVCFG1_WAVSEQ1_MASK, 1)); 375 if (err) 376 return err; 377 378 /* set wavseq 2 to zero */ 379 err = regmap_update_bits(haptics->regmap, AW86927_WAVCFG2_REG, 380 AW86927_WAVCFG2_WAVSEQ2_MASK, 381 FIELD_PREP(AW86927_WAVCFG2_WAVSEQ2_MASK, 0)); 382 if (err) 383 return err; 384 385 err = regmap_update_bits(haptics->regmap, 386 AW86927_WAVCFG9_REG, 387 AW86927_WAVCFG9_SEQ1LOOP_MASK, 388 FIELD_PREP(AW86927_WAVCFG9_SEQ1LOOP_MASK, 389 AW86927_WAVCFG9_SEQ1LOOP_INFINITELY)); 390 if (err) 391 return err; 392 393 err = regmap_write(haptics->regmap, AW86927_PLAYCFG2_REG, haptics->level * 0x80 / 0xffff); 394 if (err) 395 return err; 396 397 /* Start playback */ 398 err = regmap_write(haptics->regmap, AW86927_PLAYCFG4_REG, AW86927_PLAYCFG4_GO); 399 if (err) 400 return err; 401 402 return 0; 403 } 404 405 static void aw86927_close(struct input_dev *input) 406 { 407 struct aw86927_data *haptics = input_get_drvdata(input); 408 struct device *dev = &haptics->client->dev; 409 int err; 410 411 cancel_work_sync(&haptics->play_work); 412 413 err = aw86927_stop(haptics); 414 if (err) 415 dev_err(dev, "Failed to close the Driver: %d\n", err); 416 } 417 418 static void aw86927_haptics_play_work(struct work_struct *work) 419 { 420 struct aw86927_data *haptics = 421 container_of(work, struct aw86927_data, play_work); 422 struct device *dev = &haptics->client->dev; 423 int err; 424 425 if (haptics->level) 426 err = aw86927_play_sine(haptics); 427 else 428 err = aw86927_stop(haptics); 429 430 if (err) 431 dev_err(dev, "Failed to execute work command: %d\n", err); 432 } 433 434 static void aw86927_hw_reset(struct aw86927_data *haptics) 435 { 436 /* Assert reset */ 437 gpiod_set_value_cansleep(haptics->reset_gpio, 1); 438 /* Wait ~1ms */ 439 usleep_range(1000, 2000); 440 /* Deassert reset */ 441 gpiod_set_value_cansleep(haptics->reset_gpio, 0); 442 /* Wait ~8ms until I2C is accessible */ 443 usleep_range(8000, 8500); 444 } 445 446 static int aw86927_haptic_init(struct aw86927_data *haptics) 447 { 448 int err; 449 450 err = regmap_update_bits(haptics->regmap, 451 AW86927_SYSCTRL4_REG, 452 AW86927_SYSCTRL4_WAVDAT_MODE_MASK, 453 FIELD_PREP(AW86927_SYSCTRL4_WAVDAT_MODE_MASK, 454 AW86927_SYSCTRL4_WAVDAT_24K)); 455 if (err) 456 return err; 457 458 /* enable gain bypass */ 459 err = regmap_update_bits(haptics->regmap, 460 AW86927_SYSCTRL4_REG, 461 AW86927_SYSCTRL4_GAIN_BYPASS_MASK, 462 FIELD_PREP(AW86927_SYSCTRL4_GAIN_BYPASS_MASK, 463 0x01)); 464 if (err) 465 return err; 466 467 err = regmap_write(haptics->regmap, 468 AW86927_TMCFG_REG, AW86927_TMCFG_UNLOCK); 469 if (err) 470 return err; 471 472 err = regmap_write(haptics->regmap, AW86927_ANACFG11_REG, 0x0f); 473 if (err) 474 return err; 475 476 err = regmap_update_bits(haptics->regmap, 477 AW86927_ANACFG12_REG, 478 AW86927_ANACFG12_BST_SKIP_MASK, 479 FIELD_PREP(AW86927_ANACFG12_BST_SKIP_MASK, 480 AW86927_ANACFG12_BST_SKIP_SHUTDOWN)); 481 if (err) 482 return err; 483 484 err = regmap_update_bits(haptics->regmap, 485 AW86927_ANACFG15_REG, 486 AW86927_ANACFG15_BST_PEAK_MODE_MASK, 487 FIELD_PREP(AW86927_ANACFG15_BST_PEAK_MODE_MASK, 488 AW86927_ANACFG15_BST_PEAK_BACK)); 489 if (err) 490 return err; 491 492 err = regmap_update_bits(haptics->regmap, 493 AW86927_ANACFG16_REG, 494 AW86927_ANACFG16_BST_SRC_MASK, 495 FIELD_PREP(AW86927_ANACFG16_BST_SRC_MASK, 496 AW86927_ANACFG16_BST_SRC_3NS)); 497 if (err) 498 return err; 499 500 err = regmap_write(haptics->regmap, 501 AW86927_TMCFG_REG, AW86927_TMCFG_LOCK); 502 if (err) 503 return err; 504 505 err = regmap_update_bits(haptics->regmap, 506 AW86927_CONTCFG1_REG, 507 AW86927_CONTCFG1_BRK_BST_MD_MASK, 508 FIELD_PREP(AW86927_CONTCFG1_BRK_BST_MD_MASK, 0x00)); 509 if (err) 510 return err; 511 512 err = regmap_write(haptics->regmap, 513 AW86927_CONTCFG5_REG, 514 FIELD_PREP(AW86927_CONTCFG5_BST_BRK_GAIN_MASK, 0x05) | 515 FIELD_PREP(AW86927_CONTCFG5_BRK_GAIN_MASK, 0x08)); 516 if (err) 517 return err; 518 519 err = regmap_update_bits(haptics->regmap, AW86927_CONTCFG10_REG, 520 AW86927_CONTCFG10_BRK_TIME_MASK, 521 FIELD_PREP(AW86927_CONTCFG10_BRK_TIME_MASK, 522 AW86927_CONTCFG10_BRK_TIME_DEFAULT)); 523 if (err) 524 return err; 525 526 err = regmap_write(haptics->regmap, 527 AW86927_CONTCFG13_REG, 528 FIELD_PREP(AW86927_CONTCFG13_TSET_MASK, 0x06) | 529 FIELD_PREP(AW86927_CONTCFG13_BEME_SET_MASK, 0x02)); 530 if (err) 531 return err; 532 533 err = regmap_update_bits(haptics->regmap, 534 AW86927_DETCFG2_REG, 535 AW86927_DETCFG2_D2S_GAIN_MASK, 536 FIELD_PREP(AW86927_DETCFG2_D2S_GAIN_MASK, 537 AW86927_DETCFG2_D2S_GAIN_10)); 538 if (err) 539 return err; 540 541 err = regmap_update_bits(haptics->regmap, 542 AW86927_PWMCFG1_REG, 543 AW86927_PWMCFG1_PRC_EN_MASK, 544 FIELD_PREP(AW86927_PWMCFG1_PRC_EN_MASK, 545 AW86927_PWMCFG1_PRC_DISABLE)); 546 if (err) 547 return err; 548 549 err = regmap_write(haptics->regmap, 550 AW86927_PWMCFG3_REG, 551 FIELD_PREP(AW86927_PWMCFG3_PR_EN_MASK, 0x01) | 552 FIELD_PREP(AW86927_PWMCFG3_PRCTIME_MASK, 0x3f)); 553 if (err) 554 return err; 555 556 err = regmap_update_bits(haptics->regmap, 557 AW86927_PWMCFG4_REG, 558 AW86927_PWMCFG4_PRTIME_MASK, 559 FIELD_PREP(AW86927_PWMCFG4_PRTIME_MASK, 0x32)); 560 if (err) 561 return err; 562 563 err = regmap_write(haptics->regmap, 564 AW86927_TMCFG_REG, AW86927_TMCFG_UNLOCK); 565 if (err) 566 return err; 567 568 err = regmap_update_bits(haptics->regmap, 569 AW86927_ANACFG13_REG, 570 AW86927_ANACFG13_BST_PC_MASK, 571 FIELD_PREP(AW86927_ANACFG13_BST_PC_MASK, 572 AW86927_ANACFG13_BST_PEAKCUR_3P45A)); 573 if (err) 574 return err; 575 576 err = regmap_write(haptics->regmap, 577 AW86927_TMCFG_REG, AW86927_TMCFG_LOCK); 578 if (err) 579 return err; 580 581 switch (haptics->model) { 582 case AW86927: 583 err = regmap_update_bits(haptics->regmap, 584 AW86927_PLAYCFG1_REG, 585 AW86927_PLAYCFG1_BST_VOUT_VREFSET_MASK, 586 FIELD_PREP(AW86927_PLAYCFG1_BST_VOUT_VREFSET_MASK, 587 AW86927_PLAYCFG1_BST_8500MV)); 588 if (err) 589 return err; 590 break; 591 case AW86938: 592 err = regmap_update_bits(haptics->regmap, 593 AW86938_PLAYCFG1_REG, 594 AW86938_PLAYCFG1_BST_VOUT_VREFSET_MASK, 595 FIELD_PREP(AW86938_PLAYCFG1_BST_VOUT_VREFSET_MASK, 596 AW86938_PLAYCFG1_BST_7000MV)); 597 if (err) 598 return err; 599 break; 600 } 601 602 err = regmap_update_bits(haptics->regmap, 603 AW86927_PLAYCFG3_REG, 604 AW86927_PLAYCFG3_AUTO_BST_MASK, 605 FIELD_PREP(AW86927_PLAYCFG3_AUTO_BST_MASK, 606 AW86927_PLAYCFG3_AUTO_BST_DISABLE)); 607 if (err) 608 return err; 609 610 return 0; 611 } 612 613 static int aw86927_ram_init(struct aw86927_data *haptics) 614 { 615 int err; 616 617 err = aw86927_wait_enter_standby(haptics); 618 if (err) 619 return err; 620 621 /* Enable SRAM init */ 622 err = regmap_update_bits(haptics->regmap, 623 AW86927_SYSCTRL3_REG, 624 AW86927_SYSCTRL3_EN_RAMINIT_MASK, 625 FIELD_PREP(AW86927_SYSCTRL3_EN_RAMINIT_MASK, 626 AW86927_SYSCTRL3_EN_RAMINIT_ON)); 627 628 /* AW86938 wants a 1ms delay here */ 629 usleep_range(1000, 1500); 630 631 /* Set base address for the start of the SRAM waveforms */ 632 err = regmap_write(haptics->regmap, 633 AW86927_BASEADDRH_REG, AW86927_BASEADDRH_VAL); 634 if (err) 635 return err; 636 637 err = regmap_write(haptics->regmap, 638 AW86927_BASEADDRL_REG, AW86927_BASEADDRL_VAL); 639 if (err) 640 return err; 641 642 /* Set start of SRAM, before the data is written it will be the same as the base */ 643 err = regmap_write(haptics->regmap, 644 AW86927_RAMADDRH_REG, AW86927_BASEADDRH_VAL); 645 if (err) 646 return err; 647 648 err = regmap_write(haptics->regmap, 649 AW86927_RAMADDRL_REG, AW86927_BASEADDRL_VAL); 650 if (err) 651 return err; 652 653 /* Write waveform header to SRAM */ 654 err = regmap_noinc_write(haptics->regmap, AW86927_RAMDATA_REG, 655 &sram_waveform_header, sizeof(sram_waveform_header)); 656 if (err) 657 return err; 658 659 /* Write waveform to SRAM */ 660 err = regmap_noinc_write(haptics->regmap, AW86927_RAMDATA_REG, 661 aw86927_waveform, ARRAY_SIZE(aw86927_waveform)); 662 if (err) 663 return err; 664 665 err = regmap_update_bits(haptics->regmap, 666 AW86927_DETCFG2_REG, 667 AW86927_DETCFG2_DET_SEQ0_MASK, 668 FIELD_PREP(AW86927_DETCFG2_DET_SEQ0_MASK, 669 AW86927_DETCFG2_DET_SEQ0_VBAT)); 670 if (err) 671 return err; 672 673 err = regmap_update_bits(haptics->regmap, 674 AW86927_DETCFG1_REG, 675 AW86927_DETCFG1_DET_GO_MASK, 676 FIELD_PREP(AW86927_DETCFG1_DET_GO_MASK, 677 AW86927_DETCFG1_DET_GO_DET_SEQ0)); 678 if (err) 679 return err; 680 681 usleep_range(3000, 3500); 682 683 err = regmap_update_bits(haptics->regmap, 684 AW86927_DETCFG1_REG, 685 AW86927_DETCFG1_DET_GO_MASK, 686 FIELD_PREP(AW86927_DETCFG1_DET_GO_MASK, 687 AW86927_DETCFG1_DET_GO_NA)); 688 if (err) 689 return err; 690 691 /* Disable SRAM init */ 692 err = regmap_update_bits(haptics->regmap, 693 AW86927_SYSCTRL3_REG, 694 AW86927_SYSCTRL3_EN_RAMINIT_MASK, 695 FIELD_PREP(AW86927_SYSCTRL3_EN_RAMINIT_MASK, 696 AW86927_SYSCTRL3_EN_RAMINIT_OFF)); 697 if (err) 698 return err; 699 700 return 0; 701 } 702 703 static irqreturn_t aw86927_irq(int irq, void *data) 704 { 705 struct aw86927_data *haptics = data; 706 struct device *dev = &haptics->client->dev; 707 unsigned int reg_val; 708 int err; 709 710 err = regmap_read(haptics->regmap, AW86927_SYSINT_REG, ®_val); 711 if (err) { 712 dev_err(dev, "Failed to read SYSINT register: %d\n", err); 713 return IRQ_NONE; 714 } 715 716 if (reg_val & AW86927_SYSINT_BST_SCPI) 717 dev_err(dev, "Received a Short Circuit Protection interrupt\n"); 718 if (reg_val & AW86927_SYSINT_BST_OVPI) 719 dev_err(dev, "Received an Over Voltage Protection interrupt\n"); 720 if (reg_val & AW86927_SYSINT_UVLI) 721 dev_err(dev, "Received an Under Voltage Lock Out interrupt\n"); 722 if (reg_val & AW86927_SYSINT_OCDI) 723 dev_err(dev, "Received an Over Current interrupt\n"); 724 if (reg_val & AW86927_SYSINT_OTI) 725 dev_err(dev, "Received an Over Temperature interrupt\n"); 726 727 if (reg_val & AW86927_SYSINT_DONEI) 728 dev_dbg(dev, "Chip playback done!\n"); 729 if (reg_val & AW86927_SYSINT_FF_AFI) 730 dev_dbg(dev, "The RTP mode FIFO is almost full!\n"); 731 if (reg_val & AW86927_SYSINT_FF_AEI) 732 dev_dbg(dev, "The RTP mode FIFO is almost empty!\n"); 733 734 return IRQ_HANDLED; 735 } 736 737 static int aw86927_detect(struct aw86927_data *haptics) 738 { 739 __be16 read_buf; 740 u16 chip_id; 741 int err; 742 743 err = regmap_bulk_read(haptics->regmap, AW86927_CHIPIDH_REG, &read_buf, 2); 744 if (err) 745 return dev_err_probe(haptics->dev, err, "Failed to read CHIPID registers\n"); 746 747 chip_id = be16_to_cpu(read_buf); 748 749 switch (chip_id) { 750 case AW86927_CHIPID: 751 haptics->model = AW86927; 752 break; 753 case AW86938_CHIPID: 754 haptics->model = AW86938; 755 break; 756 default: 757 dev_err(haptics->dev, "Unexpected CHIPID value 0x%x\n", chip_id); 758 return -ENODEV; 759 } 760 761 return 0; 762 } 763 764 static int aw86927_probe(struct i2c_client *client) 765 { 766 struct aw86927_data *haptics; 767 int err; 768 769 haptics = devm_kzalloc(&client->dev, sizeof(struct aw86927_data), GFP_KERNEL); 770 if (!haptics) 771 return -ENOMEM; 772 773 haptics->dev = &client->dev; 774 haptics->client = client; 775 776 i2c_set_clientdata(client, haptics); 777 778 haptics->regmap = devm_regmap_init_i2c(client, &aw86927_regmap_config); 779 if (IS_ERR(haptics->regmap)) 780 return dev_err_probe(haptics->dev, PTR_ERR(haptics->regmap), 781 "Failed to allocate register map\n"); 782 783 haptics->input_dev = devm_input_allocate_device(haptics->dev); 784 if (!haptics->input_dev) 785 return -ENOMEM; 786 787 haptics->reset_gpio = devm_gpiod_get(haptics->dev, "reset", GPIOD_OUT_HIGH); 788 if (IS_ERR(haptics->reset_gpio)) 789 return dev_err_probe(haptics->dev, PTR_ERR(haptics->reset_gpio), 790 "Failed to get reset gpio\n"); 791 792 /* Hardware reset */ 793 aw86927_hw_reset(haptics); 794 795 /* Software reset */ 796 err = regmap_write(haptics->regmap, AW86927_RSTCFG_REG, AW86927_RSTCFG_SOFTRST); 797 if (err) 798 return dev_err_probe(haptics->dev, err, "Failed Software reset\n"); 799 800 /* Wait ~3ms until I2C is accessible */ 801 usleep_range(3000, 3500); 802 803 err = aw86927_detect(haptics); 804 if (err) 805 return dev_err_probe(haptics->dev, err, "Failed to find chip\n"); 806 807 /* IRQ config */ 808 err = regmap_write(haptics->regmap, AW86927_SYSCTRL4_REG, 809 FIELD_PREP(AW86927_SYSCTRL4_INT_MODE_MASK, 810 AW86927_SYSCTRL4_INT_MODE_EDGE) | 811 FIELD_PREP(AW86927_SYSCTRL4_INT_EDGE_MODE_MASK, 812 AW86927_SYSCTRL4_INT_EDGE_MODE_POS)); 813 if (err) 814 return dev_err_probe(haptics->dev, err, "Failed to configure interrupt modes\n"); 815 816 err = regmap_write(haptics->regmap, AW86927_SYSINTM_REG, 817 AW86927_SYSINTM_BST_OVPM | 818 AW86927_SYSINTM_FF_AEM | 819 AW86927_SYSINTM_FF_AFM | 820 AW86927_SYSINTM_DONEM); 821 if (err) 822 return dev_err_probe(haptics->dev, err, "Failed to configure interrupt masks\n"); 823 824 err = devm_request_threaded_irq(haptics->dev, client->irq, NULL, 825 aw86927_irq, IRQF_ONESHOT, NULL, haptics); 826 if (err) 827 return dev_err_probe(haptics->dev, err, "Failed to request threaded irq\n"); 828 829 INIT_WORK(&haptics->play_work, aw86927_haptics_play_work); 830 831 haptics->input_dev->name = "aw86927-haptics"; 832 haptics->input_dev->close = aw86927_close; 833 834 input_set_drvdata(haptics->input_dev, haptics); 835 input_set_capability(haptics->input_dev, EV_FF, FF_RUMBLE); 836 837 err = input_ff_create_memless(haptics->input_dev, NULL, aw86927_haptics_play); 838 if (err) 839 return dev_err_probe(haptics->dev, err, "Failed to create FF dev\n"); 840 841 /* Set up registers */ 842 err = aw86927_play_mode(haptics, AW86927_STANDBY_MODE); 843 if (err) 844 return dev_err_probe(haptics->dev, err, 845 "Failed to enter standby for Haptic init\n"); 846 847 err = aw86927_haptic_init(haptics); 848 if (err) 849 return dev_err_probe(haptics->dev, err, "Haptic init failed\n"); 850 851 /* RAM init, upload the waveform for playback */ 852 err = aw86927_ram_init(haptics); 853 if (err) 854 return dev_err_probe(haptics->dev, err, "Failed to init aw86927 sram\n"); 855 856 err = input_register_device(haptics->input_dev); 857 if (err) 858 return dev_err_probe(haptics->dev, err, "Failed to register input device\n"); 859 860 return 0; 861 } 862 863 static const struct of_device_id aw86927_of_id[] = { 864 { .compatible = "awinic,aw86927" }, 865 { /* sentinel */ } 866 }; 867 868 MODULE_DEVICE_TABLE(of, aw86927_of_id); 869 870 static struct i2c_driver aw86927_driver = { 871 .driver = { 872 .name = "aw86927-haptics", 873 .of_match_table = aw86927_of_id, 874 }, 875 .probe = aw86927_probe, 876 }; 877 878 module_i2c_driver(aw86927_driver); 879 880 MODULE_AUTHOR("Griffin Kroah-Hartman <griffin.kroah@fairphone.com>"); 881 MODULE_DESCRIPTION("AWINIC AW86927 LRA Haptic Driver"); 882 MODULE_LICENSE("GPL"); 883