1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 3 /* Authors: Bernard Metzler <bmt@zurich.ibm.com> */ 4 /* Copyright (c) 2008-2019, IBM Corporation */ 5 6 #ifndef _SIW_H 7 #define _SIW_H 8 9 #include <rdma/ib_verbs.h> 10 #include <rdma/restrack.h> 11 #include <linux/socket.h> 12 #include <linux/skbuff.h> 13 #include <crypto/hash.h> 14 #include <linux/crc32.h> 15 #include <linux/crc32c.h> 16 17 #include <rdma/siw-abi.h> 18 #include "iwarp.h" 19 20 #define SIW_VENDOR_ID 0x626d74 /* ascii 'bmt' for now */ 21 #define SIW_VENDORT_PART_ID 0 22 #define SIW_MAX_QP (1024 * 100) 23 #define SIW_MAX_QP_WR (1024 * 32) 24 #define SIW_MAX_ORD_QP 128 25 #define SIW_MAX_IRD_QP 128 26 #define SIW_MAX_SGE_PBL 256 /* max num sge's for PBL */ 27 #define SIW_MAX_SGE_RD 1 /* iwarp limitation. we could relax */ 28 #define SIW_MAX_CQ (1024 * 100) 29 #define SIW_MAX_CQE (SIW_MAX_QP_WR * 100) 30 #define SIW_MAX_MR (SIW_MAX_QP * 10) 31 #define SIW_MAX_PD SIW_MAX_QP 32 #define SIW_MAX_MW 0 /* to be set if MW's are supported */ 33 #define SIW_MAX_SRQ SIW_MAX_QP 34 #define SIW_MAX_SRQ_WR (SIW_MAX_QP_WR * 10) 35 #define SIW_MAX_CONTEXT SIW_MAX_PD 36 37 /* Min number of bytes for using zero copy transmit */ 38 #define SENDPAGE_THRESH PAGE_SIZE 39 40 /* Maximum number of frames which can be send in one SQ processing */ 41 #define SQ_USER_MAXBURST 100 42 43 /* Maximum number of consecutive IRQ elements which get served 44 * if SQ has pending work. Prevents starving local SQ processing 45 * by serving peer Read Requests. 46 */ 47 #define SIW_IRQ_MAXBURST_SQ_ACTIVE 4 48 49 /* There is always only a port 1 per siw device */ 50 #define SIW_PORT 1 51 52 struct siw_dev_cap { 53 int max_qp; 54 int max_qp_wr; 55 int max_ord; /* max. outbound read queue depth */ 56 int max_ird; /* max. inbound read queue depth */ 57 int max_sge; 58 int max_sge_rd; 59 int max_cq; 60 int max_cqe; 61 int max_mr; 62 int max_pd; 63 int max_mw; 64 int max_srq; 65 int max_srq_wr; 66 int max_srq_sge; 67 }; 68 69 struct siw_pd { 70 struct ib_pd base_pd; 71 }; 72 73 struct siw_device { 74 struct ib_device base_dev; 75 struct siw_dev_cap attrs; 76 77 u32 vendor_part_id; 78 int numa_node; 79 char raw_gid[ETH_ALEN]; 80 81 spinlock_t lock; 82 83 struct xarray qp_xa; 84 struct xarray mem_xa; 85 86 struct list_head cep_list; 87 struct list_head qp_list; 88 89 /* active objects statistics to enforce limits */ 90 atomic_t num_qp; 91 atomic_t num_cq; 92 atomic_t num_pd; 93 atomic_t num_mr; 94 atomic_t num_srq; 95 atomic_t num_ctx; 96 }; 97 98 struct siw_ucontext { 99 struct ib_ucontext base_ucontext; 100 struct siw_device *sdev; 101 }; 102 103 /* 104 * The RDMA core does not define LOCAL_READ access, which is always 105 * enabled implictely. 106 */ 107 #define IWARP_ACCESS_MASK \ 108 (IB_ACCESS_LOCAL_WRITE | IB_ACCESS_REMOTE_WRITE | \ 109 IB_ACCESS_REMOTE_READ) 110 111 /* 112 * siw presentation of user memory registered as source 113 * or target of RDMA operations. 114 */ 115 116 struct siw_page_chunk { 117 struct page **plist; 118 }; 119 120 struct siw_umem { 121 struct ib_umem *base_mem; 122 struct siw_page_chunk *page_chunk; 123 int num_pages; 124 u64 fp_addr; /* First page base address */ 125 }; 126 127 struct siw_pble { 128 dma_addr_t addr; /* Address of assigned buffer */ 129 unsigned int size; /* Size of this entry */ 130 unsigned long pbl_off; /* Total offset from start of PBL */ 131 }; 132 133 struct siw_pbl { 134 unsigned int num_buf; 135 unsigned int max_buf; 136 struct siw_pble pbe[] __counted_by(max_buf); 137 }; 138 139 /* 140 * Generic memory representation for registered siw memory. 141 * Memory lookup always via higher 24 bit of STag (STag index). 142 */ 143 struct siw_mem { 144 struct siw_device *sdev; 145 struct kref ref; 146 u64 va; /* VA of memory */ 147 u64 len; /* length of the memory buffer in bytes */ 148 u32 stag; /* iWarp memory access steering tag */ 149 u8 stag_valid; /* VALID or INVALID */ 150 u8 is_pbl; /* PBL or user space mem */ 151 u8 is_mw; /* Memory Region or Memory Window */ 152 enum ib_access_flags perms; /* local/remote READ & WRITE */ 153 union { 154 struct siw_umem *umem; 155 struct siw_pbl *pbl; 156 void *mem_obj; 157 }; 158 struct ib_pd *pd; 159 }; 160 161 struct siw_mr { 162 struct ib_mr base_mr; 163 struct siw_mem *mem; 164 struct rcu_head rcu; 165 }; 166 167 /* 168 * Error codes for local or remote 169 * access to registered memory 170 */ 171 enum siw_access_state { 172 E_ACCESS_OK, 173 E_STAG_INVALID, 174 E_BASE_BOUNDS, 175 E_ACCESS_PERM, 176 E_PD_MISMATCH 177 }; 178 179 enum siw_wr_state { 180 SIW_WR_IDLE, 181 SIW_WR_QUEUED, /* processing has not started yet */ 182 SIW_WR_INPROGRESS /* initiated processing of the WR */ 183 }; 184 185 /* The WQE currently being processed (RX or TX) */ 186 struct siw_wqe { 187 /* Copy of applications SQE or RQE */ 188 union { 189 struct siw_sqe sqe; 190 struct siw_rqe rqe; 191 }; 192 struct siw_mem *mem[SIW_MAX_SGE]; /* per sge's resolved mem */ 193 enum siw_wr_state wr_status; 194 enum siw_wc_status wc_status; 195 u32 bytes; /* total bytes to process */ 196 u32 processed; /* bytes processed */ 197 }; 198 199 struct siw_cq { 200 struct ib_cq base_cq; 201 spinlock_t lock; 202 struct siw_cq_ctrl *notify; 203 struct siw_cqe *queue; 204 u32 cq_put; 205 u32 cq_get; 206 u32 num_cqe; 207 struct rdma_user_mmap_entry *cq_entry; /* mmap info for CQE array */ 208 u32 id; /* For debugging only */ 209 }; 210 211 enum siw_qp_state { 212 SIW_QP_STATE_IDLE, 213 SIW_QP_STATE_RTR, 214 SIW_QP_STATE_RTS, 215 SIW_QP_STATE_CLOSING, 216 SIW_QP_STATE_TERMINATE, 217 SIW_QP_STATE_ERROR, 218 SIW_QP_STATE_COUNT 219 }; 220 221 enum siw_qp_flags { 222 SIW_RDMA_BIND_ENABLED = (1 << 0), 223 SIW_RDMA_WRITE_ENABLED = (1 << 1), 224 SIW_RDMA_READ_ENABLED = (1 << 2), 225 SIW_SIGNAL_ALL_WR = (1 << 3), 226 SIW_MPA_CRC = (1 << 4), 227 SIW_QP_IN_DESTROY = (1 << 5) 228 }; 229 230 enum siw_qp_attr_mask { 231 SIW_QP_ATTR_STATE = (1 << 0), 232 SIW_QP_ATTR_ACCESS_FLAGS = (1 << 1), 233 SIW_QP_ATTR_LLP_HANDLE = (1 << 2), 234 SIW_QP_ATTR_ORD = (1 << 3), 235 SIW_QP_ATTR_IRD = (1 << 4), 236 SIW_QP_ATTR_SQ_SIZE = (1 << 5), 237 SIW_QP_ATTR_RQ_SIZE = (1 << 6), 238 SIW_QP_ATTR_MPA = (1 << 7) 239 }; 240 241 struct siw_srq { 242 struct ib_srq base_srq; 243 spinlock_t lock; 244 u32 max_sge; 245 u32 limit; /* low watermark for async event */ 246 struct siw_rqe *recvq; 247 u32 rq_put; 248 u32 rq_get; 249 u32 num_rqe; /* max # of wqe's allowed */ 250 struct rdma_user_mmap_entry *srq_entry; /* mmap info for SRQ array */ 251 bool armed:1; /* inform user if limit hit */ 252 bool is_kernel_res:1; /* true if kernel client */ 253 }; 254 255 struct siw_qp_attrs { 256 enum siw_qp_state state; 257 u32 sq_size; 258 u32 rq_size; 259 u32 orq_size; 260 u32 irq_size; 261 u32 sq_max_sges; 262 u32 rq_max_sges; 263 enum siw_qp_flags flags; 264 265 struct socket *sk; 266 }; 267 268 enum siw_tx_ctx { 269 SIW_SEND_HDR, /* start or continue sending HDR */ 270 SIW_SEND_DATA, /* start or continue sending DDP payload */ 271 SIW_SEND_TRAILER, /* start or continue sending TRAILER */ 272 SIW_SEND_SHORT_FPDU/* send whole FPDU hdr|data|trailer at once */ 273 }; 274 275 enum siw_rx_state { 276 SIW_GET_HDR, /* await new hdr or within hdr */ 277 SIW_GET_DATA_START, /* start of inbound DDP payload */ 278 SIW_GET_DATA_MORE, /* continuation of (misaligned) DDP payload */ 279 SIW_GET_TRAILER/* await new trailer or within trailer */ 280 }; 281 282 struct siw_rx_stream { 283 struct sk_buff *skb; 284 int skb_new; /* pending unread bytes in skb */ 285 int skb_offset; /* offset in skb */ 286 int skb_copied; /* processed bytes in skb */ 287 288 enum siw_rx_state state; 289 290 union iwarp_hdr hdr; 291 struct mpa_trailer trailer; 292 struct shash_desc *mpa_crc_hd; 293 294 /* 295 * For each FPDU, main RX loop runs through 3 stages: 296 * Receiving protocol headers, placing DDP payload and receiving 297 * trailer information (CRC + possibly padding). 298 * Next two variables keep state on receive status of the 299 * current FPDU part (hdr, data, trailer). 300 */ 301 int fpdu_part_rcvd; /* bytes in pkt part copied */ 302 int fpdu_part_rem; /* bytes in pkt part not seen */ 303 304 /* 305 * Next expected DDP MSN for each QN + 306 * expected steering tag + 307 * expected DDP tagget offset (all HBO) 308 */ 309 u32 ddp_msn[RDMAP_UNTAGGED_QN_COUNT]; 310 u32 ddp_stag; 311 u64 ddp_to; 312 u32 inval_stag; /* Stag to be invalidated */ 313 314 u8 rx_suspend : 1; 315 u8 pad : 2; /* # of pad bytes expected */ 316 u8 rdmap_op : 4; /* opcode of current frame */ 317 }; 318 319 struct siw_rx_fpdu { 320 /* 321 * Local destination memory of inbound RDMA operation. 322 * Valid, according to wqe->wr_status 323 */ 324 struct siw_wqe wqe_active; 325 326 unsigned int pbl_idx; /* Index into current PBL */ 327 unsigned int sge_idx; /* current sge in rx */ 328 unsigned int sge_off; /* already rcvd in curr. sge */ 329 330 char first_ddp_seg; /* this is the first DDP seg */ 331 char more_ddp_segs; /* more DDP segs expected */ 332 u8 prev_rdmap_op : 4; /* opcode of prev frame */ 333 }; 334 335 /* 336 * Shorthands for short packets w/o payload 337 * to be transmitted more efficient. 338 */ 339 struct siw_send_pkt { 340 struct iwarp_send send; 341 __be32 crc; 342 }; 343 344 struct siw_write_pkt { 345 struct iwarp_rdma_write write; 346 __be32 crc; 347 }; 348 349 struct siw_rreq_pkt { 350 struct iwarp_rdma_rreq rreq; 351 __be32 crc; 352 }; 353 354 struct siw_rresp_pkt { 355 struct iwarp_rdma_rresp rresp; 356 __be32 crc; 357 }; 358 359 struct siw_iwarp_tx { 360 union { 361 union iwarp_hdr hdr; 362 363 /* Generic part of FPDU header */ 364 struct iwarp_ctrl ctrl; 365 struct iwarp_ctrl_untagged c_untagged; 366 struct iwarp_ctrl_tagged c_tagged; 367 368 /* FPDU headers */ 369 struct iwarp_rdma_write rwrite; 370 struct iwarp_rdma_rreq rreq; 371 struct iwarp_rdma_rresp rresp; 372 struct iwarp_terminate terminate; 373 struct iwarp_send send; 374 struct iwarp_send_inv send_inv; 375 376 /* complete short FPDUs */ 377 struct siw_send_pkt send_pkt; 378 struct siw_write_pkt write_pkt; 379 struct siw_rreq_pkt rreq_pkt; 380 struct siw_rresp_pkt rresp_pkt; 381 } pkt; 382 383 struct mpa_trailer trailer; 384 /* DDP MSN for untagged messages */ 385 u32 ddp_msn[RDMAP_UNTAGGED_QN_COUNT]; 386 387 enum siw_tx_ctx state; 388 u16 ctrl_len; /* ddp+rdmap hdr */ 389 u16 ctrl_sent; 390 int burst; 391 int bytes_unsent; /* ddp payload bytes */ 392 393 struct shash_desc *mpa_crc_hd; 394 395 u8 do_crc : 1; /* do crc for segment */ 396 u8 use_sendpage : 1; /* send w/o copy */ 397 u8 tx_suspend : 1; /* stop sending DDP segs. */ 398 u8 pad : 2; /* # pad in current fpdu */ 399 u8 orq_fence : 1; /* ORQ full or Send fenced */ 400 u8 in_syscall : 1; /* TX out of user context */ 401 u8 zcopy_tx : 1; /* Use TCP_SENDPAGE if possible */ 402 u8 gso_seg_limit; /* Maximum segments for GSO, 0 = unbound */ 403 404 u16 fpdu_len; /* len of FPDU to tx */ 405 unsigned int tcp_seglen; /* remaining tcp seg space */ 406 407 struct siw_wqe wqe_active; 408 409 int pbl_idx; /* Index into current PBL */ 410 int sge_idx; /* current sge in tx */ 411 u32 sge_off; /* already sent in curr. sge */ 412 }; 413 414 struct siw_qp { 415 struct ib_qp base_qp; 416 struct siw_device *sdev; 417 int tx_cpu; 418 struct kref ref; 419 struct completion qp_free; 420 struct list_head devq; 421 struct siw_qp_attrs attrs; 422 423 struct siw_cep *cep; 424 struct rw_semaphore state_lock; 425 426 struct ib_pd *pd; 427 struct siw_cq *scq; 428 struct siw_cq *rcq; 429 struct siw_srq *srq; 430 431 struct siw_iwarp_tx tx_ctx; /* Transmit context */ 432 spinlock_t sq_lock; 433 struct siw_sqe *sendq; /* send queue element array */ 434 uint32_t sq_get; /* consumer index into sq array */ 435 uint32_t sq_put; /* kernel prod. index into sq array */ 436 struct llist_node tx_list; 437 438 struct siw_sqe *orq; /* outbound read queue element array */ 439 spinlock_t orq_lock; 440 uint32_t orq_get; /* consumer index into orq array */ 441 uint32_t orq_put; /* shared producer index for ORQ */ 442 443 struct siw_rx_stream rx_stream; 444 struct siw_rx_fpdu *rx_fpdu; 445 struct siw_rx_fpdu rx_tagged; 446 struct siw_rx_fpdu rx_untagged; 447 spinlock_t rq_lock; 448 struct siw_rqe *recvq; /* recv queue element array */ 449 uint32_t rq_get; /* consumer index into rq array */ 450 uint32_t rq_put; /* kernel prod. index into rq array */ 451 452 struct siw_sqe *irq; /* inbound read queue element array */ 453 uint32_t irq_get; /* consumer index into irq array */ 454 uint32_t irq_put; /* producer index into irq array */ 455 int irq_burst; 456 457 struct { /* information to be carried in TERMINATE pkt, if valid */ 458 u8 valid; 459 u8 in_tx; 460 u8 layer : 4, etype : 4; 461 u8 ecode; 462 } term_info; 463 struct rdma_user_mmap_entry *sq_entry; /* mmap info for SQE array */ 464 struct rdma_user_mmap_entry *rq_entry; /* mmap info for RQE array */ 465 }; 466 467 /* helper macros */ 468 #define rx_qp(rx) container_of(rx, struct siw_qp, rx_stream) 469 #define tx_qp(tx) container_of(tx, struct siw_qp, tx_ctx) 470 #define tx_wqe(qp) (&(qp)->tx_ctx.wqe_active) 471 #define rx_wqe(rctx) (&(rctx)->wqe_active) 472 #define rx_mem(rctx) ((rctx)->wqe_active.mem[0]) 473 #define tx_type(wqe) ((wqe)->sqe.opcode) 474 #define rx_type(wqe) ((wqe)->rqe.opcode) 475 #define tx_flags(wqe) ((wqe)->sqe.flags) 476 477 struct iwarp_msg_info { 478 int hdr_len; 479 struct iwarp_ctrl ctrl; 480 int (*rx_data)(struct siw_qp *qp); 481 }; 482 483 struct siw_user_mmap_entry { 484 struct rdma_user_mmap_entry rdma_entry; 485 void *address; 486 }; 487 488 /* Global siw parameters. Currently set in siw_main.c */ 489 extern const bool zcopy_tx; 490 extern const bool try_gso; 491 extern const bool loopback_enabled; 492 extern const bool mpa_crc_required; 493 extern const bool mpa_crc_strict; 494 extern const bool siw_tcp_nagle; 495 extern u_char mpa_version; 496 extern const bool peer_to_peer; 497 extern struct task_struct *siw_tx_thread[]; 498 499 extern struct crypto_shash *siw_crypto_shash; 500 extern struct iwarp_msg_info iwarp_pktinfo[RDMAP_TERMINATE + 1]; 501 502 /* QP general functions */ 503 int siw_qp_modify(struct siw_qp *qp, struct siw_qp_attrs *attr, 504 enum siw_qp_attr_mask mask); 505 int siw_qp_mpa_rts(struct siw_qp *qp, enum mpa_v2_ctrl ctrl); 506 void siw_qp_llp_close(struct siw_qp *qp); 507 void siw_qp_cm_drop(struct siw_qp *qp, int schedule); 508 void siw_send_terminate(struct siw_qp *qp); 509 510 void siw_qp_get_ref(struct ib_qp *qp); 511 void siw_qp_put_ref(struct ib_qp *qp); 512 int siw_qp_add(struct siw_device *sdev, struct siw_qp *qp); 513 void siw_free_qp(struct kref *ref); 514 515 void siw_init_terminate(struct siw_qp *qp, enum term_elayer layer, 516 u8 etype, u8 ecode, int in_tx); 517 enum ddp_ecode siw_tagged_error(enum siw_access_state state); 518 enum rdmap_ecode siw_rdmap_error(enum siw_access_state state); 519 520 void siw_read_to_orq(struct siw_sqe *rreq, struct siw_sqe *sqe); 521 int siw_sqe_complete(struct siw_qp *qp, struct siw_sqe *sqe, u32 bytes, 522 enum siw_wc_status status); 523 int siw_rqe_complete(struct siw_qp *qp, struct siw_rqe *rqe, u32 bytes, 524 u32 inval_stag, enum siw_wc_status status); 525 void siw_qp_llp_data_ready(struct sock *sk); 526 void siw_qp_llp_write_space(struct sock *sk); 527 528 /* QP TX path functions */ 529 int siw_create_tx_threads(void); 530 void siw_stop_tx_threads(void); 531 int siw_run_sq(void *arg); 532 int siw_qp_sq_process(struct siw_qp *qp); 533 int siw_sq_start(struct siw_qp *qp); 534 int siw_activate_tx(struct siw_qp *qp); 535 int siw_get_tx_cpu(struct siw_device *sdev); 536 void siw_put_tx_cpu(int cpu); 537 538 /* QP RX path functions */ 539 int siw_proc_send(struct siw_qp *qp); 540 int siw_proc_rreq(struct siw_qp *qp); 541 int siw_proc_rresp(struct siw_qp *qp); 542 int siw_proc_write(struct siw_qp *qp); 543 int siw_proc_terminate(struct siw_qp *qp); 544 545 int siw_tcp_rx_data(read_descriptor_t *rd_desc, struct sk_buff *skb, 546 unsigned int off, size_t len); 547 548 static inline void set_rx_fpdu_context(struct siw_qp *qp, u8 opcode) 549 { 550 if (opcode == RDMAP_RDMA_WRITE || opcode == RDMAP_RDMA_READ_RESP) 551 qp->rx_fpdu = &qp->rx_tagged; 552 else 553 qp->rx_fpdu = &qp->rx_untagged; 554 555 qp->rx_stream.rdmap_op = opcode; 556 } 557 558 static inline struct siw_ucontext *to_siw_ctx(struct ib_ucontext *base_ctx) 559 { 560 return container_of(base_ctx, struct siw_ucontext, base_ucontext); 561 } 562 563 static inline struct siw_qp *to_siw_qp(struct ib_qp *base_qp) 564 { 565 return container_of(base_qp, struct siw_qp, base_qp); 566 } 567 568 static inline struct siw_cq *to_siw_cq(struct ib_cq *base_cq) 569 { 570 return container_of(base_cq, struct siw_cq, base_cq); 571 } 572 573 static inline struct siw_srq *to_siw_srq(struct ib_srq *base_srq) 574 { 575 return container_of(base_srq, struct siw_srq, base_srq); 576 } 577 578 static inline struct siw_device *to_siw_dev(struct ib_device *base_dev) 579 { 580 return container_of(base_dev, struct siw_device, base_dev); 581 } 582 583 static inline struct siw_mr *to_siw_mr(struct ib_mr *base_mr) 584 { 585 return container_of(base_mr, struct siw_mr, base_mr); 586 } 587 588 static inline struct siw_user_mmap_entry * 589 to_siw_mmap_entry(struct rdma_user_mmap_entry *rdma_mmap) 590 { 591 return container_of(rdma_mmap, struct siw_user_mmap_entry, rdma_entry); 592 } 593 594 static inline struct siw_qp *siw_qp_id2obj(struct siw_device *sdev, int id) 595 { 596 struct siw_qp *qp; 597 598 rcu_read_lock(); 599 qp = xa_load(&sdev->qp_xa, id); 600 if (likely(qp && kref_get_unless_zero(&qp->ref))) { 601 rcu_read_unlock(); 602 return qp; 603 } 604 rcu_read_unlock(); 605 return NULL; 606 } 607 608 static inline u32 qp_id(struct siw_qp *qp) 609 { 610 return qp->base_qp.qp_num; 611 } 612 613 static inline void siw_qp_get(struct siw_qp *qp) 614 { 615 kref_get(&qp->ref); 616 } 617 618 static inline void siw_qp_put(struct siw_qp *qp) 619 { 620 kref_put(&qp->ref, siw_free_qp); 621 } 622 623 static inline int siw_sq_empty(struct siw_qp *qp) 624 { 625 struct siw_sqe *sqe = &qp->sendq[qp->sq_get % qp->attrs.sq_size]; 626 627 return READ_ONCE(sqe->flags) == 0; 628 } 629 630 static inline struct siw_sqe *sq_get_next(struct siw_qp *qp) 631 { 632 struct siw_sqe *sqe = &qp->sendq[qp->sq_get % qp->attrs.sq_size]; 633 634 if (READ_ONCE(sqe->flags) & SIW_WQE_VALID) 635 return sqe; 636 637 return NULL; 638 } 639 640 static inline struct siw_sqe *orq_get_current(struct siw_qp *qp) 641 { 642 return &qp->orq[qp->orq_get % qp->attrs.orq_size]; 643 } 644 645 static inline struct siw_sqe *orq_get_free(struct siw_qp *qp) 646 { 647 struct siw_sqe *orq_e = &qp->orq[qp->orq_put % qp->attrs.orq_size]; 648 649 if (READ_ONCE(orq_e->flags) == 0) 650 return orq_e; 651 652 return NULL; 653 } 654 655 static inline int siw_orq_empty(struct siw_qp *qp) 656 { 657 return orq_get_current(qp)->flags == 0 ? 1 : 0; 658 } 659 660 static inline struct siw_sqe *irq_alloc_free(struct siw_qp *qp) 661 { 662 struct siw_sqe *irq_e = &qp->irq[qp->irq_put % qp->attrs.irq_size]; 663 664 if (READ_ONCE(irq_e->flags) == 0) { 665 qp->irq_put++; 666 return irq_e; 667 } 668 return NULL; 669 } 670 671 static inline __wsum siw_csum_update(const void *buff, int len, __wsum sum) 672 { 673 return (__force __wsum)crc32c((__force __u32)sum, buff, len); 674 } 675 676 static inline __wsum siw_csum_combine(__wsum csum, __wsum csum2, int offset, 677 int len) 678 { 679 return (__force __wsum)__crc32c_le_combine((__force __u32)csum, 680 (__force __u32)csum2, len); 681 } 682 683 static inline void siw_crc_skb(struct siw_rx_stream *srx, unsigned int len) 684 { 685 const struct skb_checksum_ops siw_cs_ops = { 686 .update = siw_csum_update, 687 .combine = siw_csum_combine, 688 }; 689 __wsum crc = *(u32 *)shash_desc_ctx(srx->mpa_crc_hd); 690 691 crc = __skb_checksum(srx->skb, srx->skb_offset, len, crc, 692 &siw_cs_ops); 693 *(u32 *)shash_desc_ctx(srx->mpa_crc_hd) = crc; 694 } 695 696 #define siw_dbg(ibdev, fmt, ...) \ 697 ibdev_dbg(ibdev, "%s: " fmt, __func__, ##__VA_ARGS__) 698 699 #define siw_dbg_qp(qp, fmt, ...) \ 700 ibdev_dbg(&qp->sdev->base_dev, "QP[%u] %s: " fmt, qp_id(qp), __func__, \ 701 ##__VA_ARGS__) 702 703 #define siw_dbg_cq(cq, fmt, ...) \ 704 ibdev_dbg(cq->base_cq.device, "CQ[%u] %s: " fmt, cq->id, __func__, \ 705 ##__VA_ARGS__) 706 707 #define siw_dbg_pd(pd, fmt, ...) \ 708 ibdev_dbg(pd->device, "PD[%u] %s: " fmt, pd->res.id, __func__, \ 709 ##__VA_ARGS__) 710 711 #define siw_dbg_mem(mem, fmt, ...) \ 712 ibdev_dbg(&mem->sdev->base_dev, \ 713 "MEM[0x%08x] %s: " fmt, mem->stag, __func__, ##__VA_ARGS__) 714 715 #define siw_dbg_cep(cep, fmt, ...) \ 716 ibdev_dbg(&cep->sdev->base_dev, "CEP[0x%pK] %s: " fmt, \ 717 cep, __func__, ##__VA_ARGS__) 718 719 void siw_cq_flush(struct siw_cq *cq); 720 void siw_sq_flush(struct siw_qp *qp); 721 void siw_rq_flush(struct siw_qp *qp); 722 int siw_reap_cqe(struct siw_cq *cq, struct ib_wc *wc); 723 724 #endif 725